[mirror_ubuntu-zesty-kernel.git] / arch / mips / jz4740 / platform.c

/*
 *  Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
 *  JZ4740 platform devices
 *
 *  This program is free software; you can redistribute it and/or modify it
 *  under  the terms of the GNU General	 Public License as published by the
 *  Free Software Foundation;  either version 2 of the License, or (at your
 *  option) any later version.
 *
 *  You should have received a copy of the GNU General Public License along
 *  with this program; if not, write to the Free Software Foundation, Inc.,
 *  675 Mass Ave, Cambridge, MA 02139, USA.
 *
 */

#include <linux/clk.h>
#include <linux/device.h>
#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <linux/resource.h>

#include <linux/dma-mapping.h>

#include <linux/usb/musb.h>

#include <asm/mach-jz4740/platform.h>
#include <asm/mach-jz4740/base.h>
#include <asm/mach-jz4740/irq.h>

#include <linux/serial_core.h>
#include <linux/serial_8250.h>

#include "clock.h"

/* USB Device Controller */
struct platform_device jz4740_udc_xceiv_device = {
	.name = "usb_phy_generic",
	.id   = 0,
};

static struct resource jz4740_udc_resources[] = {
	[0] = {
		.start = JZ4740_UDC_BASE_ADDR,
		.end   = JZ4740_UDC_BASE_ADDR + 0x10000 - 1,
		.flags = IORESOURCE_MEM,
	},
	[1] = {
		.start = JZ4740_IRQ_UDC,
		.end   = JZ4740_IRQ_UDC,
		.flags = IORESOURCE_IRQ,
		.name  = "mc",
	},
};

struct platform_device jz4740_udc_device = {
	.name = "musb-jz4740",
	.id   = -1,
	.dev  = {
		.dma_mask          = &jz4740_udc_device.dev.coherent_dma_mask,
		.coherent_dma_mask = DMA_BIT_MASK(32),
	},
	.num_resources = ARRAY_SIZE(jz4740_udc_resources),
	.resource      = jz4740_udc_resources,
};

/* MMC/SD controller */
static struct resource jz4740_mmc_resources[] = {
	{
		.start	= JZ4740_MSC_BASE_ADDR,
		.end	= JZ4740_MSC_BASE_ADDR + 0x1000 - 1,
		.flags	= IORESOURCE_MEM,
	},
	{
		.start	= JZ4740_IRQ_MSC,
		.end	= JZ4740_IRQ_MSC,
		.flags	= IORESOURCE_IRQ,
	}
};

struct platform_device jz4740_mmc_device = {
	.name		= "jz4740-mmc",
	.id		= 0,
	.dev = {
		.dma_mask = &jz4740_mmc_device.dev.coherent_dma_mask,
		.coherent_dma_mask = DMA_BIT_MASK(32),
	},
	.num_resources	= ARRAY_SIZE(jz4740_mmc_resources),
	.resource	= jz4740_mmc_resources,
};

/* RTC controller */
static struct resource jz4740_rtc_resources[] = {
	{
		.start	= JZ4740_RTC_BASE_ADDR,
		.end	= JZ4740_RTC_BASE_ADDR + 0x38 - 1,
		.flags	= IORESOURCE_MEM,
	},
	{
		.start	= JZ4740_IRQ_RTC,
		.end	= JZ4740_IRQ_RTC,
		.flags	= IORESOURCE_IRQ,
	},
};

struct platform_device jz4740_rtc_device = {
	.name		= "jz4740-rtc",
	.id		= -1,
	.num_resources	= ARRAY_SIZE(jz4740_rtc_resources),
	.resource	= jz4740_rtc_resources,
};

/* I2C controller */
static struct resource jz4740_i2c_resources[] = {
	{
		.start	= JZ4740_I2C_BASE_ADDR,
		.end	= JZ4740_I2C_BASE_ADDR + 0x1000 - 1,
		.flags	= IORESOURCE_MEM,
	},
	{
		.start	= JZ4740_IRQ_I2C,
		.end	= JZ4740_IRQ_I2C,
		.flags	= IORESOURCE_IRQ,
	}
};

struct platform_device jz4740_i2c_device = {
	.name		= "jz4740-i2c",
	.id		= 0,
	.num_resources	= ARRAY_SIZE(jz4740_i2c_resources),
	.resource	= jz4740_i2c_resources,
};

/* NAND controller */
static struct resource jz4740_nand_resources[] = {
	{
		.name	= "mmio",
		.start	= JZ4740_EMC_BASE_ADDR,
		.end	= JZ4740_EMC_BASE_ADDR + 0x1000 - 1,
		.flags	= IORESOURCE_MEM,
	},
	{
		.name	= "bank1",
		.start	= 0x18000000,
		.end	= 0x180C0000 - 1,
		.flags = IORESOURCE_MEM,
	},
	{
		.name	= "bank2",
		.start	= 0x14000000,
		.end	= 0x140C0000 - 1,
		.flags = IORESOURCE_MEM,
	},
	{
		.name	= "bank3",
		.start	= 0x0C000000,
		.end	= 0x0C0C0000 - 1,
		.flags = IORESOURCE_MEM,
	},
	{
		.name	= "bank4",
		.start	= 0x08000000,
		.end	= 0x080C0000 - 1,
		.flags = IORESOURCE_MEM,
	},
};

struct platform_device jz4740_nand_device = {
	.name = "jz4740-nand",
	.num_resources = ARRAY_SIZE(jz4740_nand_resources),
	.resource = jz4740_nand_resources,
};

/* LCD controller */
static struct resource jz4740_framebuffer_resources[] = {
	{
		.start	= JZ4740_LCD_BASE_ADDR,
		.end	= JZ4740_LCD_BASE_ADDR + 0x1000 - 1,
		.flags	= IORESOURCE_MEM,
	},
};

struct platform_device jz4740_framebuffer_device = {
	.name		= "jz4740-fb",
	.id		= -1,
	.num_resources	= ARRAY_SIZE(jz4740_framebuffer_resources),
	.resource	= jz4740_framebuffer_resources,
	.dev = {
		.dma_mask = &jz4740_framebuffer_device.dev.coherent_dma_mask,
		.coherent_dma_mask = DMA_BIT_MASK(32),
	},
};

/* I2S controller */
static struct resource jz4740_i2s_resources[] = {
	{
		.start	= JZ4740_AIC_BASE_ADDR,
		.end	= JZ4740_AIC_BASE_ADDR + 0x38 - 1,
		.flags	= IORESOURCE_MEM,
	},
};

struct platform_device jz4740_i2s_device = {
	.name		= "jz4740-i2s",
	.id		= -1,
	.num_resources	= ARRAY_SIZE(jz4740_i2s_resources),
	.resource	= jz4740_i2s_resources,
};

/* PCM */
struct platform_device jz4740_pcm_device = {
	.name		= "jz4740-pcm-audio",
	.id		= -1,
};

/* Codec */
static struct resource jz4740_codec_resources[] = {
	{
		.start	= JZ4740_AIC_BASE_ADDR + 0x80,
		.end	= JZ4740_AIC_BASE_ADDR + 0x88 - 1,
		.flags	= IORESOURCE_MEM,
	},
};

struct platform_device jz4740_codec_device = {
	.name		= "jz4740-codec",
	.id		= -1,
	.num_resources	= ARRAY_SIZE(jz4740_codec_resources),
	.resource	= jz4740_codec_resources,
};

/* ADC controller */
static struct resource jz4740_adc_resources[] = {
	{
		.start	= JZ4740_SADC_BASE_ADDR,
		.end	= JZ4740_SADC_BASE_ADDR + 0x30,
		.flags	= IORESOURCE_MEM,
	},
	{
		.start	= JZ4740_IRQ_SADC,
		.end	= JZ4740_IRQ_SADC,
		.flags	= IORESOURCE_IRQ,
	},
	{
		.start	= JZ4740_IRQ_ADC_BASE,
		.end	= JZ4740_IRQ_ADC_BASE,
		.flags	= IORESOURCE_IRQ,
	},
};

struct platform_device jz4740_adc_device = {
	.name		= "jz4740-adc",
	.id		= -1,
	.num_resources	= ARRAY_SIZE(jz4740_adc_resources),
	.resource	= jz4740_adc_resources,
};

/* Watchdog */
static struct resource jz4740_wdt_resources[] = {
	{
		.start = JZ4740_WDT_BASE_ADDR,
		.end   = JZ4740_WDT_BASE_ADDR + 0x10 - 1,
		.flags = IORESOURCE_MEM,
	},
};

struct platform_device jz4740_wdt_device = {
	.name	       = "jz4740-wdt",
	.id	       = -1,
	.num_resources = ARRAY_SIZE(jz4740_wdt_resources),
	.resource      = jz4740_wdt_resources,
};

/* PWM */
struct platform_device jz4740_pwm_device = {
	.name = "jz4740-pwm",
	.id   = -1,
};

/* DMA */
static struct resource jz4740_dma_resources[] = {
	{
		.start	= JZ4740_DMAC_BASE_ADDR,
		.end	= JZ4740_DMAC_BASE_ADDR + 0x400 - 1,
		.flags	= IORESOURCE_MEM,
	},
	{
		.start	= JZ4740_IRQ_DMAC,
		.end	= JZ4740_IRQ_DMAC,
		.flags	= IORESOURCE_IRQ,
	},
};

struct platform_device jz4740_dma_device = {
	.name		= "jz4740-dma",
	.id		= -1,
	.num_resources	= ARRAY_SIZE(jz4740_dma_resources),
	.resource	= jz4740_dma_resources,
};
Commit	Line	Data
c2a529f7 LPC	1	/*
	2	* Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
	3	* JZ4740 platform devices
	4	*
	5	* This program is free software; you can redistribute it and/or modify it
70342287	6	* under the terms of the GNU General Public License as published by the
c2a529f7 LPC	7	* Free Software Foundation; either version 2 of the License, or (at your
	8	* option) any later version.
	9	*
	10	* You should have received a copy of the GNU General Public License along
	11	* with this program; if not, write to the Free Software Foundation, Inc.,
	12	* 675 Mass Ave, Cambridge, MA 02139, USA.
	13	*
	14	*/
	15
e06b86a3	16	#include <linux/clk.h>
c2a529f7	17	#include <linux/device.h>
c2a529f7 LPC	18	#include <linux/kernel.h>
	19	#include <linux/platform_device.h>
	20	#include <linux/resource.h>
	21
	22	#include <linux/dma-mapping.h>
	23
c330fd90 AS	24	#include <linux/usb/musb.h>
c330fd90 AS	25
c2a529f7 LPC	26	#include <asm/mach-jz4740/platform.h>
	27	#include <asm/mach-jz4740/base.h>
	28	#include <asm/mach-jz4740/irq.h>
	29
	30	#include <linux/serial_core.h>
	31	#include <linux/serial_8250.h>
	32
c2a529f7 LPC	33	#include "clock.h"
c2a529f7 LPC	34
c330fd90 AS	35	/* USB Device Controller */
c330fd90 AS	36	struct platform_device jz4740_udc_xceiv_device = {
c7fb97d6	37	.name = "usb_phy_generic",
c330fd90 AS	38	.id = 0,
	39	};
	40
	41	static struct resource jz4740_udc_resources[] = {
	42	[0] = {
	43	.start = JZ4740_UDC_BASE_ADDR,
	44	.end = JZ4740_UDC_BASE_ADDR + 0x10000 - 1,
	45	.flags = IORESOURCE_MEM,
c2a529f7	46	},
c330fd90 AS	47	[1] = {
	48	.start = JZ4740_IRQ_UDC,
	49	.end = JZ4740_IRQ_UDC,
	50	.flags = IORESOURCE_IRQ,
	51	.name = "mc",
c2a529f7 LPC	52	},
	53	};
	54
	55	struct platform_device jz4740_udc_device = {
c330fd90 AS	56	.name = "musb-jz4740",
	57	.id = -1,
	58	.dev = {
	59	.dma_mask = &jz4740_udc_device.dev.coherent_dma_mask,
c2a529f7 LPC	60	.coherent_dma_mask = DMA_BIT_MASK(32),
c2a529f7 LPC	61	},
c330fd90 AS	62	.num_resources = ARRAY_SIZE(jz4740_udc_resources),
c330fd90 AS	63	.resource = jz4740_udc_resources,
c2a529f7 LPC	64	};
	65
	66	/* MMC/SD controller */
	67	static struct resource jz4740_mmc_resources[] = {
	68	{
	69	.start = JZ4740_MSC_BASE_ADDR,
	70	.end = JZ4740_MSC_BASE_ADDR + 0x1000 - 1,
	71	.flags = IORESOURCE_MEM,
	72	},
	73	{
	74	.start = JZ4740_IRQ_MSC,
	75	.end = JZ4740_IRQ_MSC,
	76	.flags = IORESOURCE_IRQ,
	77	}
	78	};
	79
	80	struct platform_device jz4740_mmc_device = {
	81	.name = "jz4740-mmc",
	82	.id = 0,
	83	.dev = {
	84	.dma_mask = &jz4740_mmc_device.dev.coherent_dma_mask,
	85	.coherent_dma_mask = DMA_BIT_MASK(32),
	86	},
70342287	87	.num_resources = ARRAY_SIZE(jz4740_mmc_resources),
c2a529f7 LPC	88	.resource = jz4740_mmc_resources,
	89	};
	90
	91	/* RTC controller */
	92	static struct resource jz4740_rtc_resources[] = {
	93	{
	94	.start = JZ4740_RTC_BASE_ADDR,
	95	.end = JZ4740_RTC_BASE_ADDR + 0x38 - 1,
	96	.flags = IORESOURCE_MEM,
	97	},
	98	{
70342287	99	.start = JZ4740_IRQ_RTC,
c2a529f7 LPC	100	.end = JZ4740_IRQ_RTC,
	101	.flags = IORESOURCE_IRQ,
	102	},
	103	};
	104
	105	struct platform_device jz4740_rtc_device = {
	106	.name = "jz4740-rtc",
	107	.id = -1,
	108	.num_resources = ARRAY_SIZE(jz4740_rtc_resources),
	109	.resource = jz4740_rtc_resources,
	110	};
	111
	112	/* I2C controller */
	113	static struct resource jz4740_i2c_resources[] = {
	114	{
	115	.start = JZ4740_I2C_BASE_ADDR,
	116	.end = JZ4740_I2C_BASE_ADDR + 0x1000 - 1,
	117	.flags = IORESOURCE_MEM,
	118	},
	119	{
	120	.start = JZ4740_IRQ_I2C,
	121	.end = JZ4740_IRQ_I2C,
	122	.flags = IORESOURCE_IRQ,
	123	}
	124	};
	125
	126	struct platform_device jz4740_i2c_device = {
	127	.name = "jz4740-i2c",
	128	.id = 0,
70342287	129	.num_resources = ARRAY_SIZE(jz4740_i2c_resources),
c2a529f7 LPC	130	.resource = jz4740_i2c_resources,
	131	};
	132
	133	/* NAND controller */
	134	static struct resource jz4740_nand_resources[] = {
	135	{
	136	.name = "mmio",
	137	.start = JZ4740_EMC_BASE_ADDR,
	138	.end = JZ4740_EMC_BASE_ADDR + 0x1000 - 1,
	139	.flags = IORESOURCE_MEM,
	140	},
	141	{
1471d41a	142	.name = "bank1",
c2a529f7 LPC	143	.start = 0x18000000,
	144	.end = 0x180C0000 - 1,
	145	.flags = IORESOURCE_MEM,
	146	},
1471d41a MH	147	{
	148	.name = "bank2",
	149	.start = 0x14000000,
	150	.end = 0x140C0000 - 1,
	151	.flags = IORESOURCE_MEM,
	152	},
	153	{
	154	.name = "bank3",
	155	.start = 0x0C000000,
	156	.end = 0x0C0C0000 - 1,
	157	.flags = IORESOURCE_MEM,
	158	},
	159	{
	160	.name = "bank4",
	161	.start = 0x08000000,
	162	.end = 0x080C0000 - 1,
	163	.flags = IORESOURCE_MEM,
	164	},
c2a529f7 LPC	165	};
	166
	167	struct platform_device jz4740_nand_device = {
	168	.name = "jz4740-nand",
	169	.num_resources = ARRAY_SIZE(jz4740_nand_resources),
	170	.resource = jz4740_nand_resources,
	171	};
	172
	173	/* LCD controller */
	174	static struct resource jz4740_framebuffer_resources[] = {
	175	{
	176	.start = JZ4740_LCD_BASE_ADDR,
	177	.end = JZ4740_LCD_BASE_ADDR + 0x1000 - 1,
	178	.flags = IORESOURCE_MEM,
	179	},
	180	};
	181
	182	struct platform_device jz4740_framebuffer_device = {
	183	.name = "jz4740-fb",
	184	.id = -1,
	185	.num_resources = ARRAY_SIZE(jz4740_framebuffer_resources),
	186	.resource = jz4740_framebuffer_resources,
	187	.dev = {
	188	.dma_mask = &jz4740_framebuffer_device.dev.coherent_dma_mask,
	189	.coherent_dma_mask = DMA_BIT_MASK(32),
	190	},
	191	};
	192
	193	/* I2S controller */
	194	static struct resource jz4740_i2s_resources[] = {
	195	{
	196	.start = JZ4740_AIC_BASE_ADDR,
	197	.end = JZ4740_AIC_BASE_ADDR + 0x38 - 1,
	198	.flags = IORESOURCE_MEM,
	199	},
	200	};
	201
	202	struct platform_device jz4740_i2s_device = {
	203	.name = "jz4740-i2s",
	204	.id = -1,
	205	.num_resources = ARRAY_SIZE(jz4740_i2s_resources),
	206	.resource = jz4740_i2s_resources,
	207	};
	208
	209	/* PCM */
	210	struct platform_device jz4740_pcm_device = {
4afdea81	211	.name = "jz4740-pcm-audio",
c2a529f7 LPC	212	.id = -1,
	213	};
	214
	215	/* Codec */
	216	static struct resource jz4740_codec_resources[] = {
	217	{
	218	.start = JZ4740_AIC_BASE_ADDR + 0x80,
	219	.end = JZ4740_AIC_BASE_ADDR + 0x88 - 1,
	220	.flags = IORESOURCE_MEM,
	221	},
	222	};
	223
	224	struct platform_device jz4740_codec_device = {
	225	.name = "jz4740-codec",
	226	.id = -1,
	227	.num_resources = ARRAY_SIZE(jz4740_codec_resources),
	228	.resource = jz4740_codec_resources,
	229	};
	230
	231	/* ADC controller */
	232	static struct resource jz4740_adc_resources[] = {
	233	{
	234	.start = JZ4740_SADC_BASE_ADDR,
	235	.end = JZ4740_SADC_BASE_ADDR + 0x30,
	236	.flags = IORESOURCE_MEM,
	237	},
	238	{
	239	.start = JZ4740_IRQ_SADC,
	240	.end = JZ4740_IRQ_SADC,
	241	.flags = IORESOURCE_IRQ,
	242	},
	243	{
	244	.start = JZ4740_IRQ_ADC_BASE,
	245	.end = JZ4740_IRQ_ADC_BASE,
	246	.flags = IORESOURCE_IRQ,
	247	},
	248	};
	249
	250	struct platform_device jz4740_adc_device = {
	251	.name = "jz4740-adc",
	252	.id = -1,
	253	.num_resources = ARRAY_SIZE(jz4740_adc_resources),
	254	.resource = jz4740_adc_resources,
	255	};
	256
f865c352 PC	257	/* Watchdog */
	258	static struct resource jz4740_wdt_resources[] = {
	259	{
	260	.start = JZ4740_WDT_BASE_ADDR,
	261	.end = JZ4740_WDT_BASE_ADDR + 0x10 - 1,
	262	.flags = IORESOURCE_MEM,
	263	},
	264	};
	265
	266	struct platform_device jz4740_wdt_device = {
70342287 RB	267	.name = "jz4740-wdt",
70342287 RB	268	.id = -1,
f865c352 PC	269	.num_resources = ARRAY_SIZE(jz4740_wdt_resources),
	270	.resource = jz4740_wdt_resources,
	271	};
f6b8a570 TR	272
	273	/* PWM */
	274	struct platform_device jz4740_pwm_device = {
	275	.name = "jz4740-pwm",
	276	.id = -1,
	277	};
cdcb90ad LPC	278
	279	/* DMA */
	280	static struct resource jz4740_dma_resources[] = {
	281	{
	282	.start = JZ4740_DMAC_BASE_ADDR,
	283	.end = JZ4740_DMAC_BASE_ADDR + 0x400 - 1,
	284	.flags = IORESOURCE_MEM,
	285	},
	286	{
	287	.start = JZ4740_IRQ_DMAC,
	288	.end = JZ4740_IRQ_DMAC,
	289	.flags = IORESOURCE_IRQ,
	290	},
	291	};
	292
	293	struct platform_device jz4740_dma_device = {
	294	.name = "jz4740-dma",
	295	.id = -1,
	296	.num_resources = ARRAY_SIZE(jz4740_dma_resources),
	297	.resource = jz4740_dma_resources,
	298	};