[mirror_ubuntu-zesty-kernel.git] / arch / mips / jz4740 / time.c

/*
 *  Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
 *  JZ4740 platform time support
 *
 *  This program is free software; you can redistribute it and/or modify it
 *  under  the terms of the GNU General	 Public License as published by the
 *  Free Software Foundation;  either version 2 of the License, or (at your
 *  option) any later version.
 *
 *  You should have received a copy of the GNU General Public License along
 *  with this program; if not, write to the Free Software Foundation, Inc.,
 *  675 Mass Ave, Cambridge, MA 02139, USA.
 *
 */

#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/time.h>

#include <linux/clockchips.h>
#include <linux/sched_clock.h>

#include <asm/mach-jz4740/clock.h>
#include <asm/mach-jz4740/irq.h>
#include <asm/mach-jz4740/timer.h>
#include <asm/time.h>

#include "clock.h"

#define TIMER_CLOCKEVENT 0
#define TIMER_CLOCKSOURCE 1

static uint16_t jz4740_jiffies_per_tick;

static cycle_t jz4740_clocksource_read(struct clocksource *cs)
{
	return jz4740_timer_get_count(TIMER_CLOCKSOURCE);
}

static struct clocksource jz4740_clocksource = {
	.name = "jz4740-timer",
	.rating = 200,
	.read = jz4740_clocksource_read,
	.mask = CLOCKSOURCE_MASK(16),
	.flags = CLOCK_SOURCE_IS_CONTINUOUS,
};

static u64 notrace jz4740_read_sched_clock(void)
{
	return jz4740_timer_get_count(TIMER_CLOCKSOURCE);
}

static irqreturn_t jz4740_clockevent_irq(int irq, void *devid)
{
	struct clock_event_device *cd = devid;

	jz4740_timer_ack_full(TIMER_CLOCKEVENT);

	if (cd->mode != CLOCK_EVT_MODE_PERIODIC)
		jz4740_timer_disable(TIMER_CLOCKEVENT);

	cd->event_handler(cd);

	return IRQ_HANDLED;
}

static void jz4740_clockevent_set_mode(enum clock_event_mode mode,
	struct clock_event_device *cd)
{
	switch (mode) {
	case CLOCK_EVT_MODE_PERIODIC:
		jz4740_timer_set_count(TIMER_CLOCKEVENT, 0);
		jz4740_timer_set_period(TIMER_CLOCKEVENT, jz4740_jiffies_per_tick);
	case CLOCK_EVT_MODE_RESUME:
		jz4740_timer_irq_full_enable(TIMER_CLOCKEVENT);
		jz4740_timer_enable(TIMER_CLOCKEVENT);
		break;
	case CLOCK_EVT_MODE_ONESHOT:
	case CLOCK_EVT_MODE_SHUTDOWN:
		jz4740_timer_disable(TIMER_CLOCKEVENT);
		break;
	default:
		break;
	}
}

static int jz4740_clockevent_set_next(unsigned long evt,
	struct clock_event_device *cd)
{
	jz4740_timer_set_count(TIMER_CLOCKEVENT, 0);
	jz4740_timer_set_period(TIMER_CLOCKEVENT, evt);
	jz4740_timer_enable(TIMER_CLOCKEVENT);

	return 0;
}

static struct clock_event_device jz4740_clockevent = {
	.name = "jz4740-timer",
	.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
	.set_next_event = jz4740_clockevent_set_next,
	.set_mode = jz4740_clockevent_set_mode,
	.rating = 200,
	.irq = JZ4740_IRQ_TCU0,
};

static struct irqaction timer_irqaction = {
	.handler	= jz4740_clockevent_irq,
	.flags		= IRQF_PERCPU | IRQF_TIMER,
	.name		= "jz4740-timerirq",
	.dev_id		= &jz4740_clockevent,
};

void __init plat_time_init(void)
{
	int ret;
	uint32_t clk_rate;
	uint16_t ctrl;
	struct clk *ext_clk;

	of_clk_init(NULL);
	jz4740_clock_init();
	jz4740_timer_init();

	ext_clk = clk_get(NULL, "ext");
	if (IS_ERR(ext_clk))
		panic("unable to get ext clock");
	clk_rate = clk_get_rate(ext_clk) >> 4;
	clk_put(ext_clk);

	jz4740_jiffies_per_tick = DIV_ROUND_CLOSEST(clk_rate, HZ);

	clockevent_set_clock(&jz4740_clockevent, clk_rate);
	jz4740_clockevent.min_delta_ns = clockevent_delta2ns(100, &jz4740_clockevent);
	jz4740_clockevent.max_delta_ns = clockevent_delta2ns(0xffff, &jz4740_clockevent);
	jz4740_clockevent.cpumask = cpumask_of(0);

	clockevents_register_device(&jz4740_clockevent);

	ret = clocksource_register_hz(&jz4740_clocksource, clk_rate);

	if (ret)
		printk(KERN_ERR "Failed to register clocksource: %d\n", ret);

	sched_clock_register(jz4740_read_sched_clock, 16, clk_rate);

	setup_irq(JZ4740_IRQ_TCU0, &timer_irqaction);

	ctrl = JZ_TIMER_CTRL_PRESCALE_16 | JZ_TIMER_CTRL_SRC_EXT;

	jz4740_timer_set_ctrl(TIMER_CLOCKEVENT, ctrl);
	jz4740_timer_set_ctrl(TIMER_CLOCKSOURCE, ctrl);

	jz4740_timer_set_period(TIMER_CLOCKEVENT, jz4740_jiffies_per_tick);
	jz4740_timer_irq_full_enable(TIMER_CLOCKEVENT);

	jz4740_timer_set_period(TIMER_CLOCKSOURCE, 0xffff);

	jz4740_timer_enable(TIMER_CLOCKEVENT);
	jz4740_timer_enable(TIMER_CLOCKSOURCE);
}
Commit	Line	Data
b200eff6 LPC	1	/*
	2	* Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
	3	* JZ4740 platform time support
	4	*
	5	* This program is free software; you can redistribute it and/or modify it
70342287	6	* under the terms of the GNU General Public License as published by the
b200eff6 LPC	7	* Free Software Foundation; either version 2 of the License, or (at your
	8	* option) any later version.
	9	*
	10	* You should have received a copy of the GNU General Public License along
	11	* with this program; if not, write to the Free Software Foundation, Inc.,
	12	* 675 Mass Ave, Cambridge, MA 02139, USA.
	13	*
	14	*/
	15
e06b86a3	16	#include <linux/clk.h>
ff1930c6	17	#include <linux/clk-provider.h>
b200eff6 LPC	18	#include <linux/interrupt.h>
	19	#include <linux/kernel.h>
	20	#include <linux/time.h>
	21
	22	#include <linux/clockchips.h>
944081ac	23	#include <linux/sched_clock.h>
b200eff6	24
1f4b8409	25	#include <asm/mach-jz4740/clock.h>
b200eff6	26	#include <asm/mach-jz4740/irq.h>
46a98765	27	#include <asm/mach-jz4740/timer.h>
b200eff6 LPC	28	#include <asm/time.h>
	29
	30	#include "clock.h"
b200eff6 LPC	31
	32	#define TIMER_CLOCKEVENT 0
	33	#define TIMER_CLOCKSOURCE 1
	34
	35	static uint16_t jz4740_jiffies_per_tick;
	36
	37	static cycle_t jz4740_clocksource_read(struct clocksource *cs)
	38	{
	39	return jz4740_timer_get_count(TIMER_CLOCKSOURCE);
	40	}
	41
	42	static struct clocksource jz4740_clocksource = {
	43	.name = "jz4740-timer",
	44	.rating = 200,
	45	.read = jz4740_clocksource_read,
	46	.mask = CLOCKSOURCE_MASK(16),
	47	.flags = CLOCK_SOURCE_IS_CONTINUOUS,
	48	};
	49
944081ac DCZ	50	static u64 notrace jz4740_read_sched_clock(void)
	51	{
	52	return jz4740_timer_get_count(TIMER_CLOCKSOURCE);
	53	}
	54
b200eff6 LPC	55	static irqreturn_t jz4740_clockevent_irq(int irq, void *devid)
	56	{
	57	struct clock_event_device *cd = devid;
	58
	59	jz4740_timer_ack_full(TIMER_CLOCKEVENT);
	60
	61	if (cd->mode != CLOCK_EVT_MODE_PERIODIC)
	62	jz4740_timer_disable(TIMER_CLOCKEVENT);
	63
	64	cd->event_handler(cd);
	65
	66	return IRQ_HANDLED;
	67	}
	68
	69	static void jz4740_clockevent_set_mode(enum clock_event_mode mode,
	70	struct clock_event_device *cd)
	71	{
	72	switch (mode) {
	73	case CLOCK_EVT_MODE_PERIODIC:
	74	jz4740_timer_set_count(TIMER_CLOCKEVENT, 0);
	75	jz4740_timer_set_period(TIMER_CLOCKEVENT, jz4740_jiffies_per_tick);
	76	case CLOCK_EVT_MODE_RESUME:
	77	jz4740_timer_irq_full_enable(TIMER_CLOCKEVENT);
	78	jz4740_timer_enable(TIMER_CLOCKEVENT);
	79	break;
	80	case CLOCK_EVT_MODE_ONESHOT:
	81	case CLOCK_EVT_MODE_SHUTDOWN:
	82	jz4740_timer_disable(TIMER_CLOCKEVENT);
	83	break;
	84	default:
	85	break;
	86	}
	87	}
	88
	89	static int jz4740_clockevent_set_next(unsigned long evt,
	90	struct clock_event_device *cd)
	91	{
	92	jz4740_timer_set_count(TIMER_CLOCKEVENT, 0);
	93	jz4740_timer_set_period(TIMER_CLOCKEVENT, evt);
	94	jz4740_timer_enable(TIMER_CLOCKEVENT);
	95
	96	return 0;
	97	}
	98
	99	static struct clock_event_device jz4740_clockevent = {
	100	.name = "jz4740-timer",
1e2bbde4	101	.features = CLOCK_EVT_FEAT_PERIODIC \| CLOCK_EVT_FEAT_ONESHOT,
b200eff6 LPC	102	.set_next_event = jz4740_clockevent_set_next,
	103	.set_mode = jz4740_clockevent_set_mode,
	104	.rating = 200,
	105	.irq = JZ4740_IRQ_TCU0,
	106	};
	107
	108	static struct irqaction timer_irqaction = {
	109	.handler = jz4740_clockevent_irq,
	110	.flags = IRQF_PERCPU \| IRQF_TIMER,
	111	.name = "jz4740-timerirq",
	112	.dev_id = &jz4740_clockevent,
	113	};
	114
	115	void __init plat_time_init(void)
	116	{
	117	int ret;
	118	uint32_t clk_rate;
	119	uint16_t ctrl;
e06b86a3	120	struct clk *ext_clk;
b200eff6	121
ff1930c6	122	of_clk_init(NULL);
1f4b8409	123	jz4740_clock_init();
b200eff6 LPC	124	jz4740_timer_init();
b200eff6 LPC	125
e06b86a3 PB	126	ext_clk = clk_get(NULL, "ext");
	127	if (IS_ERR(ext_clk))
	128	panic("unable to get ext clock");
	129	clk_rate = clk_get_rate(ext_clk) >> 4;
	130	clk_put(ext_clk);
	131
b200eff6 LPC	132	jz4740_jiffies_per_tick = DIV_ROUND_CLOSEST(clk_rate, HZ);
	133
	134	clockevent_set_clock(&jz4740_clockevent, clk_rate);
	135	jz4740_clockevent.min_delta_ns = clockevent_delta2ns(100, &jz4740_clockevent);
	136	jz4740_clockevent.max_delta_ns = clockevent_delta2ns(0xffff, &jz4740_clockevent);
	137	jz4740_clockevent.cpumask = cpumask_of(0);
	138
	139	clockevents_register_device(&jz4740_clockevent);
	140
75c4fd8c	141	ret = clocksource_register_hz(&jz4740_clocksource, clk_rate);
b200eff6 LPC	142
	143	if (ret)
	144	printk(KERN_ERR "Failed to register clocksource: %d\n", ret);
	145
944081ac DCZ	146	sched_clock_register(jz4740_read_sched_clock, 16, clk_rate);
944081ac DCZ	147
b200eff6 LPC	148	setup_irq(JZ4740_IRQ_TCU0, &timer_irqaction);
	149
	150	ctrl = JZ_TIMER_CTRL_PRESCALE_16 \| JZ_TIMER_CTRL_SRC_EXT;
	151
	152	jz4740_timer_set_ctrl(TIMER_CLOCKEVENT, ctrl);
	153	jz4740_timer_set_ctrl(TIMER_CLOCKSOURCE, ctrl);
	154
	155	jz4740_timer_set_period(TIMER_CLOCKEVENT, jz4740_jiffies_per_tick);
	156	jz4740_timer_irq_full_enable(TIMER_CLOCKEVENT);
	157
	158	jz4740_timer_set_period(TIMER_CLOCKSOURCE, 0xffff);
	159
	160	jz4740_timer_enable(TIMER_CLOCKEVENT);
	161	jz4740_timer_enable(TIMER_CLOCKSOURCE);
	162	}