[mirror_ubuntu-zesty-kernel.git] / arch / mips / kernel / branch.c

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 1996, 97, 2000, 2001 by Ralf Baechle
 * Copyright (C) 2001 MIPS Technologies, Inc.
 */
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/signal.h>
#include <linux/module.h>
#include <asm/branch.h>
#include <asm/cpu.h>
#include <asm/cpu-features.h>
#include <asm/fpu.h>
#include <asm/fpu_emulator.h>
#include <asm/inst.h>
#include <asm/ptrace.h>
#include <asm/uaccess.h>

/*
 * Calculate and return exception PC in case of branch delay slot
 * for microMIPS and MIPS16e. It does not clear the ISA mode bit.
 */
int __isa_exception_epc(struct pt_regs *regs)
{
	unsigned short inst;
	long epc = regs->cp0_epc;

	/* Calculate exception PC in branch delay slot. */
	if (__get_user(inst, (u16 __user *) msk_isa16_mode(epc))) {
		/* This should never happen because delay slot was checked. */
		force_sig(SIGSEGV, current);
		return epc;
	}
	if (cpu_has_mips16) {
		if (((union mips16e_instruction)inst).ri.opcode
				== MIPS16e_jal_op)
			epc += 4;
		else
			epc += 2;
	} else if (mm_insn_16bit(inst))
		epc += 2;
	else
		epc += 4;

	return epc;
}

/* (microMIPS) Convert 16-bit register encoding to 32-bit register encoding. */
static const unsigned int reg16to32map[8] = {16, 17, 2, 3, 4, 5, 6, 7};

int __mm_isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
		       unsigned long *contpc)
{
	union mips_instruction insn = (union mips_instruction)dec_insn.insn;
	int bc_false = 0;
	unsigned int fcr31;
	unsigned int bit;

	if (!cpu_has_mmips)
		return 0;

	switch (insn.mm_i_format.opcode) {
	case mm_pool32a_op:
		if ((insn.mm_i_format.simmediate & MM_POOL32A_MINOR_MASK) ==
		    mm_pool32axf_op) {
			switch (insn.mm_i_format.simmediate >>
				MM_POOL32A_MINOR_SHIFT) {
			case mm_jalr_op:
			case mm_jalrhb_op:
			case mm_jalrs_op:
			case mm_jalrshb_op:
				if (insn.mm_i_format.rt != 0)	/* Not mm_jr */
					regs->regs[insn.mm_i_format.rt] =
						regs->cp0_epc +
						dec_insn.pc_inc +
						dec_insn.next_pc_inc;
				*contpc = regs->regs[insn.mm_i_format.rs];
				return 1;
			}
		}
		break;
	case mm_pool32i_op:
		switch (insn.mm_i_format.rt) {
		case mm_bltzals_op:
		case mm_bltzal_op:
			regs->regs[31] = regs->cp0_epc +
				dec_insn.pc_inc +
				dec_insn.next_pc_inc;
			/* Fall through */
		case mm_bltz_op:
			if ((long)regs->regs[insn.mm_i_format.rs] < 0)
				*contpc = regs->cp0_epc +
					dec_insn.pc_inc +
					(insn.mm_i_format.simmediate << 1);
			else
				*contpc = regs->cp0_epc +
					dec_insn.pc_inc +
					dec_insn.next_pc_inc;
			return 1;
		case mm_bgezals_op:
		case mm_bgezal_op:
			regs->regs[31] = regs->cp0_epc +
					dec_insn.pc_inc +
					dec_insn.next_pc_inc;
			/* Fall through */
		case mm_bgez_op:
			if ((long)regs->regs[insn.mm_i_format.rs] >= 0)
				*contpc = regs->cp0_epc +
					dec_insn.pc_inc +
					(insn.mm_i_format.simmediate << 1);
			else
				*contpc = regs->cp0_epc +
					dec_insn.pc_inc +
					dec_insn.next_pc_inc;
			return 1;
		case mm_blez_op:
			if ((long)regs->regs[insn.mm_i_format.rs] <= 0)
				*contpc = regs->cp0_epc +
					dec_insn.pc_inc +
					(insn.mm_i_format.simmediate << 1);
			else
				*contpc = regs->cp0_epc +
					dec_insn.pc_inc +
					dec_insn.next_pc_inc;
			return 1;
		case mm_bgtz_op:
			if ((long)regs->regs[insn.mm_i_format.rs] <= 0)
				*contpc = regs->cp0_epc +
					dec_insn.pc_inc +
					(insn.mm_i_format.simmediate << 1);
			else
				*contpc = regs->cp0_epc +
					dec_insn.pc_inc +
					dec_insn.next_pc_inc;
			return 1;
		case mm_bc2f_op:
		case mm_bc1f_op:
			bc_false = 1;
			/* Fall through */
		case mm_bc2t_op:
		case mm_bc1t_op:
			preempt_disable();
			if (is_fpu_owner())
			        fcr31 = read_32bit_cp1_register(CP1_STATUS);
			else
				fcr31 = current->thread.fpu.fcr31;
			preempt_enable();

			if (bc_false)
				fcr31 = ~fcr31;

			bit = (insn.mm_i_format.rs >> 2);
			bit += (bit != 0);
			bit += 23;
			if (fcr31 & (1 << bit))
				*contpc = regs->cp0_epc +
					dec_insn.pc_inc +
					(insn.mm_i_format.simmediate << 1);
			else
				*contpc = regs->cp0_epc +
					dec_insn.pc_inc + dec_insn.next_pc_inc;
			return 1;
		}
		break;
	case mm_pool16c_op:
		switch (insn.mm_i_format.rt) {
		case mm_jalr16_op:
		case mm_jalrs16_op:
			regs->regs[31] = regs->cp0_epc +
				dec_insn.pc_inc + dec_insn.next_pc_inc;
			/* Fall through */
		case mm_jr16_op:
			*contpc = regs->regs[insn.mm_i_format.rs];
			return 1;
		}
		break;
	case mm_beqz16_op:
		if ((long)regs->regs[reg16to32map[insn.mm_b1_format.rs]] == 0)
			*contpc = regs->cp0_epc +
				dec_insn.pc_inc +
				(insn.mm_b1_format.simmediate << 1);
		else
			*contpc = regs->cp0_epc +
				dec_insn.pc_inc + dec_insn.next_pc_inc;
		return 1;
	case mm_bnez16_op:
		if ((long)regs->regs[reg16to32map[insn.mm_b1_format.rs]] != 0)
			*contpc = regs->cp0_epc +
				dec_insn.pc_inc +
				(insn.mm_b1_format.simmediate << 1);
		else
			*contpc = regs->cp0_epc +
				dec_insn.pc_inc + dec_insn.next_pc_inc;
		return 1;
	case mm_b16_op:
		*contpc = regs->cp0_epc + dec_insn.pc_inc +
			 (insn.mm_b0_format.simmediate << 1);
		return 1;
	case mm_beq32_op:
		if (regs->regs[insn.mm_i_format.rs] ==
		    regs->regs[insn.mm_i_format.rt])
			*contpc = regs->cp0_epc +
				dec_insn.pc_inc +
				(insn.mm_i_format.simmediate << 1);
		else
			*contpc = regs->cp0_epc +
				dec_insn.pc_inc +
				dec_insn.next_pc_inc;
		return 1;
	case mm_bne32_op:
		if (regs->regs[insn.mm_i_format.rs] !=
		    regs->regs[insn.mm_i_format.rt])
			*contpc = regs->cp0_epc +
				dec_insn.pc_inc +
				(insn.mm_i_format.simmediate << 1);
		else
			*contpc = regs->cp0_epc +
				dec_insn.pc_inc + dec_insn.next_pc_inc;
		return 1;
	case mm_jalx32_op:
		regs->regs[31] = regs->cp0_epc +
			dec_insn.pc_inc + dec_insn.next_pc_inc;
		*contpc = regs->cp0_epc + dec_insn.pc_inc;
		*contpc >>= 28;
		*contpc <<= 28;
		*contpc |= (insn.j_format.target << 2);
		return 1;
	case mm_jals32_op:
	case mm_jal32_op:
		regs->regs[31] = regs->cp0_epc +
			dec_insn.pc_inc + dec_insn.next_pc_inc;
		/* Fall through */
	case mm_j32_op:
		*contpc = regs->cp0_epc + dec_insn.pc_inc;
		*contpc >>= 27;
		*contpc <<= 27;
		*contpc |= (insn.j_format.target << 1);
		set_isa16_mode(*contpc);
		return 1;
	}
	return 0;
}

/*
 * Compute return address and emulate branch in microMIPS mode after an
 * exception only. It does not handle compact branches/jumps and cannot
 * be used in interrupt context. (Compact branches/jumps do not cause
 * exceptions.)
 */
int __microMIPS_compute_return_epc(struct pt_regs *regs)
{
	u16 __user *pc16;
	u16 halfword;
	unsigned int word;
	unsigned long contpc;
	struct mm_decoded_insn mminsn = { 0 };

	mminsn.micro_mips_mode = 1;

	/* This load never faults. */
	pc16 = (unsigned short __user *)msk_isa16_mode(regs->cp0_epc);
	__get_user(halfword, pc16);
	pc16++;
	contpc = regs->cp0_epc + 2;
	word = ((unsigned int)halfword << 16);
	mminsn.pc_inc = 2;

	if (!mm_insn_16bit(halfword)) {
		__get_user(halfword, pc16);
		pc16++;
		contpc = regs->cp0_epc + 4;
		mminsn.pc_inc = 4;
		word |= halfword;
	}
	mminsn.insn = word;

	if (get_user(halfword, pc16))
		goto sigsegv;
	mminsn.next_pc_inc = 2;
	word = ((unsigned int)halfword << 16);

	if (!mm_insn_16bit(halfword)) {
		pc16++;
		if (get_user(halfword, pc16))
			goto sigsegv;
		mminsn.next_pc_inc = 4;
		word |= halfword;
	}
	mminsn.next_insn = word;

	mm_isBranchInstr(regs, mminsn, &contpc);

	regs->cp0_epc = contpc;

	return 0;

sigsegv:
	force_sig(SIGSEGV, current);
	return -EFAULT;
}

/*
 * Compute return address and emulate branch in MIPS16e mode after an
 * exception only. It does not handle compact branches/jumps and cannot
 * be used in interrupt context. (Compact branches/jumps do not cause
 * exceptions.)
 */
int __MIPS16e_compute_return_epc(struct pt_regs *regs)
{
	u16 __user *addr;
	union mips16e_instruction inst;
	u16 inst2;
	u32 fullinst;
	long epc;

	epc = regs->cp0_epc;

	/* Read the instruction. */
	addr = (u16 __user *)msk_isa16_mode(epc);
	if (__get_user(inst.full, addr)) {
		force_sig(SIGSEGV, current);
		return -EFAULT;
	}

	switch (inst.ri.opcode) {
	case MIPS16e_extend_op:
		regs->cp0_epc += 4;
		return 0;

		/*
		 *  JAL and JALX in MIPS16e mode
		 */
	case MIPS16e_jal_op:
		addr += 1;
		if (__get_user(inst2, addr)) {
			force_sig(SIGSEGV, current);
			return -EFAULT;
		}
		fullinst = ((unsigned)inst.full << 16) | inst2;
		regs->regs[31] = epc + 6;
		epc += 4;
		epc >>= 28;
		epc <<= 28;
		/*
		 * JAL:5 X:1 TARGET[20-16]:5 TARGET[25:21]:5 TARGET[15:0]:16
		 *
		 * ......TARGET[15:0].................TARGET[20:16]...........
		 * ......TARGET[25:21]
		 */
		epc |=
		    ((fullinst & 0xffff) << 2) | ((fullinst & 0x3e00000) >> 3) |
		    ((fullinst & 0x1f0000) << 7);
		if (!inst.jal.x)
			set_isa16_mode(epc);	/* Set ISA mode bit. */
		regs->cp0_epc = epc;
		return 0;

		/*
		 *  J(AL)R(C)
		 */
	case MIPS16e_rr_op:
		if (inst.rr.func == MIPS16e_jr_func) {

			if (inst.rr.ra)
				regs->cp0_epc = regs->regs[31];
			else
				regs->cp0_epc =
				    regs->regs[reg16to32[inst.rr.rx]];

			if (inst.rr.l) {
				if (inst.rr.nd)
					regs->regs[31] = epc + 2;
				else
					regs->regs[31] = epc + 4;
			}
			return 0;
		}
		break;
	}

	/*
	 * All other cases have no branch delay slot and are 16-bits.
	 * Branches do not cause an exception.
	 */
	regs->cp0_epc += 2;

	return 0;
}

/**
 * __compute_return_epc_for_insn - Computes the return address and do emulate
 *				    branch simulation, if required.
 *
 * @regs:	Pointer to pt_regs
 * @insn:	branch instruction to decode
 * @returns:	-EFAULT on error and forces SIGBUS, and on success
 *		returns 0 or BRANCH_LIKELY_TAKEN as appropriate after
 *		evaluating the branch.
 */
int __compute_return_epc_for_insn(struct pt_regs *regs,
				   union mips_instruction insn)
{
	unsigned int bit, fcr31, dspcontrol;
	long epc = regs->cp0_epc;
	int ret = 0;

	switch (insn.i_format.opcode) {
	/*
	 * jr and jalr are in r_format format.
	 */
	case spec_op:
		switch (insn.r_format.func) {
		case jalr_op:
			regs->regs[insn.r_format.rd] = epc + 8;
			/* Fall through */
		case jr_op:
			regs->cp0_epc = regs->regs[insn.r_format.rs];
			break;
		}
		break;

	/*
	 * This group contains:
	 * bltz_op, bgez_op, bltzl_op, bgezl_op,
	 * bltzal_op, bgezal_op, bltzall_op, bgezall_op.
	 */
	case bcond_op:
		switch (insn.i_format.rt) {
		case bltz_op:
		case bltzl_op:
			if ((long)regs->regs[insn.i_format.rs] < 0) {
				epc = epc + 4 + (insn.i_format.simmediate << 2);
				if (insn.i_format.rt == bltzl_op)
					ret = BRANCH_LIKELY_TAKEN;
			} else
				epc += 8;
			regs->cp0_epc = epc;
			break;

		case bgez_op:
		case bgezl_op:
			if ((long)regs->regs[insn.i_format.rs] >= 0) {
				epc = epc + 4 + (insn.i_format.simmediate << 2);
				if (insn.i_format.rt == bgezl_op)
					ret = BRANCH_LIKELY_TAKEN;
			} else
				epc += 8;
			regs->cp0_epc = epc;
			break;

		case bltzal_op:
		case bltzall_op:
			regs->regs[31] = epc + 8;
			if ((long)regs->regs[insn.i_format.rs] < 0) {
				epc = epc + 4 + (insn.i_format.simmediate << 2);
				if (insn.i_format.rt == bltzall_op)
					ret = BRANCH_LIKELY_TAKEN;
			} else
				epc += 8;
			regs->cp0_epc = epc;
			break;

		case bgezal_op:
		case bgezall_op:
			regs->regs[31] = epc + 8;
			if ((long)regs->regs[insn.i_format.rs] >= 0) {
				epc = epc + 4 + (insn.i_format.simmediate << 2);
				if (insn.i_format.rt == bgezall_op)
					ret = BRANCH_LIKELY_TAKEN;
			} else
				epc += 8;
			regs->cp0_epc = epc;
			break;

		case bposge32_op:
			if (!cpu_has_dsp)
				goto sigill;

			dspcontrol = rddsp(0x01);

			if (dspcontrol >= 32) {
				epc = epc + 4 + (insn.i_format.simmediate << 2);
			} else
				epc += 8;
			regs->cp0_epc = epc;
			break;
		}
		break;

	/*
	 * These are unconditional and in j_format.
	 */
	case jal_op:
		regs->regs[31] = regs->cp0_epc + 8;
	case j_op:
		epc += 4;
		epc >>= 28;
		epc <<= 28;
		epc |= (insn.j_format.target << 2);
		regs->cp0_epc = epc;
		if (insn.i_format.opcode == jalx_op)
			set_isa16_mode(regs->cp0_epc);
		break;

	/*
	 * These are conditional and in i_format.
	 */
	case beq_op:
	case beql_op:
		if (regs->regs[insn.i_format.rs] ==
		    regs->regs[insn.i_format.rt]) {
			epc = epc + 4 + (insn.i_format.simmediate << 2);
			if (insn.i_format.opcode == beql_op)
				ret = BRANCH_LIKELY_TAKEN;
		} else
			epc += 8;
		regs->cp0_epc = epc;
		break;

	case bne_op:
	case bnel_op:
		if (regs->regs[insn.i_format.rs] !=
		    regs->regs[insn.i_format.rt]) {
			epc = epc + 4 + (insn.i_format.simmediate << 2);
			if (insn.i_format.opcode == bnel_op)
				ret = BRANCH_LIKELY_TAKEN;
		} else
			epc += 8;
		regs->cp0_epc = epc;
		break;

	case blez_op: /* not really i_format */
	case blezl_op:
		/* rt field assumed to be zero */
		if ((long)regs->regs[insn.i_format.rs] <= 0) {
			epc = epc + 4 + (insn.i_format.simmediate << 2);
			if (insn.i_format.opcode == blezl_op)
				ret = BRANCH_LIKELY_TAKEN;
		} else
			epc += 8;
		regs->cp0_epc = epc;
		break;

	case bgtz_op:
	case bgtzl_op:
		/* rt field assumed to be zero */
		if ((long)regs->regs[insn.i_format.rs] > 0) {
			epc = epc + 4 + (insn.i_format.simmediate << 2);
			if (insn.i_format.opcode == bgtzl_op)
				ret = BRANCH_LIKELY_TAKEN;
		} else
			epc += 8;
		regs->cp0_epc = epc;
		break;

	/*
	 * And now the FPA/cp1 branch instructions.
	 */
	case cop1_op:
		preempt_disable();
		if (is_fpu_owner())
		        fcr31 = read_32bit_cp1_register(CP1_STATUS);
		else
			fcr31 = current->thread.fpu.fcr31;
		preempt_enable();

		bit = (insn.i_format.rt >> 2);
		bit += (bit != 0);
		bit += 23;
		switch (insn.i_format.rt & 3) {
		case 0: /* bc1f */
		case 2: /* bc1fl */
			if (~fcr31 & (1 << bit)) {
				epc = epc + 4 + (insn.i_format.simmediate << 2);
				if (insn.i_format.rt == 2)
					ret = BRANCH_LIKELY_TAKEN;
			} else
				epc += 8;
			regs->cp0_epc = epc;
			break;

		case 1: /* bc1t */
		case 3: /* bc1tl */
			if (fcr31 & (1 << bit)) {
				epc = epc + 4 + (insn.i_format.simmediate << 2);
				if (insn.i_format.rt == 3)
					ret = BRANCH_LIKELY_TAKEN;
			} else
				epc += 8;
			regs->cp0_epc = epc;
			break;
		}
		break;
#ifdef CONFIG_CPU_CAVIUM_OCTEON
	case lwc2_op: /* This is bbit0 on Octeon */
		if ((regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt))
		     == 0)
			epc = epc + 4 + (insn.i_format.simmediate << 2);
		else
			epc += 8;
		regs->cp0_epc = epc;
		break;
	case ldc2_op: /* This is bbit032 on Octeon */
		if ((regs->regs[insn.i_format.rs] &
		    (1ull<<(insn.i_format.rt+32))) == 0)
			epc = epc + 4 + (insn.i_format.simmediate << 2);
		else
			epc += 8;
		regs->cp0_epc = epc;
		break;
	case swc2_op: /* This is bbit1 on Octeon */
		if (regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt))
			epc = epc + 4 + (insn.i_format.simmediate << 2);
		else
			epc += 8;
		regs->cp0_epc = epc;
		break;
	case sdc2_op: /* This is bbit132 on Octeon */
		if (regs->regs[insn.i_format.rs] &
		    (1ull<<(insn.i_format.rt+32)))
			epc = epc + 4 + (insn.i_format.simmediate << 2);
		else
			epc += 8;
		regs->cp0_epc = epc;
		break;
#endif
	}

	return ret;

sigill:
	printk("%s: DSP branch but not DSP ASE - sending SIGBUS.\n", current->comm);
	force_sig(SIGBUS, current);
	return -EFAULT;
}
EXPORT_SYMBOL_GPL(__compute_return_epc_for_insn);

int __compute_return_epc(struct pt_regs *regs)
{
	unsigned int __user *addr;
	long epc;
	union mips_instruction insn;

	epc = regs->cp0_epc;
	if (epc & 3)
		goto unaligned;

	/*
	 * Read the instruction
	 */
	addr = (unsigned int __user *) epc;
	if (__get_user(insn.word, addr)) {
		force_sig(SIGSEGV, current);
		return -EFAULT;
	}

	return __compute_return_epc_for_insn(regs, insn);

unaligned:
	printk("%s: unaligned epc - sending SIGBUS.\n", current->comm);
	force_sig(SIGBUS, current);
	return -EFAULT;
}
Commit	Line	Data
1da177e4 LT	1	/*
	2	* This file is subject to the terms and conditions of the GNU General Public
	3	* License. See the file "COPYING" in the main directory of this archive
	4	* for more details.
	5	*
	6	* Copyright (C) 1996, 97, 2000, 2001 by Ralf Baechle
	7	* Copyright (C) 2001 MIPS Technologies, Inc.
	8	*/
	9	#include <linux/kernel.h>
	10	#include <linux/sched.h>
	11	#include <linux/signal.h>
d8d4e3ae	12	#include <linux/module.h>
1da177e4 LT	13	#include <asm/branch.h>
	14	#include <asm/cpu.h>
	15	#include <asm/cpu-features.h>
1d74f6bc	16	#include <asm/fpu.h>
fb6883e5	17	#include <asm/fpu_emulator.h>
1da177e4 LT	18	#include <asm/inst.h>
	19	#include <asm/ptrace.h>
	20	#include <asm/uaccess.h>
	21
fb6883e5	22	/*
8508488f SH	23	* Calculate and return exception PC in case of branch delay slot
8508488f SH	24	* for microMIPS and MIPS16e. It does not clear the ISA mode bit.
fb6883e5 LY	25	*/
	26	int __isa_exception_epc(struct pt_regs *regs)
	27	{
fb6883e5	28	unsigned short inst;
8508488f	29	long epc = regs->cp0_epc;
fb6883e5 LY	30
	31	/* Calculate exception PC in branch delay slot. */
	32	if (__get_user(inst, (u16 __user *) msk_isa16_mode(epc))) {
	33	/* This should never happen because delay slot was checked. */
	34	force_sig(SIGSEGV, current);
	35	return epc;
	36	}
8508488f SH	37	if (cpu_has_mips16) {
	38	if (((union mips16e_instruction)inst).ri.opcode
	39	== MIPS16e_jal_op)
	40	epc += 4;
	41	else
	42	epc += 2;
	43	} else if (mm_insn_16bit(inst))
fb6883e5 LY	44	epc += 2;
	45	else
	46	epc += 4;
	47
	48	return epc;
	49	}
	50
76fbfc31 RB	51	/* (microMIPS) Convert 16-bit register encoding to 32-bit register encoding. */
	52	static const unsigned int reg16to32map[8] = {16, 17, 2, 3, 4, 5, 6, 7};
	53
	54	int __mm_isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
	55	unsigned long *contpc)
	56	{
	57	union mips_instruction insn = (union mips_instruction)dec_insn.insn;
	58	int bc_false = 0;
	59	unsigned int fcr31;
	60	unsigned int bit;
	61
	62	if (!cpu_has_mmips)
	63	return 0;
	64
	65	switch (insn.mm_i_format.opcode) {
	66	case mm_pool32a_op:
	67	if ((insn.mm_i_format.simmediate & MM_POOL32A_MINOR_MASK) ==
	68	mm_pool32axf_op) {
	69	switch (insn.mm_i_format.simmediate >>
	70	MM_POOL32A_MINOR_SHIFT) {
	71	case mm_jalr_op:
	72	case mm_jalrhb_op:
	73	case mm_jalrs_op:
	74	case mm_jalrshb_op:
	75	if (insn.mm_i_format.rt != 0) /* Not mm_jr */
	76	regs->regs[insn.mm_i_format.rt] =
	77	regs->cp0_epc +
	78	dec_insn.pc_inc +
	79	dec_insn.next_pc_inc;
	80	*contpc = regs->regs[insn.mm_i_format.rs];
	81	return 1;
	82	}
	83	}
	84	break;
	85	case mm_pool32i_op:
	86	switch (insn.mm_i_format.rt) {
	87	case mm_bltzals_op:
	88	case mm_bltzal_op:
	89	regs->regs[31] = regs->cp0_epc +
	90	dec_insn.pc_inc +
	91	dec_insn.next_pc_inc;
	92	/* Fall through */
	93	case mm_bltz_op:
	94	if ((long)regs->regs[insn.mm_i_format.rs] < 0)
	95	*contpc = regs->cp0_epc +
	96	dec_insn.pc_inc +
	97	(insn.mm_i_format.simmediate << 1);
	98	else
	99	*contpc = regs->cp0_epc +
	100	dec_insn.pc_inc +
	101	dec_insn.next_pc_inc;
	102	return 1;
	103	case mm_bgezals_op:
	104	case mm_bgezal_op:
	105	regs->regs[31] = regs->cp0_epc +
	106	dec_insn.pc_inc +
	107	dec_insn.next_pc_inc;
	108	/* Fall through */
	109	case mm_bgez_op:
	110	if ((long)regs->regs[insn.mm_i_format.rs] >= 0)
	111	*contpc = regs->cp0_epc +
	112	dec_insn.pc_inc +
	113	(insn.mm_i_format.simmediate << 1);
	114	else
115	*contpc = regs->cp0_epc +
116	dec_insn.pc_inc +
117	dec_insn.next_pc_inc;
118	return 1;
119	case mm_blez_op:
120	if ((long)regs->regs[insn.mm_i_format.rs] <= 0)
121	*contpc = regs->cp0_epc +
122	dec_insn.pc_inc +
123	(insn.mm_i_format.simmediate << 1);
124	else
125	*contpc = regs->cp0_epc +
126	dec_insn.pc_inc +
127	dec_insn.next_pc_inc;
128	return 1;
129	case mm_bgtz_op:
130	if ((long)regs->regs[insn.mm_i_format.rs] <= 0)
131	*contpc = regs->cp0_epc +
132	dec_insn.pc_inc +
133	(insn.mm_i_format.simmediate << 1);
134	else
135	*contpc = regs->cp0_epc +
136	dec_insn.pc_inc +
137	dec_insn.next_pc_inc;
138	return 1;
139	case mm_bc2f_op:
140	case mm_bc1f_op:
141	bc_false = 1;
142	/* Fall through */
143	case mm_bc2t_op:
144	case mm_bc1t_op:
145	preempt_disable();
146	if (is_fpu_owner())
842dfc11	147	fcr31 = read_32bit_cp1_register(CP1_STATUS);
76fbfc31 RB	148	else
	149	fcr31 = current->thread.fpu.fcr31;
	150	preempt_enable();
	151
	152	if (bc_false)
	153	fcr31 = ~fcr31;
	154
	155	bit = (insn.mm_i_format.rs >> 2);
	156	bit += (bit != 0);
	157	bit += 23;
	158	if (fcr31 & (1 << bit))
	159	*contpc = regs->cp0_epc +
	160	dec_insn.pc_inc +
	161	(insn.mm_i_format.simmediate << 1);
	162	else
	163	*contpc = regs->cp0_epc +
	164	dec_insn.pc_inc + dec_insn.next_pc_inc;
	165	return 1;
	166	}
	167	break;
	168	case mm_pool16c_op:
	169	switch (insn.mm_i_format.rt) {
	170	case mm_jalr16_op:
	171	case mm_jalrs16_op:
	172	regs->regs[31] = regs->cp0_epc +
	173	dec_insn.pc_inc + dec_insn.next_pc_inc;
	174	/* Fall through */
	175	case mm_jr16_op:
	176	*contpc = regs->regs[insn.mm_i_format.rs];
	177	return 1;
	178	}
	179	break;
	180	case mm_beqz16_op:
	181	if ((long)regs->regs[reg16to32map[insn.mm_b1_format.rs]] == 0)
	182	*contpc = regs->cp0_epc +
	183	dec_insn.pc_inc +
	184	(insn.mm_b1_format.simmediate << 1);
	185	else
	186	*contpc = regs->cp0_epc +
	187	dec_insn.pc_inc + dec_insn.next_pc_inc;
	188	return 1;
	189	case mm_bnez16_op:
	190	if ((long)regs->regs[reg16to32map[insn.mm_b1_format.rs]] != 0)
	191	*contpc = regs->cp0_epc +
	192	dec_insn.pc_inc +
	193	(insn.mm_b1_format.simmediate << 1);
	194	else
	195	*contpc = regs->cp0_epc +
	196	dec_insn.pc_inc + dec_insn.next_pc_inc;
	197	return 1;
	198	case mm_b16_op:
	199	*contpc = regs->cp0_epc + dec_insn.pc_inc +
	200	(insn.mm_b0_format.simmediate << 1);
	201	return 1;
	202	case mm_beq32_op:
	203	if (regs->regs[insn.mm_i_format.rs] ==
	204	regs->regs[insn.mm_i_format.rt])
	205	*contpc = regs->cp0_epc +
	206	dec_insn.pc_inc +
	207	(insn.mm_i_format.simmediate << 1);
	208	else
	209	*contpc = regs->cp0_epc +
	210	dec_insn.pc_inc +
	211	dec_insn.next_pc_inc;
212	return 1;
213	case mm_bne32_op:
214	if (regs->regs[insn.mm_i_format.rs] !=
215	regs->regs[insn.mm_i_format.rt])
216	*contpc = regs->cp0_epc +
217	dec_insn.pc_inc +
218	(insn.mm_i_format.simmediate << 1);
219	else
220	*contpc = regs->cp0_epc +
221	dec_insn.pc_inc + dec_insn.next_pc_inc;
222	return 1;
223	case mm_jalx32_op:
224	regs->regs[31] = regs->cp0_epc +
225	dec_insn.pc_inc + dec_insn.next_pc_inc;
226	*contpc = regs->cp0_epc + dec_insn.pc_inc;
227	*contpc >>= 28;
228	*contpc <<= 28;
229	*contpc \|= (insn.j_format.target << 2);
230	return 1;
231	case mm_jals32_op:
232	case mm_jal32_op:
233	regs->regs[31] = regs->cp0_epc +
234	dec_insn.pc_inc + dec_insn.next_pc_inc;
235	/* Fall through */
236	case mm_j32_op:
237	*contpc = regs->cp0_epc + dec_insn.pc_inc;
238	*contpc >>= 27;
239	*contpc <<= 27;
240	*contpc \|= (insn.j_format.target << 1);
241	set_isa16_mode(*contpc);
242	return 1;
243	}
244	return 0;
245	}
246
fb6883e5 LY	247	/*
	248	* Compute return address and emulate branch in microMIPS mode after an
	249	* exception only. It does not handle compact branches/jumps and cannot
	250	* be used in interrupt context. (Compact branches/jumps do not cause
	251	* exceptions.)
	252	*/
	253	int __microMIPS_compute_return_epc(struct pt_regs *regs)
	254	{
	255	u16 __user *pc16;
	256	u16 halfword;
	257	unsigned int word;
	258	unsigned long contpc;
	259	struct mm_decoded_insn mminsn = { 0 };
	260
	261	mminsn.micro_mips_mode = 1;
	262
	263	/* This load never faults. */
	264	pc16 = (unsigned short __user *)msk_isa16_mode(regs->cp0_epc);
	265	__get_user(halfword, pc16);
	266	pc16++;
	267	contpc = regs->cp0_epc + 2;
	268	word = ((unsigned int)halfword << 16);
	269	mminsn.pc_inc = 2;
	270
	271	if (!mm_insn_16bit(halfword)) {
	272	__get_user(halfword, pc16);
	273	pc16++;
	274	contpc = regs->cp0_epc + 4;
	275	mminsn.pc_inc = 4;
	276	word \|= halfword;
	277	}
	278	mminsn.insn = word;
	279
	280	if (get_user(halfword, pc16))
	281	goto sigsegv;
	282	mminsn.next_pc_inc = 2;
	283	word = ((unsigned int)halfword << 16);
	284
	285	if (!mm_insn_16bit(halfword)) {
	286	pc16++;
	287	if (get_user(halfword, pc16))
	288	goto sigsegv;
	289	mminsn.next_pc_inc = 4;
	290	word \|= halfword;
	291	}
	292	mminsn.next_insn = word;
	293
	294	mm_isBranchInstr(regs, mminsn, &contpc);
	295
	296	regs->cp0_epc = contpc;
	297
	298	return 0;
	299
	300	sigsegv:
	301	force_sig(SIGSEGV, current);
	302	return -EFAULT;
	303	}
	304
8508488f SH	305	/*
	306	* Compute return address and emulate branch in MIPS16e mode after an
	307	* exception only. It does not handle compact branches/jumps and cannot
	308	* be used in interrupt context. (Compact branches/jumps do not cause
	309	* exceptions.)
	310	*/
	311	int __MIPS16e_compute_return_epc(struct pt_regs *regs)
	312	{
	313	u16 __user *addr;
	314	union mips16e_instruction inst;
	315	u16 inst2;
	316	u32 fullinst;
	317	long epc;
	318
	319	epc = regs->cp0_epc;
	320
	321	/* Read the instruction. */
	322	addr = (u16 __user *)msk_isa16_mode(epc);
	323	if (__get_user(inst.full, addr)) {
	324	force_sig(SIGSEGV, current);
	325	return -EFAULT;
	326	}
	327
	328	switch (inst.ri.opcode) {
	329	case MIPS16e_extend_op:
	330	regs->cp0_epc += 4;
	331	return 0;
	332
	333	/*
	334	* JAL and JALX in MIPS16e mode
	335	*/
	336	case MIPS16e_jal_op:
	337	addr += 1;
	338	if (__get_user(inst2, addr)) {
	339	force_sig(SIGSEGV, current);
	340	return -EFAULT;
	341	}
	342	fullinst = ((unsigned)inst.full << 16) \| inst2;
	343	regs->regs[31] = epc + 6;
	344	epc += 4;
	345	epc >>= 28;
	346	epc <<= 28;
	347	/*
	348	* JAL:5 X:1 TARGET[20-16]:5 TARGET[25:21]:5 TARGET[15:0]:16
	349	*
	350	* ......TARGET[15:0].................TARGET[20:16]...........
	351	* ......TARGET[25:21]
	352	*/
	353	epc \|=
	354	((fullinst & 0xffff) << 2) \| ((fullinst & 0x3e00000) >> 3) \|
	355	((fullinst & 0x1f0000) << 7);
	356	if (!inst.jal.x)
	357	set_isa16_mode(epc); /* Set ISA mode bit. */
	358	regs->cp0_epc = epc;
	359	return 0;
	360
	361	/*
	362	* J(AL)R(C)
	363	*/
	364	case MIPS16e_rr_op:
	365	if (inst.rr.func == MIPS16e_jr_func) {
	366
	367	if (inst.rr.ra)
	368	regs->cp0_epc = regs->regs[31];
369	else
370	regs->cp0_epc =
371	regs->regs[reg16to32[inst.rr.rx]];
372
373	if (inst.rr.l) {
374	if (inst.rr.nd)
375	regs->regs[31] = epc + 2;
376	else
377	regs->regs[31] = epc + 4;
378	}
379	return 0;
380	}
381	break;
382	}
383
384	/*
385	* All other cases have no branch delay slot and are 16-bits.
386	* Branches do not cause an exception.
387	*/
388	regs->cp0_epc += 2;
389
390	return 0;
391	}
392
d8d4e3ae MS	393	/**
	394	* __compute_return_epc_for_insn - Computes the return address and do emulate
	395	* branch simulation, if required.
	396	*
	397	* @regs: Pointer to pt_regs
	398	* @insn: branch instruction to decode
	399	* @returns: -EFAULT on error and forces SIGBUS, and on success
	400	* returns 0 or BRANCH_LIKELY_TAKEN as appropriate after
	401	* evaluating the branch.
1da177e4	402	*/
d8d4e3ae MS	403	int __compute_return_epc_for_insn(struct pt_regs *regs,
d8d4e3ae MS	404	union mips_instruction insn)
1da177e4	405	{
5e0373b8	406	unsigned int bit, fcr31, dspcontrol;
d8d4e3ae MS	407	long epc = regs->cp0_epc;
d8d4e3ae MS	408	int ret = 0;
1da177e4	409
1da177e4 LT	410	switch (insn.i_format.opcode) {
	411	/*
	412	* jr and jalr are in r_format format.
	413	*/
	414	case spec_op:
	415	switch (insn.r_format.func) {
	416	case jalr_op:
	417	regs->regs[insn.r_format.rd] = epc + 8;
	418	/* Fall through */
	419	case jr_op:
	420	regs->cp0_epc = regs->regs[insn.r_format.rs];
	421	break;
	422	}
	423	break;
	424
	425	/*
	426	* This group contains:
	427	* bltz_op, bgez_op, bltzl_op, bgezl_op,
	428	* bltzal_op, bgezal_op, bltzall_op, bgezall_op.
	429	*/
	430	case bcond_op:
	431	switch (insn.i_format.rt) {
70342287	432	case bltz_op:
1da177e4	433	case bltzl_op:
d8d4e3ae	434	if ((long)regs->regs[insn.i_format.rs] < 0) {
1da177e4	435	epc = epc + 4 + (insn.i_format.simmediate << 2);
d8d4e3ae MS	436	if (insn.i_format.rt == bltzl_op)
	437	ret = BRANCH_LIKELY_TAKEN;
	438	} else
1da177e4 LT	439	epc += 8;
	440	regs->cp0_epc = epc;
	441	break;
	442
	443	case bgez_op:
	444	case bgezl_op:
d8d4e3ae	445	if ((long)regs->regs[insn.i_format.rs] >= 0) {
1da177e4	446	epc = epc + 4 + (insn.i_format.simmediate << 2);
d8d4e3ae MS	447	if (insn.i_format.rt == bgezl_op)
	448	ret = BRANCH_LIKELY_TAKEN;
	449	} else
1da177e4 LT	450	epc += 8;
	451	regs->cp0_epc = epc;
	452	break;
	453
	454	case bltzal_op:
	455	case bltzall_op:
	456	regs->regs[31] = epc + 8;
d8d4e3ae	457	if ((long)regs->regs[insn.i_format.rs] < 0) {
1da177e4	458	epc = epc + 4 + (insn.i_format.simmediate << 2);
d8d4e3ae MS	459	if (insn.i_format.rt == bltzall_op)
	460	ret = BRANCH_LIKELY_TAKEN;
	461	} else
1da177e4 LT	462	epc += 8;
	463	regs->cp0_epc = epc;
	464	break;
	465
	466	case bgezal_op:
	467	case bgezall_op:
	468	regs->regs[31] = epc + 8;
d8d4e3ae	469	if ((long)regs->regs[insn.i_format.rs] >= 0) {
1da177e4	470	epc = epc + 4 + (insn.i_format.simmediate << 2);
d8d4e3ae MS	471	if (insn.i_format.rt == bgezall_op)
	472	ret = BRANCH_LIKELY_TAKEN;
	473	} else
1da177e4 LT	474	epc += 8;
	475	regs->cp0_epc = epc;
	476	break;
d8d4e3ae	477
e50c0a8f RB	478	case bposge32_op:
	479	if (!cpu_has_dsp)
	480	goto sigill;
	481
	482	dspcontrol = rddsp(0x01);
	483
	484	if (dspcontrol >= 32) {
	485	epc = epc + 4 + (insn.i_format.simmediate << 2);
	486	} else
	487	epc += 8;
	488	regs->cp0_epc = epc;
	489	break;
1da177e4 LT	490	}
	491	break;
	492
	493	/*
	494	* These are unconditional and in j_format.
	495	*/
	496	case jal_op:
	497	regs->regs[31] = regs->cp0_epc + 8;
	498	case j_op:
	499	epc += 4;
	500	epc >>= 28;
	501	epc <<= 28;
	502	epc \|= (insn.j_format.target << 2);
	503	regs->cp0_epc = epc;
fb6883e5 LY	504	if (insn.i_format.opcode == jalx_op)
fb6883e5 LY	505	set_isa16_mode(regs->cp0_epc);
1da177e4 LT	506	break;
	507
	508	/*
	509	* These are conditional and in i_format.
	510	*/
	511	case beq_op:
	512	case beql_op:
	513	if (regs->regs[insn.i_format.rs] ==
d8d4e3ae	514	regs->regs[insn.i_format.rt]) {
1da177e4	515	epc = epc + 4 + (insn.i_format.simmediate << 2);
41ca86e8	516	if (insn.i_format.opcode == beql_op)
d8d4e3ae MS	517	ret = BRANCH_LIKELY_TAKEN;
d8d4e3ae MS	518	} else
1da177e4 LT	519	epc += 8;
	520	regs->cp0_epc = epc;
	521	break;
	522
	523	case bne_op:
	524	case bnel_op:
	525	if (regs->regs[insn.i_format.rs] !=
d8d4e3ae	526	regs->regs[insn.i_format.rt]) {
1da177e4	527	epc = epc + 4 + (insn.i_format.simmediate << 2);
41ca86e8	528	if (insn.i_format.opcode == bnel_op)
d8d4e3ae MS	529	ret = BRANCH_LIKELY_TAKEN;
d8d4e3ae MS	530	} else
1da177e4 LT	531	epc += 8;
	532	regs->cp0_epc = epc;
	533	break;
	534
	535	case blez_op: /* not really i_format */
	536	case blezl_op:
	537	/* rt field assumed to be zero */
d8d4e3ae	538	if ((long)regs->regs[insn.i_format.rs] <= 0) {
1da177e4	539	epc = epc + 4 + (insn.i_format.simmediate << 2);
41ca86e8	540	if (insn.i_format.opcode == blezl_op)
d8d4e3ae MS	541	ret = BRANCH_LIKELY_TAKEN;
d8d4e3ae MS	542	} else
1da177e4 LT	543	epc += 8;
	544	regs->cp0_epc = epc;
	545	break;
	546
	547	case bgtz_op:
	548	case bgtzl_op:
	549	/* rt field assumed to be zero */
d8d4e3ae	550	if ((long)regs->regs[insn.i_format.rs] > 0) {
1da177e4	551	epc = epc + 4 + (insn.i_format.simmediate << 2);
41ca86e8	552	if (insn.i_format.opcode == bgtzl_op)
d8d4e3ae MS	553	ret = BRANCH_LIKELY_TAKEN;
d8d4e3ae MS	554	} else
1da177e4 LT	555	epc += 8;
	556	regs->cp0_epc = epc;
	557	break;
	558
	559	/*
	560	* And now the FPA/cp1 branch instructions.
	561	*/
	562	case cop1_op:
1d74f6bc RB	563	preempt_disable();
1d74f6bc RB	564	if (is_fpu_owner())
842dfc11	565	fcr31 = read_32bit_cp1_register(CP1_STATUS);
1d74f6bc	566	else
eae89076	567	fcr31 = current->thread.fpu.fcr31;
1d74f6bc RB	568	preempt_enable();
1d74f6bc RB	569
1da177e4 LT	570	bit = (insn.i_format.rt >> 2);
	571	bit += (bit != 0);
	572	bit += 23;
ee1cca1b	573	switch (insn.i_format.rt & 3) {
70342287 RB	574	case 0: /* bc1f */
70342287 RB	575	case 2: /* bc1fl */
d8d4e3ae	576	if (~fcr31 & (1 << bit)) {
1da177e4	577	epc = epc + 4 + (insn.i_format.simmediate << 2);
d8d4e3ae MS	578	if (insn.i_format.rt == 2)
	579	ret = BRANCH_LIKELY_TAKEN;
	580	} else
1da177e4 LT	581	epc += 8;
	582	regs->cp0_epc = epc;
	583	break;
	584
70342287 RB	585	case 1: /* bc1t */
70342287 RB	586	case 3: /* bc1tl */
d8d4e3ae	587	if (fcr31 & (1 << bit)) {
1da177e4	588	epc = epc + 4 + (insn.i_format.simmediate << 2);
d8d4e3ae MS	589	if (insn.i_format.rt == 3)
	590	ret = BRANCH_LIKELY_TAKEN;
	591	} else
1da177e4 LT	592	epc += 8;
	593	regs->cp0_epc = epc;
	594	break;
	595	}
	596	break;
126336f0 DD	597	#ifdef CONFIG_CPU_CAVIUM_OCTEON
	598	case lwc2_op: /* This is bbit0 on Octeon */
	599	if ((regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt))
	600	== 0)
	601	epc = epc + 4 + (insn.i_format.simmediate << 2);
	602	else
	603	epc += 8;
	604	regs->cp0_epc = epc;
	605	break;
	606	case ldc2_op: /* This is bbit032 on Octeon */
	607	if ((regs->regs[insn.i_format.rs] &
	608	(1ull<<(insn.i_format.rt+32))) == 0)
	609	epc = epc + 4 + (insn.i_format.simmediate << 2);
	610	else
	611	epc += 8;
	612	regs->cp0_epc = epc;
	613	break;
	614	case swc2_op: /* This is bbit1 on Octeon */
	615	if (regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt))
	616	epc = epc + 4 + (insn.i_format.simmediate << 2);
	617	else
	618	epc += 8;
	619	regs->cp0_epc = epc;
	620	break;
	621	case sdc2_op: /* This is bbit132 on Octeon */
	622	if (regs->regs[insn.i_format.rs] &
	623	(1ull<<(insn.i_format.rt+32)))
	624	epc = epc + 4 + (insn.i_format.simmediate << 2);
	625	else
	626	epc += 8;
	627	regs->cp0_epc = epc;
	628	break;
	629	#endif
1da177e4 LT	630	}
1da177e4 LT	631
d8d4e3ae	632	return ret;
1da177e4	633
d8d4e3ae MS	634	sigill:
d8d4e3ae MS	635	printk("%s: DSP branch but not DSP ASE - sending SIGBUS.\n", current->comm);
1da177e4 LT	636	force_sig(SIGBUS, current);
1da177e4 LT	637	return -EFAULT;
d8d4e3ae MS	638	}
d8d4e3ae MS	639	EXPORT_SYMBOL_GPL(__compute_return_epc_for_insn);
e50c0a8f	640
d8d4e3ae MS	641	int __compute_return_epc(struct pt_regs *regs)
	642	{
	643	unsigned int __user *addr;
	644	long epc;
	645	union mips_instruction insn;
	646
	647	epc = regs->cp0_epc;
	648	if (epc & 3)
	649	goto unaligned;
	650
	651	/*
	652	* Read the instruction
	653	*/
	654	addr = (unsigned int __user *) epc;
	655	if (__get_user(insn.word, addr)) {
	656	force_sig(SIGSEGV, current);
	657	return -EFAULT;
	658	}
	659
	660	return __compute_return_epc_for_insn(regs, insn);
	661
	662	unaligned:
	663	printk("%s: unaligned epc - sending SIGBUS.\n", current->comm);
e50c0a8f RB	664	force_sig(SIGBUS, current);
e50c0a8f RB	665	return -EFAULT;
1da177e4	666	}