[mirror_ubuntu-zesty-kernel.git] / arch / mips / kernel / cevt-gt641xx.c

/*
 *  GT641xx clockevent routines.
 *
 *  Copyright (C) 2007  Yoichi Yuasa <yuasa@linux-mips.org>
 *
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License as published by
 *  the Free Software Foundation; either version 2 of the License, or
 *  (at your option) any later version.
 *
 *  This program is distributed in the hope that it will be useful,
 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *  GNU General Public License for more details.
 *
 *  You should have received a copy of the GNU General Public License
 *  along with this program; if not, write to the Free Software
 *  Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
 */
#include <linux/clockchips.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/spinlock.h>

#include <asm/gt64120.h>
#include <asm/time.h>

static DEFINE_SPINLOCK(gt641xx_timer_lock);
static unsigned int gt641xx_base_clock;

void gt641xx_set_base_clock(unsigned int clock)
{
	gt641xx_base_clock = clock;
}

int gt641xx_timer0_state(void)
{
	if (GT_READ(GT_TC0_OFS))
		return 0;

	GT_WRITE(GT_TC0_OFS, gt641xx_base_clock / HZ);
	GT_WRITE(GT_TC_CONTROL_OFS, GT_TC_CONTROL_ENTC0_MSK);

	return 1;
}

static int gt641xx_timer0_set_next_event(unsigned long delta,
					 struct clock_event_device *evt)
{
	u32 ctrl;

	spin_lock(&gt641xx_timer_lock);

	ctrl = GT_READ(GT_TC_CONTROL_OFS);
	ctrl &= ~(GT_TC_CONTROL_ENTC0_MSK | GT_TC_CONTROL_SELTC0_MSK);
	ctrl |= GT_TC_CONTROL_ENTC0_MSK;

	GT_WRITE(GT_TC0_OFS, delta);
	GT_WRITE(GT_TC_CONTROL_OFS, ctrl);

	spin_unlock(&gt641xx_timer_lock);

	return 0;
}

static void gt641xx_timer0_set_mode(enum clock_event_mode mode,
				    struct clock_event_device *evt)
{
	u32 ctrl;

	spin_lock(&gt641xx_timer_lock);

	ctrl = GT_READ(GT_TC_CONTROL_OFS);
	ctrl &= ~(GT_TC_CONTROL_ENTC0_MSK | GT_TC_CONTROL_SELTC0_MSK);

	switch (mode) {
	case CLOCK_EVT_MODE_PERIODIC:
		ctrl |= GT_TC_CONTROL_ENTC0_MSK | GT_TC_CONTROL_SELTC0_MSK;
		break;
	case CLOCK_EVT_MODE_ONESHOT:
		ctrl |= GT_TC_CONTROL_ENTC0_MSK;
		break;
	default:
		break;
	}

	GT_WRITE(GT_TC_CONTROL_OFS, ctrl);

	spin_unlock(&gt641xx_timer_lock);
}

static void gt641xx_timer0_event_handler(struct clock_event_device *dev)
{
}

static struct clock_event_device gt641xx_timer0_clockevent = {
	.name		= "gt641xx-timer0",
	.features	= CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
	.irq		= GT641XX_TIMER0_IRQ,
	.set_next_event	= gt641xx_timer0_set_next_event,
	.set_mode	= gt641xx_timer0_set_mode,
	.event_handler	= gt641xx_timer0_event_handler,
};

static irqreturn_t gt641xx_timer0_interrupt(int irq, void *dev_id)
{
	struct clock_event_device *cd = &gt641xx_timer0_clockevent;

	cd->event_handler(cd);

	return IRQ_HANDLED;
}

static struct irqaction gt641xx_timer0_irqaction = {
	.handler	= gt641xx_timer0_interrupt,
	.flags		= IRQF_DISABLED | IRQF_PERCPU | IRQF_TIMER,
	.name		= "gt641xx_timer0",
};

static int __init gt641xx_timer0_clockevent_init(void)
{
	struct clock_event_device *cd;

	if (!gt641xx_base_clock)
		return 0;

	GT_WRITE(GT_TC0_OFS, gt641xx_base_clock / HZ);

	cd = &gt641xx_timer0_clockevent;
	cd->rating = 200 + gt641xx_base_clock / 10000000;
	clockevent_set_clock(cd, gt641xx_base_clock);
	cd->max_delta_ns = clockevent_delta2ns(0x7fffffff, cd);
	cd->min_delta_ns = clockevent_delta2ns(0x300, cd);
	cd->cpumask = cpumask_of(0);

	clockevents_register_device(&gt641xx_timer0_clockevent);

	return setup_irq(GT641XX_TIMER0_IRQ, &gt641xx_timer0_irqaction);
}
arch_initcall(gt641xx_timer0_clockevent_init);
Commit	Line	Data
1097c6ac YY	1	/*
	2	* GT641xx clockevent routines.
	3	*
ada8e951	4	* Copyright (C) 2007 Yoichi Yuasa <yuasa@linux-mips.org>
1097c6ac YY	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License, or
	9	* (at your option) any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program; if not, write to the Free Software
	18	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
	19	*/
	20	#include <linux/clockchips.h>
	21	#include <linux/init.h>
	22	#include <linux/interrupt.h>
	23	#include <linux/spinlock.h>
	24
	25	#include <asm/gt64120.h>
	26	#include <asm/time.h>
	27
1097c6ac YY	28	static DEFINE_SPINLOCK(gt641xx_timer_lock);
	29	static unsigned int gt641xx_base_clock;
	30
	31	void gt641xx_set_base_clock(unsigned int clock)
	32	{
	33	gt641xx_base_clock = clock;
	34	}
	35
	36	int gt641xx_timer0_state(void)
	37	{
	38	if (GT_READ(GT_TC0_OFS))
	39	return 0;
	40
	41	GT_WRITE(GT_TC0_OFS, gt641xx_base_clock / HZ);
	42	GT_WRITE(GT_TC_CONTROL_OFS, GT_TC_CONTROL_ENTC0_MSK);
	43
	44	return 1;
	45	}
	46
	47	static int gt641xx_timer0_set_next_event(unsigned long delta,
	48	struct clock_event_device *evt)
	49	{
1097c6ac YY	50	u32 ctrl;
1097c6ac YY	51
c984c878	52	spin_lock(&gt641xx_timer_lock);
1097c6ac YY	53
	54	ctrl = GT_READ(GT_TC_CONTROL_OFS);
	55	ctrl &= ~(GT_TC_CONTROL_ENTC0_MSK \| GT_TC_CONTROL_SELTC0_MSK);
	56	ctrl \|= GT_TC_CONTROL_ENTC0_MSK;
	57
	58	GT_WRITE(GT_TC0_OFS, delta);
	59	GT_WRITE(GT_TC_CONTROL_OFS, ctrl);
	60
c984c878	61	spin_unlock(&gt641xx_timer_lock);
1097c6ac YY	62
	63	return 0;
	64	}
	65
	66	static void gt641xx_timer0_set_mode(enum clock_event_mode mode,
	67	struct clock_event_device *evt)
	68	{
1097c6ac YY	69	u32 ctrl;
1097c6ac YY	70
c984c878	71	spin_lock(&gt641xx_timer_lock);
1097c6ac YY	72
	73	ctrl = GT_READ(GT_TC_CONTROL_OFS);
	74	ctrl &= ~(GT_TC_CONTROL_ENTC0_MSK \| GT_TC_CONTROL_SELTC0_MSK);
	75
	76	switch (mode) {
	77	case CLOCK_EVT_MODE_PERIODIC:
	78	ctrl \|= GT_TC_CONTROL_ENTC0_MSK \| GT_TC_CONTROL_SELTC0_MSK;
	79	break;
	80	case CLOCK_EVT_MODE_ONESHOT:
	81	ctrl \|= GT_TC_CONTROL_ENTC0_MSK;
	82	break;
	83	default:
	84	break;
	85	}
	86
	87	GT_WRITE(GT_TC_CONTROL_OFS, ctrl);
	88
c984c878	89	spin_unlock(&gt641xx_timer_lock);
1097c6ac YY	90	}
	91
	92	static void gt641xx_timer0_event_handler(struct clock_event_device *dev)
	93	{
	94	}
	95
	96	static struct clock_event_device gt641xx_timer0_clockevent = {
	97	.name = "gt641xx-timer0",
	98	.features = CLOCK_EVT_FEAT_PERIODIC \| CLOCK_EVT_FEAT_ONESHOT,
1097c6ac YY	99	.irq = GT641XX_TIMER0_IRQ,
	100	.set_next_event = gt641xx_timer0_set_next_event,
	101	.set_mode = gt641xx_timer0_set_mode,
	102	.event_handler = gt641xx_timer0_event_handler,
	103	};
	104
	105	static irqreturn_t gt641xx_timer0_interrupt(int irq, void *dev_id)
	106	{
	107	struct clock_event_device *cd = &gt641xx_timer0_clockevent;
	108
	109	cd->event_handler(cd);
	110
	111	return IRQ_HANDLED;
	112	}
	113
	114	static struct irqaction gt641xx_timer0_irqaction = {
	115	.handler = gt641xx_timer0_interrupt,
f45e5183	116	.flags = IRQF_DISABLED \| IRQF_PERCPU \| IRQF_TIMER,
1097c6ac YY	117	.name = "gt641xx_timer0",
	118	};
	119
	120	static int __init gt641xx_timer0_clockevent_init(void)
	121	{
	122	struct clock_event_device *cd;
	123
	124	if (!gt641xx_base_clock)
	125	return 0;
	126
	127	GT_WRITE(GT_TC0_OFS, gt641xx_base_clock / HZ);
	128
	129	cd = &gt641xx_timer0_clockevent;
	130	cd->rating = 200 + gt641xx_base_clock / 10000000;
11c03a6f	131	clockevent_set_clock(cd, gt641xx_base_clock);
1097c6ac YY	132	cd->max_delta_ns = clockevent_delta2ns(0x7fffffff, cd);
1097c6ac YY	133	cd->min_delta_ns = clockevent_delta2ns(0x300, cd);
320ab2b0	134	cd->cpumask = cpumask_of(0);
1097c6ac YY	135
	136	clockevents_register_device(&gt641xx_timer0_clockevent);
	137
	138	return setup_irq(GT641XX_TIMER0_IRQ, &gt641xx_timer0_irqaction);
	139	}
	140	arch_initcall(gt641xx_timer0_clockevent_init);