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0ee958e1 PB |
1 | /* |
2 | * Copyright (C) 2013 Imagination Technologies | |
3 | * Author: Paul Burton <paul.burton@imgtec.com> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms of the GNU General Public License as published by the | |
7 | * Free Software Foundation; either version 2 of the License, or (at your | |
8 | * option) any later version. | |
9 | */ | |
10 | ||
11 | #include <asm/addrspace.h> | |
12 | #include <asm/asm.h> | |
13 | #include <asm/asm-offsets.h> | |
14 | #include <asm/asmmacro.h> | |
15 | #include <asm/cacheops.h> | |
6521d9a4 | 16 | #include <asm/eva.h> |
0ee958e1 | 17 | #include <asm/mipsregs.h> |
245a7868 | 18 | #include <asm/mipsmtregs.h> |
3179d37e | 19 | #include <asm/pm.h> |
0ee958e1 | 20 | |
245a7868 PB |
21 | #define GCR_CL_COHERENCE_OFS 0x2008 |
22 | #define GCR_CL_ID_OFS 0x2028 | |
23 | ||
24 | .extern mips_cm_base | |
25 | ||
26 | .set noreorder | |
27 | ||
28 | /* | |
29 | * Set dest to non-zero if the core supports the MT ASE, else zero. If | |
30 | * MT is not supported then branch to nomt. | |
31 | */ | |
32 | .macro has_mt dest, nomt | |
33 | mfc0 \dest, CP0_CONFIG | |
34 | bgez \dest, \nomt | |
35 | mfc0 \dest, CP0_CONFIG, 1 | |
36 | bgez \dest, \nomt | |
37 | mfc0 \dest, CP0_CONFIG, 2 | |
38 | bgez \dest, \nomt | |
39 | mfc0 \dest, CP0_CONFIG, 3 | |
40 | andi \dest, \dest, MIPS_CONF3_MT | |
41 | beqz \dest, \nomt | |
1e5fb282 | 42 | nop |
245a7868 | 43 | .endm |
0ee958e1 PB |
44 | |
45 | .section .text.cps-vec | |
46 | .balign 0x1000 | |
0ee958e1 PB |
47 | |
48 | LEAF(mips_cps_core_entry) | |
49 | /* | |
0155a065 PB |
50 | * These first 12 bytes will be patched by cps_smp_setup to load the |
51 | * base address of the CM GCRs into register v1 and the CCA to use into | |
52 | * register s0. | |
0ee958e1 PB |
53 | */ |
54 | .quad 0 | |
0155a065 | 55 | .word 0 |
0ee958e1 PB |
56 | |
57 | /* Check whether we're here due to an NMI */ | |
58 | mfc0 k0, CP0_STATUS | |
59 | and k0, k0, ST0_NMI | |
60 | beqz k0, not_nmi | |
61 | nop | |
62 | ||
63 | /* This is an NMI */ | |
81a02e34 | 64 | PTR_LA k0, nmi_handler |
0ee958e1 PB |
65 | jr k0 |
66 | nop | |
67 | ||
68 | not_nmi: | |
69 | /* Setup Cause */ | |
70 | li t0, CAUSEF_IV | |
71 | mtc0 t0, CP0_CAUSE | |
72 | ||
73 | /* Setup Status */ | |
74 | li t0, ST0_CU1 | ST0_CU0 | |
75 | mtc0 t0, CP0_STATUS | |
76 | ||
77 | /* | |
78 | * Clear the bits used to index the caches. Note that the architecture | |
79 | * dictates that writing to any of TagLo or TagHi selects 0 or 2 should | |
80 | * be valid for all MIPS32 CPUs, even those for which said writes are | |
81 | * unnecessary. | |
82 | */ | |
83 | mtc0 zero, CP0_TAGLO, 0 | |
84 | mtc0 zero, CP0_TAGHI, 0 | |
85 | mtc0 zero, CP0_TAGLO, 2 | |
86 | mtc0 zero, CP0_TAGHI, 2 | |
87 | ehb | |
88 | ||
89 | /* Primary cache configuration is indicated by Config1 */ | |
90 | mfc0 v0, CP0_CONFIG, 1 | |
91 | ||
92 | /* Detect I-cache line size */ | |
93 | _EXT t0, v0, MIPS_CONF1_IL_SHF, MIPS_CONF1_IL_SZ | |
94 | beqz t0, icache_done | |
95 | li t1, 2 | |
96 | sllv t0, t1, t0 | |
97 | ||
98 | /* Detect I-cache size */ | |
99 | _EXT t1, v0, MIPS_CONF1_IS_SHF, MIPS_CONF1_IS_SZ | |
100 | xori t2, t1, 0x7 | |
101 | beqz t2, 1f | |
102 | li t3, 32 | |
acac4108 | 103 | addiu t1, t1, 1 |
0ee958e1 PB |
104 | sllv t1, t3, t1 |
105 | 1: /* At this point t1 == I-cache sets per way */ | |
106 | _EXT t2, v0, MIPS_CONF1_IA_SHF, MIPS_CONF1_IA_SZ | |
acac4108 | 107 | addiu t2, t2, 1 |
0ee958e1 PB |
108 | mul t1, t1, t0 |
109 | mul t1, t1, t2 | |
110 | ||
717f1425 | 111 | li a0, CKSEG0 |
b677bc03 | 112 | PTR_ADD a1, a0, t1 |
0ee958e1 | 113 | 1: cache Index_Store_Tag_I, 0(a0) |
b677bc03 | 114 | PTR_ADD a0, a0, t0 |
0ee958e1 PB |
115 | bne a0, a1, 1b |
116 | nop | |
117 | icache_done: | |
118 | ||
119 | /* Detect D-cache line size */ | |
120 | _EXT t0, v0, MIPS_CONF1_DL_SHF, MIPS_CONF1_DL_SZ | |
121 | beqz t0, dcache_done | |
122 | li t1, 2 | |
123 | sllv t0, t1, t0 | |
124 | ||
125 | /* Detect D-cache size */ | |
126 | _EXT t1, v0, MIPS_CONF1_DS_SHF, MIPS_CONF1_DS_SZ | |
127 | xori t2, t1, 0x7 | |
128 | beqz t2, 1f | |
129 | li t3, 32 | |
acac4108 | 130 | addiu t1, t1, 1 |
0ee958e1 PB |
131 | sllv t1, t3, t1 |
132 | 1: /* At this point t1 == D-cache sets per way */ | |
133 | _EXT t2, v0, MIPS_CONF1_DA_SHF, MIPS_CONF1_DA_SZ | |
acac4108 | 134 | addiu t2, t2, 1 |
0ee958e1 PB |
135 | mul t1, t1, t0 |
136 | mul t1, t1, t2 | |
137 | ||
717f1425 | 138 | li a0, CKSEG0 |
b677bc03 MC |
139 | PTR_ADDU a1, a0, t1 |
140 | PTR_SUBU a1, a1, t0 | |
0ee958e1 PB |
141 | 1: cache Index_Store_Tag_D, 0(a0) |
142 | bne a0, a1, 1b | |
b677bc03 | 143 | PTR_ADD a0, a0, t0 |
0ee958e1 PB |
144 | dcache_done: |
145 | ||
0155a065 | 146 | /* Set Kseg0 CCA to that in s0 */ |
0ee958e1 PB |
147 | mfc0 t0, CP0_CONFIG |
148 | ori t0, 0x7 | |
0155a065 PB |
149 | xori t0, 0x7 |
150 | or t0, t0, s0 | |
0ee958e1 PB |
151 | mtc0 t0, CP0_CONFIG |
152 | ehb | |
153 | ||
154 | /* Enter the coherent domain */ | |
155 | li t0, 0xff | |
90996511 | 156 | sw t0, GCR_CL_COHERENCE_OFS(v1) |
0ee958e1 PB |
157 | ehb |
158 | ||
159 | /* Jump to kseg0 */ | |
81a02e34 | 160 | PTR_LA t0, 1f |
0ee958e1 PB |
161 | jr t0 |
162 | nop | |
163 | ||
245a7868 PB |
164 | /* |
165 | * We're up, cached & coherent. Perform any further required core-level | |
166 | * initialisation. | |
167 | */ | |
168 | 1: jal mips_cps_core_init | |
169 | nop | |
0ee958e1 | 170 | |
6521d9a4 MC |
171 | /* Do any EVA initialization if necessary */ |
172 | eva_init | |
173 | ||
0ee958e1 | 174 | /* |
245a7868 PB |
175 | * Boot any other VPEs within this core that should be online, and |
176 | * deactivate this VPE if it should be offline. | |
0ee958e1 | 177 | */ |
245a7868 PB |
178 | jal mips_cps_boot_vpes |
179 | nop | |
0ee958e1 PB |
180 | |
181 | /* Off we go! */ | |
b677bc03 MC |
182 | PTR_L t1, VPEBOOTCFG_PC(v0) |
183 | PTR_L gp, VPEBOOTCFG_GP(v0) | |
184 | PTR_L sp, VPEBOOTCFG_SP(v0) | |
0ee958e1 PB |
185 | jr t1 |
186 | nop | |
187 | END(mips_cps_core_entry) | |
188 | ||
189 | .org 0x200 | |
190 | LEAF(excep_tlbfill) | |
191 | b . | |
192 | nop | |
193 | END(excep_tlbfill) | |
194 | ||
195 | .org 0x280 | |
196 | LEAF(excep_xtlbfill) | |
197 | b . | |
198 | nop | |
199 | END(excep_xtlbfill) | |
200 | ||
201 | .org 0x300 | |
202 | LEAF(excep_cache) | |
203 | b . | |
204 | nop | |
205 | END(excep_cache) | |
206 | ||
207 | .org 0x380 | |
208 | LEAF(excep_genex) | |
209 | b . | |
210 | nop | |
211 | END(excep_genex) | |
212 | ||
213 | .org 0x400 | |
214 | LEAF(excep_intex) | |
215 | b . | |
216 | nop | |
217 | END(excep_intex) | |
218 | ||
219 | .org 0x480 | |
220 | LEAF(excep_ejtag) | |
81a02e34 | 221 | PTR_LA k0, ejtag_debug_handler |
0ee958e1 PB |
222 | jr k0 |
223 | nop | |
224 | END(excep_ejtag) | |
245a7868 PB |
225 | |
226 | LEAF(mips_cps_core_init) | |
227 | #ifdef CONFIG_MIPS_MT | |
228 | /* Check that the core implements the MT ASE */ | |
229 | has_mt t0, 3f | |
245a7868 PB |
230 | |
231 | .set push | |
977e043d | 232 | .set mips64r2 |
245a7868 PB |
233 | .set mt |
234 | ||
235 | /* Only allow 1 TC per VPE to execute... */ | |
236 | dmt | |
237 | ||
238 | /* ...and for the moment only 1 VPE */ | |
239 | dvpe | |
81a02e34 | 240 | PTR_LA t1, 1f |
245a7868 PB |
241 | jr.hb t1 |
242 | nop | |
243 | ||
244 | /* Enter VPE configuration state */ | |
245 | 1: mfc0 t0, CP0_MVPCONTROL | |
246 | ori t0, t0, MVPCONTROL_VPC | |
247 | mtc0 t0, CP0_MVPCONTROL | |
248 | ||
249 | /* Retrieve the number of VPEs within the core */ | |
250 | mfc0 t0, CP0_MVPCONF0 | |
251 | srl t0, t0, MVPCONF0_PVPE_SHIFT | |
252 | andi t0, t0, (MVPCONF0_PVPE >> MVPCONF0_PVPE_SHIFT) | |
0586ac75 | 253 | addiu ta3, t0, 1 |
245a7868 PB |
254 | |
255 | /* If there's only 1, we're done */ | |
256 | beqz t0, 2f | |
257 | nop | |
258 | ||
259 | /* Loop through each VPE within this core */ | |
0586ac75 | 260 | li ta1, 1 |
245a7868 PB |
261 | |
262 | 1: /* Operate on the appropriate TC */ | |
0586ac75 | 263 | mtc0 ta1, CP0_VPECONTROL |
245a7868 PB |
264 | ehb |
265 | ||
266 | /* Bind TC to VPE (1:1 TC:VPE mapping) */ | |
0586ac75 | 267 | mttc0 ta1, CP0_TCBIND |
245a7868 PB |
268 | |
269 | /* Set exclusive TC, non-active, master */ | |
270 | li t0, VPECONF0_MVP | |
0586ac75 | 271 | sll t1, ta1, VPECONF0_XTC_SHIFT |
245a7868 PB |
272 | or t0, t0, t1 |
273 | mttc0 t0, CP0_VPECONF0 | |
274 | ||
275 | /* Set TC non-active, non-allocatable */ | |
276 | mttc0 zero, CP0_TCSTATUS | |
277 | ||
278 | /* Set TC halted */ | |
279 | li t0, TCHALT_H | |
280 | mttc0 t0, CP0_TCHALT | |
281 | ||
282 | /* Next VPE */ | |
0586ac75 MC |
283 | addiu ta1, ta1, 1 |
284 | slt t0, ta1, ta3 | |
245a7868 PB |
285 | bnez t0, 1b |
286 | nop | |
287 | ||
288 | /* Leave VPE configuration state */ | |
289 | 2: mfc0 t0, CP0_MVPCONTROL | |
290 | xori t0, t0, MVPCONTROL_VPC | |
291 | mtc0 t0, CP0_MVPCONTROL | |
292 | ||
293 | 3: .set pop | |
294 | #endif | |
295 | jr ra | |
296 | nop | |
297 | END(mips_cps_core_init) | |
298 | ||
299 | LEAF(mips_cps_boot_vpes) | |
300 | /* Retrieve CM base address */ | |
81a02e34 | 301 | PTR_LA t0, mips_cm_base |
b677bc03 | 302 | PTR_L t0, 0(t0) |
245a7868 PB |
303 | |
304 | /* Calculate a pointer to this cores struct core_boot_config */ | |
90996511 | 305 | lw t0, GCR_CL_ID_OFS(t0) |
245a7868 PB |
306 | li t1, COREBOOTCFG_SIZE |
307 | mul t0, t0, t1 | |
81a02e34 | 308 | PTR_LA t1, mips_cps_core_bootcfg |
b677bc03 MC |
309 | PTR_L t1, 0(t1) |
310 | PTR_ADDU t0, t0, t1 | |
245a7868 PB |
311 | |
312 | /* Calculate this VPEs ID. If the core doesn't support MT use 0 */ | |
1e5fb282 | 313 | li t9, 0 |
0586ac75 | 314 | has_mt ta2, 1f |
245a7868 PB |
315 | |
316 | /* Find the number of VPEs present in the core */ | |
317 | mfc0 t1, CP0_MVPCONF0 | |
318 | srl t1, t1, MVPCONF0_PVPE_SHIFT | |
319 | andi t1, t1, MVPCONF0_PVPE >> MVPCONF0_PVPE_SHIFT | |
acac4108 | 320 | addiu t1, t1, 1 |
245a7868 PB |
321 | |
322 | /* Calculate a mask for the VPE ID from EBase.CPUNum */ | |
323 | clz t1, t1 | |
324 | li t2, 31 | |
325 | subu t1, t2, t1 | |
326 | li t2, 1 | |
327 | sll t1, t2, t1 | |
328 | addiu t1, t1, -1 | |
329 | ||
330 | /* Retrieve the VPE ID from EBase.CPUNum */ | |
331 | mfc0 t9, $15, 1 | |
332 | and t9, t9, t1 | |
333 | ||
334 | 1: /* Calculate a pointer to this VPEs struct vpe_boot_config */ | |
335 | li t1, VPEBOOTCFG_SIZE | |
336 | mul v0, t9, t1 | |
b677bc03 MC |
337 | PTR_L ta3, COREBOOTCFG_VPECONFIG(t0) |
338 | PTR_ADDU v0, v0, ta3 | |
245a7868 PB |
339 | |
340 | #ifdef CONFIG_MIPS_MT | |
341 | ||
342 | /* If the core doesn't support MT then return */ | |
0586ac75 | 343 | bnez ta2, 1f |
245a7868 PB |
344 | nop |
345 | jr ra | |
346 | nop | |
347 | ||
348 | .set push | |
977e043d | 349 | .set mips64r2 |
245a7868 PB |
350 | .set mt |
351 | ||
352 | 1: /* Enter VPE configuration state */ | |
353 | dvpe | |
81a02e34 | 354 | PTR_LA t1, 1f |
245a7868 PB |
355 | jr.hb t1 |
356 | nop | |
357 | 1: mfc0 t1, CP0_MVPCONTROL | |
358 | ori t1, t1, MVPCONTROL_VPC | |
359 | mtc0 t1, CP0_MVPCONTROL | |
360 | ehb | |
361 | ||
362 | /* Loop through each VPE */ | |
b677bc03 | 363 | PTR_L ta2, COREBOOTCFG_VPEMASK(t0) |
0586ac75 MC |
364 | move t8, ta2 |
365 | li ta1, 0 | |
245a7868 PB |
366 | |
367 | /* Check whether the VPE should be running. If not, skip it */ | |
0586ac75 | 368 | 1: andi t0, ta2, 1 |
245a7868 PB |
369 | beqz t0, 2f |
370 | nop | |
371 | ||
372 | /* Operate on the appropriate TC */ | |
373 | mfc0 t0, CP0_VPECONTROL | |
374 | ori t0, t0, VPECONTROL_TARGTC | |
375 | xori t0, t0, VPECONTROL_TARGTC | |
0586ac75 | 376 | or t0, t0, ta1 |
245a7868 PB |
377 | mtc0 t0, CP0_VPECONTROL |
378 | ehb | |
379 | ||
380 | /* Skip the VPE if its TC is not halted */ | |
381 | mftc0 t0, CP0_TCHALT | |
382 | beqz t0, 2f | |
383 | nop | |
384 | ||
385 | /* Calculate a pointer to the VPEs struct vpe_boot_config */ | |
386 | li t0, VPEBOOTCFG_SIZE | |
0586ac75 MC |
387 | mul t0, t0, ta1 |
388 | addu t0, t0, ta3 | |
245a7868 PB |
389 | |
390 | /* Set the TC restart PC */ | |
391 | lw t1, VPEBOOTCFG_PC(t0) | |
392 | mttc0 t1, CP0_TCRESTART | |
393 | ||
394 | /* Set the TC stack pointer */ | |
395 | lw t1, VPEBOOTCFG_SP(t0) | |
396 | mttgpr t1, sp | |
397 | ||
398 | /* Set the TC global pointer */ | |
399 | lw t1, VPEBOOTCFG_GP(t0) | |
400 | mttgpr t1, gp | |
401 | ||
402 | /* Copy config from this VPE */ | |
403 | mfc0 t0, CP0_CONFIG | |
404 | mttc0 t0, CP0_CONFIG | |
405 | ||
406 | /* Ensure no software interrupts are pending */ | |
407 | mttc0 zero, CP0_CAUSE | |
408 | mttc0 zero, CP0_STATUS | |
409 | ||
410 | /* Set TC active, not interrupt exempt */ | |
411 | mftc0 t0, CP0_TCSTATUS | |
412 | li t1, ~TCSTATUS_IXMT | |
413 | and t0, t0, t1 | |
414 | ori t0, t0, TCSTATUS_A | |
415 | mttc0 t0, CP0_TCSTATUS | |
416 | ||
417 | /* Clear the TC halt bit */ | |
418 | mttc0 zero, CP0_TCHALT | |
419 | ||
420 | /* Set VPE active */ | |
421 | mftc0 t0, CP0_VPECONF0 | |
422 | ori t0, t0, VPECONF0_VPA | |
423 | mttc0 t0, CP0_VPECONF0 | |
424 | ||
425 | /* Next VPE */ | |
0586ac75 MC |
426 | 2: srl ta2, ta2, 1 |
427 | addiu ta1, ta1, 1 | |
428 | bnez ta2, 1b | |
245a7868 PB |
429 | nop |
430 | ||
431 | /* Leave VPE configuration state */ | |
432 | mfc0 t1, CP0_MVPCONTROL | |
433 | xori t1, t1, MVPCONTROL_VPC | |
434 | mtc0 t1, CP0_MVPCONTROL | |
435 | ehb | |
436 | evpe | |
437 | ||
438 | /* Check whether this VPE is meant to be running */ | |
439 | li t0, 1 | |
440 | sll t0, t0, t9 | |
441 | and t0, t0, t8 | |
442 | bnez t0, 2f | |
443 | nop | |
444 | ||
445 | /* This VPE should be offline, halt the TC */ | |
446 | li t0, TCHALT_H | |
447 | mtc0 t0, CP0_TCHALT | |
81a02e34 | 448 | PTR_LA t0, 1f |
245a7868 PB |
449 | 1: jr.hb t0 |
450 | nop | |
451 | ||
452 | 2: .set pop | |
453 | ||
454 | #endif /* CONFIG_MIPS_MT */ | |
455 | ||
456 | /* Return */ | |
457 | jr ra | |
458 | nop | |
459 | END(mips_cps_boot_vpes) | |
3179d37e PB |
460 | |
461 | #if defined(CONFIG_MIPS_CPS_PM) && defined(CONFIG_CPU_PM) | |
462 | ||
463 | /* Calculate a pointer to this CPUs struct mips_static_suspend_state */ | |
464 | .macro psstate dest | |
465 | .set push | |
466 | .set noat | |
467 | lw $1, TI_CPU(gp) | |
468 | sll $1, $1, LONGLOG | |
81a02e34 | 469 | PTR_LA \dest, __per_cpu_offset |
3179d37e PB |
470 | addu $1, $1, \dest |
471 | lw $1, 0($1) | |
81a02e34 | 472 | PTR_LA \dest, cps_cpu_state |
3179d37e PB |
473 | addu \dest, \dest, $1 |
474 | .set pop | |
475 | .endm | |
476 | ||
477 | LEAF(mips_cps_pm_save) | |
478 | /* Save CPU state */ | |
479 | SUSPEND_SAVE_REGS | |
480 | psstate t1 | |
481 | SUSPEND_SAVE_STATIC | |
482 | jr v0 | |
483 | nop | |
484 | END(mips_cps_pm_save) | |
485 | ||
486 | LEAF(mips_cps_pm_restore) | |
487 | /* Restore CPU state */ | |
488 | psstate t1 | |
489 | RESUME_RESTORE_STATIC | |
490 | RESUME_RESTORE_REGS_RETURN | |
491 | END(mips_cps_pm_restore) | |
492 | ||
493 | #endif /* CONFIG_MIPS_CPS_PM && CONFIG_CPU_PM */ |