[mirror_ubuntu-focal-kernel.git] / arch / mips / kernel / cps-vec.S

/*
 * Copyright (C) 2013 Imagination Technologies
 * Author: Paul Burton <paul.burton@imgtec.com>
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 */

#include <asm/addrspace.h>
#include <asm/asm.h>
#include <asm/asm-offsets.h>
#include <asm/asmmacro.h>
#include <asm/cacheops.h>
#include <asm/eva.h>
#include <asm/mipsregs.h>
#include <asm/mipsmtregs.h>
#include <asm/pm.h>

#define GCR_CL_COHERENCE_OFS	0x2008
#define GCR_CL_ID_OFS		0x2028

.extern mips_cm_base

.set noreorder

#ifdef CONFIG_64BIT
# define STATUS_BITDEPS		ST0_KX
#else
# define STATUS_BITDEPS		0
#endif

#ifdef CONFIG_MIPS_CPS_NS16550

#define DUMP_EXCEP(name)		\
	PTR_LA	a0, 8f;			\
	jal	mips_cps_bev_dump;	\
	 nop;				\
	TEXT(name)

#else /* !CONFIG_MIPS_CPS_NS16550 */

#define DUMP_EXCEP(name)

#endif /* !CONFIG_MIPS_CPS_NS16550 */

	/*
	 * Set dest to non-zero if the core supports the MT ASE, else zero. If
	 * MT is not supported then branch to nomt.
	 */
	.macro	has_mt	dest, nomt
	mfc0	\dest, CP0_CONFIG, 1
	bgez	\dest, \nomt
	 mfc0	\dest, CP0_CONFIG, 2
	bgez	\dest, \nomt
	 mfc0	\dest, CP0_CONFIG, 3
	andi	\dest, \dest, MIPS_CONF3_MT
	beqz	\dest, \nomt
	 nop
	.endm

.section .text.cps-vec
.balign 0x1000

LEAF(mips_cps_core_entry)
	/*
	 * These first 4 bytes will be patched by cps_smp_setup to load the
	 * CCA to use into register s0.
	 */
	.word	0

	/* Check whether we're here due to an NMI */
	mfc0	k0, CP0_STATUS
	and	k0, k0, ST0_NMI
	beqz	k0, not_nmi
	 nop

	/* This is an NMI */
	PTR_LA	k0, nmi_handler
	jr	k0
	 nop

not_nmi:
	/* Setup Cause */
	li	t0, CAUSEF_IV
	mtc0	t0, CP0_CAUSE

	/* Setup Status */
	li	t0, ST0_CU1 | ST0_CU0 | ST0_BEV | STATUS_BITDEPS
	mtc0	t0, CP0_STATUS

	/* Initialize the L1 caches */
	jal	mips_cps_cache_init
	 nop

	/* Set Kseg0 CCA to that in s0 */
	mfc0	t0, CP0_CONFIG
	ori	t0, 0x7
	xori	t0, 0x7
	or	t0, t0, s0
	mtc0	t0, CP0_CONFIG
	ehb

	/* Calculate an uncached address for the CM GCRs */
	MFC0	v1, CP0_CMGCRBASE
	PTR_SLL	v1, v1, 4
	PTR_LI	t0, UNCAC_BASE
	PTR_ADDU v1, v1, t0

	/* Enter the coherent domain */
	li	t0, 0xff
	sw	t0, GCR_CL_COHERENCE_OFS(v1)
	ehb

	/* Jump to kseg0 */
	PTR_LA	t0, 1f
	jr	t0
	 nop

	/*
	 * We're up, cached & coherent. Perform any further required core-level
	 * initialisation.
	 */
1:	jal	mips_cps_core_init
	 nop

	/* Do any EVA initialization if necessary */
	eva_init

	/*
	 * Boot any other VPEs within this core that should be online, and
	 * deactivate this VPE if it should be offline.
	 */
	jal	mips_cps_boot_vpes
	 nop

	/* Off we go! */
	PTR_L	t1, VPEBOOTCFG_PC(v0)
	PTR_L	gp, VPEBOOTCFG_GP(v0)
	PTR_L	sp, VPEBOOTCFG_SP(v0)
	jr	t1
	 nop
	END(mips_cps_core_entry)

.org 0x200
LEAF(excep_tlbfill)
	DUMP_EXCEP("TLB Fill")
	b	.
	 nop
	END(excep_tlbfill)

.org 0x280
LEAF(excep_xtlbfill)
	DUMP_EXCEP("XTLB Fill")
	b	.
	 nop
	END(excep_xtlbfill)

.org 0x300
LEAF(excep_cache)
	DUMP_EXCEP("Cache")
	b	.
	 nop
	END(excep_cache)

.org 0x380
LEAF(excep_genex)
	DUMP_EXCEP("General")
	b	.
	 nop
	END(excep_genex)

.org 0x400
LEAF(excep_intex)
	DUMP_EXCEP("Interrupt")
	b	.
	 nop
	END(excep_intex)

.org 0x480
LEAF(excep_ejtag)
	DUMP_EXCEP("EJTAG")
	PTR_LA	k0, ejtag_debug_handler
	jr	k0
	 nop
	END(excep_ejtag)

LEAF(mips_cps_core_init)
#ifdef CONFIG_MIPS_MT_SMP
	/* Check that the core implements the MT ASE */
	has_mt	t0, 3f

	.set	push
	.set	mt

	/* Only allow 1 TC per VPE to execute... */
	dmt

	/* ...and for the moment only 1 VPE */
	dvpe
	PTR_LA	t1, 1f
	jr.hb	t1
	 nop

	/* Enter VPE configuration state */
1:	mfc0	t0, CP0_MVPCONTROL
	ori	t0, t0, MVPCONTROL_VPC
	mtc0	t0, CP0_MVPCONTROL

	/* Retrieve the number of VPEs within the core */
	mfc0	t0, CP0_MVPCONF0
	srl	t0, t0, MVPCONF0_PVPE_SHIFT
	andi	t0, t0, (MVPCONF0_PVPE >> MVPCONF0_PVPE_SHIFT)
	addiu	ta3, t0, 1

	/* If there's only 1, we're done */
	beqz	t0, 2f
	 nop

	/* Loop through each VPE within this core */
	li	ta1, 1

1:	/* Operate on the appropriate TC */
	mtc0	ta1, CP0_VPECONTROL
	ehb

	/* Bind TC to VPE (1:1 TC:VPE mapping) */
	mttc0	ta1, CP0_TCBIND

	/* Set exclusive TC, non-active, master */
	li	t0, VPECONF0_MVP
	sll	t1, ta1, VPECONF0_XTC_SHIFT
	or	t0, t0, t1
	mttc0	t0, CP0_VPECONF0

	/* Set TC non-active, non-allocatable */
	mttc0	zero, CP0_TCSTATUS

	/* Set TC halted */
	li	t0, TCHALT_H
	mttc0	t0, CP0_TCHALT

	/* Next VPE */
	addiu	ta1, ta1, 1
	slt	t0, ta1, ta3
	bnez	t0, 1b
	 nop

	/* Leave VPE configuration state */
2:	mfc0	t0, CP0_MVPCONTROL
	xori	t0, t0, MVPCONTROL_VPC
	mtc0	t0, CP0_MVPCONTROL

3:	.set	pop
#endif
	jr	ra
	 nop
	END(mips_cps_core_init)

LEAF(mips_cps_boot_vpes)
	/* Retrieve CM base address */
	PTR_LA	t0, mips_cm_base
	PTR_L	t0, 0(t0)

	/* Calculate a pointer to this cores struct core_boot_config */
	lw	t0, GCR_CL_ID_OFS(t0)
	li	t1, COREBOOTCFG_SIZE
	mul	t0, t0, t1
	PTR_LA	t1, mips_cps_core_bootcfg
	PTR_L	t1, 0(t1)
	PTR_ADDU t0, t0, t1

	/* Calculate this VPEs ID. If the core doesn't support MT use 0 */
	li	t9, 0
#ifdef CONFIG_MIPS_MT_SMP
	has_mt	ta2, 1f

	/* Find the number of VPEs present in the core */
	mfc0	t1, CP0_MVPCONF0
	srl	t1, t1, MVPCONF0_PVPE_SHIFT
	andi	t1, t1, MVPCONF0_PVPE >> MVPCONF0_PVPE_SHIFT
	addiu	t1, t1, 1

	/* Calculate a mask for the VPE ID from EBase.CPUNum */
	clz	t1, t1
	li	t2, 31
	subu	t1, t2, t1
	li	t2, 1
	sll	t1, t2, t1
	addiu	t1, t1, -1

	/* Retrieve the VPE ID from EBase.CPUNum */
	mfc0	t9, $15, 1
	and	t9, t9, t1
#endif

1:	/* Calculate a pointer to this VPEs struct vpe_boot_config */
	li	t1, VPEBOOTCFG_SIZE
	mul	v0, t9, t1
	PTR_L	ta3, COREBOOTCFG_VPECONFIG(t0)
	PTR_ADDU v0, v0, ta3

#ifdef CONFIG_MIPS_MT_SMP

	/* If the core doesn't support MT then return */
	bnez	ta2, 1f
	 nop
	jr	ra
	 nop

	.set	push
	.set	mt

1:	/* Enter VPE configuration state */
	dvpe
	PTR_LA	t1, 1f
	jr.hb	t1
	 nop
1:	mfc0	t1, CP0_MVPCONTROL
	ori	t1, t1, MVPCONTROL_VPC
	mtc0	t1, CP0_MVPCONTROL
	ehb

	/* Loop through each VPE */
	PTR_L	ta2, COREBOOTCFG_VPEMASK(t0)
	move	t8, ta2
	li	ta1, 0

	/* Check whether the VPE should be running. If not, skip it */
1:	andi	t0, ta2, 1
	beqz	t0, 2f
	 nop

	/* Operate on the appropriate TC */
	mfc0	t0, CP0_VPECONTROL
	ori	t0, t0, VPECONTROL_TARGTC
	xori	t0, t0, VPECONTROL_TARGTC
	or	t0, t0, ta1
	mtc0	t0, CP0_VPECONTROL
	ehb

	/* Skip the VPE if its TC is not halted */
	mftc0	t0, CP0_TCHALT
	beqz	t0, 2f
	 nop

	/* Calculate a pointer to the VPEs struct vpe_boot_config */
	li	t0, VPEBOOTCFG_SIZE
	mul	t0, t0, ta1
	addu	t0, t0, ta3

	/* Set the TC restart PC */
	lw	t1, VPEBOOTCFG_PC(t0)
	mttc0	t1, CP0_TCRESTART

	/* Set the TC stack pointer */
	lw	t1, VPEBOOTCFG_SP(t0)
	mttgpr	t1, sp

	/* Set the TC global pointer */
	lw	t1, VPEBOOTCFG_GP(t0)
	mttgpr	t1, gp

	/* Copy config from this VPE */
	mfc0	t0, CP0_CONFIG
	mttc0	t0, CP0_CONFIG

	/* Ensure no software interrupts are pending */
	mttc0	zero, CP0_CAUSE
	mttc0	zero, CP0_STATUS

	/* Set TC active, not interrupt exempt */
	mftc0	t0, CP0_TCSTATUS
	li	t1, ~TCSTATUS_IXMT
	and	t0, t0, t1
	ori	t0, t0, TCSTATUS_A
	mttc0	t0, CP0_TCSTATUS

	/* Clear the TC halt bit */
	mttc0	zero, CP0_TCHALT

	/* Set VPE active */
	mftc0	t0, CP0_VPECONF0
	ori	t0, t0, VPECONF0_VPA
	mttc0	t0, CP0_VPECONF0

	/* Next VPE */
2:	srl	ta2, ta2, 1
	addiu	ta1, ta1, 1
	bnez	ta2, 1b
	 nop

	/* Leave VPE configuration state */
	mfc0	t1, CP0_MVPCONTROL
	xori	t1, t1, MVPCONTROL_VPC
	mtc0	t1, CP0_MVPCONTROL
	ehb
	evpe

	/* Check whether this VPE is meant to be running */
	li	t0, 1
	sll	t0, t0, t9
	and	t0, t0, t8
	bnez	t0, 2f
	 nop

	/* This VPE should be offline, halt the TC */
	li	t0, TCHALT_H
	mtc0	t0, CP0_TCHALT
	PTR_LA	t0, 1f
1:	jr.hb	t0
	 nop

2:	.set	pop

#endif /* CONFIG_MIPS_MT_SMP */

	/* Return */
	jr	ra
	 nop
	END(mips_cps_boot_vpes)

LEAF(mips_cps_cache_init)
	/*
	 * Clear the bits used to index the caches. Note that the architecture
	 * dictates that writing to any of TagLo or TagHi selects 0 or 2 should
	 * be valid for all MIPS32 CPUs, even those for which said writes are
	 * unnecessary.
	 */
	mtc0	zero, CP0_TAGLO, 0
	mtc0	zero, CP0_TAGHI, 0
	mtc0	zero, CP0_TAGLO, 2
	mtc0	zero, CP0_TAGHI, 2
	ehb

	/* Primary cache configuration is indicated by Config1 */
	mfc0	v0, CP0_CONFIG, 1

	/* Detect I-cache line size */
	_EXT	t0, v0, MIPS_CONF1_IL_SHF, MIPS_CONF1_IL_SZ
	beqz	t0, icache_done
	 li	t1, 2
	sllv	t0, t1, t0

	/* Detect I-cache size */
	_EXT	t1, v0, MIPS_CONF1_IS_SHF, MIPS_CONF1_IS_SZ
	xori	t2, t1, 0x7
	beqz	t2, 1f
	 li	t3, 32
	addiu	t1, t1, 1
	sllv	t1, t3, t1
1:	/* At this point t1 == I-cache sets per way */
	_EXT	t2, v0, MIPS_CONF1_IA_SHF, MIPS_CONF1_IA_SZ
	addiu	t2, t2, 1
	mul	t1, t1, t0
	mul	t1, t1, t2

	li	a0, CKSEG0
	PTR_ADD	a1, a0, t1
1:	cache	Index_Store_Tag_I, 0(a0)
	PTR_ADD	a0, a0, t0
	bne	a0, a1, 1b
	 nop
icache_done:

	/* Detect D-cache line size */
	_EXT	t0, v0, MIPS_CONF1_DL_SHF, MIPS_CONF1_DL_SZ
	beqz	t0, dcache_done
	 li	t1, 2
	sllv	t0, t1, t0

	/* Detect D-cache size */
	_EXT	t1, v0, MIPS_CONF1_DS_SHF, MIPS_CONF1_DS_SZ
	xori	t2, t1, 0x7
	beqz	t2, 1f
	 li	t3, 32
	addiu	t1, t1, 1
	sllv	t1, t3, t1
1:	/* At this point t1 == D-cache sets per way */
	_EXT	t2, v0, MIPS_CONF1_DA_SHF, MIPS_CONF1_DA_SZ
	addiu	t2, t2, 1
	mul	t1, t1, t0
	mul	t1, t1, t2

	li	a0, CKSEG0
	PTR_ADDU a1, a0, t1
	PTR_SUBU a1, a1, t0
1:	cache	Index_Store_Tag_D, 0(a0)
	bne	a0, a1, 1b
	 PTR_ADD a0, a0, t0
dcache_done:

	jr	ra
	 nop
	END(mips_cps_cache_init)

#if defined(CONFIG_MIPS_CPS_PM) && defined(CONFIG_CPU_PM)

	/* Calculate a pointer to this CPUs struct mips_static_suspend_state */
	.macro	psstate	dest
	.set	push
	.set	noat
	lw	$1, TI_CPU(gp)
	sll	$1, $1, LONGLOG
	PTR_LA	\dest, __per_cpu_offset
	addu	$1, $1, \dest
	lw	$1, 0($1)
	PTR_LA	\dest, cps_cpu_state
	addu	\dest, \dest, $1
	.set	pop
	.endm

LEAF(mips_cps_pm_save)
	/* Save CPU state */
	SUSPEND_SAVE_REGS
	psstate	t1
	SUSPEND_SAVE_STATIC
	jr	v0
	 nop
	END(mips_cps_pm_save)

LEAF(mips_cps_pm_restore)
	/* Restore CPU state */
	psstate	t1
	RESUME_RESTORE_STATIC
	RESUME_RESTORE_REGS_RETURN
	END(mips_cps_pm_restore)

#endif /* CONFIG_MIPS_CPS_PM && CONFIG_CPU_PM */
Commit	Line	Data
0ee958e1 PB	1	/*
	2	* Copyright (C) 2013 Imagination Technologies
	3	* Author: Paul Burton <paul.burton@imgtec.com>
	4	*
	5	* This program is free software; you can redistribute it and/or modify it
	6	* under the terms of the GNU General Public License as published by the
	7	* Free Software Foundation; either version 2 of the License, or (at your
	8	* option) any later version.
	9	*/
	10
	11	#include <asm/addrspace.h>
	12	#include <asm/asm.h>
	13	#include <asm/asm-offsets.h>
	14	#include <asm/asmmacro.h>
	15	#include <asm/cacheops.h>
6521d9a4	16	#include <asm/eva.h>
0ee958e1	17	#include <asm/mipsregs.h>
245a7868	18	#include <asm/mipsmtregs.h>
3179d37e	19	#include <asm/pm.h>
0ee958e1	20
245a7868 PB	21	#define GCR_CL_COHERENCE_OFS 0x2008
	22	#define GCR_CL_ID_OFS 0x2028
	23
	24	.extern mips_cm_base
	25
	26	.set noreorder
	27
8fe2c547 PB	28	#ifdef CONFIG_64BIT
	29	# define STATUS_BITDEPS ST0_KX
	30	#else
	31	# define STATUS_BITDEPS 0
	32	#endif
	33
609cf6f2 PB	34	#ifdef CONFIG_MIPS_CPS_NS16550
	35
	36	#define DUMP_EXCEP(name) \
	37	PTR_LA a0, 8f; \
	38	jal mips_cps_bev_dump; \
	39	nop; \
	40	TEXT(name)
	41
	42	#else /* !CONFIG_MIPS_CPS_NS16550 */
	43
	44	#define DUMP_EXCEP(name)
	45
	46	#endif /* !CONFIG_MIPS_CPS_NS16550 */
	47
245a7868 PB	48	/*
	49	* Set dest to non-zero if the core supports the MT ASE, else zero. If
	50	* MT is not supported then branch to nomt.
	51	*/
	52	.macro has_mt dest, nomt
192fbc20	53	mfc0 \dest, CP0_CONFIG, 1
245a7868 PB	54	bgez \dest, \nomt
	55	mfc0 \dest, CP0_CONFIG, 2
	56	bgez \dest, \nomt
	57	mfc0 \dest, CP0_CONFIG, 3
	58	andi \dest, \dest, MIPS_CONF3_MT
	59	beqz \dest, \nomt
1e5fb282	60	nop
245a7868	61	.endm
0ee958e1 PB	62
	63	.section .text.cps-vec
	64	.balign 0x1000
0ee958e1 PB	65
	66	LEAF(mips_cps_core_entry)
	67	/*
946db173 PB	68	* These first 4 bytes will be patched by cps_smp_setup to load the
946db173 PB	69	* CCA to use into register s0.
0ee958e1	70	*/
0155a065	71	.word 0
0ee958e1 PB	72
	73	/* Check whether we're here due to an NMI */
	74	mfc0 k0, CP0_STATUS
	75	and k0, k0, ST0_NMI
	76	beqz k0, not_nmi
	77	nop
	78
	79	/* This is an NMI */
81a02e34	80	PTR_LA k0, nmi_handler
0ee958e1 PB	81	jr k0
	82	nop
	83
	84	not_nmi:
	85	/* Setup Cause */
	86	li t0, CAUSEF_IV
	87	mtc0 t0, CP0_CAUSE
	88
	89	/* Setup Status */
8fe2c547	90	li t0, ST0_CU1 \| ST0_CU0 \| ST0_BEV \| STATUS_BITDEPS
0ee958e1 PB	91	mtc0 t0, CP0_STATUS
0ee958e1 PB	92
3dbc9971 PB	93	/* Initialize the L1 caches */
3dbc9971 PB	94	jal mips_cps_cache_init
0ee958e1	95	nop
0ee958e1	96
0155a065	97	/* Set Kseg0 CCA to that in s0 */
0ee958e1 PB	98	mfc0 t0, CP0_CONFIG
0ee958e1 PB	99	ori t0, 0x7
0155a065 PB	100	xori t0, 0x7
0155a065 PB	101	or t0, t0, s0
0ee958e1 PB	102	mtc0 t0, CP0_CONFIG
	103	ehb
	104
946db173 PB	105	/* Calculate an uncached address for the CM GCRs */
	106	MFC0 v1, CP0_CMGCRBASE
	107	PTR_SLL v1, v1, 4
	108	PTR_LI t0, UNCAC_BASE
	109	PTR_ADDU v1, v1, t0
	110
0ee958e1 PB	111	/* Enter the coherent domain */
0ee958e1 PB	112	li t0, 0xff
90996511	113	sw t0, GCR_CL_COHERENCE_OFS(v1)
0ee958e1 PB	114	ehb
	115
	116	/* Jump to kseg0 */
81a02e34	117	PTR_LA t0, 1f
0ee958e1 PB	118	jr t0
	119	nop
	120
245a7868 PB	121	/*
	122	* We're up, cached & coherent. Perform any further required core-level
	123	* initialisation.
	124	*/
	125	1: jal mips_cps_core_init
	126	nop
0ee958e1	127
6521d9a4 MC	128	/* Do any EVA initialization if necessary */
	129	eva_init
	130
0ee958e1	131	/*
245a7868 PB	132	* Boot any other VPEs within this core that should be online, and
245a7868 PB	133	* deactivate this VPE if it should be offline.
0ee958e1	134	*/
245a7868 PB	135	jal mips_cps_boot_vpes
245a7868 PB	136	nop
0ee958e1 PB	137
0ee958e1 PB	138	/* Off we go! */
b677bc03 MC	139	PTR_L t1, VPEBOOTCFG_PC(v0)
	140	PTR_L gp, VPEBOOTCFG_GP(v0)
	141	PTR_L sp, VPEBOOTCFG_SP(v0)
0ee958e1 PB	142	jr t1
	143	nop
	144	END(mips_cps_core_entry)
	145
	146	.org 0x200
	147	LEAF(excep_tlbfill)
609cf6f2	148	DUMP_EXCEP("TLB Fill")
0ee958e1 PB	149	b .
	150	nop
	151	END(excep_tlbfill)
	152
	153	.org 0x280
	154	LEAF(excep_xtlbfill)
609cf6f2	155	DUMP_EXCEP("XTLB Fill")
0ee958e1 PB	156	b .
	157	nop
	158	END(excep_xtlbfill)
	159
	160	.org 0x300
	161	LEAF(excep_cache)
609cf6f2	162	DUMP_EXCEP("Cache")
0ee958e1 PB	163	b .
	164	nop
	165	END(excep_cache)
	166
	167	.org 0x380
	168	LEAF(excep_genex)
609cf6f2	169	DUMP_EXCEP("General")
0ee958e1 PB	170	b .
	171	nop
	172	END(excep_genex)
	173
	174	.org 0x400
	175	LEAF(excep_intex)
609cf6f2	176	DUMP_EXCEP("Interrupt")
0ee958e1 PB	177	b .
	178	nop
	179	END(excep_intex)
	180
	181	.org 0x480
	182	LEAF(excep_ejtag)
609cf6f2	183	DUMP_EXCEP("EJTAG")
81a02e34	184	PTR_LA k0, ejtag_debug_handler
0ee958e1 PB	185	jr k0
	186	nop
	187	END(excep_ejtag)
245a7868 PB	188
245a7868 PB	189	LEAF(mips_cps_core_init)
7a63076d	190	#ifdef CONFIG_MIPS_MT_SMP
245a7868 PB	191	/* Check that the core implements the MT ASE */
245a7868 PB	192	has_mt t0, 3f
245a7868 PB	193
	194	.set push
	195	.set mt
	196
	197	/* Only allow 1 TC per VPE to execute... */
	198	dmt
	199
	200	/* ...and for the moment only 1 VPE */
	201	dvpe
81a02e34	202	PTR_LA t1, 1f
245a7868 PB	203	jr.hb t1
	204	nop
	205
	206	/* Enter VPE configuration state */
	207	1: mfc0 t0, CP0_MVPCONTROL
	208	ori t0, t0, MVPCONTROL_VPC
	209	mtc0 t0, CP0_MVPCONTROL
	210
	211	/* Retrieve the number of VPEs within the core */
	212	mfc0 t0, CP0_MVPCONF0
	213	srl t0, t0, MVPCONF0_PVPE_SHIFT
	214	andi t0, t0, (MVPCONF0_PVPE >> MVPCONF0_PVPE_SHIFT)
0586ac75	215	addiu ta3, t0, 1
245a7868 PB	216
	217	/* If there's only 1, we're done */
	218	beqz t0, 2f
	219	nop
	220
	221	/* Loop through each VPE within this core */
0586ac75	222	li ta1, 1
245a7868 PB	223
245a7868 PB	224	1: /* Operate on the appropriate TC */
0586ac75	225	mtc0 ta1, CP0_VPECONTROL
245a7868 PB	226	ehb
	227
	228	/* Bind TC to VPE (1:1 TC:VPE mapping) */
0586ac75	229	mttc0 ta1, CP0_TCBIND
245a7868 PB	230
	231	/* Set exclusive TC, non-active, master */
	232	li t0, VPECONF0_MVP
0586ac75	233	sll t1, ta1, VPECONF0_XTC_SHIFT
245a7868 PB	234	or t0, t0, t1
	235	mttc0 t0, CP0_VPECONF0
	236
	237	/* Set TC non-active, non-allocatable */
	238	mttc0 zero, CP0_TCSTATUS
	239
	240	/* Set TC halted */
	241	li t0, TCHALT_H
	242	mttc0 t0, CP0_TCHALT
	243
	244	/* Next VPE */
0586ac75 MC	245	addiu ta1, ta1, 1
0586ac75 MC	246	slt t0, ta1, ta3
245a7868 PB	247	bnez t0, 1b
	248	nop
	249
	250	/* Leave VPE configuration state */
	251	2: mfc0 t0, CP0_MVPCONTROL
	252	xori t0, t0, MVPCONTROL_VPC
	253	mtc0 t0, CP0_MVPCONTROL
	254
	255	3: .set pop
	256	#endif
	257	jr ra
	258	nop
	259	END(mips_cps_core_init)
	260
	261	LEAF(mips_cps_boot_vpes)
	262	/* Retrieve CM base address */
81a02e34	263	PTR_LA t0, mips_cm_base
b677bc03	264	PTR_L t0, 0(t0)
245a7868 PB	265
245a7868 PB	266	/* Calculate a pointer to this cores struct core_boot_config */
90996511	267	lw t0, GCR_CL_ID_OFS(t0)
245a7868 PB	268	li t1, COREBOOTCFG_SIZE
245a7868 PB	269	mul t0, t0, t1
81a02e34	270	PTR_LA t1, mips_cps_core_bootcfg
b677bc03 MC	271	PTR_L t1, 0(t1)
b677bc03 MC	272	PTR_ADDU t0, t0, t1
245a7868 PB	273
245a7868 PB	274	/* Calculate this VPEs ID. If the core doesn't support MT use 0 */
1e5fb282	275	li t9, 0
7a63076d	276	#ifdef CONFIG_MIPS_MT_SMP
0586ac75	277	has_mt ta2, 1f
245a7868 PB	278
	279	/* Find the number of VPEs present in the core */
	280	mfc0 t1, CP0_MVPCONF0
	281	srl t1, t1, MVPCONF0_PVPE_SHIFT
	282	andi t1, t1, MVPCONF0_PVPE >> MVPCONF0_PVPE_SHIFT
acac4108	283	addiu t1, t1, 1
245a7868 PB	284
	285	/* Calculate a mask for the VPE ID from EBase.CPUNum */
	286	clz t1, t1
	287	li t2, 31
	288	subu t1, t2, t1
	289	li t2, 1
	290	sll t1, t2, t1
	291	addiu t1, t1, -1
	292
	293	/* Retrieve the VPE ID from EBase.CPUNum */
	294	mfc0 t9, $15, 1
	295	and t9, t9, t1
a5b0f6db	296	#endif
245a7868 PB	297
	298	1: /* Calculate a pointer to this VPEs struct vpe_boot_config */
	299	li t1, VPEBOOTCFG_SIZE
	300	mul v0, t9, t1
b677bc03 MC	301	PTR_L ta3, COREBOOTCFG_VPECONFIG(t0)
b677bc03 MC	302	PTR_ADDU v0, v0, ta3
245a7868	303
7a63076d	304	#ifdef CONFIG_MIPS_MT_SMP
245a7868 PB	305
245a7868 PB	306	/* If the core doesn't support MT then return */
0586ac75	307	bnez ta2, 1f
245a7868 PB	308	nop
	309	jr ra
	310	nop
	311
	312	.set push
	313	.set mt
	314
	315	1: /* Enter VPE configuration state */
	316	dvpe
81a02e34	317	PTR_LA t1, 1f
245a7868 PB	318	jr.hb t1
	319	nop
	320	1: mfc0 t1, CP0_MVPCONTROL
	321	ori t1, t1, MVPCONTROL_VPC
	322	mtc0 t1, CP0_MVPCONTROL
	323	ehb
	324
	325	/* Loop through each VPE */
b677bc03	326	PTR_L ta2, COREBOOTCFG_VPEMASK(t0)
0586ac75 MC	327	move t8, ta2
0586ac75 MC	328	li ta1, 0
245a7868 PB	329
245a7868 PB	330	/* Check whether the VPE should be running. If not, skip it */
0586ac75	331	1: andi t0, ta2, 1
245a7868 PB	332	beqz t0, 2f
	333	nop
	334
	335	/* Operate on the appropriate TC */
	336	mfc0 t0, CP0_VPECONTROL
	337	ori t0, t0, VPECONTROL_TARGTC
	338	xori t0, t0, VPECONTROL_TARGTC
0586ac75	339	or t0, t0, ta1
245a7868 PB	340	mtc0 t0, CP0_VPECONTROL
	341	ehb
	342
	343	/* Skip the VPE if its TC is not halted */
	344	mftc0 t0, CP0_TCHALT
	345	beqz t0, 2f
	346	nop
	347
	348	/* Calculate a pointer to the VPEs struct vpe_boot_config */
	349	li t0, VPEBOOTCFG_SIZE
0586ac75 MC	350	mul t0, t0, ta1
0586ac75 MC	351	addu t0, t0, ta3
245a7868 PB	352
	353	/* Set the TC restart PC */
	354	lw t1, VPEBOOTCFG_PC(t0)
	355	mttc0 t1, CP0_TCRESTART
	356
	357	/* Set the TC stack pointer */
	358	lw t1, VPEBOOTCFG_SP(t0)
	359	mttgpr t1, sp
	360
	361	/* Set the TC global pointer */
	362	lw t1, VPEBOOTCFG_GP(t0)
	363	mttgpr t1, gp
	364
	365	/* Copy config from this VPE */
	366	mfc0 t0, CP0_CONFIG
	367	mttc0 t0, CP0_CONFIG
	368
	369	/* Ensure no software interrupts are pending */
	370	mttc0 zero, CP0_CAUSE
	371	mttc0 zero, CP0_STATUS
	372
	373	/* Set TC active, not interrupt exempt */
	374	mftc0 t0, CP0_TCSTATUS
	375	li t1, ~TCSTATUS_IXMT
	376	and t0, t0, t1
	377	ori t0, t0, TCSTATUS_A
	378	mttc0 t0, CP0_TCSTATUS
	379
	380	/* Clear the TC halt bit */
	381	mttc0 zero, CP0_TCHALT
	382
	383	/* Set VPE active */
	384	mftc0 t0, CP0_VPECONF0
	385	ori t0, t0, VPECONF0_VPA
	386	mttc0 t0, CP0_VPECONF0
	387
	388	/* Next VPE */
0586ac75 MC	389	2: srl ta2, ta2, 1
	390	addiu ta1, ta1, 1
	391	bnez ta2, 1b
245a7868 PB	392	nop
	393
	394	/* Leave VPE configuration state */
	395	mfc0 t1, CP0_MVPCONTROL
	396	xori t1, t1, MVPCONTROL_VPC
	397	mtc0 t1, CP0_MVPCONTROL
	398	ehb
	399	evpe
	400
	401	/* Check whether this VPE is meant to be running */
	402	li t0, 1
	403	sll t0, t0, t9
	404	and t0, t0, t8
	405	bnez t0, 2f
	406	nop
	407
	408	/* This VPE should be offline, halt the TC */
	409	li t0, TCHALT_H
	410	mtc0 t0, CP0_TCHALT
81a02e34	411	PTR_LA t0, 1f
245a7868 PB	412	1: jr.hb t0
	413	nop
	414
	415	2: .set pop
	416
7a63076d	417	#endif /* CONFIG_MIPS_MT_SMP */
245a7868 PB	418
	419	/* Return */
	420	jr ra
	421	nop
	422	END(mips_cps_boot_vpes)
3179d37e	423
3dbc9971 PB	424	LEAF(mips_cps_cache_init)
	425	/*
	426	* Clear the bits used to index the caches. Note that the architecture
	427	* dictates that writing to any of TagLo or TagHi selects 0 or 2 should
	428	* be valid for all MIPS32 CPUs, even those for which said writes are
	429	* unnecessary.
	430	*/
	431	mtc0 zero, CP0_TAGLO, 0
	432	mtc0 zero, CP0_TAGHI, 0
	433	mtc0 zero, CP0_TAGLO, 2
	434	mtc0 zero, CP0_TAGHI, 2
	435	ehb
	436
	437	/* Primary cache configuration is indicated by Config1 */
	438	mfc0 v0, CP0_CONFIG, 1
	439
	440	/* Detect I-cache line size */
	441	_EXT t0, v0, MIPS_CONF1_IL_SHF, MIPS_CONF1_IL_SZ
	442	beqz t0, icache_done
	443	li t1, 2
	444	sllv t0, t1, t0
	445
	446	/* Detect I-cache size */
	447	_EXT t1, v0, MIPS_CONF1_IS_SHF, MIPS_CONF1_IS_SZ
	448	xori t2, t1, 0x7
	449	beqz t2, 1f
	450	li t3, 32
	451	addiu t1, t1, 1
	452	sllv t1, t3, t1
	453	1: /* At this point t1 == I-cache sets per way */
	454	_EXT t2, v0, MIPS_CONF1_IA_SHF, MIPS_CONF1_IA_SZ
	455	addiu t2, t2, 1
	456	mul t1, t1, t0
	457	mul t1, t1, t2
	458
	459	li a0, CKSEG0
	460	PTR_ADD a1, a0, t1
	461	1: cache Index_Store_Tag_I, 0(a0)
	462	PTR_ADD a0, a0, t0
	463	bne a0, a1, 1b
	464	nop
	465	icache_done:
	466
	467	/* Detect D-cache line size */
	468	_EXT t0, v0, MIPS_CONF1_DL_SHF, MIPS_CONF1_DL_SZ
	469	beqz t0, dcache_done
	470	li t1, 2
	471	sllv t0, t1, t0
	472
	473	/* Detect D-cache size */
	474	_EXT t1, v0, MIPS_CONF1_DS_SHF, MIPS_CONF1_DS_SZ
	475	xori t2, t1, 0x7
	476	beqz t2, 1f
	477	li t3, 32
	478	addiu t1, t1, 1
	479	sllv t1, t3, t1
	480	1: /* At this point t1 == D-cache sets per way */
	481	_EXT t2, v0, MIPS_CONF1_DA_SHF, MIPS_CONF1_DA_SZ
	482	addiu t2, t2, 1
	483	mul t1, t1, t0
	484	mul t1, t1, t2
	485
	486	li a0, CKSEG0
	487	PTR_ADDU a1, a0, t1
488	PTR_SUBU a1, a1, t0
489	1: cache Index_Store_Tag_D, 0(a0)
490	bne a0, a1, 1b
491	PTR_ADD a0, a0, t0
492	dcache_done:
493
494	jr ra
495	nop
496	END(mips_cps_cache_init)
497
3179d37e PB	498	#if defined(CONFIG_MIPS_CPS_PM) && defined(CONFIG_CPU_PM)
	499
	500	/* Calculate a pointer to this CPUs struct mips_static_suspend_state */
	501	.macro psstate dest
	502	.set push
	503	.set noat
	504	lw $1, TI_CPU(gp)
	505	sll $1, $1, LONGLOG
81a02e34	506	PTR_LA \dest, __per_cpu_offset
3179d37e PB	507	addu $1, $1, \dest
3179d37e PB	508	lw $1, 0($1)
81a02e34	509	PTR_LA \dest, cps_cpu_state
3179d37e PB	510	addu \dest, \dest, $1
	511	.set pop
	512	.endm
	513
	514	LEAF(mips_cps_pm_save)
	515	/* Save CPU state */
	516	SUSPEND_SAVE_REGS
	517	psstate t1
	518	SUSPEND_SAVE_STATIC
	519	jr v0
	520	nop
	521	END(mips_cps_pm_save)
	522
	523	LEAF(mips_cps_pm_restore)
	524	/* Restore CPU state */
	525	psstate t1
	526	RESUME_RESTORE_STATIC
	527	RESUME_RESTORE_REGS_RETURN
	528	END(mips_cps_pm_restore)
	529
	530	#endif /* CONFIG_MIPS_CPS_PM && CONFIG_CPU_PM */