[mirror_ubuntu-zesty-kernel.git] / arch / mips / kernel / cps-vec.S

/*
 * Copyright (C) 2013 Imagination Technologies
 * Author: Paul Burton <paul.burton@imgtec.com>
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 */

#include <asm/addrspace.h>
#include <asm/asm.h>
#include <asm/asm-offsets.h>
#include <asm/asmmacro.h>
#include <asm/cacheops.h>
#include <asm/eva.h>
#include <asm/mipsregs.h>
#include <asm/mipsmtregs.h>
#include <asm/pm.h>

#define GCR_CL_COHERENCE_OFS	0x2008
#define GCR_CL_ID_OFS		0x2028

.extern mips_cm_base

.set noreorder

#ifdef CONFIG_64BIT
# define STATUS_BITDEPS		ST0_KX
#else
# define STATUS_BITDEPS		0
#endif

#ifdef CONFIG_MIPS_CPS_NS16550

#define DUMP_EXCEP(name)		\
	PTR_LA	a0, 8f;			\
	jal	mips_cps_bev_dump;	\
	 nop;				\
	TEXT(name)

#else /* !CONFIG_MIPS_CPS_NS16550 */

#define DUMP_EXCEP(name)

#endif /* !CONFIG_MIPS_CPS_NS16550 */

	/*
	 * Set dest to non-zero if the core supports the MT ASE, else zero. If
	 * MT is not supported then branch to nomt.
	 */
	.macro	has_mt	dest, nomt
	mfc0	\dest, CP0_CONFIG
	bgez	\dest, \nomt
	 mfc0	\dest, CP0_CONFIG, 1
	bgez	\dest, \nomt
	 mfc0	\dest, CP0_CONFIG, 2
	bgez	\dest, \nomt
	 mfc0	\dest, CP0_CONFIG, 3
	andi	\dest, \dest, MIPS_CONF3_MT
	beqz	\dest, \nomt
	 nop
	.endm

.section .text.cps-vec
.balign 0x1000

LEAF(mips_cps_core_entry)
	/*
	 * These first 4 bytes will be patched by cps_smp_setup to load the
	 * CCA to use into register s0.
	 */
	.word	0

	/* Check whether we're here due to an NMI */
	mfc0	k0, CP0_STATUS
	and	k0, k0, ST0_NMI
	beqz	k0, not_nmi
	 nop

	/* This is an NMI */
	PTR_LA	k0, nmi_handler
	jr	k0
	 nop

not_nmi:
	/* Setup Cause */
	li	t0, CAUSEF_IV
	mtc0	t0, CP0_CAUSE

	/* Setup Status */
	li	t0, ST0_CU1 | ST0_CU0 | ST0_BEV | STATUS_BITDEPS
	mtc0	t0, CP0_STATUS

	/*
	 * Clear the bits used to index the caches. Note that the architecture
	 * dictates that writing to any of TagLo or TagHi selects 0 or 2 should
	 * be valid for all MIPS32 CPUs, even those for which said writes are
	 * unnecessary.
	 */
	mtc0	zero, CP0_TAGLO, 0
	mtc0	zero, CP0_TAGHI, 0
	mtc0	zero, CP0_TAGLO, 2
	mtc0	zero, CP0_TAGHI, 2
	ehb

	/* Primary cache configuration is indicated by Config1 */
	mfc0	v0, CP0_CONFIG, 1

	/* Detect I-cache line size */
	_EXT	t0, v0, MIPS_CONF1_IL_SHF, MIPS_CONF1_IL_SZ
	beqz	t0, icache_done
	 li	t1, 2
	sllv	t0, t1, t0

	/* Detect I-cache size */
	_EXT	t1, v0, MIPS_CONF1_IS_SHF, MIPS_CONF1_IS_SZ
	xori	t2, t1, 0x7
	beqz	t2, 1f
	 li	t3, 32
	addiu	t1, t1, 1
	sllv	t1, t3, t1
1:	/* At this point t1 == I-cache sets per way */
	_EXT	t2, v0, MIPS_CONF1_IA_SHF, MIPS_CONF1_IA_SZ
	addiu	t2, t2, 1
	mul	t1, t1, t0
	mul	t1, t1, t2

	li	a0, CKSEG0
	PTR_ADD	a1, a0, t1
1:	cache	Index_Store_Tag_I, 0(a0)
	PTR_ADD	a0, a0, t0
	bne	a0, a1, 1b
	 nop
icache_done:

	/* Detect D-cache line size */
	_EXT	t0, v0, MIPS_CONF1_DL_SHF, MIPS_CONF1_DL_SZ
	beqz	t0, dcache_done
	 li	t1, 2
	sllv	t0, t1, t0

	/* Detect D-cache size */
	_EXT	t1, v0, MIPS_CONF1_DS_SHF, MIPS_CONF1_DS_SZ
	xori	t2, t1, 0x7
	beqz	t2, 1f
	 li	t3, 32
	addiu	t1, t1, 1
	sllv	t1, t3, t1
1:	/* At this point t1 == D-cache sets per way */
	_EXT	t2, v0, MIPS_CONF1_DA_SHF, MIPS_CONF1_DA_SZ
	addiu	t2, t2, 1
	mul	t1, t1, t0
	mul	t1, t1, t2

	li	a0, CKSEG0
	PTR_ADDU a1, a0, t1
	PTR_SUBU a1, a1, t0
1:	cache	Index_Store_Tag_D, 0(a0)
	bne	a0, a1, 1b
	 PTR_ADD a0, a0, t0
dcache_done:

	/* Set Kseg0 CCA to that in s0 */
	mfc0	t0, CP0_CONFIG
	ori	t0, 0x7
	xori	t0, 0x7
	or	t0, t0, s0
	mtc0	t0, CP0_CONFIG
	ehb

	/* Calculate an uncached address for the CM GCRs */
	MFC0	v1, CP0_CMGCRBASE
	PTR_SLL	v1, v1, 4
	PTR_LI	t0, UNCAC_BASE
	PTR_ADDU v1, v1, t0

	/* Enter the coherent domain */
	li	t0, 0xff
	sw	t0, GCR_CL_COHERENCE_OFS(v1)
	ehb

	/* Jump to kseg0 */
	PTR_LA	t0, 1f
	jr	t0
	 nop

	/*
	 * We're up, cached & coherent. Perform any further required core-level
	 * initialisation.
	 */
1:	jal	mips_cps_core_init
	 nop

	/* Do any EVA initialization if necessary */
	eva_init

	/*
	 * Boot any other VPEs within this core that should be online, and
	 * deactivate this VPE if it should be offline.
	 */
	jal	mips_cps_boot_vpes
	 nop

	/* Off we go! */
	PTR_L	t1, VPEBOOTCFG_PC(v0)
	PTR_L	gp, VPEBOOTCFG_GP(v0)
	PTR_L	sp, VPEBOOTCFG_SP(v0)
	jr	t1
	 nop
	END(mips_cps_core_entry)

.org 0x200
LEAF(excep_tlbfill)
	DUMP_EXCEP("TLB Fill")
	b	.
	 nop
	END(excep_tlbfill)

.org 0x280
LEAF(excep_xtlbfill)
	DUMP_EXCEP("XTLB Fill")
	b	.
	 nop
	END(excep_xtlbfill)

.org 0x300
LEAF(excep_cache)
	DUMP_EXCEP("Cache")
	b	.
	 nop
	END(excep_cache)

.org 0x380
LEAF(excep_genex)
	DUMP_EXCEP("General")
	b	.
	 nop
	END(excep_genex)

.org 0x400
LEAF(excep_intex)
	DUMP_EXCEP("Interrupt")
	b	.
	 nop
	END(excep_intex)

.org 0x480
LEAF(excep_ejtag)
	DUMP_EXCEP("EJTAG")
	PTR_LA	k0, ejtag_debug_handler
	jr	k0
	 nop
	END(excep_ejtag)

LEAF(mips_cps_core_init)
#ifdef CONFIG_MIPS_MT_SMP
	/* Check that the core implements the MT ASE */
	has_mt	t0, 3f

	.set	push
	.set	mips64r2
	.set	mt

	/* Only allow 1 TC per VPE to execute... */
	dmt

	/* ...and for the moment only 1 VPE */
	dvpe
	PTR_LA	t1, 1f
	jr.hb	t1
	 nop

	/* Enter VPE configuration state */
1:	mfc0	t0, CP0_MVPCONTROL
	ori	t0, t0, MVPCONTROL_VPC
	mtc0	t0, CP0_MVPCONTROL

	/* Retrieve the number of VPEs within the core */
	mfc0	t0, CP0_MVPCONF0
	srl	t0, t0, MVPCONF0_PVPE_SHIFT
	andi	t0, t0, (MVPCONF0_PVPE >> MVPCONF0_PVPE_SHIFT)
	addiu	ta3, t0, 1

	/* If there's only 1, we're done */
	beqz	t0, 2f
	 nop

	/* Loop through each VPE within this core */
	li	ta1, 1

1:	/* Operate on the appropriate TC */
	mtc0	ta1, CP0_VPECONTROL
	ehb

	/* Bind TC to VPE (1:1 TC:VPE mapping) */
	mttc0	ta1, CP0_TCBIND

	/* Set exclusive TC, non-active, master */
	li	t0, VPECONF0_MVP
	sll	t1, ta1, VPECONF0_XTC_SHIFT
	or	t0, t0, t1
	mttc0	t0, CP0_VPECONF0

	/* Set TC non-active, non-allocatable */
	mttc0	zero, CP0_TCSTATUS

	/* Set TC halted */
	li	t0, TCHALT_H
	mttc0	t0, CP0_TCHALT

	/* Next VPE */
	addiu	ta1, ta1, 1
	slt	t0, ta1, ta3
	bnez	t0, 1b
	 nop

	/* Leave VPE configuration state */
2:	mfc0	t0, CP0_MVPCONTROL
	xori	t0, t0, MVPCONTROL_VPC
	mtc0	t0, CP0_MVPCONTROL

3:	.set	pop
#endif
	jr	ra
	 nop
	END(mips_cps_core_init)

LEAF(mips_cps_boot_vpes)
	/* Retrieve CM base address */
	PTR_LA	t0, mips_cm_base
	PTR_L	t0, 0(t0)

	/* Calculate a pointer to this cores struct core_boot_config */
	lw	t0, GCR_CL_ID_OFS(t0)
	li	t1, COREBOOTCFG_SIZE
	mul	t0, t0, t1
	PTR_LA	t1, mips_cps_core_bootcfg
	PTR_L	t1, 0(t1)
	PTR_ADDU t0, t0, t1

	/* Calculate this VPEs ID. If the core doesn't support MT use 0 */
	li	t9, 0
#ifdef CONFIG_MIPS_MT_SMP
	has_mt	ta2, 1f

	/* Find the number of VPEs present in the core */
	mfc0	t1, CP0_MVPCONF0
	srl	t1, t1, MVPCONF0_PVPE_SHIFT
	andi	t1, t1, MVPCONF0_PVPE >> MVPCONF0_PVPE_SHIFT
	addiu	t1, t1, 1

	/* Calculate a mask for the VPE ID from EBase.CPUNum */
	clz	t1, t1
	li	t2, 31
	subu	t1, t2, t1
	li	t2, 1
	sll	t1, t2, t1
	addiu	t1, t1, -1

	/* Retrieve the VPE ID from EBase.CPUNum */
	mfc0	t9, $15, 1
	and	t9, t9, t1
#endif

1:	/* Calculate a pointer to this VPEs struct vpe_boot_config */
	li	t1, VPEBOOTCFG_SIZE
	mul	v0, t9, t1
	PTR_L	ta3, COREBOOTCFG_VPECONFIG(t0)
	PTR_ADDU v0, v0, ta3

#ifdef CONFIG_MIPS_MT_SMP

	/* If the core doesn't support MT then return */
	bnez	ta2, 1f
	 nop
	jr	ra
	 nop

	.set	push
	.set	mips64r2
	.set	mt

1:	/* Enter VPE configuration state */
	dvpe
	PTR_LA	t1, 1f
	jr.hb	t1
	 nop
1:	mfc0	t1, CP0_MVPCONTROL
	ori	t1, t1, MVPCONTROL_VPC
	mtc0	t1, CP0_MVPCONTROL
	ehb

	/* Loop through each VPE */
	PTR_L	ta2, COREBOOTCFG_VPEMASK(t0)
	move	t8, ta2
	li	ta1, 0

	/* Check whether the VPE should be running. If not, skip it */
1:	andi	t0, ta2, 1
	beqz	t0, 2f
	 nop

	/* Operate on the appropriate TC */
	mfc0	t0, CP0_VPECONTROL
	ori	t0, t0, VPECONTROL_TARGTC
	xori	t0, t0, VPECONTROL_TARGTC
	or	t0, t0, ta1
	mtc0	t0, CP0_VPECONTROL
	ehb

	/* Skip the VPE if its TC is not halted */
	mftc0	t0, CP0_TCHALT
	beqz	t0, 2f
	 nop

	/* Calculate a pointer to the VPEs struct vpe_boot_config */
	li	t0, VPEBOOTCFG_SIZE
	mul	t0, t0, ta1
	addu	t0, t0, ta3

	/* Set the TC restart PC */
	lw	t1, VPEBOOTCFG_PC(t0)
	mttc0	t1, CP0_TCRESTART

	/* Set the TC stack pointer */
	lw	t1, VPEBOOTCFG_SP(t0)
	mttgpr	t1, sp

	/* Set the TC global pointer */
	lw	t1, VPEBOOTCFG_GP(t0)
	mttgpr	t1, gp

	/* Copy config from this VPE */
	mfc0	t0, CP0_CONFIG
	mttc0	t0, CP0_CONFIG

	/* Ensure no software interrupts are pending */
	mttc0	zero, CP0_CAUSE
	mttc0	zero, CP0_STATUS

	/* Set TC active, not interrupt exempt */
	mftc0	t0, CP0_TCSTATUS
	li	t1, ~TCSTATUS_IXMT
	and	t0, t0, t1
	ori	t0, t0, TCSTATUS_A
	mttc0	t0, CP0_TCSTATUS

	/* Clear the TC halt bit */
	mttc0	zero, CP0_TCHALT

	/* Set VPE active */
	mftc0	t0, CP0_VPECONF0
	ori	t0, t0, VPECONF0_VPA
	mttc0	t0, CP0_VPECONF0

	/* Next VPE */
2:	srl	ta2, ta2, 1
	addiu	ta1, ta1, 1
	bnez	ta2, 1b
	 nop

	/* Leave VPE configuration state */
	mfc0	t1, CP0_MVPCONTROL
	xori	t1, t1, MVPCONTROL_VPC
	mtc0	t1, CP0_MVPCONTROL
	ehb
	evpe

	/* Check whether this VPE is meant to be running */
	li	t0, 1
	sll	t0, t0, t9
	and	t0, t0, t8
	bnez	t0, 2f
	 nop

	/* This VPE should be offline, halt the TC */
	li	t0, TCHALT_H
	mtc0	t0, CP0_TCHALT
	PTR_LA	t0, 1f
1:	jr.hb	t0
	 nop

2:	.set	pop

#endif /* CONFIG_MIPS_MT_SMP */

	/* Return */
	jr	ra
	 nop
	END(mips_cps_boot_vpes)

#if defined(CONFIG_MIPS_CPS_PM) && defined(CONFIG_CPU_PM)

	/* Calculate a pointer to this CPUs struct mips_static_suspend_state */
	.macro	psstate	dest
	.set	push
	.set	noat
	lw	$1, TI_CPU(gp)
	sll	$1, $1, LONGLOG
	PTR_LA	\dest, __per_cpu_offset
	addu	$1, $1, \dest
	lw	$1, 0($1)
	PTR_LA	\dest, cps_cpu_state
	addu	\dest, \dest, $1
	.set	pop
	.endm

LEAF(mips_cps_pm_save)
	/* Save CPU state */
	SUSPEND_SAVE_REGS
	psstate	t1
	SUSPEND_SAVE_STATIC
	jr	v0
	 nop
	END(mips_cps_pm_save)

LEAF(mips_cps_pm_restore)
	/* Restore CPU state */
	psstate	t1
	RESUME_RESTORE_STATIC
	RESUME_RESTORE_REGS_RETURN
	END(mips_cps_pm_restore)

#endif /* CONFIG_MIPS_CPS_PM && CONFIG_CPU_PM */
Commit	Line	Data
0ee958e1 PB	1	/*
	2	* Copyright (C) 2013 Imagination Technologies
	3	* Author: Paul Burton <paul.burton@imgtec.com>
	4	*
	5	* This program is free software; you can redistribute it and/or modify it
	6	* under the terms of the GNU General Public License as published by the
	7	* Free Software Foundation; either version 2 of the License, or (at your
	8	* option) any later version.
	9	*/
	10
	11	#include <asm/addrspace.h>
	12	#include <asm/asm.h>
	13	#include <asm/asm-offsets.h>
	14	#include <asm/asmmacro.h>
	15	#include <asm/cacheops.h>
6521d9a4	16	#include <asm/eva.h>
0ee958e1	17	#include <asm/mipsregs.h>
245a7868	18	#include <asm/mipsmtregs.h>
3179d37e	19	#include <asm/pm.h>
0ee958e1	20
245a7868 PB	21	#define GCR_CL_COHERENCE_OFS 0x2008
	22	#define GCR_CL_ID_OFS 0x2028
	23
	24	.extern mips_cm_base
	25
	26	.set noreorder
	27
8fe2c547 PB	28	#ifdef CONFIG_64BIT
	29	# define STATUS_BITDEPS ST0_KX
	30	#else
	31	# define STATUS_BITDEPS 0
	32	#endif
	33
609cf6f2 PB	34	#ifdef CONFIG_MIPS_CPS_NS16550
	35
	36	#define DUMP_EXCEP(name) \
	37	PTR_LA a0, 8f; \
	38	jal mips_cps_bev_dump; \
	39	nop; \
	40	TEXT(name)
	41
	42	#else /* !CONFIG_MIPS_CPS_NS16550 */
	43
	44	#define DUMP_EXCEP(name)
	45
	46	#endif /* !CONFIG_MIPS_CPS_NS16550 */
	47
245a7868 PB	48	/*
	49	* Set dest to non-zero if the core supports the MT ASE, else zero. If
	50	* MT is not supported then branch to nomt.
	51	*/
	52	.macro has_mt dest, nomt
	53	mfc0 \dest, CP0_CONFIG
	54	bgez \dest, \nomt
	55	mfc0 \dest, CP0_CONFIG, 1
	56	bgez \dest, \nomt
	57	mfc0 \dest, CP0_CONFIG, 2
	58	bgez \dest, \nomt
	59	mfc0 \dest, CP0_CONFIG, 3
	60	andi \dest, \dest, MIPS_CONF3_MT
	61	beqz \dest, \nomt
1e5fb282	62	nop
245a7868	63	.endm
0ee958e1 PB	64
	65	.section .text.cps-vec
	66	.balign 0x1000
0ee958e1 PB	67
	68	LEAF(mips_cps_core_entry)
	69	/*
946db173 PB	70	* These first 4 bytes will be patched by cps_smp_setup to load the
946db173 PB	71	* CCA to use into register s0.
0ee958e1	72	*/
0155a065	73	.word 0
0ee958e1 PB	74
	75	/* Check whether we're here due to an NMI */
	76	mfc0 k0, CP0_STATUS
	77	and k0, k0, ST0_NMI
	78	beqz k0, not_nmi
	79	nop
	80
	81	/* This is an NMI */
81a02e34	82	PTR_LA k0, nmi_handler
0ee958e1 PB	83	jr k0
	84	nop
	85
	86	not_nmi:
	87	/* Setup Cause */
	88	li t0, CAUSEF_IV
	89	mtc0 t0, CP0_CAUSE
	90
	91	/* Setup Status */
8fe2c547	92	li t0, ST0_CU1 \| ST0_CU0 \| ST0_BEV \| STATUS_BITDEPS
0ee958e1 PB	93	mtc0 t0, CP0_STATUS
	94
	95	/*
	96	* Clear the bits used to index the caches. Note that the architecture
	97	* dictates that writing to any of TagLo or TagHi selects 0 or 2 should
	98	* be valid for all MIPS32 CPUs, even those for which said writes are
	99	* unnecessary.
	100	*/
	101	mtc0 zero, CP0_TAGLO, 0
	102	mtc0 zero, CP0_TAGHI, 0
	103	mtc0 zero, CP0_TAGLO, 2
	104	mtc0 zero, CP0_TAGHI, 2
	105	ehb
	106
	107	/* Primary cache configuration is indicated by Config1 */
	108	mfc0 v0, CP0_CONFIG, 1
	109
	110	/* Detect I-cache line size */
	111	_EXT t0, v0, MIPS_CONF1_IL_SHF, MIPS_CONF1_IL_SZ
	112	beqz t0, icache_done
	113	li t1, 2
	114	sllv t0, t1, t0
	115
	116	/* Detect I-cache size */
	117	_EXT t1, v0, MIPS_CONF1_IS_SHF, MIPS_CONF1_IS_SZ
	118	xori t2, t1, 0x7
	119	beqz t2, 1f
	120	li t3, 32
acac4108	121	addiu t1, t1, 1
0ee958e1 PB	122	sllv t1, t3, t1
	123	1: /* At this point t1 == I-cache sets per way */
	124	_EXT t2, v0, MIPS_CONF1_IA_SHF, MIPS_CONF1_IA_SZ
acac4108	125	addiu t2, t2, 1
0ee958e1 PB	126	mul t1, t1, t0
	127	mul t1, t1, t2
	128
717f1425	129	li a0, CKSEG0
b677bc03	130	PTR_ADD a1, a0, t1
0ee958e1	131	1: cache Index_Store_Tag_I, 0(a0)
b677bc03	132	PTR_ADD a0, a0, t0
0ee958e1 PB	133	bne a0, a1, 1b
	134	nop
	135	icache_done:
	136
	137	/* Detect D-cache line size */
	138	_EXT t0, v0, MIPS_CONF1_DL_SHF, MIPS_CONF1_DL_SZ
	139	beqz t0, dcache_done
	140	li t1, 2
	141	sllv t0, t1, t0
	142
	143	/* Detect D-cache size */
	144	_EXT t1, v0, MIPS_CONF1_DS_SHF, MIPS_CONF1_DS_SZ
	145	xori t2, t1, 0x7
	146	beqz t2, 1f
	147	li t3, 32
acac4108	148	addiu t1, t1, 1
0ee958e1 PB	149	sllv t1, t3, t1
	150	1: /* At this point t1 == D-cache sets per way */
	151	_EXT t2, v0, MIPS_CONF1_DA_SHF, MIPS_CONF1_DA_SZ
acac4108	152	addiu t2, t2, 1
0ee958e1 PB	153	mul t1, t1, t0
	154	mul t1, t1, t2
	155
717f1425	156	li a0, CKSEG0
b677bc03 MC	157	PTR_ADDU a1, a0, t1
b677bc03 MC	158	PTR_SUBU a1, a1, t0
0ee958e1 PB	159	1: cache Index_Store_Tag_D, 0(a0)
0ee958e1 PB	160	bne a0, a1, 1b
b677bc03	161	PTR_ADD a0, a0, t0
0ee958e1 PB	162	dcache_done:
0ee958e1 PB	163
0155a065	164	/* Set Kseg0 CCA to that in s0 */
0ee958e1 PB	165	mfc0 t0, CP0_CONFIG
0ee958e1 PB	166	ori t0, 0x7
0155a065 PB	167	xori t0, 0x7
0155a065 PB	168	or t0, t0, s0
0ee958e1 PB	169	mtc0 t0, CP0_CONFIG
	170	ehb
	171
946db173 PB	172	/* Calculate an uncached address for the CM GCRs */
	173	MFC0 v1, CP0_CMGCRBASE
	174	PTR_SLL v1, v1, 4
	175	PTR_LI t0, UNCAC_BASE
	176	PTR_ADDU v1, v1, t0
	177
0ee958e1 PB	178	/* Enter the coherent domain */
0ee958e1 PB	179	li t0, 0xff
90996511	180	sw t0, GCR_CL_COHERENCE_OFS(v1)
0ee958e1 PB	181	ehb
	182
	183	/* Jump to kseg0 */
81a02e34	184	PTR_LA t0, 1f
0ee958e1 PB	185	jr t0
	186	nop
	187
245a7868 PB	188	/*
	189	* We're up, cached & coherent. Perform any further required core-level
	190	* initialisation.
	191	*/
	192	1: jal mips_cps_core_init
	193	nop
0ee958e1	194
6521d9a4 MC	195	/* Do any EVA initialization if necessary */
	196	eva_init
	197
0ee958e1	198	/*
245a7868 PB	199	* Boot any other VPEs within this core that should be online, and
245a7868 PB	200	* deactivate this VPE if it should be offline.
0ee958e1	201	*/
245a7868 PB	202	jal mips_cps_boot_vpes
245a7868 PB	203	nop
0ee958e1 PB	204
0ee958e1 PB	205	/* Off we go! */
b677bc03 MC	206	PTR_L t1, VPEBOOTCFG_PC(v0)
	207	PTR_L gp, VPEBOOTCFG_GP(v0)
	208	PTR_L sp, VPEBOOTCFG_SP(v0)
0ee958e1 PB	209	jr t1
	210	nop
	211	END(mips_cps_core_entry)
	212
	213	.org 0x200
	214	LEAF(excep_tlbfill)
609cf6f2	215	DUMP_EXCEP("TLB Fill")
0ee958e1 PB	216	b .
	217	nop
	218	END(excep_tlbfill)
	219
	220	.org 0x280
	221	LEAF(excep_xtlbfill)
609cf6f2	222	DUMP_EXCEP("XTLB Fill")
0ee958e1 PB	223	b .
	224	nop
	225	END(excep_xtlbfill)
	226
	227	.org 0x300
	228	LEAF(excep_cache)
609cf6f2	229	DUMP_EXCEP("Cache")
0ee958e1 PB	230	b .
	231	nop
	232	END(excep_cache)
	233
	234	.org 0x380
	235	LEAF(excep_genex)
609cf6f2	236	DUMP_EXCEP("General")
0ee958e1 PB	237	b .
	238	nop
	239	END(excep_genex)
	240
	241	.org 0x400
	242	LEAF(excep_intex)
609cf6f2	243	DUMP_EXCEP("Interrupt")
0ee958e1 PB	244	b .
	245	nop
	246	END(excep_intex)
	247
	248	.org 0x480
	249	LEAF(excep_ejtag)
609cf6f2	250	DUMP_EXCEP("EJTAG")
81a02e34	251	PTR_LA k0, ejtag_debug_handler
0ee958e1 PB	252	jr k0
	253	nop
	254	END(excep_ejtag)
245a7868 PB	255
245a7868 PB	256	LEAF(mips_cps_core_init)
7a63076d	257	#ifdef CONFIG_MIPS_MT_SMP
245a7868 PB	258	/* Check that the core implements the MT ASE */
245a7868 PB	259	has_mt t0, 3f
245a7868 PB	260
245a7868 PB	261	.set push
977e043d	262	.set mips64r2
245a7868 PB	263	.set mt
	264
	265	/* Only allow 1 TC per VPE to execute... */
	266	dmt
	267
	268	/* ...and for the moment only 1 VPE */
	269	dvpe
81a02e34	270	PTR_LA t1, 1f
245a7868 PB	271	jr.hb t1
	272	nop
	273
	274	/* Enter VPE configuration state */
	275	1: mfc0 t0, CP0_MVPCONTROL
	276	ori t0, t0, MVPCONTROL_VPC
	277	mtc0 t0, CP0_MVPCONTROL
	278
	279	/* Retrieve the number of VPEs within the core */
	280	mfc0 t0, CP0_MVPCONF0
	281	srl t0, t0, MVPCONF0_PVPE_SHIFT
	282	andi t0, t0, (MVPCONF0_PVPE >> MVPCONF0_PVPE_SHIFT)
0586ac75	283	addiu ta3, t0, 1
245a7868 PB	284
	285	/* If there's only 1, we're done */
	286	beqz t0, 2f
	287	nop
	288
	289	/* Loop through each VPE within this core */
0586ac75	290	li ta1, 1
245a7868 PB	291
245a7868 PB	292	1: /* Operate on the appropriate TC */
0586ac75	293	mtc0 ta1, CP0_VPECONTROL
245a7868 PB	294	ehb
	295
	296	/* Bind TC to VPE (1:1 TC:VPE mapping) */
0586ac75	297	mttc0 ta1, CP0_TCBIND
245a7868 PB	298
	299	/* Set exclusive TC, non-active, master */
	300	li t0, VPECONF0_MVP
0586ac75	301	sll t1, ta1, VPECONF0_XTC_SHIFT
245a7868 PB	302	or t0, t0, t1
	303	mttc0 t0, CP0_VPECONF0
	304
	305	/* Set TC non-active, non-allocatable */
	306	mttc0 zero, CP0_TCSTATUS
	307
	308	/* Set TC halted */
	309	li t0, TCHALT_H
	310	mttc0 t0, CP0_TCHALT
	311
	312	/* Next VPE */
0586ac75 MC	313	addiu ta1, ta1, 1
0586ac75 MC	314	slt t0, ta1, ta3
245a7868 PB	315	bnez t0, 1b
	316	nop
	317
	318	/* Leave VPE configuration state */
	319	2: mfc0 t0, CP0_MVPCONTROL
	320	xori t0, t0, MVPCONTROL_VPC
	321	mtc0 t0, CP0_MVPCONTROL
	322
	323	3: .set pop
	324	#endif
	325	jr ra
	326	nop
	327	END(mips_cps_core_init)
	328
	329	LEAF(mips_cps_boot_vpes)
	330	/* Retrieve CM base address */
81a02e34	331	PTR_LA t0, mips_cm_base
b677bc03	332	PTR_L t0, 0(t0)
245a7868 PB	333
245a7868 PB	334	/* Calculate a pointer to this cores struct core_boot_config */
90996511	335	lw t0, GCR_CL_ID_OFS(t0)
245a7868 PB	336	li t1, COREBOOTCFG_SIZE
245a7868 PB	337	mul t0, t0, t1
81a02e34	338	PTR_LA t1, mips_cps_core_bootcfg
b677bc03 MC	339	PTR_L t1, 0(t1)
b677bc03 MC	340	PTR_ADDU t0, t0, t1
245a7868 PB	341
245a7868 PB	342	/* Calculate this VPEs ID. If the core doesn't support MT use 0 */
1e5fb282	343	li t9, 0
7a63076d	344	#ifdef CONFIG_MIPS_MT_SMP
0586ac75	345	has_mt ta2, 1f
245a7868 PB	346
	347	/* Find the number of VPEs present in the core */
	348	mfc0 t1, CP0_MVPCONF0
	349	srl t1, t1, MVPCONF0_PVPE_SHIFT
	350	andi t1, t1, MVPCONF0_PVPE >> MVPCONF0_PVPE_SHIFT
acac4108	351	addiu t1, t1, 1
245a7868 PB	352
	353	/* Calculate a mask for the VPE ID from EBase.CPUNum */
	354	clz t1, t1
	355	li t2, 31
	356	subu t1, t2, t1
	357	li t2, 1
	358	sll t1, t2, t1
	359	addiu t1, t1, -1
	360
	361	/* Retrieve the VPE ID from EBase.CPUNum */
	362	mfc0 t9, $15, 1
	363	and t9, t9, t1
a5b0f6db	364	#endif
245a7868 PB	365
	366	1: /* Calculate a pointer to this VPEs struct vpe_boot_config */
	367	li t1, VPEBOOTCFG_SIZE
	368	mul v0, t9, t1
b677bc03 MC	369	PTR_L ta3, COREBOOTCFG_VPECONFIG(t0)
b677bc03 MC	370	PTR_ADDU v0, v0, ta3
245a7868	371
7a63076d	372	#ifdef CONFIG_MIPS_MT_SMP
245a7868 PB	373
245a7868 PB	374	/* If the core doesn't support MT then return */
0586ac75	375	bnez ta2, 1f
245a7868 PB	376	nop
	377	jr ra
	378	nop
	379
	380	.set push
977e043d	381	.set mips64r2
245a7868 PB	382	.set mt
	383
	384	1: /* Enter VPE configuration state */
	385	dvpe
81a02e34	386	PTR_LA t1, 1f
245a7868 PB	387	jr.hb t1
	388	nop
	389	1: mfc0 t1, CP0_MVPCONTROL
	390	ori t1, t1, MVPCONTROL_VPC
	391	mtc0 t1, CP0_MVPCONTROL
	392	ehb
	393
	394	/* Loop through each VPE */
b677bc03	395	PTR_L ta2, COREBOOTCFG_VPEMASK(t0)
0586ac75 MC	396	move t8, ta2
0586ac75 MC	397	li ta1, 0
245a7868 PB	398
245a7868 PB	399	/* Check whether the VPE should be running. If not, skip it */
0586ac75	400	1: andi t0, ta2, 1
245a7868 PB	401	beqz t0, 2f
	402	nop
	403
	404	/* Operate on the appropriate TC */
	405	mfc0 t0, CP0_VPECONTROL
	406	ori t0, t0, VPECONTROL_TARGTC
	407	xori t0, t0, VPECONTROL_TARGTC
0586ac75	408	or t0, t0, ta1
245a7868 PB	409	mtc0 t0, CP0_VPECONTROL
	410	ehb
	411
	412	/* Skip the VPE if its TC is not halted */
	413	mftc0 t0, CP0_TCHALT
	414	beqz t0, 2f
	415	nop
	416
	417	/* Calculate a pointer to the VPEs struct vpe_boot_config */
	418	li t0, VPEBOOTCFG_SIZE
0586ac75 MC	419	mul t0, t0, ta1
0586ac75 MC	420	addu t0, t0, ta3
245a7868 PB	421
	422	/* Set the TC restart PC */
	423	lw t1, VPEBOOTCFG_PC(t0)
	424	mttc0 t1, CP0_TCRESTART
	425
	426	/* Set the TC stack pointer */
	427	lw t1, VPEBOOTCFG_SP(t0)
	428	mttgpr t1, sp
	429
	430	/* Set the TC global pointer */
	431	lw t1, VPEBOOTCFG_GP(t0)
	432	mttgpr t1, gp
	433
	434	/* Copy config from this VPE */
	435	mfc0 t0, CP0_CONFIG
	436	mttc0 t0, CP0_CONFIG
	437
	438	/* Ensure no software interrupts are pending */
	439	mttc0 zero, CP0_CAUSE
	440	mttc0 zero, CP0_STATUS
	441
	442	/* Set TC active, not interrupt exempt */
	443	mftc0 t0, CP0_TCSTATUS
	444	li t1, ~TCSTATUS_IXMT
	445	and t0, t0, t1
	446	ori t0, t0, TCSTATUS_A
	447	mttc0 t0, CP0_TCSTATUS
	448
	449	/* Clear the TC halt bit */
	450	mttc0 zero, CP0_TCHALT
	451
	452	/* Set VPE active */
	453	mftc0 t0, CP0_VPECONF0
	454	ori t0, t0, VPECONF0_VPA
	455	mttc0 t0, CP0_VPECONF0
	456
	457	/* Next VPE */
0586ac75 MC	458	2: srl ta2, ta2, 1
	459	addiu ta1, ta1, 1
	460	bnez ta2, 1b
245a7868 PB	461	nop
	462
	463	/* Leave VPE configuration state */
	464	mfc0 t1, CP0_MVPCONTROL
	465	xori t1, t1, MVPCONTROL_VPC
	466	mtc0 t1, CP0_MVPCONTROL
	467	ehb
	468	evpe
	469
	470	/* Check whether this VPE is meant to be running */
	471	li t0, 1
	472	sll t0, t0, t9
	473	and t0, t0, t8
	474	bnez t0, 2f
	475	nop
	476
	477	/* This VPE should be offline, halt the TC */
	478	li t0, TCHALT_H
	479	mtc0 t0, CP0_TCHALT
81a02e34	480	PTR_LA t0, 1f
245a7868 PB	481	1: jr.hb t0
	482	nop
	483
	484	2: .set pop
	485
7a63076d	486	#endif /* CONFIG_MIPS_MT_SMP */
245a7868 PB	487
	488	/* Return */
	489	jr ra
	490	nop
	491	END(mips_cps_boot_vpes)
3179d37e PB	492
	493	#if defined(CONFIG_MIPS_CPS_PM) && defined(CONFIG_CPU_PM)
	494
	495	/* Calculate a pointer to this CPUs struct mips_static_suspend_state */
	496	.macro psstate dest
	497	.set push
	498	.set noat
	499	lw $1, TI_CPU(gp)
	500	sll $1, $1, LONGLOG
81a02e34	501	PTR_LA \dest, __per_cpu_offset
3179d37e PB	502	addu $1, $1, \dest
3179d37e PB	503	lw $1, 0($1)
81a02e34	504	PTR_LA \dest, cps_cpu_state
3179d37e PB	505	addu \dest, \dest, $1
	506	.set pop
	507	.endm
	508
	509	LEAF(mips_cps_pm_save)
	510	/* Save CPU state */
	511	SUSPEND_SAVE_REGS
	512	psstate t1
	513	SUSPEND_SAVE_STATIC
	514	jr v0
	515	nop
	516	END(mips_cps_pm_save)
	517
	518	LEAF(mips_cps_pm_restore)
	519	/* Restore CPU state */
	520	psstate t1
	521	RESUME_RESTORE_STATIC
	522	RESUME_RESTORE_REGS_RETURN
	523	END(mips_cps_pm_restore)
	524
	525	#endif /* CONFIG_MIPS_CPS_PM && CONFIG_CPU_PM */