[mirror_ubuntu-focal-kernel.git] / arch / mips / kernel / cps-vec.S

/*
 * Copyright (C) 2013 Imagination Technologies
 * Author: Paul Burton <paul.burton@imgtec.com>
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 */

#include <asm/addrspace.h>
#include <asm/asm.h>
#include <asm/asm-offsets.h>
#include <asm/asmmacro.h>
#include <asm/cacheops.h>
#include <asm/eva.h>
#include <asm/mipsregs.h>
#include <asm/mipsmtregs.h>
#include <asm/pm.h>

#define GCR_CL_COHERENCE_OFS	0x2008
#define GCR_CL_ID_OFS		0x2028

.extern mips_cm_base

.set noreorder

#ifdef CONFIG_64BIT
# define STATUS_BITDEPS		ST0_KX
#else
# define STATUS_BITDEPS		0
#endif

#ifdef CONFIG_MIPS_CPS_NS16550

#define DUMP_EXCEP(name)		\
	PTR_LA	a0, 8f;			\
	jal	mips_cps_bev_dump;	\
	 nop;				\
	TEXT(name)

#else /* !CONFIG_MIPS_CPS_NS16550 */

#define DUMP_EXCEP(name)

#endif /* !CONFIG_MIPS_CPS_NS16550 */

	/*
	 * Set dest to non-zero if the core supports the MT ASE, else zero. If
	 * MT is not supported then branch to nomt.
	 */
	.macro	has_mt	dest, nomt
	mfc0	\dest, CP0_CONFIG, 1
	bgez	\dest, \nomt
	 mfc0	\dest, CP0_CONFIG, 2
	bgez	\dest, \nomt
	 mfc0	\dest, CP0_CONFIG, 3
	andi	\dest, \dest, MIPS_CONF3_MT
	beqz	\dest, \nomt
	 nop
	.endm

.section .text.cps-vec
.balign 0x1000

LEAF(mips_cps_core_entry)
	/*
	 * These first 4 bytes will be patched by cps_smp_setup to load the
	 * CCA to use into register s0.
	 */
	.word	0

	/* Check whether we're here due to an NMI */
	mfc0	k0, CP0_STATUS
	and	k0, k0, ST0_NMI
	beqz	k0, not_nmi
	 nop

	/* This is an NMI */
	PTR_LA	k0, nmi_handler
	jr	k0
	 nop

not_nmi:
	/* Setup Cause */
	li	t0, CAUSEF_IV
	mtc0	t0, CP0_CAUSE

	/* Setup Status */
	li	t0, ST0_CU1 | ST0_CU0 | ST0_BEV | STATUS_BITDEPS
	mtc0	t0, CP0_STATUS

	/*
	 * Clear the bits used to index the caches. Note that the architecture
	 * dictates that writing to any of TagLo or TagHi selects 0 or 2 should
	 * be valid for all MIPS32 CPUs, even those for which said writes are
	 * unnecessary.
	 */
	mtc0	zero, CP0_TAGLO, 0
	mtc0	zero, CP0_TAGHI, 0
	mtc0	zero, CP0_TAGLO, 2
	mtc0	zero, CP0_TAGHI, 2
	ehb

	/* Primary cache configuration is indicated by Config1 */
	mfc0	v0, CP0_CONFIG, 1

	/* Detect I-cache line size */
	_EXT	t0, v0, MIPS_CONF1_IL_SHF, MIPS_CONF1_IL_SZ
	beqz	t0, icache_done
	 li	t1, 2
	sllv	t0, t1, t0

	/* Detect I-cache size */
	_EXT	t1, v0, MIPS_CONF1_IS_SHF, MIPS_CONF1_IS_SZ
	xori	t2, t1, 0x7
	beqz	t2, 1f
	 li	t3, 32
	addiu	t1, t1, 1
	sllv	t1, t3, t1
1:	/* At this point t1 == I-cache sets per way */
	_EXT	t2, v0, MIPS_CONF1_IA_SHF, MIPS_CONF1_IA_SZ
	addiu	t2, t2, 1
	mul	t1, t1, t0
	mul	t1, t1, t2

	li	a0, CKSEG0
	PTR_ADD	a1, a0, t1
1:	cache	Index_Store_Tag_I, 0(a0)
	PTR_ADD	a0, a0, t0
	bne	a0, a1, 1b
	 nop
icache_done:

	/* Detect D-cache line size */
	_EXT	t0, v0, MIPS_CONF1_DL_SHF, MIPS_CONF1_DL_SZ
	beqz	t0, dcache_done
	 li	t1, 2
	sllv	t0, t1, t0

	/* Detect D-cache size */
	_EXT	t1, v0, MIPS_CONF1_DS_SHF, MIPS_CONF1_DS_SZ
	xori	t2, t1, 0x7
	beqz	t2, 1f
	 li	t3, 32
	addiu	t1, t1, 1
	sllv	t1, t3, t1
1:	/* At this point t1 == D-cache sets per way */
	_EXT	t2, v0, MIPS_CONF1_DA_SHF, MIPS_CONF1_DA_SZ
	addiu	t2, t2, 1
	mul	t1, t1, t0
	mul	t1, t1, t2

	li	a0, CKSEG0
	PTR_ADDU a1, a0, t1
	PTR_SUBU a1, a1, t0
1:	cache	Index_Store_Tag_D, 0(a0)
	bne	a0, a1, 1b
	 PTR_ADD a0, a0, t0
dcache_done:

	/* Set Kseg0 CCA to that in s0 */
	mfc0	t0, CP0_CONFIG
	ori	t0, 0x7
	xori	t0, 0x7
	or	t0, t0, s0
	mtc0	t0, CP0_CONFIG
	ehb

	/* Calculate an uncached address for the CM GCRs */
	MFC0	v1, CP0_CMGCRBASE
	PTR_SLL	v1, v1, 4
	PTR_LI	t0, UNCAC_BASE
	PTR_ADDU v1, v1, t0

	/* Enter the coherent domain */
	li	t0, 0xff
	sw	t0, GCR_CL_COHERENCE_OFS(v1)
	ehb

	/* Jump to kseg0 */
	PTR_LA	t0, 1f
	jr	t0
	 nop

	/*
	 * We're up, cached & coherent. Perform any further required core-level
	 * initialisation.
	 */
1:	jal	mips_cps_core_init
	 nop

	/* Do any EVA initialization if necessary */
	eva_init

	/*
	 * Boot any other VPEs within this core that should be online, and
	 * deactivate this VPE if it should be offline.
	 */
	jal	mips_cps_boot_vpes
	 nop

	/* Off we go! */
	PTR_L	t1, VPEBOOTCFG_PC(v0)
	PTR_L	gp, VPEBOOTCFG_GP(v0)
	PTR_L	sp, VPEBOOTCFG_SP(v0)
	jr	t1
	 nop
	END(mips_cps_core_entry)

.org 0x200
LEAF(excep_tlbfill)
	DUMP_EXCEP("TLB Fill")
	b	.
	 nop
	END(excep_tlbfill)

.org 0x280
LEAF(excep_xtlbfill)
	DUMP_EXCEP("XTLB Fill")
	b	.
	 nop
	END(excep_xtlbfill)

.org 0x300
LEAF(excep_cache)
	DUMP_EXCEP("Cache")
	b	.
	 nop
	END(excep_cache)

.org 0x380
LEAF(excep_genex)
	DUMP_EXCEP("General")
	b	.
	 nop
	END(excep_genex)

.org 0x400
LEAF(excep_intex)
	DUMP_EXCEP("Interrupt")
	b	.
	 nop
	END(excep_intex)

.org 0x480
LEAF(excep_ejtag)
	DUMP_EXCEP("EJTAG")
	PTR_LA	k0, ejtag_debug_handler
	jr	k0
	 nop
	END(excep_ejtag)

LEAF(mips_cps_core_init)
#ifdef CONFIG_MIPS_MT_SMP
	/* Check that the core implements the MT ASE */
	has_mt	t0, 3f

	.set	push
	.set	mt

	/* Only allow 1 TC per VPE to execute... */
	dmt

	/* ...and for the moment only 1 VPE */
	dvpe
	PTR_LA	t1, 1f
	jr.hb	t1
	 nop

	/* Enter VPE configuration state */
1:	mfc0	t0, CP0_MVPCONTROL
	ori	t0, t0, MVPCONTROL_VPC
	mtc0	t0, CP0_MVPCONTROL

	/* Retrieve the number of VPEs within the core */
	mfc0	t0, CP0_MVPCONF0
	srl	t0, t0, MVPCONF0_PVPE_SHIFT
	andi	t0, t0, (MVPCONF0_PVPE >> MVPCONF0_PVPE_SHIFT)
	addiu	ta3, t0, 1

	/* If there's only 1, we're done */
	beqz	t0, 2f
	 nop

	/* Loop through each VPE within this core */
	li	ta1, 1

1:	/* Operate on the appropriate TC */
	mtc0	ta1, CP0_VPECONTROL
	ehb

	/* Bind TC to VPE (1:1 TC:VPE mapping) */
	mttc0	ta1, CP0_TCBIND

	/* Set exclusive TC, non-active, master */
	li	t0, VPECONF0_MVP
	sll	t1, ta1, VPECONF0_XTC_SHIFT
	or	t0, t0, t1
	mttc0	t0, CP0_VPECONF0

	/* Set TC non-active, non-allocatable */
	mttc0	zero, CP0_TCSTATUS

	/* Set TC halted */
	li	t0, TCHALT_H
	mttc0	t0, CP0_TCHALT

	/* Next VPE */
	addiu	ta1, ta1, 1
	slt	t0, ta1, ta3
	bnez	t0, 1b
	 nop

	/* Leave VPE configuration state */
2:	mfc0	t0, CP0_MVPCONTROL
	xori	t0, t0, MVPCONTROL_VPC
	mtc0	t0, CP0_MVPCONTROL

3:	.set	pop
#endif
	jr	ra
	 nop
	END(mips_cps_core_init)

LEAF(mips_cps_boot_vpes)
	/* Retrieve CM base address */
	PTR_LA	t0, mips_cm_base
	PTR_L	t0, 0(t0)

	/* Calculate a pointer to this cores struct core_boot_config */
	lw	t0, GCR_CL_ID_OFS(t0)
	li	t1, COREBOOTCFG_SIZE
	mul	t0, t0, t1
	PTR_LA	t1, mips_cps_core_bootcfg
	PTR_L	t1, 0(t1)
	PTR_ADDU t0, t0, t1

	/* Calculate this VPEs ID. If the core doesn't support MT use 0 */
	li	t9, 0
#ifdef CONFIG_MIPS_MT_SMP
	has_mt	ta2, 1f

	/* Find the number of VPEs present in the core */
	mfc0	t1, CP0_MVPCONF0
	srl	t1, t1, MVPCONF0_PVPE_SHIFT
	andi	t1, t1, MVPCONF0_PVPE >> MVPCONF0_PVPE_SHIFT
	addiu	t1, t1, 1

	/* Calculate a mask for the VPE ID from EBase.CPUNum */
	clz	t1, t1
	li	t2, 31
	subu	t1, t2, t1
	li	t2, 1
	sll	t1, t2, t1
	addiu	t1, t1, -1

	/* Retrieve the VPE ID from EBase.CPUNum */
	mfc0	t9, $15, 1
	and	t9, t9, t1
#endif

1:	/* Calculate a pointer to this VPEs struct vpe_boot_config */
	li	t1, VPEBOOTCFG_SIZE
	mul	v0, t9, t1
	PTR_L	ta3, COREBOOTCFG_VPECONFIG(t0)
	PTR_ADDU v0, v0, ta3

#ifdef CONFIG_MIPS_MT_SMP

	/* If the core doesn't support MT then return */
	bnez	ta2, 1f
	 nop
	jr	ra
	 nop

	.set	push
	.set	mt

1:	/* Enter VPE configuration state */
	dvpe
	PTR_LA	t1, 1f
	jr.hb	t1
	 nop
1:	mfc0	t1, CP0_MVPCONTROL
	ori	t1, t1, MVPCONTROL_VPC
	mtc0	t1, CP0_MVPCONTROL
	ehb

	/* Loop through each VPE */
	PTR_L	ta2, COREBOOTCFG_VPEMASK(t0)
	move	t8, ta2
	li	ta1, 0

	/* Check whether the VPE should be running. If not, skip it */
1:	andi	t0, ta2, 1
	beqz	t0, 2f
	 nop

	/* Operate on the appropriate TC */
	mfc0	t0, CP0_VPECONTROL
	ori	t0, t0, VPECONTROL_TARGTC
	xori	t0, t0, VPECONTROL_TARGTC
	or	t0, t0, ta1
	mtc0	t0, CP0_VPECONTROL
	ehb

	/* Skip the VPE if its TC is not halted */
	mftc0	t0, CP0_TCHALT
	beqz	t0, 2f
	 nop

	/* Calculate a pointer to the VPEs struct vpe_boot_config */
	li	t0, VPEBOOTCFG_SIZE
	mul	t0, t0, ta1
	addu	t0, t0, ta3

	/* Set the TC restart PC */
	lw	t1, VPEBOOTCFG_PC(t0)
	mttc0	t1, CP0_TCRESTART

	/* Set the TC stack pointer */
	lw	t1, VPEBOOTCFG_SP(t0)
	mttgpr	t1, sp

	/* Set the TC global pointer */
	lw	t1, VPEBOOTCFG_GP(t0)
	mttgpr	t1, gp

	/* Copy config from this VPE */
	mfc0	t0, CP0_CONFIG
	mttc0	t0, CP0_CONFIG

	/* Ensure no software interrupts are pending */
	mttc0	zero, CP0_CAUSE
	mttc0	zero, CP0_STATUS

	/* Set TC active, not interrupt exempt */
	mftc0	t0, CP0_TCSTATUS
	li	t1, ~TCSTATUS_IXMT
	and	t0, t0, t1
	ori	t0, t0, TCSTATUS_A
	mttc0	t0, CP0_TCSTATUS

	/* Clear the TC halt bit */
	mttc0	zero, CP0_TCHALT

	/* Set VPE active */
	mftc0	t0, CP0_VPECONF0
	ori	t0, t0, VPECONF0_VPA
	mttc0	t0, CP0_VPECONF0

	/* Next VPE */
2:	srl	ta2, ta2, 1
	addiu	ta1, ta1, 1
	bnez	ta2, 1b
	 nop

	/* Leave VPE configuration state */
	mfc0	t1, CP0_MVPCONTROL
	xori	t1, t1, MVPCONTROL_VPC
	mtc0	t1, CP0_MVPCONTROL
	ehb
	evpe

	/* Check whether this VPE is meant to be running */
	li	t0, 1
	sll	t0, t0, t9
	and	t0, t0, t8
	bnez	t0, 2f
	 nop

	/* This VPE should be offline, halt the TC */
	li	t0, TCHALT_H
	mtc0	t0, CP0_TCHALT
	PTR_LA	t0, 1f
1:	jr.hb	t0
	 nop

2:	.set	pop

#endif /* CONFIG_MIPS_MT_SMP */

	/* Return */
	jr	ra
	 nop
	END(mips_cps_boot_vpes)

#if defined(CONFIG_MIPS_CPS_PM) && defined(CONFIG_CPU_PM)

	/* Calculate a pointer to this CPUs struct mips_static_suspend_state */
	.macro	psstate	dest
	.set	push
	.set	noat
	lw	$1, TI_CPU(gp)
	sll	$1, $1, LONGLOG
	PTR_LA	\dest, __per_cpu_offset
	addu	$1, $1, \dest
	lw	$1, 0($1)
	PTR_LA	\dest, cps_cpu_state
	addu	\dest, \dest, $1
	.set	pop
	.endm

LEAF(mips_cps_pm_save)
	/* Save CPU state */
	SUSPEND_SAVE_REGS
	psstate	t1
	SUSPEND_SAVE_STATIC
	jr	v0
	 nop
	END(mips_cps_pm_save)

LEAF(mips_cps_pm_restore)
	/* Restore CPU state */
	psstate	t1
	RESUME_RESTORE_STATIC
	RESUME_RESTORE_REGS_RETURN
	END(mips_cps_pm_restore)

#endif /* CONFIG_MIPS_CPS_PM && CONFIG_CPU_PM */
Commit	Line	Data
0ee958e1 PB	1	/*
	2	* Copyright (C) 2013 Imagination Technologies
	3	* Author: Paul Burton <paul.burton@imgtec.com>
	4	*
	5	* This program is free software; you can redistribute it and/or modify it
	6	* under the terms of the GNU General Public License as published by the
	7	* Free Software Foundation; either version 2 of the License, or (at your
	8	* option) any later version.
	9	*/
	10
	11	#include <asm/addrspace.h>
	12	#include <asm/asm.h>
	13	#include <asm/asm-offsets.h>
	14	#include <asm/asmmacro.h>
	15	#include <asm/cacheops.h>
6521d9a4	16	#include <asm/eva.h>
0ee958e1	17	#include <asm/mipsregs.h>
245a7868	18	#include <asm/mipsmtregs.h>
3179d37e	19	#include <asm/pm.h>
0ee958e1	20
245a7868 PB	21	#define GCR_CL_COHERENCE_OFS 0x2008
	22	#define GCR_CL_ID_OFS 0x2028
	23
	24	.extern mips_cm_base
	25
	26	.set noreorder
	27
8fe2c547 PB	28	#ifdef CONFIG_64BIT
	29	# define STATUS_BITDEPS ST0_KX
	30	#else
	31	# define STATUS_BITDEPS 0
	32	#endif
	33
609cf6f2 PB	34	#ifdef CONFIG_MIPS_CPS_NS16550
	35
	36	#define DUMP_EXCEP(name) \
	37	PTR_LA a0, 8f; \
	38	jal mips_cps_bev_dump; \
	39	nop; \
	40	TEXT(name)
	41
	42	#else /* !CONFIG_MIPS_CPS_NS16550 */
	43
	44	#define DUMP_EXCEP(name)
	45
	46	#endif /* !CONFIG_MIPS_CPS_NS16550 */
	47
245a7868 PB	48	/*
	49	* Set dest to non-zero if the core supports the MT ASE, else zero. If
	50	* MT is not supported then branch to nomt.
	51	*/
	52	.macro has_mt dest, nomt
192fbc20	53	mfc0 \dest, CP0_CONFIG, 1
245a7868 PB	54	bgez \dest, \nomt
	55	mfc0 \dest, CP0_CONFIG, 2
	56	bgez \dest, \nomt
	57	mfc0 \dest, CP0_CONFIG, 3
	58	andi \dest, \dest, MIPS_CONF3_MT
	59	beqz \dest, \nomt
1e5fb282	60	nop
245a7868	61	.endm
0ee958e1 PB	62
	63	.section .text.cps-vec
	64	.balign 0x1000
0ee958e1 PB	65
	66	LEAF(mips_cps_core_entry)
	67	/*
946db173 PB	68	* These first 4 bytes will be patched by cps_smp_setup to load the
946db173 PB	69	* CCA to use into register s0.
0ee958e1	70	*/
0155a065	71	.word 0
0ee958e1 PB	72
	73	/* Check whether we're here due to an NMI */
	74	mfc0 k0, CP0_STATUS
	75	and k0, k0, ST0_NMI
	76	beqz k0, not_nmi
	77	nop
	78
	79	/* This is an NMI */
81a02e34	80	PTR_LA k0, nmi_handler
0ee958e1 PB	81	jr k0
	82	nop
	83
	84	not_nmi:
	85	/* Setup Cause */
	86	li t0, CAUSEF_IV
	87	mtc0 t0, CP0_CAUSE
	88
	89	/* Setup Status */
8fe2c547	90	li t0, ST0_CU1 \| ST0_CU0 \| ST0_BEV \| STATUS_BITDEPS
0ee958e1 PB	91	mtc0 t0, CP0_STATUS
	92
	93	/*
	94	* Clear the bits used to index the caches. Note that the architecture
	95	* dictates that writing to any of TagLo or TagHi selects 0 or 2 should
	96	* be valid for all MIPS32 CPUs, even those for which said writes are
	97	* unnecessary.
	98	*/
	99	mtc0 zero, CP0_TAGLO, 0
	100	mtc0 zero, CP0_TAGHI, 0
	101	mtc0 zero, CP0_TAGLO, 2
	102	mtc0 zero, CP0_TAGHI, 2
	103	ehb
	104
	105	/* Primary cache configuration is indicated by Config1 */
	106	mfc0 v0, CP0_CONFIG, 1
	107
	108	/* Detect I-cache line size */
	109	_EXT t0, v0, MIPS_CONF1_IL_SHF, MIPS_CONF1_IL_SZ
	110	beqz t0, icache_done
	111	li t1, 2
	112	sllv t0, t1, t0
	113
	114	/* Detect I-cache size */
	115	_EXT t1, v0, MIPS_CONF1_IS_SHF, MIPS_CONF1_IS_SZ
	116	xori t2, t1, 0x7
	117	beqz t2, 1f
	118	li t3, 32
acac4108	119	addiu t1, t1, 1
0ee958e1 PB	120	sllv t1, t3, t1
	121	1: /* At this point t1 == I-cache sets per way */
	122	_EXT t2, v0, MIPS_CONF1_IA_SHF, MIPS_CONF1_IA_SZ
acac4108	123	addiu t2, t2, 1
0ee958e1 PB	124	mul t1, t1, t0
	125	mul t1, t1, t2
	126
717f1425	127	li a0, CKSEG0
b677bc03	128	PTR_ADD a1, a0, t1
0ee958e1	129	1: cache Index_Store_Tag_I, 0(a0)
b677bc03	130	PTR_ADD a0, a0, t0
0ee958e1 PB	131	bne a0, a1, 1b
	132	nop
	133	icache_done:
	134
	135	/* Detect D-cache line size */
	136	_EXT t0, v0, MIPS_CONF1_DL_SHF, MIPS_CONF1_DL_SZ
	137	beqz t0, dcache_done
	138	li t1, 2
	139	sllv t0, t1, t0
	140
	141	/* Detect D-cache size */
	142	_EXT t1, v0, MIPS_CONF1_DS_SHF, MIPS_CONF1_DS_SZ
	143	xori t2, t1, 0x7
	144	beqz t2, 1f
	145	li t3, 32
acac4108	146	addiu t1, t1, 1
0ee958e1 PB	147	sllv t1, t3, t1
	148	1: /* At this point t1 == D-cache sets per way */
	149	_EXT t2, v0, MIPS_CONF1_DA_SHF, MIPS_CONF1_DA_SZ
acac4108	150	addiu t2, t2, 1
0ee958e1 PB	151	mul t1, t1, t0
	152	mul t1, t1, t2
	153
717f1425	154	li a0, CKSEG0
b677bc03 MC	155	PTR_ADDU a1, a0, t1
b677bc03 MC	156	PTR_SUBU a1, a1, t0
0ee958e1 PB	157	1: cache Index_Store_Tag_D, 0(a0)
0ee958e1 PB	158	bne a0, a1, 1b
b677bc03	159	PTR_ADD a0, a0, t0
0ee958e1 PB	160	dcache_done:
0ee958e1 PB	161
0155a065	162	/* Set Kseg0 CCA to that in s0 */
0ee958e1 PB	163	mfc0 t0, CP0_CONFIG
0ee958e1 PB	164	ori t0, 0x7
0155a065 PB	165	xori t0, 0x7
0155a065 PB	166	or t0, t0, s0
0ee958e1 PB	167	mtc0 t0, CP0_CONFIG
	168	ehb
	169
946db173 PB	170	/* Calculate an uncached address for the CM GCRs */
	171	MFC0 v1, CP0_CMGCRBASE
	172	PTR_SLL v1, v1, 4
	173	PTR_LI t0, UNCAC_BASE
	174	PTR_ADDU v1, v1, t0
	175
0ee958e1 PB	176	/* Enter the coherent domain */
0ee958e1 PB	177	li t0, 0xff
90996511	178	sw t0, GCR_CL_COHERENCE_OFS(v1)
0ee958e1 PB	179	ehb
	180
	181	/* Jump to kseg0 */
81a02e34	182	PTR_LA t0, 1f
0ee958e1 PB	183	jr t0
	184	nop
	185
245a7868 PB	186	/*
	187	* We're up, cached & coherent. Perform any further required core-level
	188	* initialisation.
	189	*/
	190	1: jal mips_cps_core_init
	191	nop
0ee958e1	192
6521d9a4 MC	193	/* Do any EVA initialization if necessary */
	194	eva_init
	195
0ee958e1	196	/*
245a7868 PB	197	* Boot any other VPEs within this core that should be online, and
245a7868 PB	198	* deactivate this VPE if it should be offline.
0ee958e1	199	*/
245a7868 PB	200	jal mips_cps_boot_vpes
245a7868 PB	201	nop
0ee958e1 PB	202
0ee958e1 PB	203	/* Off we go! */
b677bc03 MC	204	PTR_L t1, VPEBOOTCFG_PC(v0)
	205	PTR_L gp, VPEBOOTCFG_GP(v0)
	206	PTR_L sp, VPEBOOTCFG_SP(v0)
0ee958e1 PB	207	jr t1
	208	nop
	209	END(mips_cps_core_entry)
	210
	211	.org 0x200
	212	LEAF(excep_tlbfill)
609cf6f2	213	DUMP_EXCEP("TLB Fill")
0ee958e1 PB	214	b .
	215	nop
	216	END(excep_tlbfill)
	217
	218	.org 0x280
	219	LEAF(excep_xtlbfill)
609cf6f2	220	DUMP_EXCEP("XTLB Fill")
0ee958e1 PB	221	b .
	222	nop
	223	END(excep_xtlbfill)
	224
	225	.org 0x300
	226	LEAF(excep_cache)
609cf6f2	227	DUMP_EXCEP("Cache")
0ee958e1 PB	228	b .
	229	nop
	230	END(excep_cache)
	231
	232	.org 0x380
	233	LEAF(excep_genex)
609cf6f2	234	DUMP_EXCEP("General")
0ee958e1 PB	235	b .
	236	nop
	237	END(excep_genex)
	238
	239	.org 0x400
	240	LEAF(excep_intex)
609cf6f2	241	DUMP_EXCEP("Interrupt")
0ee958e1 PB	242	b .
	243	nop
	244	END(excep_intex)
	245
	246	.org 0x480
	247	LEAF(excep_ejtag)
609cf6f2	248	DUMP_EXCEP("EJTAG")
81a02e34	249	PTR_LA k0, ejtag_debug_handler
0ee958e1 PB	250	jr k0
	251	nop
	252	END(excep_ejtag)
245a7868 PB	253
245a7868 PB	254	LEAF(mips_cps_core_init)
7a63076d	255	#ifdef CONFIG_MIPS_MT_SMP
245a7868 PB	256	/* Check that the core implements the MT ASE */
245a7868 PB	257	has_mt t0, 3f
245a7868 PB	258
	259	.set push
	260	.set mt
	261
	262	/* Only allow 1 TC per VPE to execute... */
	263	dmt
	264
	265	/* ...and for the moment only 1 VPE */
	266	dvpe
81a02e34	267	PTR_LA t1, 1f
245a7868 PB	268	jr.hb t1
	269	nop
	270
	271	/* Enter VPE configuration state */
	272	1: mfc0 t0, CP0_MVPCONTROL
	273	ori t0, t0, MVPCONTROL_VPC
	274	mtc0 t0, CP0_MVPCONTROL
	275
	276	/* Retrieve the number of VPEs within the core */
	277	mfc0 t0, CP0_MVPCONF0
	278	srl t0, t0, MVPCONF0_PVPE_SHIFT
	279	andi t0, t0, (MVPCONF0_PVPE >> MVPCONF0_PVPE_SHIFT)
0586ac75	280	addiu ta3, t0, 1
245a7868 PB	281
	282	/* If there's only 1, we're done */
	283	beqz t0, 2f
	284	nop
	285
	286	/* Loop through each VPE within this core */
0586ac75	287	li ta1, 1
245a7868 PB	288
245a7868 PB	289	1: /* Operate on the appropriate TC */
0586ac75	290	mtc0 ta1, CP0_VPECONTROL
245a7868 PB	291	ehb
	292
	293	/* Bind TC to VPE (1:1 TC:VPE mapping) */
0586ac75	294	mttc0 ta1, CP0_TCBIND
245a7868 PB	295
	296	/* Set exclusive TC, non-active, master */
	297	li t0, VPECONF0_MVP
0586ac75	298	sll t1, ta1, VPECONF0_XTC_SHIFT
245a7868 PB	299	or t0, t0, t1
	300	mttc0 t0, CP0_VPECONF0
	301
	302	/* Set TC non-active, non-allocatable */
	303	mttc0 zero, CP0_TCSTATUS
	304
	305	/* Set TC halted */
	306	li t0, TCHALT_H
	307	mttc0 t0, CP0_TCHALT
	308
	309	/* Next VPE */
0586ac75 MC	310	addiu ta1, ta1, 1
0586ac75 MC	311	slt t0, ta1, ta3
245a7868 PB	312	bnez t0, 1b
	313	nop
	314
	315	/* Leave VPE configuration state */
	316	2: mfc0 t0, CP0_MVPCONTROL
	317	xori t0, t0, MVPCONTROL_VPC
	318	mtc0 t0, CP0_MVPCONTROL
	319
	320	3: .set pop
	321	#endif
	322	jr ra
	323	nop
	324	END(mips_cps_core_init)
	325
	326	LEAF(mips_cps_boot_vpes)
	327	/* Retrieve CM base address */
81a02e34	328	PTR_LA t0, mips_cm_base
b677bc03	329	PTR_L t0, 0(t0)
245a7868 PB	330
245a7868 PB	331	/* Calculate a pointer to this cores struct core_boot_config */
90996511	332	lw t0, GCR_CL_ID_OFS(t0)
245a7868 PB	333	li t1, COREBOOTCFG_SIZE
245a7868 PB	334	mul t0, t0, t1
81a02e34	335	PTR_LA t1, mips_cps_core_bootcfg
b677bc03 MC	336	PTR_L t1, 0(t1)
b677bc03 MC	337	PTR_ADDU t0, t0, t1
245a7868 PB	338
245a7868 PB	339	/* Calculate this VPEs ID. If the core doesn't support MT use 0 */
1e5fb282	340	li t9, 0
7a63076d	341	#ifdef CONFIG_MIPS_MT_SMP
0586ac75	342	has_mt ta2, 1f
245a7868 PB	343
	344	/* Find the number of VPEs present in the core */
	345	mfc0 t1, CP0_MVPCONF0
	346	srl t1, t1, MVPCONF0_PVPE_SHIFT
	347	andi t1, t1, MVPCONF0_PVPE >> MVPCONF0_PVPE_SHIFT
acac4108	348	addiu t1, t1, 1
245a7868 PB	349
	350	/* Calculate a mask for the VPE ID from EBase.CPUNum */
	351	clz t1, t1
	352	li t2, 31
	353	subu t1, t2, t1
	354	li t2, 1
	355	sll t1, t2, t1
	356	addiu t1, t1, -1
	357
	358	/* Retrieve the VPE ID from EBase.CPUNum */
	359	mfc0 t9, $15, 1
	360	and t9, t9, t1
a5b0f6db	361	#endif
245a7868 PB	362
	363	1: /* Calculate a pointer to this VPEs struct vpe_boot_config */
	364	li t1, VPEBOOTCFG_SIZE
	365	mul v0, t9, t1
b677bc03 MC	366	PTR_L ta3, COREBOOTCFG_VPECONFIG(t0)
b677bc03 MC	367	PTR_ADDU v0, v0, ta3
245a7868	368
7a63076d	369	#ifdef CONFIG_MIPS_MT_SMP
245a7868 PB	370
245a7868 PB	371	/* If the core doesn't support MT then return */
0586ac75	372	bnez ta2, 1f
245a7868 PB	373	nop
	374	jr ra
	375	nop
	376
	377	.set push
	378	.set mt
	379
	380	1: /* Enter VPE configuration state */
	381	dvpe
81a02e34	382	PTR_LA t1, 1f
245a7868 PB	383	jr.hb t1
	384	nop
	385	1: mfc0 t1, CP0_MVPCONTROL
	386	ori t1, t1, MVPCONTROL_VPC
	387	mtc0 t1, CP0_MVPCONTROL
	388	ehb
	389
	390	/* Loop through each VPE */
b677bc03	391	PTR_L ta2, COREBOOTCFG_VPEMASK(t0)
0586ac75 MC	392	move t8, ta2
0586ac75 MC	393	li ta1, 0
245a7868 PB	394
245a7868 PB	395	/* Check whether the VPE should be running. If not, skip it */
0586ac75	396	1: andi t0, ta2, 1
245a7868 PB	397	beqz t0, 2f
	398	nop
	399
	400	/* Operate on the appropriate TC */
	401	mfc0 t0, CP0_VPECONTROL
	402	ori t0, t0, VPECONTROL_TARGTC
	403	xori t0, t0, VPECONTROL_TARGTC
0586ac75	404	or t0, t0, ta1
245a7868 PB	405	mtc0 t0, CP0_VPECONTROL
	406	ehb
	407
	408	/* Skip the VPE if its TC is not halted */
	409	mftc0 t0, CP0_TCHALT
	410	beqz t0, 2f
	411	nop
	412
	413	/* Calculate a pointer to the VPEs struct vpe_boot_config */
	414	li t0, VPEBOOTCFG_SIZE
0586ac75 MC	415	mul t0, t0, ta1
0586ac75 MC	416	addu t0, t0, ta3
245a7868 PB	417
	418	/* Set the TC restart PC */
	419	lw t1, VPEBOOTCFG_PC(t0)
	420	mttc0 t1, CP0_TCRESTART
	421
	422	/* Set the TC stack pointer */
	423	lw t1, VPEBOOTCFG_SP(t0)
	424	mttgpr t1, sp
	425
	426	/* Set the TC global pointer */
	427	lw t1, VPEBOOTCFG_GP(t0)
	428	mttgpr t1, gp
	429
	430	/* Copy config from this VPE */
	431	mfc0 t0, CP0_CONFIG
	432	mttc0 t0, CP0_CONFIG
	433
	434	/* Ensure no software interrupts are pending */
	435	mttc0 zero, CP0_CAUSE
	436	mttc0 zero, CP0_STATUS
	437
	438	/* Set TC active, not interrupt exempt */
	439	mftc0 t0, CP0_TCSTATUS
	440	li t1, ~TCSTATUS_IXMT
	441	and t0, t0, t1
	442	ori t0, t0, TCSTATUS_A
	443	mttc0 t0, CP0_TCSTATUS
	444
	445	/* Clear the TC halt bit */
	446	mttc0 zero, CP0_TCHALT
	447
	448	/* Set VPE active */
	449	mftc0 t0, CP0_VPECONF0
	450	ori t0, t0, VPECONF0_VPA
	451	mttc0 t0, CP0_VPECONF0
	452
	453	/* Next VPE */
0586ac75 MC	454	2: srl ta2, ta2, 1
	455	addiu ta1, ta1, 1
	456	bnez ta2, 1b
245a7868 PB	457	nop
	458
	459	/* Leave VPE configuration state */
	460	mfc0 t1, CP0_MVPCONTROL
	461	xori t1, t1, MVPCONTROL_VPC
	462	mtc0 t1, CP0_MVPCONTROL
	463	ehb
	464	evpe
	465
	466	/* Check whether this VPE is meant to be running */
	467	li t0, 1
	468	sll t0, t0, t9
	469	and t0, t0, t8
	470	bnez t0, 2f
	471	nop
	472
	473	/* This VPE should be offline, halt the TC */
	474	li t0, TCHALT_H
	475	mtc0 t0, CP0_TCHALT
81a02e34	476	PTR_LA t0, 1f
245a7868 PB	477	1: jr.hb t0
	478	nop
	479
	480	2: .set pop
	481
7a63076d	482	#endif /* CONFIG_MIPS_MT_SMP */
245a7868 PB	483
	484	/* Return */
	485	jr ra
	486	nop
	487	END(mips_cps_boot_vpes)
3179d37e PB	488
	489	#if defined(CONFIG_MIPS_CPS_PM) && defined(CONFIG_CPU_PM)
	490
	491	/* Calculate a pointer to this CPUs struct mips_static_suspend_state */
	492	.macro psstate dest
	493	.set push
	494	.set noat
	495	lw $1, TI_CPU(gp)
	496	sll $1, $1, LONGLOG
81a02e34	497	PTR_LA \dest, __per_cpu_offset
3179d37e PB	498	addu $1, $1, \dest
3179d37e PB	499	lw $1, 0($1)
81a02e34	500	PTR_LA \dest, cps_cpu_state
3179d37e PB	501	addu \dest, \dest, $1
	502	.set pop
	503	.endm
	504
	505	LEAF(mips_cps_pm_save)
	506	/* Save CPU state */
	507	SUSPEND_SAVE_REGS
	508	psstate t1
	509	SUSPEND_SAVE_STATIC
	510	jr v0
	511	nop
	512	END(mips_cps_pm_save)
	513
	514	LEAF(mips_cps_pm_restore)
	515	/* Restore CPU state */
	516	psstate t1
	517	RESUME_RESTORE_STATIC
	518	RESUME_RESTORE_REGS_RETURN
	519	END(mips_cps_pm_restore)
	520
	521	#endif /* CONFIG_MIPS_CPS_PM && CONFIG_CPU_PM */