]> git.proxmox.com Git - mirror_ubuntu-artful-kernel.git/blame - arch/mips/kernel/cpu-probe.c
projects / mirror_ubuntu-artful-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
MIPS: Coherent Processing System SMP implementation
[mirror_ubuntu-artful-kernel.git] / arch / mips / kernel / cpu-probe.c
CommitLineData
1da177e4
LT		 1/*
2 * Processor capabilities determination functions.
3 *
4 * Copyright (C) xxxx the Anonymous
010b853b 5 * Copyright (C) 1994 - 2006 Ralf Baechle
4194318c 6 * Copyright (C) 2003, 2004 Maciej W. Rozycki
70342287 7 * Copyright (C) 2001, 2004, 2011, 2012 MIPS Technologies, Inc.
1da177e4
LT		 8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
13 */
1da177e4
LT		 14#include <linux/init.h>
15#include <linux/kernel.h>
16#include <linux/ptrace.h>
631330f5 17#include <linux/smp.h>
1da177e4 18#include <linux/stddef.h>
73bc256d 19#include <linux/export.h>
1da177e4 20
5759906c 21#include <asm/bugs.h>
1da177e4 22#include <asm/cpu.h>
69f24d17 23#include <asm/cpu-type.h>
1da177e4
LT		 24#include <asm/fpu.h>
25#include <asm/mipsregs.h>
654f57bf 26#include <asm/watch.h>
06372a63 27#include <asm/elf.h>
a074f0e8 28#include <asm/spram.h>
949e51be
DD		 29#include <asm/uaccess.h>
30
078a55fc 31static int mips_fpu_disabled;
0103d23f
KC		 32
33static int __init fpu_disable(char *s)
34{
35 cpu_data[0].options &= ~MIPS_CPU_FPU;
36 mips_fpu_disabled = 1;
37
38 return 1;
39}
40
41__setup("nofpu", fpu_disable);
42
078a55fc 43int mips_dsp_disabled;
0103d23f
KC		 44
45static int __init dsp_disable(char *s)
46{
ee80f7c7 47 cpu_data[0].ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
0103d23f
KC		 48 mips_dsp_disabled = 1;
49
50 return 1;
51}
52
53__setup("nodsp", dsp_disable);
54
9267a30d
MSJ		 55static inline void check_errata(void)
56{
57 struct cpuinfo_mips *c = &current_cpu_data;
58
69f24d17 59 switch (current_cpu_type()) {
9267a30d
MSJ		 60 case CPU_34K:
61 /*
62 * Erratum "RPS May Cause Incorrect Instruction Execution"
63 * This code only handles VPE0, any SMP/SMTC/RTOS code
64 * making use of VPE1 will be responsable for that VPE.
65 */
66 if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2)
67 write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS);
68 break;
69 default:
70 break;
71 }
72}
73
1da177e4
LT		 74void __init check_bugs32(void)
75{
9267a30d 76 check_errata();
1da177e4
LT		 77}
78
79/*
80 * Probe whether cpu has config register by trying to play with
81 * alternate cache bit and see whether it matters.
82 * It's used by cpu_probe to distinguish between R3000A and R3081.
83 */
84static inline int cpu_has_confreg(void)
85{
86#ifdef CONFIG_CPU_R3000
87 extern unsigned long r3k_cache_size(unsigned long);
88 unsigned long size1, size2;
89 unsigned long cfg = read_c0_conf();
90
91 size1 = r3k_cache_size(ST0_ISC);
92 write_c0_conf(cfg ^ R30XX_CONF_AC);
93 size2 = r3k_cache_size(ST0_ISC);
94 write_c0_conf(cfg);
95 return size1 != size2;
96#else
97 return 0;
98#endif
99}
100
c094c99e
RM		 101static inline void set_elf_platform(int cpu, const char *plat)
102{
103 if (cpu == 0)
104 __elf_platform = plat;
105}
106
1da177e4
LT		 107/*
108 * Get the FPU Implementation/Revision.
109 */
110static inline unsigned long cpu_get_fpu_id(void)
111{
112 unsigned long tmp, fpu_id;
113
114 tmp = read_c0_status();
597ce172 115 __enable_fpu(FPU_AS_IS);
1da177e4
LT		 116 fpu_id = read_32bit_cp1_register(CP1_REVISION);
117 write_c0_status(tmp);
118 return fpu_id;
119}
120
121/*
122 * Check the CPU has an FPU the official way.
123 */
124static inline int __cpu_has_fpu(void)
125{
8ff374b9 126 return ((cpu_get_fpu_id() & FPIR_IMP_MASK) != FPIR_IMP_NONE);
1da177e4
LT		 127}
128
91dfc423
GR		 129static inline void cpu_probe_vmbits(struct cpuinfo_mips *c)
130{
131#ifdef __NEED_VMBITS_PROBE
5b7efa89 132 write_c0_entryhi(0x3fffffffffffe000ULL);
91dfc423 133 back_to_back_c0_hazard();
5b7efa89 134 c->vmbits = fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL);
91dfc423
GR		 135#endif
136}
137
078a55fc 138static void set_isa(struct cpuinfo_mips *c, unsigned int isa)
a96102be
SH		 139{
140 switch (isa) {
141 case MIPS_CPU_ISA_M64R2:
142 c->isa_level |= MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2;
143 case MIPS_CPU_ISA_M64R1:
144 c->isa_level |= MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1;
145 case MIPS_CPU_ISA_V:
146 c->isa_level |= MIPS_CPU_ISA_V;
147 case MIPS_CPU_ISA_IV:
148 c->isa_level |= MIPS_CPU_ISA_IV;
149 case MIPS_CPU_ISA_III:
1990e542 150 c->isa_level |= MIPS_CPU_ISA_II | MIPS_CPU_ISA_III;
a96102be
SH		 151 break;
152
153 case MIPS_CPU_ISA_M32R2:
154 c->isa_level |= MIPS_CPU_ISA_M32R2;
155 case MIPS_CPU_ISA_M32R1:
156 c->isa_level |= MIPS_CPU_ISA_M32R1;
157 case MIPS_CPU_ISA_II:
158 c->isa_level |= MIPS_CPU_ISA_II;
a96102be
SH		 159 break;
160 }
161}
162
078a55fc 163static char unknown_isa[] = KERN_ERR \
2fa36399
KC		 164 "Unsupported ISA type, c0.config0: %d.";
165
75b5b5e0
LY		 166static void set_ftlb_enable(struct cpuinfo_mips *c, int enable)
167{
168 unsigned int config6;
169 /*
170 * Config6 is implementation dependent and it's currently only
171 * used by proAptiv
172 */
173 if (c->cputype == CPU_PROAPTIV) {
174 config6 = read_c0_config6();
175 if (enable)
176 /* Enable FTLB */
177 write_c0_config6(config6 | MIPS_CONF6_FTLBEN);
178 else
179 /* Disable FTLB */
180 write_c0_config6(config6 & ~MIPS_CONF6_FTLBEN);
181 back_to_back_c0_hazard();
182 }
183}
184
2fa36399
KC		 185static inline unsigned int decode_config0(struct cpuinfo_mips *c)
186{
187 unsigned int config0;
188 int isa;
189
190 config0 = read_c0_config();
191
75b5b5e0
LY		 192 /*
193 * Look for Standard TLB or Dual VTLB and FTLB
194 */
195 if ((((config0 & MIPS_CONF_MT) >> 7) == 1) ||
196 (((config0 & MIPS_CONF_MT) >> 7) == 4))
2fa36399 197 c->options |= MIPS_CPU_TLB;
75b5b5e0 198
2fa36399
KC		 199 isa = (config0 & MIPS_CONF_AT) >> 13;
200 switch (isa) {
201 case 0:
202 switch ((config0 & MIPS_CONF_AR) >> 10) {
203 case 0:
a96102be 204 set_isa(c, MIPS_CPU_ISA_M32R1);
2fa36399
KC		 205 break;
206 case 1:
a96102be 207 set_isa(c, MIPS_CPU_ISA_M32R2);
2fa36399
KC		 208 break;
209 default:
210 goto unknown;
211 }
212 break;
213 case 2:
214 switch ((config0 & MIPS_CONF_AR) >> 10) {
215 case 0:
a96102be 216 set_isa(c, MIPS_CPU_ISA_M64R1);
2fa36399
KC		 217 break;
218 case 1:
a96102be 219 set_isa(c, MIPS_CPU_ISA_M64R2);
2fa36399
KC		 220 break;
221 default:
222 goto unknown;
223 }
224 break;
225 default:
226 goto unknown;
227 }
228
229 return config0 & MIPS_CONF_M;
230
231unknown:
232 panic(unknown_isa, config0);
233}
234
235static inline unsigned int decode_config1(struct cpuinfo_mips *c)
236{
237 unsigned int config1;
238
239 config1 = read_c0_config1();
240
241 if (config1 & MIPS_CONF1_MD)
242 c->ases |= MIPS_ASE_MDMX;
243 if (config1 & MIPS_CONF1_WR)
244 c->options |= MIPS_CPU_WATCH;
245 if (config1 & MIPS_CONF1_CA)
246 c->ases |= MIPS_ASE_MIPS16;
247 if (config1 & MIPS_CONF1_EP)
248 c->options |= MIPS_CPU_EJTAG;
249 if (config1 & MIPS_CONF1_FP) {
250 c->options |= MIPS_CPU_FPU;
251 c->options |= MIPS_CPU_32FPR;
252 }
75b5b5e0 253 if (cpu_has_tlb) {
2fa36399 254 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;
75b5b5e0
LY		 255 c->tlbsizevtlb = c->tlbsize;
256 c->tlbsizeftlbsets = 0;
257 }
2fa36399
KC		 258
259 return config1 & MIPS_CONF_M;
260}
261
262static inline unsigned int decode_config2(struct cpuinfo_mips *c)
263{
264 unsigned int config2;
265
266 config2 = read_c0_config2();
267
268 if (config2 & MIPS_CONF2_SL)
269 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
270
271 return config2 & MIPS_CONF_M;
272}
273
274static inline unsigned int decode_config3(struct cpuinfo_mips *c)
275{
276 unsigned int config3;
277
278 config3 = read_c0_config3();
279
b2ab4f08 280 if (config3 & MIPS_CONF3_SM) {
2fa36399 281 c->ases |= MIPS_ASE_SMARTMIPS;
b2ab4f08
SH		 282 c->options |= MIPS_CPU_RIXI;
283 }
284 if (config3 & MIPS_CONF3_RXI)
285 c->options |= MIPS_CPU_RIXI;
2fa36399
KC		 286 if (config3 & MIPS_CONF3_DSP)
287 c->ases |= MIPS_ASE_DSP;
ee80f7c7
SH		 288 if (config3 & MIPS_CONF3_DSP2P)
289 c->ases |= MIPS_ASE_DSP2P;
2fa36399
KC		 290 if (config3 & MIPS_CONF3_VINT)
291 c->options |= MIPS_CPU_VINT;
292 if (config3 & MIPS_CONF3_VEIC)
293 c->options |= MIPS_CPU_VEIC;
294 if (config3 & MIPS_CONF3_MT)
295 c->ases |= MIPS_ASE_MIPSMT;
296 if (config3 & MIPS_CONF3_ULRI)
297 c->options |= MIPS_CPU_ULRI;
f8fa4811
SH		 298 if (config3 & MIPS_CONF3_ISA)
299 c->options |= MIPS_CPU_MICROMIPS;
1e7decdb
DD		 300 if (config3 & MIPS_CONF3_VZ)
301 c->ases |= MIPS_ASE_VZ;
4a0156fb
SH		 302 if (config3 & MIPS_CONF3_SC)
303 c->options |= MIPS_CPU_SEGMENTS;
2fa36399
KC		 304
305 return config3 & MIPS_CONF_M;
306}
307
308static inline unsigned int decode_config4(struct cpuinfo_mips *c)
309{
310 unsigned int config4;
75b5b5e0
LY		 311 unsigned int newcf4;
312 unsigned int mmuextdef;
313 unsigned int ftlb_page = MIPS_CONF4_FTLBPAGESIZE;
2fa36399
KC		 314
315 config4 = read_c0_config4();
316
1745c1ef
LY		 317 if (cpu_has_tlb) {
318 if (((config4 & MIPS_CONF4_IE) >> 29) == 2)
319 c->options |= MIPS_CPU_TLBINV;
75b5b5e0
LY		 320 mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF;
321 switch (mmuextdef) {
322 case MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT:
323 c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40;
324 c->tlbsizevtlb = c->tlbsize;
325 break;
326 case MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT:
327 c->tlbsizevtlb +=
328 ((config4 & MIPS_CONF4_VTLBSIZEEXT) >>
329 MIPS_CONF4_VTLBSIZEEXT_SHIFT) * 0x40;
330 c->tlbsize = c->tlbsizevtlb;
331 ftlb_page = MIPS_CONF4_VFTLBPAGESIZE;
332 /* fall through */
333 case MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT:
334 newcf4 = (config4 & ~ftlb_page) |
335 (page_size_ftlb(mmuextdef) <<
336 MIPS_CONF4_FTLBPAGESIZE_SHIFT);
337 write_c0_config4(newcf4);
338 back_to_back_c0_hazard();
339 config4 = read_c0_config4();
340 if (config4 != newcf4) {
341 pr_err("PAGE_SIZE 0x%lx is not supported by FTLB (config4=0x%x)\n",
342 PAGE_SIZE, config4);
343 /* Switch FTLB off */
344 set_ftlb_enable(c, 0);
345 break;
346 }
347 c->tlbsizeftlbsets = 1 <<
348 ((config4 & MIPS_CONF4_FTLBSETS) >>
349 MIPS_CONF4_FTLBSETS_SHIFT);
350 c->tlbsizeftlbways = ((config4 & MIPS_CONF4_FTLBWAYS) >>
351 MIPS_CONF4_FTLBWAYS_SHIFT) + 2;
352 c->tlbsize += c->tlbsizeftlbways * c->tlbsizeftlbsets;
353 break;
354 }
1745c1ef
LY		 355 }
356
2fa36399
KC		 357 c->kscratch_mask = (config4 >> 16) & 0xff;
358
359 return config4 & MIPS_CONF_M;
360}
361
8b8a7634
RB		 362static inline unsigned int decode_config5(struct cpuinfo_mips *c)
363{
364 unsigned int config5;
365
366 config5 = read_c0_config5();
367 config5 &= ~MIPS_CONF5_UFR;
368 write_c0_config5(config5);
369
370 return config5 & MIPS_CONF_M;
371}
372
078a55fc 373static void decode_configs(struct cpuinfo_mips *c)
2fa36399
KC		 374{
375 int ok;
376
377 /* MIPS32 or MIPS64 compliant CPU. */
378 c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
379 MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
380
381 c->scache.flags = MIPS_CACHE_NOT_PRESENT;
382
75b5b5e0
LY		 383 /* Enable FTLB if present */
384 set_ftlb_enable(c, 1);
385
2fa36399 386 ok = decode_config0(c); /* Read Config registers. */
70342287 387 BUG_ON(!ok); /* Arch spec violation! */
2fa36399
KC		 388 if (ok)
389 ok = decode_config1(c);
390 if (ok)
391 ok = decode_config2(c);
392 if (ok)
393 ok = decode_config3(c);
394 if (ok)
395 ok = decode_config4(c);
8b8a7634
RB		 396 if (ok)
397 ok = decode_config5(c);
2fa36399
KC		 398
399 mips_probe_watch_registers(c);
400
0ee958e1 401#ifndef CONFIG_MIPS_CPS
2fa36399
KC		 402 if (cpu_has_mips_r2)
403 c->core = read_c0_ebase() & 0x3ff;
0ee958e1 404#endif
2fa36399
KC		 405}
406
02cf2119 407#define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
1da177e4
LT		 408 | MIPS_CPU_COUNTER)
409
cea7e2df 410static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4 411{
8ff374b9 412 switch (c->processor_id & PRID_IMP_MASK) {
1da177e4
LT		 413 case PRID_IMP_R2000:
414 c->cputype = CPU_R2000;
cea7e2df 415 __cpu_name[cpu] = "R2000";
02cf2119 416 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
03751e79 417 MIPS_CPU_NOFPUEX;
1da177e4
LT		 418 if (__cpu_has_fpu())
419 c->options |= MIPS_CPU_FPU;
420 c->tlbsize = 64;
421 break;
422 case PRID_IMP_R3000:
8ff374b9 423 if ((c->processor_id & PRID_REV_MASK) == PRID_REV_R3000A) {
cea7e2df 424 if (cpu_has_confreg()) {
1da177e4 425 c->cputype = CPU_R3081E;
cea7e2df
RB		 426 __cpu_name[cpu] = "R3081";
427 } else {
1da177e4 428 c->cputype = CPU_R3000A;
cea7e2df
RB		 429 __cpu_name[cpu] = "R3000A";
430 }
cea7e2df 431 } else {
1da177e4 432 c->cputype = CPU_R3000;
cea7e2df
RB		 433 __cpu_name[cpu] = "R3000";
434 }
02cf2119 435 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
03751e79 436 MIPS_CPU_NOFPUEX;
1da177e4
LT		 437 if (__cpu_has_fpu())
438 c->options |= MIPS_CPU_FPU;
439 c->tlbsize = 64;
440 break;
441 case PRID_IMP_R4000:
442 if (read_c0_config() & CONF_SC) {
8ff374b9
MR		 443 if ((c->processor_id & PRID_REV_MASK) >=
444 PRID_REV_R4400) {
1da177e4 445 c->cputype = CPU_R4400PC;
cea7e2df
RB		 446 __cpu_name[cpu] = "R4400PC";
447 } else {
1da177e4 448 c->cputype = CPU_R4000PC;
cea7e2df
RB		 449 __cpu_name[cpu] = "R4000PC";
450 }
1da177e4 451 } else {
7f177a52
MR		 452 int cca = read_c0_config() & CONF_CM_CMASK;
453 int mc;
454
455 /*
456 * SC and MC versions can't be reliably told apart,
457 * but only the latter support coherent caching
458 * modes so assume the firmware has set the KSEG0
459 * coherency attribute reasonably (if uncached, we
460 * assume SC).
461 */
462 switch (cca) {
463 case CONF_CM_CACHABLE_CE:
464 case CONF_CM_CACHABLE_COW:
465 case CONF_CM_CACHABLE_CUW:
466 mc = 1;
467 break;
468 default:
469 mc = 0;
470 break;
471 }
8ff374b9
MR		 472 if ((c->processor_id & PRID_REV_MASK) >=
473 PRID_REV_R4400) {
7f177a52
MR		 474 c->cputype = mc ? CPU_R4400MC : CPU_R4400SC;
475 __cpu_name[cpu] = mc ? "R4400MC" : "R4400SC";
cea7e2df 476 } else {
7f177a52
MR		 477 c->cputype = mc ? CPU_R4000MC : CPU_R4000SC;
478 __cpu_name[cpu] = mc ? "R4000MC" : "R4000SC";
cea7e2df 479 }
1da177e4
LT		 480 }
481
a96102be 482 set_isa(c, MIPS_CPU_ISA_III);
1da177e4 483 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79
SH		 484 MIPS_CPU_WATCH | MIPS_CPU_VCE |
485 MIPS_CPU_LLSC;
1da177e4
LT		 486 c->tlbsize = 48;
487 break;
488 case PRID_IMP_VR41XX:
9f91e506
YY		 489 set_isa(c, MIPS_CPU_ISA_III);
490 c->options = R4K_OPTS;
491 c->tlbsize = 32;
1da177e4 492 switch (c->processor_id & 0xf0) {
1da177e4
LT		 493 case PRID_REV_VR4111:
494 c->cputype = CPU_VR4111;
cea7e2df 495 __cpu_name[cpu] = "NEC VR4111";
1da177e4 496 break;
1da177e4
LT		 497 case PRID_REV_VR4121:
498 c->cputype = CPU_VR4121;
cea7e2df 499 __cpu_name[cpu] = "NEC VR4121";
1da177e4
LT		 500 break;
501 case PRID_REV_VR4122:
cea7e2df 502 if ((c->processor_id & 0xf) < 0x3) {
1da177e4 503 c->cputype = CPU_VR4122;
cea7e2df
RB		 504 __cpu_name[cpu] = "NEC VR4122";
505 } else {
1da177e4 506 c->cputype = CPU_VR4181A;
cea7e2df
RB		 507 __cpu_name[cpu] = "NEC VR4181A";
508 }
1da177e4
LT		 509 break;
510 case PRID_REV_VR4130:
cea7e2df 511 if ((c->processor_id & 0xf) < 0x4) {
1da177e4 512 c->cputype = CPU_VR4131;
cea7e2df
RB		 513 __cpu_name[cpu] = "NEC VR4131";
514 } else {
1da177e4 515 c->cputype = CPU_VR4133;
9f91e506 516 c->options |= MIPS_CPU_LLSC;
cea7e2df
RB		 517 __cpu_name[cpu] = "NEC VR4133";
518 }
1da177e4
LT		 519 break;
520 default:
521 printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
522 c->cputype = CPU_VR41XX;
cea7e2df 523 __cpu_name[cpu] = "NEC Vr41xx";
1da177e4
LT		 524 break;
525 }
1da177e4
LT		 526 break;
527 case PRID_IMP_R4300:
528 c->cputype = CPU_R4300;
cea7e2df 529 __cpu_name[cpu] = "R4300";
a96102be 530 set_isa(c, MIPS_CPU_ISA_III);
1da177e4 531 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 532 MIPS_CPU_LLSC;
1da177e4
LT		 533 c->tlbsize = 32;
534 break;
535 case PRID_IMP_R4600:
536 c->cputype = CPU_R4600;
cea7e2df 537 __cpu_name[cpu] = "R4600";
a96102be 538 set_isa(c, MIPS_CPU_ISA_III);
075e7502
TS		 539 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
540 MIPS_CPU_LLSC;
1da177e4
LT		 541 c->tlbsize = 48;
542 break;
543 #if 0
03751e79 544 case PRID_IMP_R4650:
1da177e4
LT		 545 /*
546 * This processor doesn't have an MMU, so it's not
547 * "real easy" to run Linux on it. It is left purely
548 * for documentation. Commented out because it shares
549 * it's c0_prid id number with the TX3900.
550 */
a3dddd56 551 c->cputype = CPU_R4650;
cea7e2df 552 __cpu_name[cpu] = "R4650";
a96102be 553 set_isa(c, MIPS_CPU_ISA_III);
1da177e4 554 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
03751e79 555 c->tlbsize = 48;
1da177e4
LT		 556 break;
557 #endif
558 case PRID_IMP_TX39:
02cf2119 559 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE;
1da177e4
LT		 560
561 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
562 c->cputype = CPU_TX3927;
cea7e2df 563 __cpu_name[cpu] = "TX3927";
1da177e4
LT		 564 c->tlbsize = 64;
565 } else {
8ff374b9 566 switch (c->processor_id & PRID_REV_MASK) {
1da177e4
LT		 567 case PRID_REV_TX3912:
568 c->cputype = CPU_TX3912;
cea7e2df 569 __cpu_name[cpu] = "TX3912";
1da177e4
LT		 570 c->tlbsize = 32;
571 break;
572 case PRID_REV_TX3922:
573 c->cputype = CPU_TX3922;
cea7e2df 574 __cpu_name[cpu] = "TX3922";
1da177e4
LT		 575 c->tlbsize = 64;
576 break;
1da177e4
LT		 577 }
578 }
579 break;
580 case PRID_IMP_R4700:
581 c->cputype = CPU_R4700;
cea7e2df 582 __cpu_name[cpu] = "R4700";
a96102be 583 set_isa(c, MIPS_CPU_ISA_III);
1da177e4 584 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 585 MIPS_CPU_LLSC;
1da177e4
LT		 586 c->tlbsize = 48;
587 break;
588 case PRID_IMP_TX49:
589 c->cputype = CPU_TX49XX;
cea7e2df 590 __cpu_name[cpu] = "R49XX";
a96102be 591 set_isa(c, MIPS_CPU_ISA_III);
1da177e4
LT		 592 c->options = R4K_OPTS | MIPS_CPU_LLSC;
593 if (!(c->processor_id & 0x08))
594 c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
595 c->tlbsize = 48;
596 break;
597 case PRID_IMP_R5000:
598 c->cputype = CPU_R5000;
cea7e2df 599 __cpu_name[cpu] = "R5000";
a96102be 600 set_isa(c, MIPS_CPU_ISA_IV);
1da177e4 601 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 602 MIPS_CPU_LLSC;
1da177e4
LT		 603 c->tlbsize = 48;
604 break;
605 case PRID_IMP_R5432:
606 c->cputype = CPU_R5432;
cea7e2df 607 __cpu_name[cpu] = "R5432";
a96102be 608 set_isa(c, MIPS_CPU_ISA_IV);
1da177e4 609 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 610 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
1da177e4
LT		 611 c->tlbsize = 48;
612 break;
613 case PRID_IMP_R5500:
614 c->cputype = CPU_R5500;
cea7e2df 615 __cpu_name[cpu] = "R5500";
a96102be 616 set_isa(c, MIPS_CPU_ISA_IV);
1da177e4 617 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 618 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
1da177e4
LT		 619 c->tlbsize = 48;
620 break;
621 case PRID_IMP_NEVADA:
622 c->cputype = CPU_NEVADA;
cea7e2df 623 __cpu_name[cpu] = "Nevada";
a96102be 624 set_isa(c, MIPS_CPU_ISA_IV);
1da177e4 625 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 626 MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
1da177e4
LT		 627 c->tlbsize = 48;
628 break;
629 case PRID_IMP_R6000:
630 c->cputype = CPU_R6000;
cea7e2df 631 __cpu_name[cpu] = "R6000";
a96102be 632 set_isa(c, MIPS_CPU_ISA_II);
1da177e4 633 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
03751e79 634 MIPS_CPU_LLSC;
1da177e4
LT		 635 c->tlbsize = 32;
636 break;
637 case PRID_IMP_R6000A:
638 c->cputype = CPU_R6000A;
cea7e2df 639 __cpu_name[cpu] = "R6000A";
a96102be 640 set_isa(c, MIPS_CPU_ISA_II);
1da177e4 641 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
03751e79 642 MIPS_CPU_LLSC;
1da177e4
LT		 643 c->tlbsize = 32;
644 break;
645 case PRID_IMP_RM7000:
646 c->cputype = CPU_RM7000;
cea7e2df 647 __cpu_name[cpu] = "RM7000";
a96102be 648 set_isa(c, MIPS_CPU_ISA_IV);
1da177e4 649 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 650 MIPS_CPU_LLSC;
1da177e4 651 /*
70342287 652 * Undocumented RM7000: Bit 29 in the info register of
1da177e4
LT		 653 * the RM7000 v2.0 indicates if the TLB has 48 or 64
654 * entries.
655 *
70342287
RB		 656 * 29 1 => 64 entry JTLB
657 * 0 => 48 entry JTLB
1da177e4
LT		 658 */
659 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
660 break;
661 case PRID_IMP_RM9000:
662 c->cputype = CPU_RM9000;
cea7e2df 663 __cpu_name[cpu] = "RM9000";
a96102be 664 set_isa(c, MIPS_CPU_ISA_IV);
1da177e4 665 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 666 MIPS_CPU_LLSC;
1da177e4
LT		 667 /*
668 * Bit 29 in the info register of the RM9000
669 * indicates if the TLB has 48 or 64 entries.
670 *
70342287
RB		 671 * 29 1 => 64 entry JTLB
672 * 0 => 48 entry JTLB
1da177e4
LT		 673 */
674 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
675 break;
676 case PRID_IMP_R8000:
677 c->cputype = CPU_R8000;
cea7e2df 678 __cpu_name[cpu] = "RM8000";
a96102be 679 set_isa(c, MIPS_CPU_ISA_IV);
1da177e4 680 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
03751e79
SH		 681 MIPS_CPU_FPU | MIPS_CPU_32FPR |
682 MIPS_CPU_LLSC;
1da177e4
LT		 683 c->tlbsize = 384; /* has weird TLB: 3-way x 128 */
684 break;
685 case PRID_IMP_R10000:
686 c->cputype = CPU_R10000;
cea7e2df 687 __cpu_name[cpu] = "R10000";
a96102be 688 set_isa(c, MIPS_CPU_ISA_IV);
8b36612a 689 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
03751e79 690 MIPS_CPU_FPU | MIPS_CPU_32FPR |
1da177e4 691 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
03751e79 692 MIPS_CPU_LLSC;
1da177e4
LT		 693 c->tlbsize = 64;
694 break;
695 case PRID_IMP_R12000:
696 c->cputype = CPU_R12000;
cea7e2df 697 __cpu_name[cpu] = "R12000";
a96102be 698 set_isa(c, MIPS_CPU_ISA_IV);
8b36612a 699 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
03751e79 700 MIPS_CPU_FPU | MIPS_CPU_32FPR |
1da177e4 701 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
03751e79 702 MIPS_CPU_LLSC;
1da177e4
LT		 703 c->tlbsize = 64;
704 break;
44d921b2
K		 705 case PRID_IMP_R14000:
706 c->cputype = CPU_R14000;
cea7e2df 707 __cpu_name[cpu] = "R14000";
a96102be 708 set_isa(c, MIPS_CPU_ISA_IV);
44d921b2 709 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
03751e79 710 MIPS_CPU_FPU | MIPS_CPU_32FPR |
44d921b2 711 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
03751e79 712 MIPS_CPU_LLSC;
44d921b2
K		 713 c->tlbsize = 64;
714 break;
2a21c730
FZ		 715 case PRID_IMP_LOONGSON2:
716 c->cputype = CPU_LOONGSON2;
cea7e2df 717 __cpu_name[cpu] = "ICT Loongson-2";
5aac1e8a
RM		 718
719 switch (c->processor_id & PRID_REV_MASK) {
720 case PRID_REV_LOONGSON2E:
721 set_elf_platform(cpu, "loongson2e");
722 break;
723 case PRID_REV_LOONGSON2F:
724 set_elf_platform(cpu, "loongson2f");
725 break;
726 }
727
a96102be 728 set_isa(c, MIPS_CPU_ISA_III);
2a21c730
FZ		 729 c->options = R4K_OPTS |
730 MIPS_CPU_FPU | MIPS_CPU_LLSC |
731 MIPS_CPU_32FPR;
732 c->tlbsize = 64;
733 break;
2fa36399
KC		 734 case PRID_IMP_LOONGSON1:
735 decode_configs(c);
b4672d37 736
2fa36399 737 c->cputype = CPU_LOONGSON1;
1da177e4 738
2fa36399
KC		 739 switch (c->processor_id & PRID_REV_MASK) {
740 case PRID_REV_LOONGSON1B:
741 __cpu_name[cpu] = "Loongson 1B";
b4672d37 742 break;
b4672d37 743 }
4194318c 744
2fa36399 745 break;
1da177e4 746 }
1da177e4
LT		 747}
748
cea7e2df 749static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4 750{
8ff374b9 751 switch (c->processor_id & PRID_IMP_MASK) {
1da177e4
LT		 752 case PRID_IMP_4KC:
753 c->cputype = CPU_4KC;
cea7e2df 754 __cpu_name[cpu] = "MIPS 4Kc";
1da177e4
LT		 755 break;
756 case PRID_IMP_4KEC:
2b07bd02
RB		 757 case PRID_IMP_4KECR2:
758 c->cputype = CPU_4KEC;
cea7e2df 759 __cpu_name[cpu] = "MIPS 4KEc";
2b07bd02 760 break;
1da177e4 761 case PRID_IMP_4KSC:
8afcb5d8 762 case PRID_IMP_4KSD:
1da177e4 763 c->cputype = CPU_4KSC;
cea7e2df 764 __cpu_name[cpu] = "MIPS 4KSc";
1da177e4
LT		 765 break;
766 case PRID_IMP_5KC:
767 c->cputype = CPU_5KC;
cea7e2df 768 __cpu_name[cpu] = "MIPS 5Kc";
1da177e4 769 break;
78d4803f
LY		 770 case PRID_IMP_5KE:
771 c->cputype = CPU_5KE;
772 __cpu_name[cpu] = "MIPS 5KE";
773 break;
1da177e4
LT		 774 case PRID_IMP_20KC:
775 c->cputype = CPU_20KC;
cea7e2df 776 __cpu_name[cpu] = "MIPS 20Kc";
1da177e4
LT		 777 break;
778 case PRID_IMP_24K:
779 c->cputype = CPU_24K;
cea7e2df 780 __cpu_name[cpu] = "MIPS 24Kc";
1da177e4 781 break;
42f3caef
JC		 782 case PRID_IMP_24KE:
783 c->cputype = CPU_24K;
784 __cpu_name[cpu] = "MIPS 24KEc";
785 break;
1da177e4
LT		 786 case PRID_IMP_25KF:
787 c->cputype = CPU_25KF;
cea7e2df 788 __cpu_name[cpu] = "MIPS 25Kc";
1da177e4 789 break;
bbc7f22f
RB		 790 case PRID_IMP_34K:
791 c->cputype = CPU_34K;
cea7e2df 792 __cpu_name[cpu] = "MIPS 34Kc";
bbc7f22f 793 break;
c620953c
CD		 794 case PRID_IMP_74K:
795 c->cputype = CPU_74K;
cea7e2df 796 __cpu_name[cpu] = "MIPS 74Kc";
c620953c 797 break;
113c62d9
SH		 798 case PRID_IMP_M14KC:
799 c->cputype = CPU_M14KC;
800 __cpu_name[cpu] = "MIPS M14Kc";
801 break;
f8fa4811
SH		 802 case PRID_IMP_M14KEC:
803 c->cputype = CPU_M14KEC;
804 __cpu_name[cpu] = "MIPS M14KEc";
805 break;
39b8d525
RB		 806 case PRID_IMP_1004K:
807 c->cputype = CPU_1004K;
cea7e2df 808 __cpu_name[cpu] = "MIPS 1004Kc";
39b8d525 809 break;
006a851b 810 case PRID_IMP_1074K:
442e14a2 811 c->cputype = CPU_1074K;
006a851b
SH		 812 __cpu_name[cpu] = "MIPS 1074Kc";
813 break;
b5f065e7
LY		 814 case PRID_IMP_INTERAPTIV_UP:
815 c->cputype = CPU_INTERAPTIV;
816 __cpu_name[cpu] = "MIPS interAptiv";
817 break;
818 case PRID_IMP_INTERAPTIV_MP:
819 c->cputype = CPU_INTERAPTIV;
820 __cpu_name[cpu] = "MIPS interAptiv (multi)";
821 break;
b0d4d300
LY		 822 case PRID_IMP_PROAPTIV_UP:
823 c->cputype = CPU_PROAPTIV;
824 __cpu_name[cpu] = "MIPS proAptiv";
825 break;
826 case PRID_IMP_PROAPTIV_MP:
827 c->cputype = CPU_PROAPTIV;
828 __cpu_name[cpu] = "MIPS proAptiv (multi)";
829 break;
1da177e4 830 }
0b6d497f 831
75b5b5e0
LY		 832 decode_configs(c);
833
0b6d497f 834 spram_config();
1da177e4
LT		 835}
836
cea7e2df 837static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4 838{
4194318c 839 decode_configs(c);
8ff374b9 840 switch (c->processor_id & PRID_IMP_MASK) {
1da177e4
LT		 841 case PRID_IMP_AU1_REV1:
842 case PRID_IMP_AU1_REV2:
270717a8 843 c->cputype = CPU_ALCHEMY;
1da177e4
LT		 844 switch ((c->processor_id >> 24) & 0xff) {
845 case 0:
cea7e2df 846 __cpu_name[cpu] = "Au1000";
1da177e4
LT		 847 break;
848 case 1:
cea7e2df 849 __cpu_name[cpu] = "Au1500";
1da177e4
LT		 850 break;
851 case 2:
cea7e2df 852 __cpu_name[cpu] = "Au1100";
1da177e4
LT		 853 break;
854 case 3:
cea7e2df 855 __cpu_name[cpu] = "Au1550";
1da177e4 856 break;
e3ad1c23 857 case 4:
cea7e2df 858 __cpu_name[cpu] = "Au1200";
8ff374b9 859 if ((c->processor_id & PRID_REV_MASK) == 2)
cea7e2df 860 __cpu_name[cpu] = "Au1250";
237cfee1
ML		 861 break;
862 case 5:
cea7e2df 863 __cpu_name[cpu] = "Au1210";
e3ad1c23 864 break;
1da177e4 865 default:
270717a8 866 __cpu_name[cpu] = "Au1xxx";
1da177e4
LT		 867 break;
868 }
1da177e4
LT		 869 break;
870 }
871}
872
cea7e2df 873static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4 874{
4194318c 875 decode_configs(c);
02cf2119 876
8ff374b9 877 switch (c->processor_id & PRID_IMP_MASK) {
1da177e4
LT		 878 case PRID_IMP_SB1:
879 c->cputype = CPU_SB1;
cea7e2df 880 __cpu_name[cpu] = "SiByte SB1";
1da177e4 881 /* FPU in pass1 is known to have issues. */
8ff374b9 882 if ((c->processor_id & PRID_REV_MASK) < 0x02)
010b853b 883 c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
1da177e4 884 break;
93ce2f52
AI		 885 case PRID_IMP_SB1A:
886 c->cputype = CPU_SB1A;
cea7e2df 887 __cpu_name[cpu] = "SiByte SB1A";
93ce2f52 888 break;
1da177e4
LT		 889 }
890}
891
cea7e2df 892static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4 893{
4194318c 894 decode_configs(c);
8ff374b9 895 switch (c->processor_id & PRID_IMP_MASK) {
1da177e4
LT		 896 case PRID_IMP_SR71000:
897 c->cputype = CPU_SR71000;
cea7e2df 898 __cpu_name[cpu] = "Sandcraft SR71000";
1da177e4
LT		 899 c->scache.ways = 8;
900 c->tlbsize = 64;
901 break;
902 }
903}
904
cea7e2df 905static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu)
bdf21b18
PP		 906{
907 decode_configs(c);
8ff374b9 908 switch (c->processor_id & PRID_IMP_MASK) {
bdf21b18
PP		 909 case PRID_IMP_PR4450:
910 c->cputype = CPU_PR4450;
cea7e2df 911 __cpu_name[cpu] = "Philips PR4450";
a96102be 912 set_isa(c, MIPS_CPU_ISA_M32R1);
bdf21b18 913 break;
bdf21b18
PP		 914 }
915}
916
cea7e2df 917static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
1c0c13eb
AJ		 918{
919 decode_configs(c);
8ff374b9 920 switch (c->processor_id & PRID_IMP_MASK) {
190fca3e
KC		 921 case PRID_IMP_BMIPS32_REV4:
922 case PRID_IMP_BMIPS32_REV8:
602977b0
KC		 923 c->cputype = CPU_BMIPS32;
924 __cpu_name[cpu] = "Broadcom BMIPS32";
06785df0 925 set_elf_platform(cpu, "bmips32");
602977b0
KC		 926 break;
927 case PRID_IMP_BMIPS3300:
928 case PRID_IMP_BMIPS3300_ALT:
929 case PRID_IMP_BMIPS3300_BUG:
930 c->cputype = CPU_BMIPS3300;
931 __cpu_name[cpu] = "Broadcom BMIPS3300";
06785df0 932 set_elf_platform(cpu, "bmips3300");
602977b0
KC		 933 break;
934 case PRID_IMP_BMIPS43XX: {
8ff374b9 935 int rev = c->processor_id & PRID_REV_MASK;
602977b0
KC		 936
937 if (rev >= PRID_REV_BMIPS4380_LO &&
938 rev <= PRID_REV_BMIPS4380_HI) {
939 c->cputype = CPU_BMIPS4380;
940 __cpu_name[cpu] = "Broadcom BMIPS4380";
06785df0 941 set_elf_platform(cpu, "bmips4380");
602977b0
KC		 942 } else {
943 c->cputype = CPU_BMIPS4350;
944 __cpu_name[cpu] = "Broadcom BMIPS4350";
06785df0 945 set_elf_platform(cpu, "bmips4350");
602977b0 946 }
0de663ef 947 break;
602977b0
KC		 948 }
949 case PRID_IMP_BMIPS5000:
950 c->cputype = CPU_BMIPS5000;
951 __cpu_name[cpu] = "Broadcom BMIPS5000";
06785df0 952 set_elf_platform(cpu, "bmips5000");
602977b0 953 c->options |= MIPS_CPU_ULRI;
0de663ef 954 break;
1c0c13eb
AJ		 955 }
956}
957
0dd4781b
DD		 958static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu)
959{
960 decode_configs(c);
8ff374b9 961 switch (c->processor_id & PRID_IMP_MASK) {
0dd4781b
DD		 962 case PRID_IMP_CAVIUM_CN38XX:
963 case PRID_IMP_CAVIUM_CN31XX:
964 case PRID_IMP_CAVIUM_CN30XX:
6f329468
DD		 965 c->cputype = CPU_CAVIUM_OCTEON;
966 __cpu_name[cpu] = "Cavium Octeon";
967 goto platform;
0dd4781b
DD		 968 case PRID_IMP_CAVIUM_CN58XX:
969 case PRID_IMP_CAVIUM_CN56XX:
970 case PRID_IMP_CAVIUM_CN50XX:
971 case PRID_IMP_CAVIUM_CN52XX:
6f329468
DD		 972 c->cputype = CPU_CAVIUM_OCTEON_PLUS;
973 __cpu_name[cpu] = "Cavium Octeon+";
974platform:
c094c99e 975 set_elf_platform(cpu, "octeon");
0dd4781b 976 break;
a1431b61 977 case PRID_IMP_CAVIUM_CN61XX:
0e56b385 978 case PRID_IMP_CAVIUM_CN63XX:
a1431b61
DD		 979 case PRID_IMP_CAVIUM_CN66XX:
980 case PRID_IMP_CAVIUM_CN68XX:
af04bb85 981 case PRID_IMP_CAVIUM_CNF71XX:
0e56b385
DD		 982 c->cputype = CPU_CAVIUM_OCTEON2;
983 __cpu_name[cpu] = "Cavium Octeon II";
c094c99e 984 set_elf_platform(cpu, "octeon2");
0e56b385 985 break;
af04bb85
DD		 986 case PRID_IMP_CAVIUM_CN70XX:
987 case PRID_IMP_CAVIUM_CN78XX:
988 c->cputype = CPU_CAVIUM_OCTEON3;
989 __cpu_name[cpu] = "Cavium Octeon III";
990 set_elf_platform(cpu, "octeon3");
991 break;
0dd4781b
DD		 992 default:
993 printk(KERN_INFO "Unknown Octeon chip!\n");
994 c->cputype = CPU_UNKNOWN;
995 break;
996 }
997}
998
83ccf69d
LPC		 999static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
1000{
1001 decode_configs(c);
1002 /* JZRISC does not implement the CP0 counter. */
1003 c->options &= ~MIPS_CPU_COUNTER;
8ff374b9 1004 switch (c->processor_id & PRID_IMP_MASK) {
83ccf69d
LPC		 1005 case PRID_IMP_JZRISC:
1006 c->cputype = CPU_JZRISC;
1007 __cpu_name[cpu] = "Ingenic JZRISC";
1008 break;
1009 default:
1010 panic("Unknown Ingenic Processor ID!");
1011 break;
1012 }
1013}
1014
a7117c6b
J		 1015static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu)
1016{
1017 decode_configs(c);
1018
8ff374b9 1019 if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_NETLOGIC_AU13XX) {
809f36c6
ML		 1020 c->cputype = CPU_ALCHEMY;
1021 __cpu_name[cpu] = "Au1300";
1022 /* following stuff is not for Alchemy */
1023 return;
1024 }
1025
70342287
RB		 1026 c->options = (MIPS_CPU_TLB |
1027 MIPS_CPU_4KEX |
a7117c6b 1028 MIPS_CPU_COUNTER |
70342287
RB		 1029 MIPS_CPU_DIVEC |
1030 MIPS_CPU_WATCH |
1031 MIPS_CPU_EJTAG |
a7117c6b
J		 1032 MIPS_CPU_LLSC);
1033
8ff374b9 1034 switch (c->processor_id & PRID_IMP_MASK) {
4ca86a2f 1035 case PRID_IMP_NETLOGIC_XLP2XX:
8907c55e 1036 case PRID_IMP_NETLOGIC_XLP9XX:
4ca86a2f
J		 1037 c->cputype = CPU_XLP;
1038 __cpu_name[cpu] = "Broadcom XLPII";
1039 break;
1040
2aa54b20
J		 1041 case PRID_IMP_NETLOGIC_XLP8XX:
1042 case PRID_IMP_NETLOGIC_XLP3XX:
a3d4fb2d
J		 1043 c->cputype = CPU_XLP;
1044 __cpu_name[cpu] = "Netlogic XLP";
1045 break;
1046
a7117c6b
J		 1047 case PRID_IMP_NETLOGIC_XLR732:
1048 case PRID_IMP_NETLOGIC_XLR716:
1049 case PRID_IMP_NETLOGIC_XLR532:
1050 case PRID_IMP_NETLOGIC_XLR308:
1051 case PRID_IMP_NETLOGIC_XLR532C:
1052 case PRID_IMP_NETLOGIC_XLR516C:
1053 case PRID_IMP_NETLOGIC_XLR508C:
1054 case PRID_IMP_NETLOGIC_XLR308C:
1055 c->cputype = CPU_XLR;
1056 __cpu_name[cpu] = "Netlogic XLR";
1057 break;
1058
1059 case PRID_IMP_NETLOGIC_XLS608:
1060 case PRID_IMP_NETLOGIC_XLS408:
1061 case PRID_IMP_NETLOGIC_XLS404:
1062 case PRID_IMP_NETLOGIC_XLS208:
1063 case PRID_IMP_NETLOGIC_XLS204:
1064 case PRID_IMP_NETLOGIC_XLS108:
1065 case PRID_IMP_NETLOGIC_XLS104:
1066 case PRID_IMP_NETLOGIC_XLS616B:
1067 case PRID_IMP_NETLOGIC_XLS608B:
1068 case PRID_IMP_NETLOGIC_XLS416B:
1069 case PRID_IMP_NETLOGIC_XLS412B:
1070 case PRID_IMP_NETLOGIC_XLS408B:
1071 case PRID_IMP_NETLOGIC_XLS404B:
1072 c->cputype = CPU_XLR;
1073 __cpu_name[cpu] = "Netlogic XLS";
1074 break;
1075
1076 default:
a3d4fb2d 1077 pr_info("Unknown Netlogic chip id [%02x]!\n",
a7117c6b
J		 1078 c->processor_id);
1079 c->cputype = CPU_XLR;
1080 break;
1081 }
1082
a3d4fb2d 1083 if (c->cputype == CPU_XLP) {
a96102be 1084 set_isa(c, MIPS_CPU_ISA_M64R2);
a3d4fb2d
J		 1085 c->options |= (MIPS_CPU_FPU | MIPS_CPU_ULRI | MIPS_CPU_MCHECK);
1086 /* This will be updated again after all threads are woken up */
1087 c->tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1;
1088 } else {
a96102be 1089 set_isa(c, MIPS_CPU_ISA_M64R1);
a3d4fb2d
J		 1090 c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1;
1091 }
7777b939 1092 c->kscratch_mask = 0xf;
a7117c6b
J		 1093}
1094
949e51be
DD		 1095#ifdef CONFIG_64BIT
1096/* For use by uaccess.h */
1097u64 __ua_limit;
1098EXPORT_SYMBOL(__ua_limit);
1099#endif
1100
9966db25 1101const char *__cpu_name[NR_CPUS];
874fd3b5 1102const char *__elf_platform;
9966db25 1103
078a55fc 1104void cpu_probe(void)
1da177e4
LT		 1105{
1106 struct cpuinfo_mips *c = &current_cpu_data;
9966db25 1107 unsigned int cpu = smp_processor_id();
1da177e4 1108
70342287 1109 c->processor_id = PRID_IMP_UNKNOWN;
1da177e4
LT		 1110 c->fpu_id = FPIR_IMP_NONE;
1111 c->cputype = CPU_UNKNOWN;
1112
1113 c->processor_id = read_c0_prid();
8ff374b9 1114 switch (c->processor_id & PRID_COMP_MASK) {
1da177e4 1115 case PRID_COMP_LEGACY:
cea7e2df 1116 cpu_probe_legacy(c, cpu);
1da177e4
LT		 1117 break;
1118 case PRID_COMP_MIPS:
cea7e2df 1119 cpu_probe_mips(c, cpu);
1da177e4
LT		 1120 break;
1121 case PRID_COMP_ALCHEMY:
cea7e2df 1122 cpu_probe_alchemy(c, cpu);
1da177e4
LT		 1123 break;
1124 case PRID_COMP_SIBYTE:
cea7e2df 1125 cpu_probe_sibyte(c, cpu);
1da177e4 1126 break;
1c0c13eb 1127 case PRID_COMP_BROADCOM:
cea7e2df 1128 cpu_probe_broadcom(c, cpu);
1c0c13eb 1129 break;
1da177e4 1130 case PRID_COMP_SANDCRAFT:
cea7e2df 1131 cpu_probe_sandcraft(c, cpu);
1da177e4 1132 break;
a92b0588 1133 case PRID_COMP_NXP:
cea7e2df 1134 cpu_probe_nxp(c, cpu);
a3dddd56 1135 break;
0dd4781b
DD		 1136 case PRID_COMP_CAVIUM:
1137 cpu_probe_cavium(c, cpu);
1138 break;
83ccf69d
LPC		 1139 case PRID_COMP_INGENIC:
1140 cpu_probe_ingenic(c, cpu);
1141 break;
a7117c6b
J		 1142 case PRID_COMP_NETLOGIC:
1143 cpu_probe_netlogic(c, cpu);
1144 break;
1da177e4 1145 }
dec8b1ca 1146
cea7e2df
RB		 1147 BUG_ON(!__cpu_name[cpu]);
1148 BUG_ON(c->cputype == CPU_UNKNOWN);
1149
dec8b1ca
FBH		 1150 /*
1151 * Platform code can force the cpu type to optimize code
1152 * generation. In that case be sure the cpu type is correctly
1153 * manually setup otherwise it could trigger some nasty bugs.
1154 */
1155 BUG_ON(current_cpu_type() != c->cputype);
1156
0103d23f
KC		 1157 if (mips_fpu_disabled)
1158 c->options &= ~MIPS_CPU_FPU;
1159
1160 if (mips_dsp_disabled)
ee80f7c7 1161 c->ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
0103d23f 1162
4194318c 1163 if (c->options & MIPS_CPU_FPU) {
1da177e4 1164 c->fpu_id = cpu_get_fpu_id();
4194318c 1165
adb37892
DCZ		 1166 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 |
1167 MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2)) {
4194318c
RB		 1168 if (c->fpu_id & MIPS_FPIR_3D)
1169 c->ases |= MIPS_ASE_MIPS3D;
1170 }
1171 }
9966db25 1172
da4b62cd 1173 if (cpu_has_mips_r2) {
f6771dbb 1174 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
da4b62cd
AC		 1175 /* R2 has Performance Counter Interrupt indicator */
1176 c->options |= MIPS_CPU_PCI;
1177 }
f6771dbb
RB		 1178 else
1179 c->srsets = 1;
91dfc423
GR		 1180
1181 cpu_probe_vmbits(c);
949e51be
DD		 1182
1183#ifdef CONFIG_64BIT
1184 if (cpu == 0)
1185 __ua_limit = ~((1ull << cpu_vmbits) - 1);
1186#endif
1da177e4
LT		 1187}
1188
078a55fc 1189void cpu_report(void)
1da177e4
LT		 1190{
1191 struct cpuinfo_mips *c = &current_cpu_data;
1192
d9f897c9
LY		 1193 pr_info("CPU%d revision is: %08x (%s)\n",
1194 smp_processor_id(), c->processor_id, cpu_name_string());
1da177e4 1195 if (c->options & MIPS_CPU_FPU)
9966db25 1196 printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id);
1da177e4 1197}
Ubuntu Artful kernel mirror