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MIPS: Add support for the M14Kc core.
[mirror_ubuntu-zesty-kernel.git] / arch / mips / kernel / cpu-probe.c
CommitLineData
1da177e4
LT		 1/*
2 * Processor capabilities determination functions.
3 *
4 * Copyright (C) xxxx the Anonymous
010b853b 5 * Copyright (C) 1994 - 2006 Ralf Baechle
4194318c 6 * Copyright (C) 2003, 2004 Maciej W. Rozycki
113c62d9 7 * Copyright (C) 2001, 2004, 2011, 2012 MIPS Technologies, Inc.
1da177e4
LT		 8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
13 */
1da177e4
LT		 14#include <linux/init.h>
15#include <linux/kernel.h>
16#include <linux/ptrace.h>
631330f5 17#include <linux/smp.h>
1da177e4 18#include <linux/stddef.h>
73bc256d 19#include <linux/export.h>
1da177e4 20
5759906c 21#include <asm/bugs.h>
1da177e4
LT		 22#include <asm/cpu.h>
23#include <asm/fpu.h>
24#include <asm/mipsregs.h>
654f57bf 25#include <asm/watch.h>
06372a63 26#include <asm/elf.h>
a074f0e8 27#include <asm/spram.h>
949e51be
DD		 28#include <asm/uaccess.h>
29
1da177e4
LT		 30/*
31 * Not all of the MIPS CPUs have the "wait" instruction available. Moreover,
32 * the implementation of the "wait" feature differs between CPU families. This
33 * points to the function that implements CPU specific wait.
34 * The wait instruction stops the pipeline and reduces the power consumption of
35 * the CPU very much.
36 */
982f6ffe 37void (*cpu_wait)(void);
f8ede0f7 38EXPORT_SYMBOL(cpu_wait);
1da177e4
LT		 39
40static void r3081_wait(void)
41{
42 unsigned long cfg = read_c0_conf();
43 write_c0_conf(cfg | R30XX_CONF_HALT);
44}
45
46static void r39xx_wait(void)
47{
60a6c377
AN		 48 local_irq_disable();
49 if (!need_resched())
50 write_c0_conf(read_c0_conf() | TX39_CONF_HALT);
51 local_irq_enable();
1da177e4
LT		 52}
53
c65a5480 54extern void r4k_wait(void);
60a6c377
AN		 55
56/*
57 * This variant is preferable as it allows testing need_resched and going to
58 * sleep depending on the outcome atomically. Unfortunately the "It is
59 * implementation-dependent whether the pipeline restarts when a non-enabled
60 * interrupt is requested" restriction in the MIPS32/MIPS64 architecture makes
61 * using this version a gamble.
62 */
8531a35e 63void r4k_wait_irqoff(void)
60a6c377
AN		 64{
65 local_irq_disable();
66 if (!need_resched())
8531a35e
KK		 67 __asm__(" .set push \n"
68 " .set mips3 \n"
60a6c377 69 " wait \n"
8531a35e 70 " .set pop \n");
60a6c377 71 local_irq_enable();
8531a35e
KK		 72 __asm__(" .globl __pastwait \n"
73 "__pastwait: \n");
1da177e4
LT		 74}
75
5a812999
RB		 76/*
77 * The RM7000 variant has to handle erratum 38. The workaround is to not
78 * have any pending stores when the WAIT instruction is executed.
79 */
80static void rm7k_wait_irqoff(void)
81{
82 local_irq_disable();
83 if (!need_resched())
84 __asm__(
85 " .set push \n"
86 " .set mips3 \n"
87 " .set noat \n"
88 " mfc0 $1, $12 \n"
89 " sync \n"
90 " mtc0 $1, $12 # stalls until W stage \n"
91 " wait \n"
92 " mtc0 $1, $12 # stalls until W stage \n"
93 " .set pop \n");
94 local_irq_enable();
95}
96
2882b0c6
ML		 97/*
98 * The Au1xxx wait is available only if using 32khz counter or
99 * external timer source, but specifically not CP0 Counter.
100 * alchemy/common/time.c may override cpu_wait!
101 */
494900af 102static void au1k_wait(void)
1da177e4 103{
60a6c377
AN		 104 __asm__(" .set mips3 \n"
105 " cache 0x14, 0(%0) \n"
106 " cache 0x14, 32(%0) \n"
107 " sync \n"
108 " nop \n"
109 " wait \n"
110 " nop \n"
111 " nop \n"
112 " nop \n"
113 " nop \n"
114 " .set mips0 \n"
10f650db 115 : : "r" (au1k_wait));
1da177e4
LT		 116}
117
982f6ffe 118static int __initdata nowait;
55d04dff 119
f49a747c 120static int __init wait_disable(char *s)
55d04dff
RB		 121{
122 nowait = 1;
123
124 return 1;
125}
126
127__setup("nowait", wait_disable);
128
0103d23f
KC		 129static int __cpuinitdata mips_fpu_disabled;
130
131static int __init fpu_disable(char *s)
132{
133 cpu_data[0].options &= ~MIPS_CPU_FPU;
134 mips_fpu_disabled = 1;
135
136 return 1;
137}
138
139__setup("nofpu", fpu_disable);
140
141int __cpuinitdata mips_dsp_disabled;
142
143static int __init dsp_disable(char *s)
144{
145 cpu_data[0].ases &= ~MIPS_ASE_DSP;
146 mips_dsp_disabled = 1;
147
148 return 1;
149}
150
151__setup("nodsp", dsp_disable);
152
c65a5480 153void __init check_wait(void)
1da177e4
LT		 154{
155 struct cpuinfo_mips *c = &current_cpu_data;
156
55d04dff 157 if (nowait) {
c2379230 158 printk("Wait instruction disabled.\n");
55d04dff
RB		 159 return;
160 }
161
1da177e4
LT		 162 switch (c->cputype) {
163 case CPU_R3081:
164 case CPU_R3081E:
165 cpu_wait = r3081_wait;
1da177e4
LT		 166 break;
167 case CPU_TX3927:
168 cpu_wait = r39xx_wait;
1da177e4
LT		 169 break;
170 case CPU_R4200:
171/* case CPU_R4300: */
172 case CPU_R4600:
173 case CPU_R4640:
174 case CPU_R4650:
175 case CPU_R4700:
176 case CPU_R5000:
a644b277 177 case CPU_R5500:
1da177e4 178 case CPU_NEVADA:
1da177e4
LT		 179 case CPU_4KC:
180 case CPU_4KEC:
181 case CPU_4KSC:
182 case CPU_5KC:
1da177e4 183 case CPU_25KF:
4b3e975e 184 case CPU_PR4450:
602977b0
KC		 185 case CPU_BMIPS3300:
186 case CPU_BMIPS4350:
187 case CPU_BMIPS4380:
188 case CPU_BMIPS5000:
0dd4781b 189 case CPU_CAVIUM_OCTEON:
6f329468 190 case CPU_CAVIUM_OCTEON_PLUS:
0e56b385 191 case CPU_CAVIUM_OCTEON2:
83ccf69d 192 case CPU_JZRISC:
11d48aac 193 case CPU_XLR:
a3d4fb2d 194 case CPU_XLP:
4b3e975e
RB		 195 cpu_wait = r4k_wait;
196 break;
197
5a812999
RB		 198 case CPU_RM7000:
199 cpu_wait = rm7k_wait_irqoff;
200 break;
201
113c62d9 202 case CPU_M14KC:
4b3e975e 203 case CPU_24K:
bbc7f22f 204 case CPU_34K:
39b8d525 205 case CPU_1004K:
4b3e975e
RB		 206 cpu_wait = r4k_wait;
207 if (read_c0_config7() & MIPS_CONF7_WII)
208 cpu_wait = r4k_wait_irqoff;
209 break;
210
c620953c 211 case CPU_74K:
1da177e4 212 cpu_wait = r4k_wait;
4b3e975e
RB		 213 if ((c->processor_id & 0xff) >= PRID_REV_ENCODE_332(2, 1, 0))
214 cpu_wait = r4k_wait_irqoff;
1da177e4 215 break;
4b3e975e 216
60a6c377
AN		 217 case CPU_TX49XX:
218 cpu_wait = r4k_wait_irqoff;
60a6c377 219 break;
270717a8 220 case CPU_ALCHEMY:
0c694de1 221 cpu_wait = au1k_wait;
1da177e4 222 break;
c8eae71d
RB		 223 case CPU_20KC:
224 /*
225 * WAIT on Rev1.0 has E1, E2, E3 and E16.
226 * WAIT on Rev2.0 and Rev3.0 has E16.
227 * Rev3.1 WAIT is nop, why bother
228 */
229 if ((c->processor_id & 0xff) <= 0x64)
230 break;
231
50da469a
RB		 232 /*
233 * Another rev is incremeting c0_count at a reduced clock
234 * rate while in WAIT mode. So we basically have the choice
235 * between using the cp0 timer as clocksource or avoiding
236 * the WAIT instruction. Until more details are known,
237 * disable the use of WAIT for 20Kc entirely.
238 cpu_wait = r4k_wait;
239 */
c8eae71d 240 break;
441ee341 241 case CPU_RM9000:
c2379230 242 if ((c->processor_id & 0x00ff) >= 0x40)
441ee341 243 cpu_wait = r4k_wait;
441ee341 244 break;
1da177e4 245 default:
1da177e4
LT		 246 break;
247 }
248}
249
9267a30d
MSJ		 250static inline void check_errata(void)
251{
252 struct cpuinfo_mips *c = &current_cpu_data;
253
254 switch (c->cputype) {
255 case CPU_34K:
256 /*
257 * Erratum "RPS May Cause Incorrect Instruction Execution"
258 * This code only handles VPE0, any SMP/SMTC/RTOS code
259 * making use of VPE1 will be responsable for that VPE.
260 */
261 if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2)
262 write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS);
263 break;
264 default:
265 break;
266 }
267}
268
1da177e4
LT		 269void __init check_bugs32(void)
270{
9267a30d 271 check_errata();
1da177e4
LT		 272}
273
274/*
275 * Probe whether cpu has config register by trying to play with
276 * alternate cache bit and see whether it matters.
277 * It's used by cpu_probe to distinguish between R3000A and R3081.
278 */
279static inline int cpu_has_confreg(void)
280{
281#ifdef CONFIG_CPU_R3000
282 extern unsigned long r3k_cache_size(unsigned long);
283 unsigned long size1, size2;
284 unsigned long cfg = read_c0_conf();
285
286 size1 = r3k_cache_size(ST0_ISC);
287 write_c0_conf(cfg ^ R30XX_CONF_AC);
288 size2 = r3k_cache_size(ST0_ISC);
289 write_c0_conf(cfg);
290 return size1 != size2;
291#else
292 return 0;
293#endif
294}
295
c094c99e
RM		 296static inline void set_elf_platform(int cpu, const char *plat)
297{
298 if (cpu == 0)
299 __elf_platform = plat;
300}
301
1da177e4
LT		 302/*
303 * Get the FPU Implementation/Revision.
304 */
305static inline unsigned long cpu_get_fpu_id(void)
306{
307 unsigned long tmp, fpu_id;
308
309 tmp = read_c0_status();
310 __enable_fpu();
311 fpu_id = read_32bit_cp1_register(CP1_REVISION);
312 write_c0_status(tmp);
313 return fpu_id;
314}
315
316/*
317 * Check the CPU has an FPU the official way.
318 */
319static inline int __cpu_has_fpu(void)
320{
321 return ((cpu_get_fpu_id() & 0xff00) != FPIR_IMP_NONE);
322}
323
91dfc423
GR		 324static inline void cpu_probe_vmbits(struct cpuinfo_mips *c)
325{
326#ifdef __NEED_VMBITS_PROBE
5b7efa89 327 write_c0_entryhi(0x3fffffffffffe000ULL);
91dfc423 328 back_to_back_c0_hazard();
5b7efa89 329 c->vmbits = fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL);
91dfc423
GR		 330#endif
331}
332
02cf2119 333#define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
1da177e4
LT		 334 | MIPS_CPU_COUNTER)
335
cea7e2df 336static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4
LT		 337{
338 switch (c->processor_id & 0xff00) {
339 case PRID_IMP_R2000:
340 c->cputype = CPU_R2000;
cea7e2df 341 __cpu_name[cpu] = "R2000";
1da177e4 342 c->isa_level = MIPS_CPU_ISA_I;
02cf2119 343 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
03751e79 344 MIPS_CPU_NOFPUEX;
1da177e4
LT		 345 if (__cpu_has_fpu())
346 c->options |= MIPS_CPU_FPU;
347 c->tlbsize = 64;
348 break;
349 case PRID_IMP_R3000:
cea7e2df
RB		 350 if ((c->processor_id & 0xff) == PRID_REV_R3000A) {
351 if (cpu_has_confreg()) {
1da177e4 352 c->cputype = CPU_R3081E;
cea7e2df
RB		 353 __cpu_name[cpu] = "R3081";
354 } else {
1da177e4 355 c->cputype = CPU_R3000A;
cea7e2df
RB		 356 __cpu_name[cpu] = "R3000A";
357 }
358 break;
359 } else {
1da177e4 360 c->cputype = CPU_R3000;
cea7e2df
RB		 361 __cpu_name[cpu] = "R3000";
362 }
1da177e4 363 c->isa_level = MIPS_CPU_ISA_I;
02cf2119 364 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
03751e79 365 MIPS_CPU_NOFPUEX;
1da177e4
LT		 366 if (__cpu_has_fpu())
367 c->options |= MIPS_CPU_FPU;
368 c->tlbsize = 64;
369 break;
370 case PRID_IMP_R4000:
371 if (read_c0_config() & CONF_SC) {
cea7e2df 372 if ((c->processor_id & 0xff) >= PRID_REV_R4400) {
1da177e4 373 c->cputype = CPU_R4400PC;
cea7e2df
RB		 374 __cpu_name[cpu] = "R4400PC";
375 } else {
1da177e4 376 c->cputype = CPU_R4000PC;
cea7e2df
RB		 377 __cpu_name[cpu] = "R4000PC";
378 }
1da177e4 379 } else {
cea7e2df 380 if ((c->processor_id & 0xff) >= PRID_REV_R4400) {
1da177e4 381 c->cputype = CPU_R4400SC;
cea7e2df
RB		 382 __cpu_name[cpu] = "R4400SC";
383 } else {
1da177e4 384 c->cputype = CPU_R4000SC;
cea7e2df
RB		 385 __cpu_name[cpu] = "R4000SC";
386 }
1da177e4
LT		 387 }
388
389 c->isa_level = MIPS_CPU_ISA_III;
390 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79
SH		 391 MIPS_CPU_WATCH | MIPS_CPU_VCE |
392 MIPS_CPU_LLSC;
1da177e4
LT		 393 c->tlbsize = 48;
394 break;
395 case PRID_IMP_VR41XX:
396 switch (c->processor_id & 0xf0) {
1da177e4
LT		 397 case PRID_REV_VR4111:
398 c->cputype = CPU_VR4111;
cea7e2df 399 __cpu_name[cpu] = "NEC VR4111";
1da177e4 400 break;
1da177e4
LT		 401 case PRID_REV_VR4121:
402 c->cputype = CPU_VR4121;
cea7e2df 403 __cpu_name[cpu] = "NEC VR4121";
1da177e4
LT		 404 break;
405 case PRID_REV_VR4122:
cea7e2df 406 if ((c->processor_id & 0xf) < 0x3) {
1da177e4 407 c->cputype = CPU_VR4122;
cea7e2df
RB		 408 __cpu_name[cpu] = "NEC VR4122";
409 } else {
1da177e4 410 c->cputype = CPU_VR4181A;
cea7e2df
RB		 411 __cpu_name[cpu] = "NEC VR4181A";
412 }
1da177e4
LT		 413 break;
414 case PRID_REV_VR4130:
cea7e2df 415 if ((c->processor_id & 0xf) < 0x4) {
1da177e4 416 c->cputype = CPU_VR4131;
cea7e2df
RB		 417 __cpu_name[cpu] = "NEC VR4131";
418 } else {
1da177e4 419 c->cputype = CPU_VR4133;
cea7e2df
RB		 420 __cpu_name[cpu] = "NEC VR4133";
421 }
1da177e4
LT		 422 break;
423 default:
424 printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
425 c->cputype = CPU_VR41XX;
cea7e2df 426 __cpu_name[cpu] = "NEC Vr41xx";
1da177e4
LT		 427 break;
428 }
429 c->isa_level = MIPS_CPU_ISA_III;
430 c->options = R4K_OPTS;
431 c->tlbsize = 32;
432 break;
433 case PRID_IMP_R4300:
434 c->cputype = CPU_R4300;
cea7e2df 435 __cpu_name[cpu] = "R4300";
1da177e4
LT		 436 c->isa_level = MIPS_CPU_ISA_III;
437 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 438 MIPS_CPU_LLSC;
1da177e4
LT		 439 c->tlbsize = 32;
440 break;
441 case PRID_IMP_R4600:
442 c->cputype = CPU_R4600;
cea7e2df 443 __cpu_name[cpu] = "R4600";
1da177e4 444 c->isa_level = MIPS_CPU_ISA_III;
075e7502
TS		 445 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
446 MIPS_CPU_LLSC;
1da177e4
LT		 447 c->tlbsize = 48;
448 break;
449 #if 0
03751e79 450 case PRID_IMP_R4650:
1da177e4
LT		 451 /*
452 * This processor doesn't have an MMU, so it's not
453 * "real easy" to run Linux on it. It is left purely
454 * for documentation. Commented out because it shares
455 * it's c0_prid id number with the TX3900.
456 */
a3dddd56 457 c->cputype = CPU_R4650;
cea7e2df 458 __cpu_name[cpu] = "R4650";
03751e79 459 c->isa_level = MIPS_CPU_ISA_III;
1da177e4 460 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
03751e79 461 c->tlbsize = 48;
1da177e4
LT		 462 break;
463 #endif
464 case PRID_IMP_TX39:
465 c->isa_level = MIPS_CPU_ISA_I;
02cf2119 466 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE;
1da177e4
LT		 467
468 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
469 c->cputype = CPU_TX3927;
cea7e2df 470 __cpu_name[cpu] = "TX3927";
1da177e4
LT		 471 c->tlbsize = 64;
472 } else {
473 switch (c->processor_id & 0xff) {
474 case PRID_REV_TX3912:
475 c->cputype = CPU_TX3912;
cea7e2df 476 __cpu_name[cpu] = "TX3912";
1da177e4
LT		 477 c->tlbsize = 32;
478 break;
479 case PRID_REV_TX3922:
480 c->cputype = CPU_TX3922;
cea7e2df 481 __cpu_name[cpu] = "TX3922";
1da177e4
LT		 482 c->tlbsize = 64;
483 break;
1da177e4
LT		 484 }
485 }
486 break;
487 case PRID_IMP_R4700:
488 c->cputype = CPU_R4700;
cea7e2df 489 __cpu_name[cpu] = "R4700";
1da177e4
LT		 490 c->isa_level = MIPS_CPU_ISA_III;
491 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 492 MIPS_CPU_LLSC;
1da177e4
LT		 493 c->tlbsize = 48;
494 break;
495 case PRID_IMP_TX49:
496 c->cputype = CPU_TX49XX;
cea7e2df 497 __cpu_name[cpu] = "R49XX";
1da177e4
LT		 498 c->isa_level = MIPS_CPU_ISA_III;
499 c->options = R4K_OPTS | MIPS_CPU_LLSC;
500 if (!(c->processor_id & 0x08))
501 c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
502 c->tlbsize = 48;
503 break;
504 case PRID_IMP_R5000:
505 c->cputype = CPU_R5000;
cea7e2df 506 __cpu_name[cpu] = "R5000";
1da177e4
LT		 507 c->isa_level = MIPS_CPU_ISA_IV;
508 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 509 MIPS_CPU_LLSC;
1da177e4
LT		 510 c->tlbsize = 48;
511 break;
512 case PRID_IMP_R5432:
513 c->cputype = CPU_R5432;
cea7e2df 514 __cpu_name[cpu] = "R5432";
1da177e4
LT		 515 c->isa_level = MIPS_CPU_ISA_IV;
516 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 517 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
1da177e4
LT		 518 c->tlbsize = 48;
519 break;
520 case PRID_IMP_R5500:
521 c->cputype = CPU_R5500;
cea7e2df 522 __cpu_name[cpu] = "R5500";
1da177e4
LT		 523 c->isa_level = MIPS_CPU_ISA_IV;
524 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 525 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
1da177e4
LT		 526 c->tlbsize = 48;
527 break;
528 case PRID_IMP_NEVADA:
529 c->cputype = CPU_NEVADA;
cea7e2df 530 __cpu_name[cpu] = "Nevada";
1da177e4
LT		 531 c->isa_level = MIPS_CPU_ISA_IV;
532 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 533 MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
1da177e4
LT		 534 c->tlbsize = 48;
535 break;
536 case PRID_IMP_R6000:
537 c->cputype = CPU_R6000;
cea7e2df 538 __cpu_name[cpu] = "R6000";
1da177e4
LT		 539 c->isa_level = MIPS_CPU_ISA_II;
540 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
03751e79 541 MIPS_CPU_LLSC;
1da177e4
LT		 542 c->tlbsize = 32;
543 break;
544 case PRID_IMP_R6000A:
545 c->cputype = CPU_R6000A;
cea7e2df 546 __cpu_name[cpu] = "R6000A";
1da177e4
LT		 547 c->isa_level = MIPS_CPU_ISA_II;
548 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
03751e79 549 MIPS_CPU_LLSC;
1da177e4
LT		 550 c->tlbsize = 32;
551 break;
552 case PRID_IMP_RM7000:
553 c->cputype = CPU_RM7000;
cea7e2df 554 __cpu_name[cpu] = "RM7000";
1da177e4
LT		 555 c->isa_level = MIPS_CPU_ISA_IV;
556 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 557 MIPS_CPU_LLSC;
1da177e4
LT		 558 /*
559 * Undocumented RM7000: Bit 29 in the info register of
560 * the RM7000 v2.0 indicates if the TLB has 48 or 64
561 * entries.
562 *
563 * 29 1 => 64 entry JTLB
564 * 0 => 48 entry JTLB
565 */
566 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
567 break;
568 case PRID_IMP_RM9000:
569 c->cputype = CPU_RM9000;
cea7e2df 570 __cpu_name[cpu] = "RM9000";
1da177e4
LT		 571 c->isa_level = MIPS_CPU_ISA_IV;
572 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 573 MIPS_CPU_LLSC;
1da177e4
LT		 574 /*
575 * Bit 29 in the info register of the RM9000
576 * indicates if the TLB has 48 or 64 entries.
577 *
578 * 29 1 => 64 entry JTLB
579 * 0 => 48 entry JTLB
580 */
581 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
582 break;
583 case PRID_IMP_R8000:
584 c->cputype = CPU_R8000;
cea7e2df 585 __cpu_name[cpu] = "RM8000";
1da177e4
LT		 586 c->isa_level = MIPS_CPU_ISA_IV;
587 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
03751e79
SH		 588 MIPS_CPU_FPU | MIPS_CPU_32FPR |
589 MIPS_CPU_LLSC;
1da177e4
LT		 590 c->tlbsize = 384; /* has weird TLB: 3-way x 128 */
591 break;
592 case PRID_IMP_R10000:
593 c->cputype = CPU_R10000;
cea7e2df 594 __cpu_name[cpu] = "R10000";
1da177e4 595 c->isa_level = MIPS_CPU_ISA_IV;
8b36612a 596 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
03751e79 597 MIPS_CPU_FPU | MIPS_CPU_32FPR |
1da177e4 598 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
03751e79 599 MIPS_CPU_LLSC;
1da177e4
LT		 600 c->tlbsize = 64;
601 break;
602 case PRID_IMP_R12000:
603 c->cputype = CPU_R12000;
cea7e2df 604 __cpu_name[cpu] = "R12000";
1da177e4 605 c->isa_level = MIPS_CPU_ISA_IV;
8b36612a 606 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
03751e79 607 MIPS_CPU_FPU | MIPS_CPU_32FPR |
1da177e4 608 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
03751e79 609 MIPS_CPU_LLSC;
1da177e4
LT		 610 c->tlbsize = 64;
611 break;
44d921b2
K		 612 case PRID_IMP_R14000:
613 c->cputype = CPU_R14000;
cea7e2df 614 __cpu_name[cpu] = "R14000";
44d921b2
K		 615 c->isa_level = MIPS_CPU_ISA_IV;
616 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
03751e79 617 MIPS_CPU_FPU | MIPS_CPU_32FPR |
44d921b2 618 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
03751e79 619 MIPS_CPU_LLSC;
44d921b2
K		 620 c->tlbsize = 64;
621 break;
2a21c730
FZ		 622 case PRID_IMP_LOONGSON2:
623 c->cputype = CPU_LOONGSON2;
cea7e2df 624 __cpu_name[cpu] = "ICT Loongson-2";
5aac1e8a
RM		 625
626 switch (c->processor_id & PRID_REV_MASK) {
627 case PRID_REV_LOONGSON2E:
628 set_elf_platform(cpu, "loongson2e");
629 break;
630 case PRID_REV_LOONGSON2F:
631 set_elf_platform(cpu, "loongson2f");
632 break;
633 }
634
2a21c730
FZ		 635 c->isa_level = MIPS_CPU_ISA_III;
636 c->options = R4K_OPTS |
637 MIPS_CPU_FPU | MIPS_CPU_LLSC |
638 MIPS_CPU_32FPR;
639 c->tlbsize = 64;
640 break;
1da177e4
LT		 641 }
642}
643
234fcd14 644static char unknown_isa[] __cpuinitdata = KERN_ERR \
b4672d37
RB		 645 "Unsupported ISA type, c0.config0: %d.";
646
4194318c 647static inline unsigned int decode_config0(struct cpuinfo_mips *c)
1da177e4 648{
4194318c
RB		 649 unsigned int config0;
650 int isa;
1da177e4 651
4194318c
RB		 652 config0 = read_c0_config();
653
654 if (((config0 & MIPS_CONF_MT) >> 7) == 1)
02cf2119 655 c->options |= MIPS_CPU_TLB;
4194318c
RB		 656 isa = (config0 & MIPS_CONF_AT) >> 13;
657 switch (isa) {
658 case 0:
3a01c49a 659 switch ((config0 & MIPS_CONF_AR) >> 10) {
b4672d37
RB		 660 case 0:
661 c->isa_level = MIPS_CPU_ISA_M32R1;
662 break;
663 case 1:
664 c->isa_level = MIPS_CPU_ISA_M32R2;
665 break;
666 default:
667 goto unknown;
668 }
4194318c
RB		 669 break;
670 case 2:
3a01c49a 671 switch ((config0 & MIPS_CONF_AR) >> 10) {
b4672d37
RB		 672 case 0:
673 c->isa_level = MIPS_CPU_ISA_M64R1;
674 break;
675 case 1:
676 c->isa_level = MIPS_CPU_ISA_M64R2;
677 break;
678 default:
679 goto unknown;
680 }
4194318c
RB		 681 break;
682 default:
b4672d37 683 goto unknown;
4194318c
RB		 684 }
685
686 return config0 & MIPS_CONF_M;
b4672d37
RB		 687
688unknown:
689 panic(unknown_isa, config0);
4194318c
RB		 690}
691
692static inline unsigned int decode_config1(struct cpuinfo_mips *c)
693{
694 unsigned int config1;
1da177e4 695
1da177e4 696 config1 = read_c0_config1();
4194318c
RB		 697
698 if (config1 & MIPS_CONF1_MD)
699 c->ases |= MIPS_ASE_MDMX;
700 if (config1 & MIPS_CONF1_WR)
1da177e4 701 c->options |= MIPS_CPU_WATCH;
4194318c
RB		 702 if (config1 & MIPS_CONF1_CA)
703 c->ases |= MIPS_ASE_MIPS16;
704 if (config1 & MIPS_CONF1_EP)
1da177e4 705 c->options |= MIPS_CPU_EJTAG;
4194318c 706 if (config1 & MIPS_CONF1_FP) {
1da177e4
LT		 707 c->options |= MIPS_CPU_FPU;
708 c->options |= MIPS_CPU_32FPR;
709 }
4194318c
RB		 710 if (cpu_has_tlb)
711 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;
712
713 return config1 & MIPS_CONF_M;
714}
715
716static inline unsigned int decode_config2(struct cpuinfo_mips *c)
717{
718 unsigned int config2;
719
720 config2 = read_c0_config2();
721
722 if (config2 & MIPS_CONF2_SL)
723 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
724
725 return config2 & MIPS_CONF_M;
726}
727
728static inline unsigned int decode_config3(struct cpuinfo_mips *c)
729{
730 unsigned int config3;
731
732 config3 = read_c0_config3();
733
734 if (config3 & MIPS_CONF3_SM)
735 c->ases |= MIPS_ASE_SMARTMIPS;
e50c0a8f
RB		 736 if (config3 & MIPS_CONF3_DSP)
737 c->ases |= MIPS_ASE_DSP;
8f40611d
RB		 738 if (config3 & MIPS_CONF3_VINT)
739 c->options |= MIPS_CPU_VINT;
740 if (config3 & MIPS_CONF3_VEIC)
741 c->options |= MIPS_CPU_VEIC;
742 if (config3 & MIPS_CONF3_MT)
03751e79 743 c->ases |= MIPS_ASE_MIPSMT;
a3692020
RB		 744 if (config3 & MIPS_CONF3_ULRI)
745 c->options |= MIPS_CPU_ULRI;
4194318c
RB		 746
747 return config3 & MIPS_CONF_M;
748}
749
1b362e3e
DD		 750static inline unsigned int decode_config4(struct cpuinfo_mips *c)
751{
752 unsigned int config4;
753
754 config4 = read_c0_config4();
755
756 if ((config4 & MIPS_CONF4_MMUEXTDEF) == MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT
757 && cpu_has_tlb)
758 c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40;
759
e77c32fe
DD		 760 c->kscratch_mask = (config4 >> 16) & 0xff;
761
1b362e3e
DD		 762 return config4 & MIPS_CONF_M;
763}
764
234fcd14 765static void __cpuinit decode_configs(struct cpuinfo_mips *c)
4194318c 766{
558ce124
RB		 767 int ok;
768
4194318c 769 /* MIPS32 or MIPS64 compliant CPU. */
02cf2119 770 c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
03751e79 771 MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
4194318c 772
1da177e4
LT		 773 c->scache.flags = MIPS_CACHE_NOT_PRESENT;
774
558ce124
RB		 775 ok = decode_config0(c); /* Read Config registers. */
776 BUG_ON(!ok); /* Arch spec violation! */
777 if (ok)
778 ok = decode_config1(c);
779 if (ok)
780 ok = decode_config2(c);
781 if (ok)
782 ok = decode_config3(c);
1b362e3e
DD		 783 if (ok)
784 ok = decode_config4(c);
558ce124
RB		 785
786 mips_probe_watch_registers(c);
0c2f4551
DD		 787
788 if (cpu_has_mips_r2)
789 c->core = read_c0_ebase() & 0x3ff;
1da177e4
LT		 790}
791
cea7e2df 792static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4 793{
4194318c 794 decode_configs(c);
1da177e4
LT		 795 switch (c->processor_id & 0xff00) {
796 case PRID_IMP_4KC:
797 c->cputype = CPU_4KC;
cea7e2df 798 __cpu_name[cpu] = "MIPS 4Kc";
1da177e4
LT		 799 break;
800 case PRID_IMP_4KEC:
2b07bd02
RB		 801 case PRID_IMP_4KECR2:
802 c->cputype = CPU_4KEC;
cea7e2df 803 __cpu_name[cpu] = "MIPS 4KEc";
2b07bd02 804 break;
1da177e4 805 case PRID_IMP_4KSC:
8afcb5d8 806 case PRID_IMP_4KSD:
1da177e4 807 c->cputype = CPU_4KSC;
cea7e2df 808 __cpu_name[cpu] = "MIPS 4KSc";
1da177e4
LT		 809 break;
810 case PRID_IMP_5KC:
811 c->cputype = CPU_5KC;
cea7e2df 812 __cpu_name[cpu] = "MIPS 5Kc";
1da177e4
LT		 813 break;
814 case PRID_IMP_20KC:
815 c->cputype = CPU_20KC;
cea7e2df 816 __cpu_name[cpu] = "MIPS 20Kc";
1da177e4
LT		 817 break;
818 case PRID_IMP_24K:
e50c0a8f 819 case PRID_IMP_24KE:
1da177e4 820 c->cputype = CPU_24K;
cea7e2df 821 __cpu_name[cpu] = "MIPS 24Kc";
1da177e4
LT		 822 break;
823 case PRID_IMP_25KF:
824 c->cputype = CPU_25KF;
cea7e2df 825 __cpu_name[cpu] = "MIPS 25Kc";
1da177e4 826 break;
bbc7f22f
RB		 827 case PRID_IMP_34K:
828 c->cputype = CPU_34K;
cea7e2df 829 __cpu_name[cpu] = "MIPS 34Kc";
bbc7f22f 830 break;
c620953c
CD		 831 case PRID_IMP_74K:
832 c->cputype = CPU_74K;
cea7e2df 833 __cpu_name[cpu] = "MIPS 74Kc";
c620953c 834 break;
113c62d9
SH		 835 case PRID_IMP_M14KC:
836 c->cputype = CPU_M14KC;
837 __cpu_name[cpu] = "MIPS M14Kc";
838 break;
39b8d525
RB		 839 case PRID_IMP_1004K:
840 c->cputype = CPU_1004K;
cea7e2df 841 __cpu_name[cpu] = "MIPS 1004Kc";
39b8d525 842 break;
1da177e4 843 }
0b6d497f
CD		 844
845 spram_config();
1da177e4
LT		 846}
847
cea7e2df 848static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4 849{
4194318c 850 decode_configs(c);
1da177e4
LT		 851 switch (c->processor_id & 0xff00) {
852 case PRID_IMP_AU1_REV1:
853 case PRID_IMP_AU1_REV2:
270717a8 854 c->cputype = CPU_ALCHEMY;
1da177e4
LT		 855 switch ((c->processor_id >> 24) & 0xff) {
856 case 0:
cea7e2df 857 __cpu_name[cpu] = "Au1000";
1da177e4
LT		 858 break;
859 case 1:
cea7e2df 860 __cpu_name[cpu] = "Au1500";
1da177e4
LT		 861 break;
862 case 2:
cea7e2df 863 __cpu_name[cpu] = "Au1100";
1da177e4
LT		 864 break;
865 case 3:
cea7e2df 866 __cpu_name[cpu] = "Au1550";
1da177e4 867 break;
e3ad1c23 868 case 4:
cea7e2df 869 __cpu_name[cpu] = "Au1200";
270717a8 870 if ((c->processor_id & 0xff) == 2)
cea7e2df 871 __cpu_name[cpu] = "Au1250";
237cfee1
ML		 872 break;
873 case 5:
cea7e2df 874 __cpu_name[cpu] = "Au1210";
e3ad1c23 875 break;
1da177e4 876 default:
270717a8 877 __cpu_name[cpu] = "Au1xxx";
1da177e4
LT		 878 break;
879 }
1da177e4
LT		 880 break;
881 }
882}
883
cea7e2df 884static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4 885{
4194318c 886 decode_configs(c);
02cf2119 887
1da177e4
LT		 888 switch (c->processor_id & 0xff00) {
889 case PRID_IMP_SB1:
890 c->cputype = CPU_SB1;
cea7e2df 891 __cpu_name[cpu] = "SiByte SB1";
1da177e4 892 /* FPU in pass1 is known to have issues. */
aa32374a 893 if ((c->processor_id & 0xff) < 0x02)
010b853b 894 c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
1da177e4 895 break;
93ce2f52
AI		 896 case PRID_IMP_SB1A:
897 c->cputype = CPU_SB1A;
cea7e2df 898 __cpu_name[cpu] = "SiByte SB1A";
93ce2f52 899 break;
1da177e4
LT		 900 }
901}
902
cea7e2df 903static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4 904{
4194318c 905 decode_configs(c);
1da177e4
LT		 906 switch (c->processor_id & 0xff00) {
907 case PRID_IMP_SR71000:
908 c->cputype = CPU_SR71000;
cea7e2df 909 __cpu_name[cpu] = "Sandcraft SR71000";
1da177e4
LT		 910 c->scache.ways = 8;
911 c->tlbsize = 64;
912 break;
913 }
914}
915
cea7e2df 916static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu)
bdf21b18
PP		 917{
918 decode_configs(c);
919 switch (c->processor_id & 0xff00) {
920 case PRID_IMP_PR4450:
921 c->cputype = CPU_PR4450;
cea7e2df 922 __cpu_name[cpu] = "Philips PR4450";
e7958bb9 923 c->isa_level = MIPS_CPU_ISA_M32R1;
bdf21b18 924 break;
bdf21b18
PP		 925 }
926}
927
cea7e2df 928static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
1c0c13eb
AJ		 929{
930 decode_configs(c);
931 switch (c->processor_id & 0xff00) {
190fca3e
KC		 932 case PRID_IMP_BMIPS32_REV4:
933 case PRID_IMP_BMIPS32_REV8:
602977b0
KC		 934 c->cputype = CPU_BMIPS32;
935 __cpu_name[cpu] = "Broadcom BMIPS32";
06785df0 936 set_elf_platform(cpu, "bmips32");
602977b0
KC		 937 break;
938 case PRID_IMP_BMIPS3300:
939 case PRID_IMP_BMIPS3300_ALT:
940 case PRID_IMP_BMIPS3300_BUG:
941 c->cputype = CPU_BMIPS3300;
942 __cpu_name[cpu] = "Broadcom BMIPS3300";
06785df0 943 set_elf_platform(cpu, "bmips3300");
602977b0
KC		 944 break;
945 case PRID_IMP_BMIPS43XX: {
946 int rev = c->processor_id & 0xff;
947
948 if (rev >= PRID_REV_BMIPS4380_LO &&
949 rev <= PRID_REV_BMIPS4380_HI) {
950 c->cputype = CPU_BMIPS4380;
951 __cpu_name[cpu] = "Broadcom BMIPS4380";
06785df0 952 set_elf_platform(cpu, "bmips4380");
602977b0
KC		 953 } else {
954 c->cputype = CPU_BMIPS4350;
955 __cpu_name[cpu] = "Broadcom BMIPS4350";
06785df0 956 set_elf_platform(cpu, "bmips4350");
602977b0 957 }
0de663ef 958 break;
602977b0
KC		 959 }
960 case PRID_IMP_BMIPS5000:
961 c->cputype = CPU_BMIPS5000;
962 __cpu_name[cpu] = "Broadcom BMIPS5000";
06785df0 963 set_elf_platform(cpu, "bmips5000");
602977b0 964 c->options |= MIPS_CPU_ULRI;
0de663ef 965 break;
1c0c13eb
AJ		 966 }
967}
968
0dd4781b
DD		 969static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu)
970{
971 decode_configs(c);
972 switch (c->processor_id & 0xff00) {
973 case PRID_IMP_CAVIUM_CN38XX:
974 case PRID_IMP_CAVIUM_CN31XX:
975 case PRID_IMP_CAVIUM_CN30XX:
6f329468
DD		 976 c->cputype = CPU_CAVIUM_OCTEON;
977 __cpu_name[cpu] = "Cavium Octeon";
978 goto platform;
0dd4781b
DD		 979 case PRID_IMP_CAVIUM_CN58XX:
980 case PRID_IMP_CAVIUM_CN56XX:
981 case PRID_IMP_CAVIUM_CN50XX:
982 case PRID_IMP_CAVIUM_CN52XX:
6f329468
DD		 983 c->cputype = CPU_CAVIUM_OCTEON_PLUS;
984 __cpu_name[cpu] = "Cavium Octeon+";
985platform:
c094c99e 986 set_elf_platform(cpu, "octeon");
0dd4781b 987 break;
a1431b61 988 case PRID_IMP_CAVIUM_CN61XX:
0e56b385 989 case PRID_IMP_CAVIUM_CN63XX:
a1431b61
DD		 990 case PRID_IMP_CAVIUM_CN66XX:
991 case PRID_IMP_CAVIUM_CN68XX:
0e56b385
DD		 992 c->cputype = CPU_CAVIUM_OCTEON2;
993 __cpu_name[cpu] = "Cavium Octeon II";
c094c99e 994 set_elf_platform(cpu, "octeon2");
0e56b385 995 break;
0dd4781b
DD		 996 default:
997 printk(KERN_INFO "Unknown Octeon chip!\n");
998 c->cputype = CPU_UNKNOWN;
999 break;
1000 }
1001}
1002
83ccf69d
LPC		 1003static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
1004{
1005 decode_configs(c);
1006 /* JZRISC does not implement the CP0 counter. */
1007 c->options &= ~MIPS_CPU_COUNTER;
1008 switch (c->processor_id & 0xff00) {
1009 case PRID_IMP_JZRISC:
1010 c->cputype = CPU_JZRISC;
1011 __cpu_name[cpu] = "Ingenic JZRISC";
1012 break;
1013 default:
1014 panic("Unknown Ingenic Processor ID!");
1015 break;
1016 }
1017}
1018
a7117c6b
J		 1019static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu)
1020{
1021 decode_configs(c);
1022
809f36c6
ML		 1023 if ((c->processor_id & 0xff00) == PRID_IMP_NETLOGIC_AU13XX) {
1024 c->cputype = CPU_ALCHEMY;
1025 __cpu_name[cpu] = "Au1300";
1026 /* following stuff is not for Alchemy */
1027 return;
1028 }
1029
a7117c6b
J		 1030 c->options = (MIPS_CPU_TLB |
1031 MIPS_CPU_4KEX |
1032 MIPS_CPU_COUNTER |
1033 MIPS_CPU_DIVEC |
1034 MIPS_CPU_WATCH |
1035 MIPS_CPU_EJTAG |
1036 MIPS_CPU_LLSC);
1037
1038 switch (c->processor_id & 0xff00) {
2aa54b20
J		 1039 case PRID_IMP_NETLOGIC_XLP8XX:
1040 case PRID_IMP_NETLOGIC_XLP3XX:
a3d4fb2d
J		 1041 c->cputype = CPU_XLP;
1042 __cpu_name[cpu] = "Netlogic XLP";
1043 break;
1044
a7117c6b
J		 1045 case PRID_IMP_NETLOGIC_XLR732:
1046 case PRID_IMP_NETLOGIC_XLR716:
1047 case PRID_IMP_NETLOGIC_XLR532:
1048 case PRID_IMP_NETLOGIC_XLR308:
1049 case PRID_IMP_NETLOGIC_XLR532C:
1050 case PRID_IMP_NETLOGIC_XLR516C:
1051 case PRID_IMP_NETLOGIC_XLR508C:
1052 case PRID_IMP_NETLOGIC_XLR308C:
1053 c->cputype = CPU_XLR;
1054 __cpu_name[cpu] = "Netlogic XLR";
1055 break;
1056
1057 case PRID_IMP_NETLOGIC_XLS608:
1058 case PRID_IMP_NETLOGIC_XLS408:
1059 case PRID_IMP_NETLOGIC_XLS404:
1060 case PRID_IMP_NETLOGIC_XLS208:
1061 case PRID_IMP_NETLOGIC_XLS204:
1062 case PRID_IMP_NETLOGIC_XLS108:
1063 case PRID_IMP_NETLOGIC_XLS104:
1064 case PRID_IMP_NETLOGIC_XLS616B:
1065 case PRID_IMP_NETLOGIC_XLS608B:
1066 case PRID_IMP_NETLOGIC_XLS416B:
1067 case PRID_IMP_NETLOGIC_XLS412B:
1068 case PRID_IMP_NETLOGIC_XLS408B:
1069 case PRID_IMP_NETLOGIC_XLS404B:
1070 c->cputype = CPU_XLR;
1071 __cpu_name[cpu] = "Netlogic XLS";
1072 break;
1073
1074 default:
a3d4fb2d 1075 pr_info("Unknown Netlogic chip id [%02x]!\n",
a7117c6b
J		 1076 c->processor_id);
1077 c->cputype = CPU_XLR;
1078 break;
1079 }
1080
a3d4fb2d
J		 1081 if (c->cputype == CPU_XLP) {
1082 c->isa_level = MIPS_CPU_ISA_M64R2;
1083 c->options |= (MIPS_CPU_FPU | MIPS_CPU_ULRI | MIPS_CPU_MCHECK);
1084 /* This will be updated again after all threads are woken up */
1085 c->tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1;
1086 } else {
1087 c->isa_level = MIPS_CPU_ISA_M64R1;
1088 c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1;
1089 }
a7117c6b
J		 1090}
1091
949e51be
DD		 1092#ifdef CONFIG_64BIT
1093/* For use by uaccess.h */
1094u64 __ua_limit;
1095EXPORT_SYMBOL(__ua_limit);
1096#endif
1097
9966db25 1098const char *__cpu_name[NR_CPUS];
874fd3b5 1099const char *__elf_platform;
9966db25 1100
234fcd14 1101__cpuinit void cpu_probe(void)
1da177e4
LT		 1102{
1103 struct cpuinfo_mips *c = &current_cpu_data;
9966db25 1104 unsigned int cpu = smp_processor_id();
1da177e4
LT		 1105
1106 c->processor_id = PRID_IMP_UNKNOWN;
1107 c->fpu_id = FPIR_IMP_NONE;
1108 c->cputype = CPU_UNKNOWN;
1109
1110 c->processor_id = read_c0_prid();
1111 switch (c->processor_id & 0xff0000) {
1112 case PRID_COMP_LEGACY:
cea7e2df 1113 cpu_probe_legacy(c, cpu);
1da177e4
LT		 1114 break;
1115 case PRID_COMP_MIPS:
cea7e2df 1116 cpu_probe_mips(c, cpu);
1da177e4
LT		 1117 break;
1118 case PRID_COMP_ALCHEMY:
cea7e2df 1119 cpu_probe_alchemy(c, cpu);
1da177e4
LT		 1120 break;
1121 case PRID_COMP_SIBYTE:
cea7e2df 1122 cpu_probe_sibyte(c, cpu);
1da177e4 1123 break;
1c0c13eb 1124 case PRID_COMP_BROADCOM:
cea7e2df 1125 cpu_probe_broadcom(c, cpu);
1c0c13eb 1126 break;
1da177e4 1127 case PRID_COMP_SANDCRAFT:
cea7e2df 1128 cpu_probe_sandcraft(c, cpu);
1da177e4 1129 break;
a92b0588 1130 case PRID_COMP_NXP:
cea7e2df 1131 cpu_probe_nxp(c, cpu);
a3dddd56 1132 break;
0dd4781b
DD		 1133 case PRID_COMP_CAVIUM:
1134 cpu_probe_cavium(c, cpu);
1135 break;
83ccf69d
LPC		 1136 case PRID_COMP_INGENIC:
1137 cpu_probe_ingenic(c, cpu);
1138 break;
a7117c6b
J		 1139 case PRID_COMP_NETLOGIC:
1140 cpu_probe_netlogic(c, cpu);
1141 break;
1da177e4 1142 }
dec8b1ca 1143
cea7e2df
RB		 1144 BUG_ON(!__cpu_name[cpu]);
1145 BUG_ON(c->cputype == CPU_UNKNOWN);
1146
dec8b1ca
FBH		 1147 /*
1148 * Platform code can force the cpu type to optimize code
1149 * generation. In that case be sure the cpu type is correctly
1150 * manually setup otherwise it could trigger some nasty bugs.
1151 */
1152 BUG_ON(current_cpu_type() != c->cputype);
1153
0103d23f
KC		 1154 if (mips_fpu_disabled)
1155 c->options &= ~MIPS_CPU_FPU;
1156
1157 if (mips_dsp_disabled)
1158 c->ases &= ~MIPS_ASE_DSP;
1159
4194318c 1160 if (c->options & MIPS_CPU_FPU) {
1da177e4 1161 c->fpu_id = cpu_get_fpu_id();
4194318c 1162
e7958bb9 1163 if (c->isa_level == MIPS_CPU_ISA_M32R1 ||
b4672d37
RB		 1164 c->isa_level == MIPS_CPU_ISA_M32R2 ||
1165 c->isa_level == MIPS_CPU_ISA_M64R1 ||
1166 c->isa_level == MIPS_CPU_ISA_M64R2) {
4194318c
RB		 1167 if (c->fpu_id & MIPS_FPIR_3D)
1168 c->ases |= MIPS_ASE_MIPS3D;
1169 }
1170 }
9966db25 1171
f6771dbb
RB		 1172 if (cpu_has_mips_r2)
1173 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
1174 else
1175 c->srsets = 1;
91dfc423
GR		 1176
1177 cpu_probe_vmbits(c);
949e51be
DD		 1178
1179#ifdef CONFIG_64BIT
1180 if (cpu == 0)
1181 __ua_limit = ~((1ull << cpu_vmbits) - 1);
1182#endif
1da177e4
LT		 1183}
1184
234fcd14 1185__cpuinit void cpu_report(void)
1da177e4
LT		 1186{
1187 struct cpuinfo_mips *c = &current_cpu_data;
1188
9966db25
RB		 1189 printk(KERN_INFO "CPU revision is: %08x (%s)\n",
1190 c->processor_id, cpu_name_string());
1da177e4 1191 if (c->options & MIPS_CPU_FPU)
9966db25 1192 printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id);
1da177e4 1193}
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