]>
Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * Processor capabilities determination functions. | |
3 | * | |
4 | * Copyright (C) xxxx the Anonymous | |
010b853b | 5 | * Copyright (C) 1994 - 2006 Ralf Baechle |
4194318c | 6 | * Copyright (C) 2003, 2004 Maciej W. Rozycki |
70342287 | 7 | * Copyright (C) 2001, 2004, 2011, 2012 MIPS Technologies, Inc. |
1da177e4 LT |
8 | * |
9 | * This program is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License | |
11 | * as published by the Free Software Foundation; either version | |
12 | * 2 of the License, or (at your option) any later version. | |
13 | */ | |
1da177e4 LT |
14 | #include <linux/init.h> |
15 | #include <linux/kernel.h> | |
16 | #include <linux/ptrace.h> | |
631330f5 | 17 | #include <linux/smp.h> |
1da177e4 | 18 | #include <linux/stddef.h> |
73bc256d | 19 | #include <linux/export.h> |
1da177e4 | 20 | |
5759906c | 21 | #include <asm/bugs.h> |
1da177e4 | 22 | #include <asm/cpu.h> |
69f24d17 | 23 | #include <asm/cpu-type.h> |
1da177e4 LT |
24 | #include <asm/fpu.h> |
25 | #include <asm/mipsregs.h> | |
30ee615b | 26 | #include <asm/mipsmtregs.h> |
a5e9a69e | 27 | #include <asm/msa.h> |
654f57bf | 28 | #include <asm/watch.h> |
06372a63 | 29 | #include <asm/elf.h> |
4f12b91d | 30 | #include <asm/pgtable-bits.h> |
a074f0e8 | 31 | #include <asm/spram.h> |
949e51be DD |
32 | #include <asm/uaccess.h> |
33 | ||
078a55fc | 34 | static int mips_fpu_disabled; |
0103d23f KC |
35 | |
36 | static int __init fpu_disable(char *s) | |
37 | { | |
38 | cpu_data[0].options &= ~MIPS_CPU_FPU; | |
39 | mips_fpu_disabled = 1; | |
40 | ||
41 | return 1; | |
42 | } | |
43 | ||
44 | __setup("nofpu", fpu_disable); | |
45 | ||
078a55fc | 46 | int mips_dsp_disabled; |
0103d23f KC |
47 | |
48 | static int __init dsp_disable(char *s) | |
49 | { | |
ee80f7c7 | 50 | cpu_data[0].ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P); |
0103d23f KC |
51 | mips_dsp_disabled = 1; |
52 | ||
53 | return 1; | |
54 | } | |
55 | ||
56 | __setup("nodsp", dsp_disable); | |
57 | ||
3d528b32 MC |
58 | static int mips_htw_disabled; |
59 | ||
60 | static int __init htw_disable(char *s) | |
61 | { | |
62 | mips_htw_disabled = 1; | |
63 | cpu_data[0].options &= ~MIPS_CPU_HTW; | |
64 | write_c0_pwctl(read_c0_pwctl() & | |
65 | ~(1 << MIPS_PWCTL_PWEN_SHIFT)); | |
66 | ||
67 | return 1; | |
68 | } | |
69 | ||
70 | __setup("nohtw", htw_disable); | |
71 | ||
97f4ad29 MC |
72 | static int mips_ftlb_disabled; |
73 | static int mips_has_ftlb_configured; | |
74 | ||
75 | static void set_ftlb_enable(struct cpuinfo_mips *c, int enable); | |
76 | ||
77 | static int __init ftlb_disable(char *s) | |
78 | { | |
79 | unsigned int config4, mmuextdef; | |
80 | ||
81 | /* | |
82 | * If the core hasn't done any FTLB configuration, there is nothing | |
83 | * for us to do here. | |
84 | */ | |
85 | if (!mips_has_ftlb_configured) | |
86 | return 1; | |
87 | ||
88 | /* Disable it in the boot cpu */ | |
89 | set_ftlb_enable(&cpu_data[0], 0); | |
90 | ||
91 | back_to_back_c0_hazard(); | |
92 | ||
93 | config4 = read_c0_config4(); | |
94 | ||
95 | /* Check that FTLB has been disabled */ | |
96 | mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF; | |
97 | /* MMUSIZEEXT == VTLB ON, FTLB OFF */ | |
98 | if (mmuextdef == MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT) { | |
99 | /* This should never happen */ | |
100 | pr_warn("FTLB could not be disabled!\n"); | |
101 | return 1; | |
102 | } | |
103 | ||
104 | mips_ftlb_disabled = 1; | |
105 | mips_has_ftlb_configured = 0; | |
106 | ||
107 | /* | |
108 | * noftlb is mainly used for debug purposes so print | |
109 | * an informative message instead of using pr_debug() | |
110 | */ | |
111 | pr_info("FTLB has been disabled\n"); | |
112 | ||
113 | /* | |
114 | * Some of these bits are duplicated in the decode_config4. | |
115 | * MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT is the only possible case | |
116 | * once FTLB has been disabled so undo what decode_config4 did. | |
117 | */ | |
118 | cpu_data[0].tlbsize -= cpu_data[0].tlbsizeftlbways * | |
119 | cpu_data[0].tlbsizeftlbsets; | |
120 | cpu_data[0].tlbsizeftlbsets = 0; | |
121 | cpu_data[0].tlbsizeftlbways = 0; | |
122 | ||
123 | return 1; | |
124 | } | |
125 | ||
126 | __setup("noftlb", ftlb_disable); | |
127 | ||
128 | ||
9267a30d MSJ |
129 | static inline void check_errata(void) |
130 | { | |
131 | struct cpuinfo_mips *c = ¤t_cpu_data; | |
132 | ||
69f24d17 | 133 | switch (current_cpu_type()) { |
9267a30d MSJ |
134 | case CPU_34K: |
135 | /* | |
136 | * Erratum "RPS May Cause Incorrect Instruction Execution" | |
b633648c | 137 | * This code only handles VPE0, any SMP/RTOS code |
9267a30d MSJ |
138 | * making use of VPE1 will be responsable for that VPE. |
139 | */ | |
140 | if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2) | |
141 | write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS); | |
142 | break; | |
143 | default: | |
144 | break; | |
145 | } | |
146 | } | |
147 | ||
1da177e4 LT |
148 | void __init check_bugs32(void) |
149 | { | |
9267a30d | 150 | check_errata(); |
1da177e4 LT |
151 | } |
152 | ||
153 | /* | |
154 | * Probe whether cpu has config register by trying to play with | |
155 | * alternate cache bit and see whether it matters. | |
156 | * It's used by cpu_probe to distinguish between R3000A and R3081. | |
157 | */ | |
158 | static inline int cpu_has_confreg(void) | |
159 | { | |
160 | #ifdef CONFIG_CPU_R3000 | |
161 | extern unsigned long r3k_cache_size(unsigned long); | |
162 | unsigned long size1, size2; | |
163 | unsigned long cfg = read_c0_conf(); | |
164 | ||
165 | size1 = r3k_cache_size(ST0_ISC); | |
166 | write_c0_conf(cfg ^ R30XX_CONF_AC); | |
167 | size2 = r3k_cache_size(ST0_ISC); | |
168 | write_c0_conf(cfg); | |
169 | return size1 != size2; | |
170 | #else | |
171 | return 0; | |
172 | #endif | |
173 | } | |
174 | ||
c094c99e RM |
175 | static inline void set_elf_platform(int cpu, const char *plat) |
176 | { | |
177 | if (cpu == 0) | |
178 | __elf_platform = plat; | |
179 | } | |
180 | ||
1da177e4 LT |
181 | /* |
182 | * Get the FPU Implementation/Revision. | |
183 | */ | |
184 | static inline unsigned long cpu_get_fpu_id(void) | |
185 | { | |
186 | unsigned long tmp, fpu_id; | |
187 | ||
188 | tmp = read_c0_status(); | |
597ce172 | 189 | __enable_fpu(FPU_AS_IS); |
1da177e4 LT |
190 | fpu_id = read_32bit_cp1_register(CP1_REVISION); |
191 | write_c0_status(tmp); | |
192 | return fpu_id; | |
193 | } | |
194 | ||
195 | /* | |
196 | * Check the CPU has an FPU the official way. | |
197 | */ | |
198 | static inline int __cpu_has_fpu(void) | |
199 | { | |
635c9907 | 200 | return (cpu_get_fpu_id() & FPIR_IMP_MASK) != FPIR_IMP_NONE; |
1da177e4 LT |
201 | } |
202 | ||
a5e9a69e PB |
203 | static inline unsigned long cpu_get_msa_id(void) |
204 | { | |
3587ea88 | 205 | unsigned long status, msa_id; |
a5e9a69e PB |
206 | |
207 | status = read_c0_status(); | |
208 | __enable_fpu(FPU_64BIT); | |
a5e9a69e PB |
209 | enable_msa(); |
210 | msa_id = read_msa_ir(); | |
3587ea88 | 211 | disable_msa(); |
a5e9a69e PB |
212 | write_c0_status(status); |
213 | return msa_id; | |
214 | } | |
215 | ||
91dfc423 GR |
216 | static inline void cpu_probe_vmbits(struct cpuinfo_mips *c) |
217 | { | |
218 | #ifdef __NEED_VMBITS_PROBE | |
5b7efa89 | 219 | write_c0_entryhi(0x3fffffffffffe000ULL); |
91dfc423 | 220 | back_to_back_c0_hazard(); |
5b7efa89 | 221 | c->vmbits = fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL); |
91dfc423 GR |
222 | #endif |
223 | } | |
224 | ||
078a55fc | 225 | static void set_isa(struct cpuinfo_mips *c, unsigned int isa) |
a96102be SH |
226 | { |
227 | switch (isa) { | |
228 | case MIPS_CPU_ISA_M64R2: | |
229 | c->isa_level |= MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2; | |
230 | case MIPS_CPU_ISA_M64R1: | |
231 | c->isa_level |= MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1; | |
232 | case MIPS_CPU_ISA_V: | |
233 | c->isa_level |= MIPS_CPU_ISA_V; | |
234 | case MIPS_CPU_ISA_IV: | |
235 | c->isa_level |= MIPS_CPU_ISA_IV; | |
236 | case MIPS_CPU_ISA_III: | |
1990e542 | 237 | c->isa_level |= MIPS_CPU_ISA_II | MIPS_CPU_ISA_III; |
a96102be SH |
238 | break; |
239 | ||
8b8aa636 LY |
240 | /* R6 incompatible with everything else */ |
241 | case MIPS_CPU_ISA_M64R6: | |
242 | c->isa_level |= MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6; | |
243 | case MIPS_CPU_ISA_M32R6: | |
244 | c->isa_level |= MIPS_CPU_ISA_M32R6; | |
245 | /* Break here so we don't add incompatible ISAs */ | |
246 | break; | |
a96102be SH |
247 | case MIPS_CPU_ISA_M32R2: |
248 | c->isa_level |= MIPS_CPU_ISA_M32R2; | |
249 | case MIPS_CPU_ISA_M32R1: | |
250 | c->isa_level |= MIPS_CPU_ISA_M32R1; | |
251 | case MIPS_CPU_ISA_II: | |
252 | c->isa_level |= MIPS_CPU_ISA_II; | |
a96102be SH |
253 | break; |
254 | } | |
255 | } | |
256 | ||
078a55fc | 257 | static char unknown_isa[] = KERN_ERR \ |
2fa36399 KC |
258 | "Unsupported ISA type, c0.config0: %d."; |
259 | ||
cf0a8aa0 MC |
260 | static unsigned int calculate_ftlb_probability(struct cpuinfo_mips *c) |
261 | { | |
262 | ||
263 | unsigned int probability = c->tlbsize / c->tlbsizevtlb; | |
264 | ||
265 | /* | |
266 | * 0 = All TLBWR instructions go to FTLB | |
267 | * 1 = 15:1: For every 16 TBLWR instructions, 15 go to the | |
268 | * FTLB and 1 goes to the VTLB. | |
269 | * 2 = 7:1: As above with 7:1 ratio. | |
270 | * 3 = 3:1: As above with 3:1 ratio. | |
271 | * | |
272 | * Use the linear midpoint as the probability threshold. | |
273 | */ | |
274 | if (probability >= 12) | |
275 | return 1; | |
276 | else if (probability >= 6) | |
277 | return 2; | |
278 | else | |
279 | /* | |
280 | * So FTLB is less than 4 times bigger than VTLB. | |
281 | * A 3:1 ratio can still be useful though. | |
282 | */ | |
283 | return 3; | |
284 | } | |
285 | ||
75b5b5e0 LY |
286 | static void set_ftlb_enable(struct cpuinfo_mips *c, int enable) |
287 | { | |
288 | unsigned int config6; | |
d83b0e82 JH |
289 | |
290 | /* It's implementation dependent how the FTLB can be enabled */ | |
291 | switch (c->cputype) { | |
292 | case CPU_PROAPTIV: | |
293 | case CPU_P5600: | |
294 | /* proAptiv & related cores use Config6 to enable the FTLB */ | |
75b5b5e0 | 295 | config6 = read_c0_config6(); |
cf0a8aa0 MC |
296 | /* Clear the old probability value */ |
297 | config6 &= ~(3 << MIPS_CONF6_FTLBP_SHIFT); | |
75b5b5e0 LY |
298 | if (enable) |
299 | /* Enable FTLB */ | |
cf0a8aa0 MC |
300 | write_c0_config6(config6 | |
301 | (calculate_ftlb_probability(c) | |
302 | << MIPS_CONF6_FTLBP_SHIFT) | |
303 | | MIPS_CONF6_FTLBEN); | |
75b5b5e0 LY |
304 | else |
305 | /* Disable FTLB */ | |
306 | write_c0_config6(config6 & ~MIPS_CONF6_FTLBEN); | |
307 | back_to_back_c0_hazard(); | |
d83b0e82 | 308 | break; |
75b5b5e0 LY |
309 | } |
310 | } | |
311 | ||
2fa36399 KC |
312 | static inline unsigned int decode_config0(struct cpuinfo_mips *c) |
313 | { | |
314 | unsigned int config0; | |
315 | int isa; | |
316 | ||
317 | config0 = read_c0_config(); | |
318 | ||
75b5b5e0 LY |
319 | /* |
320 | * Look for Standard TLB or Dual VTLB and FTLB | |
321 | */ | |
322 | if ((((config0 & MIPS_CONF_MT) >> 7) == 1) || | |
323 | (((config0 & MIPS_CONF_MT) >> 7) == 4)) | |
2fa36399 | 324 | c->options |= MIPS_CPU_TLB; |
75b5b5e0 | 325 | |
2fa36399 KC |
326 | isa = (config0 & MIPS_CONF_AT) >> 13; |
327 | switch (isa) { | |
328 | case 0: | |
329 | switch ((config0 & MIPS_CONF_AR) >> 10) { | |
330 | case 0: | |
a96102be | 331 | set_isa(c, MIPS_CPU_ISA_M32R1); |
2fa36399 KC |
332 | break; |
333 | case 1: | |
a96102be | 334 | set_isa(c, MIPS_CPU_ISA_M32R2); |
2fa36399 | 335 | break; |
8b8aa636 LY |
336 | case 2: |
337 | set_isa(c, MIPS_CPU_ISA_M32R6); | |
338 | break; | |
2fa36399 KC |
339 | default: |
340 | goto unknown; | |
341 | } | |
342 | break; | |
343 | case 2: | |
344 | switch ((config0 & MIPS_CONF_AR) >> 10) { | |
345 | case 0: | |
a96102be | 346 | set_isa(c, MIPS_CPU_ISA_M64R1); |
2fa36399 KC |
347 | break; |
348 | case 1: | |
a96102be | 349 | set_isa(c, MIPS_CPU_ISA_M64R2); |
2fa36399 | 350 | break; |
8b8aa636 LY |
351 | case 2: |
352 | set_isa(c, MIPS_CPU_ISA_M64R6); | |
353 | break; | |
2fa36399 KC |
354 | default: |
355 | goto unknown; | |
356 | } | |
357 | break; | |
358 | default: | |
359 | goto unknown; | |
360 | } | |
361 | ||
362 | return config0 & MIPS_CONF_M; | |
363 | ||
364 | unknown: | |
365 | panic(unknown_isa, config0); | |
366 | } | |
367 | ||
368 | static inline unsigned int decode_config1(struct cpuinfo_mips *c) | |
369 | { | |
370 | unsigned int config1; | |
371 | ||
372 | config1 = read_c0_config1(); | |
373 | ||
374 | if (config1 & MIPS_CONF1_MD) | |
375 | c->ases |= MIPS_ASE_MDMX; | |
376 | if (config1 & MIPS_CONF1_WR) | |
377 | c->options |= MIPS_CPU_WATCH; | |
378 | if (config1 & MIPS_CONF1_CA) | |
379 | c->ases |= MIPS_ASE_MIPS16; | |
380 | if (config1 & MIPS_CONF1_EP) | |
381 | c->options |= MIPS_CPU_EJTAG; | |
382 | if (config1 & MIPS_CONF1_FP) { | |
383 | c->options |= MIPS_CPU_FPU; | |
384 | c->options |= MIPS_CPU_32FPR; | |
385 | } | |
75b5b5e0 | 386 | if (cpu_has_tlb) { |
2fa36399 | 387 | c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1; |
75b5b5e0 LY |
388 | c->tlbsizevtlb = c->tlbsize; |
389 | c->tlbsizeftlbsets = 0; | |
390 | } | |
2fa36399 KC |
391 | |
392 | return config1 & MIPS_CONF_M; | |
393 | } | |
394 | ||
395 | static inline unsigned int decode_config2(struct cpuinfo_mips *c) | |
396 | { | |
397 | unsigned int config2; | |
398 | ||
399 | config2 = read_c0_config2(); | |
400 | ||
401 | if (config2 & MIPS_CONF2_SL) | |
402 | c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT; | |
403 | ||
404 | return config2 & MIPS_CONF_M; | |
405 | } | |
406 | ||
407 | static inline unsigned int decode_config3(struct cpuinfo_mips *c) | |
408 | { | |
409 | unsigned int config3; | |
410 | ||
411 | config3 = read_c0_config3(); | |
412 | ||
b2ab4f08 | 413 | if (config3 & MIPS_CONF3_SM) { |
2fa36399 | 414 | c->ases |= MIPS_ASE_SMARTMIPS; |
b2ab4f08 SH |
415 | c->options |= MIPS_CPU_RIXI; |
416 | } | |
417 | if (config3 & MIPS_CONF3_RXI) | |
418 | c->options |= MIPS_CPU_RIXI; | |
2fa36399 KC |
419 | if (config3 & MIPS_CONF3_DSP) |
420 | c->ases |= MIPS_ASE_DSP; | |
ee80f7c7 SH |
421 | if (config3 & MIPS_CONF3_DSP2P) |
422 | c->ases |= MIPS_ASE_DSP2P; | |
2fa36399 KC |
423 | if (config3 & MIPS_CONF3_VINT) |
424 | c->options |= MIPS_CPU_VINT; | |
425 | if (config3 & MIPS_CONF3_VEIC) | |
426 | c->options |= MIPS_CPU_VEIC; | |
427 | if (config3 & MIPS_CONF3_MT) | |
428 | c->ases |= MIPS_ASE_MIPSMT; | |
429 | if (config3 & MIPS_CONF3_ULRI) | |
430 | c->options |= MIPS_CPU_ULRI; | |
f8fa4811 SH |
431 | if (config3 & MIPS_CONF3_ISA) |
432 | c->options |= MIPS_CPU_MICROMIPS; | |
1e7decdb DD |
433 | if (config3 & MIPS_CONF3_VZ) |
434 | c->ases |= MIPS_ASE_VZ; | |
4a0156fb SH |
435 | if (config3 & MIPS_CONF3_SC) |
436 | c->options |= MIPS_CPU_SEGMENTS; | |
a5e9a69e PB |
437 | if (config3 & MIPS_CONF3_MSA) |
438 | c->ases |= MIPS_ASE_MSA; | |
3d528b32 | 439 | /* Only tested on 32-bit cores */ |
ed4cbc81 MC |
440 | if ((config3 & MIPS_CONF3_PW) && config_enabled(CONFIG_32BIT)) { |
441 | c->htw_seq = 0; | |
3d528b32 | 442 | c->options |= MIPS_CPU_HTW; |
ed4cbc81 | 443 | } |
2fa36399 KC |
444 | |
445 | return config3 & MIPS_CONF_M; | |
446 | } | |
447 | ||
448 | static inline unsigned int decode_config4(struct cpuinfo_mips *c) | |
449 | { | |
450 | unsigned int config4; | |
75b5b5e0 LY |
451 | unsigned int newcf4; |
452 | unsigned int mmuextdef; | |
453 | unsigned int ftlb_page = MIPS_CONF4_FTLBPAGESIZE; | |
2fa36399 KC |
454 | |
455 | config4 = read_c0_config4(); | |
456 | ||
1745c1ef LY |
457 | if (cpu_has_tlb) { |
458 | if (((config4 & MIPS_CONF4_IE) >> 29) == 2) | |
459 | c->options |= MIPS_CPU_TLBINV; | |
75b5b5e0 LY |
460 | mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF; |
461 | switch (mmuextdef) { | |
462 | case MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT: | |
463 | c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40; | |
464 | c->tlbsizevtlb = c->tlbsize; | |
465 | break; | |
466 | case MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT: | |
467 | c->tlbsizevtlb += | |
468 | ((config4 & MIPS_CONF4_VTLBSIZEEXT) >> | |
469 | MIPS_CONF4_VTLBSIZEEXT_SHIFT) * 0x40; | |
470 | c->tlbsize = c->tlbsizevtlb; | |
471 | ftlb_page = MIPS_CONF4_VFTLBPAGESIZE; | |
472 | /* fall through */ | |
473 | case MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT: | |
97f4ad29 MC |
474 | if (mips_ftlb_disabled) |
475 | break; | |
75b5b5e0 LY |
476 | newcf4 = (config4 & ~ftlb_page) | |
477 | (page_size_ftlb(mmuextdef) << | |
478 | MIPS_CONF4_FTLBPAGESIZE_SHIFT); | |
479 | write_c0_config4(newcf4); | |
480 | back_to_back_c0_hazard(); | |
481 | config4 = read_c0_config4(); | |
482 | if (config4 != newcf4) { | |
483 | pr_err("PAGE_SIZE 0x%lx is not supported by FTLB (config4=0x%x)\n", | |
484 | PAGE_SIZE, config4); | |
485 | /* Switch FTLB off */ | |
486 | set_ftlb_enable(c, 0); | |
487 | break; | |
488 | } | |
489 | c->tlbsizeftlbsets = 1 << | |
490 | ((config4 & MIPS_CONF4_FTLBSETS) >> | |
491 | MIPS_CONF4_FTLBSETS_SHIFT); | |
492 | c->tlbsizeftlbways = ((config4 & MIPS_CONF4_FTLBWAYS) >> | |
493 | MIPS_CONF4_FTLBWAYS_SHIFT) + 2; | |
494 | c->tlbsize += c->tlbsizeftlbways * c->tlbsizeftlbsets; | |
97f4ad29 | 495 | mips_has_ftlb_configured = 1; |
75b5b5e0 LY |
496 | break; |
497 | } | |
1745c1ef LY |
498 | } |
499 | ||
2fa36399 KC |
500 | c->kscratch_mask = (config4 >> 16) & 0xff; |
501 | ||
502 | return config4 & MIPS_CONF_M; | |
503 | } | |
504 | ||
8b8a7634 RB |
505 | static inline unsigned int decode_config5(struct cpuinfo_mips *c) |
506 | { | |
507 | unsigned int config5; | |
508 | ||
509 | config5 = read_c0_config5(); | |
d175ed2b | 510 | config5 &= ~(MIPS_CONF5_UFR | MIPS_CONF5_UFE); |
8b8a7634 RB |
511 | write_c0_config5(config5); |
512 | ||
49016748 MC |
513 | if (config5 & MIPS_CONF5_EVA) |
514 | c->options |= MIPS_CPU_EVA; | |
1f6c52ff PB |
515 | if (config5 & MIPS_CONF5_MRP) |
516 | c->options |= MIPS_CPU_MAAR; | |
49016748 | 517 | |
8b8a7634 RB |
518 | return config5 & MIPS_CONF_M; |
519 | } | |
520 | ||
078a55fc | 521 | static void decode_configs(struct cpuinfo_mips *c) |
2fa36399 KC |
522 | { |
523 | int ok; | |
524 | ||
525 | /* MIPS32 or MIPS64 compliant CPU. */ | |
526 | c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER | | |
527 | MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK; | |
528 | ||
529 | c->scache.flags = MIPS_CACHE_NOT_PRESENT; | |
530 | ||
97f4ad29 MC |
531 | /* Enable FTLB if present and not disabled */ |
532 | set_ftlb_enable(c, !mips_ftlb_disabled); | |
75b5b5e0 | 533 | |
2fa36399 | 534 | ok = decode_config0(c); /* Read Config registers. */ |
70342287 | 535 | BUG_ON(!ok); /* Arch spec violation! */ |
2fa36399 KC |
536 | if (ok) |
537 | ok = decode_config1(c); | |
538 | if (ok) | |
539 | ok = decode_config2(c); | |
540 | if (ok) | |
541 | ok = decode_config3(c); | |
542 | if (ok) | |
543 | ok = decode_config4(c); | |
8b8a7634 RB |
544 | if (ok) |
545 | ok = decode_config5(c); | |
2fa36399 KC |
546 | |
547 | mips_probe_watch_registers(c); | |
548 | ||
6575b1d4 LY |
549 | if (cpu_has_rixi) { |
550 | /* Enable the RIXI exceptions */ | |
551 | write_c0_pagegrain(read_c0_pagegrain() | PG_IEC); | |
552 | back_to_back_c0_hazard(); | |
553 | /* Verify the IEC bit is set */ | |
554 | if (read_c0_pagegrain() & PG_IEC) | |
555 | c->options |= MIPS_CPU_RIXIEX; | |
556 | } | |
557 | ||
0ee958e1 | 558 | #ifndef CONFIG_MIPS_CPS |
8b8aa636 | 559 | if (cpu_has_mips_r2_r6) { |
45b585c8 | 560 | c->core = get_ebase_cpunum(); |
30ee615b PB |
561 | if (cpu_has_mipsmt) |
562 | c->core >>= fls(core_nvpes()) - 1; | |
563 | } | |
0ee958e1 | 564 | #endif |
2fa36399 KC |
565 | } |
566 | ||
02cf2119 | 567 | #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \ |
1da177e4 LT |
568 | | MIPS_CPU_COUNTER) |
569 | ||
cea7e2df | 570 | static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu) |
1da177e4 | 571 | { |
8ff374b9 | 572 | switch (c->processor_id & PRID_IMP_MASK) { |
1da177e4 LT |
573 | case PRID_IMP_R2000: |
574 | c->cputype = CPU_R2000; | |
cea7e2df | 575 | __cpu_name[cpu] = "R2000"; |
02cf2119 | 576 | c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE | |
03751e79 | 577 | MIPS_CPU_NOFPUEX; |
1da177e4 LT |
578 | if (__cpu_has_fpu()) |
579 | c->options |= MIPS_CPU_FPU; | |
580 | c->tlbsize = 64; | |
581 | break; | |
582 | case PRID_IMP_R3000: | |
8ff374b9 | 583 | if ((c->processor_id & PRID_REV_MASK) == PRID_REV_R3000A) { |
cea7e2df | 584 | if (cpu_has_confreg()) { |
1da177e4 | 585 | c->cputype = CPU_R3081E; |
cea7e2df RB |
586 | __cpu_name[cpu] = "R3081"; |
587 | } else { | |
1da177e4 | 588 | c->cputype = CPU_R3000A; |
cea7e2df RB |
589 | __cpu_name[cpu] = "R3000A"; |
590 | } | |
cea7e2df | 591 | } else { |
1da177e4 | 592 | c->cputype = CPU_R3000; |
cea7e2df RB |
593 | __cpu_name[cpu] = "R3000"; |
594 | } | |
02cf2119 | 595 | c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE | |
03751e79 | 596 | MIPS_CPU_NOFPUEX; |
1da177e4 LT |
597 | if (__cpu_has_fpu()) |
598 | c->options |= MIPS_CPU_FPU; | |
599 | c->tlbsize = 64; | |
600 | break; | |
601 | case PRID_IMP_R4000: | |
602 | if (read_c0_config() & CONF_SC) { | |
8ff374b9 MR |
603 | if ((c->processor_id & PRID_REV_MASK) >= |
604 | PRID_REV_R4400) { | |
1da177e4 | 605 | c->cputype = CPU_R4400PC; |
cea7e2df RB |
606 | __cpu_name[cpu] = "R4400PC"; |
607 | } else { | |
1da177e4 | 608 | c->cputype = CPU_R4000PC; |
cea7e2df RB |
609 | __cpu_name[cpu] = "R4000PC"; |
610 | } | |
1da177e4 | 611 | } else { |
7f177a52 MR |
612 | int cca = read_c0_config() & CONF_CM_CMASK; |
613 | int mc; | |
614 | ||
615 | /* | |
616 | * SC and MC versions can't be reliably told apart, | |
617 | * but only the latter support coherent caching | |
618 | * modes so assume the firmware has set the KSEG0 | |
619 | * coherency attribute reasonably (if uncached, we | |
620 | * assume SC). | |
621 | */ | |
622 | switch (cca) { | |
623 | case CONF_CM_CACHABLE_CE: | |
624 | case CONF_CM_CACHABLE_COW: | |
625 | case CONF_CM_CACHABLE_CUW: | |
626 | mc = 1; | |
627 | break; | |
628 | default: | |
629 | mc = 0; | |
630 | break; | |
631 | } | |
8ff374b9 MR |
632 | if ((c->processor_id & PRID_REV_MASK) >= |
633 | PRID_REV_R4400) { | |
7f177a52 MR |
634 | c->cputype = mc ? CPU_R4400MC : CPU_R4400SC; |
635 | __cpu_name[cpu] = mc ? "R4400MC" : "R4400SC"; | |
cea7e2df | 636 | } else { |
7f177a52 MR |
637 | c->cputype = mc ? CPU_R4000MC : CPU_R4000SC; |
638 | __cpu_name[cpu] = mc ? "R4000MC" : "R4000SC"; | |
cea7e2df | 639 | } |
1da177e4 LT |
640 | } |
641 | ||
a96102be | 642 | set_isa(c, MIPS_CPU_ISA_III); |
1da177e4 | 643 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | |
03751e79 SH |
644 | MIPS_CPU_WATCH | MIPS_CPU_VCE | |
645 | MIPS_CPU_LLSC; | |
1da177e4 LT |
646 | c->tlbsize = 48; |
647 | break; | |
648 | case PRID_IMP_VR41XX: | |
9f91e506 YY |
649 | set_isa(c, MIPS_CPU_ISA_III); |
650 | c->options = R4K_OPTS; | |
651 | c->tlbsize = 32; | |
1da177e4 | 652 | switch (c->processor_id & 0xf0) { |
1da177e4 LT |
653 | case PRID_REV_VR4111: |
654 | c->cputype = CPU_VR4111; | |
cea7e2df | 655 | __cpu_name[cpu] = "NEC VR4111"; |
1da177e4 | 656 | break; |
1da177e4 LT |
657 | case PRID_REV_VR4121: |
658 | c->cputype = CPU_VR4121; | |
cea7e2df | 659 | __cpu_name[cpu] = "NEC VR4121"; |
1da177e4 LT |
660 | break; |
661 | case PRID_REV_VR4122: | |
cea7e2df | 662 | if ((c->processor_id & 0xf) < 0x3) { |
1da177e4 | 663 | c->cputype = CPU_VR4122; |
cea7e2df RB |
664 | __cpu_name[cpu] = "NEC VR4122"; |
665 | } else { | |
1da177e4 | 666 | c->cputype = CPU_VR4181A; |
cea7e2df RB |
667 | __cpu_name[cpu] = "NEC VR4181A"; |
668 | } | |
1da177e4 LT |
669 | break; |
670 | case PRID_REV_VR4130: | |
cea7e2df | 671 | if ((c->processor_id & 0xf) < 0x4) { |
1da177e4 | 672 | c->cputype = CPU_VR4131; |
cea7e2df RB |
673 | __cpu_name[cpu] = "NEC VR4131"; |
674 | } else { | |
1da177e4 | 675 | c->cputype = CPU_VR4133; |
9f91e506 | 676 | c->options |= MIPS_CPU_LLSC; |
cea7e2df RB |
677 | __cpu_name[cpu] = "NEC VR4133"; |
678 | } | |
1da177e4 LT |
679 | break; |
680 | default: | |
681 | printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n"); | |
682 | c->cputype = CPU_VR41XX; | |
cea7e2df | 683 | __cpu_name[cpu] = "NEC Vr41xx"; |
1da177e4 LT |
684 | break; |
685 | } | |
1da177e4 LT |
686 | break; |
687 | case PRID_IMP_R4300: | |
688 | c->cputype = CPU_R4300; | |
cea7e2df | 689 | __cpu_name[cpu] = "R4300"; |
a96102be | 690 | set_isa(c, MIPS_CPU_ISA_III); |
1da177e4 | 691 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | |
03751e79 | 692 | MIPS_CPU_LLSC; |
1da177e4 LT |
693 | c->tlbsize = 32; |
694 | break; | |
695 | case PRID_IMP_R4600: | |
696 | c->cputype = CPU_R4600; | |
cea7e2df | 697 | __cpu_name[cpu] = "R4600"; |
a96102be | 698 | set_isa(c, MIPS_CPU_ISA_III); |
075e7502 TS |
699 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | |
700 | MIPS_CPU_LLSC; | |
1da177e4 LT |
701 | c->tlbsize = 48; |
702 | break; | |
703 | #if 0 | |
03751e79 | 704 | case PRID_IMP_R4650: |
1da177e4 LT |
705 | /* |
706 | * This processor doesn't have an MMU, so it's not | |
707 | * "real easy" to run Linux on it. It is left purely | |
708 | * for documentation. Commented out because it shares | |
709 | * it's c0_prid id number with the TX3900. | |
710 | */ | |
a3dddd56 | 711 | c->cputype = CPU_R4650; |
cea7e2df | 712 | __cpu_name[cpu] = "R4650"; |
a96102be | 713 | set_isa(c, MIPS_CPU_ISA_III); |
1da177e4 | 714 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC; |
03751e79 | 715 | c->tlbsize = 48; |
1da177e4 LT |
716 | break; |
717 | #endif | |
718 | case PRID_IMP_TX39: | |
02cf2119 | 719 | c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE; |
1da177e4 LT |
720 | |
721 | if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) { | |
722 | c->cputype = CPU_TX3927; | |
cea7e2df | 723 | __cpu_name[cpu] = "TX3927"; |
1da177e4 LT |
724 | c->tlbsize = 64; |
725 | } else { | |
8ff374b9 | 726 | switch (c->processor_id & PRID_REV_MASK) { |
1da177e4 LT |
727 | case PRID_REV_TX3912: |
728 | c->cputype = CPU_TX3912; | |
cea7e2df | 729 | __cpu_name[cpu] = "TX3912"; |
1da177e4 LT |
730 | c->tlbsize = 32; |
731 | break; | |
732 | case PRID_REV_TX3922: | |
733 | c->cputype = CPU_TX3922; | |
cea7e2df | 734 | __cpu_name[cpu] = "TX3922"; |
1da177e4 LT |
735 | c->tlbsize = 64; |
736 | break; | |
1da177e4 LT |
737 | } |
738 | } | |
739 | break; | |
740 | case PRID_IMP_R4700: | |
741 | c->cputype = CPU_R4700; | |
cea7e2df | 742 | __cpu_name[cpu] = "R4700"; |
a96102be | 743 | set_isa(c, MIPS_CPU_ISA_III); |
1da177e4 | 744 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | |
03751e79 | 745 | MIPS_CPU_LLSC; |
1da177e4 LT |
746 | c->tlbsize = 48; |
747 | break; | |
748 | case PRID_IMP_TX49: | |
749 | c->cputype = CPU_TX49XX; | |
cea7e2df | 750 | __cpu_name[cpu] = "R49XX"; |
a96102be | 751 | set_isa(c, MIPS_CPU_ISA_III); |
1da177e4 LT |
752 | c->options = R4K_OPTS | MIPS_CPU_LLSC; |
753 | if (!(c->processor_id & 0x08)) | |
754 | c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR; | |
755 | c->tlbsize = 48; | |
756 | break; | |
757 | case PRID_IMP_R5000: | |
758 | c->cputype = CPU_R5000; | |
cea7e2df | 759 | __cpu_name[cpu] = "R5000"; |
a96102be | 760 | set_isa(c, MIPS_CPU_ISA_IV); |
1da177e4 | 761 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | |
03751e79 | 762 | MIPS_CPU_LLSC; |
1da177e4 LT |
763 | c->tlbsize = 48; |
764 | break; | |
765 | case PRID_IMP_R5432: | |
766 | c->cputype = CPU_R5432; | |
cea7e2df | 767 | __cpu_name[cpu] = "R5432"; |
a96102be | 768 | set_isa(c, MIPS_CPU_ISA_IV); |
1da177e4 | 769 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | |
03751e79 | 770 | MIPS_CPU_WATCH | MIPS_CPU_LLSC; |
1da177e4 LT |
771 | c->tlbsize = 48; |
772 | break; | |
773 | case PRID_IMP_R5500: | |
774 | c->cputype = CPU_R5500; | |
cea7e2df | 775 | __cpu_name[cpu] = "R5500"; |
a96102be | 776 | set_isa(c, MIPS_CPU_ISA_IV); |
1da177e4 | 777 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | |
03751e79 | 778 | MIPS_CPU_WATCH | MIPS_CPU_LLSC; |
1da177e4 LT |
779 | c->tlbsize = 48; |
780 | break; | |
781 | case PRID_IMP_NEVADA: | |
782 | c->cputype = CPU_NEVADA; | |
cea7e2df | 783 | __cpu_name[cpu] = "Nevada"; |
a96102be | 784 | set_isa(c, MIPS_CPU_ISA_IV); |
1da177e4 | 785 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | |
03751e79 | 786 | MIPS_CPU_DIVEC | MIPS_CPU_LLSC; |
1da177e4 LT |
787 | c->tlbsize = 48; |
788 | break; | |
789 | case PRID_IMP_R6000: | |
790 | c->cputype = CPU_R6000; | |
cea7e2df | 791 | __cpu_name[cpu] = "R6000"; |
a96102be | 792 | set_isa(c, MIPS_CPU_ISA_II); |
1da177e4 | 793 | c->options = MIPS_CPU_TLB | MIPS_CPU_FPU | |
03751e79 | 794 | MIPS_CPU_LLSC; |
1da177e4 LT |
795 | c->tlbsize = 32; |
796 | break; | |
797 | case PRID_IMP_R6000A: | |
798 | c->cputype = CPU_R6000A; | |
cea7e2df | 799 | __cpu_name[cpu] = "R6000A"; |
a96102be | 800 | set_isa(c, MIPS_CPU_ISA_II); |
1da177e4 | 801 | c->options = MIPS_CPU_TLB | MIPS_CPU_FPU | |
03751e79 | 802 | MIPS_CPU_LLSC; |
1da177e4 LT |
803 | c->tlbsize = 32; |
804 | break; | |
805 | case PRID_IMP_RM7000: | |
806 | c->cputype = CPU_RM7000; | |
cea7e2df | 807 | __cpu_name[cpu] = "RM7000"; |
a96102be | 808 | set_isa(c, MIPS_CPU_ISA_IV); |
1da177e4 | 809 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | |
03751e79 | 810 | MIPS_CPU_LLSC; |
1da177e4 | 811 | /* |
70342287 | 812 | * Undocumented RM7000: Bit 29 in the info register of |
1da177e4 LT |
813 | * the RM7000 v2.0 indicates if the TLB has 48 or 64 |
814 | * entries. | |
815 | * | |
70342287 RB |
816 | * 29 1 => 64 entry JTLB |
817 | * 0 => 48 entry JTLB | |
1da177e4 LT |
818 | */ |
819 | c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48; | |
1da177e4 LT |
820 | break; |
821 | case PRID_IMP_R8000: | |
822 | c->cputype = CPU_R8000; | |
cea7e2df | 823 | __cpu_name[cpu] = "RM8000"; |
a96102be | 824 | set_isa(c, MIPS_CPU_ISA_IV); |
1da177e4 | 825 | c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX | |
03751e79 SH |
826 | MIPS_CPU_FPU | MIPS_CPU_32FPR | |
827 | MIPS_CPU_LLSC; | |
1da177e4 LT |
828 | c->tlbsize = 384; /* has weird TLB: 3-way x 128 */ |
829 | break; | |
830 | case PRID_IMP_R10000: | |
831 | c->cputype = CPU_R10000; | |
cea7e2df | 832 | __cpu_name[cpu] = "R10000"; |
a96102be | 833 | set_isa(c, MIPS_CPU_ISA_IV); |
8b36612a | 834 | c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | |
03751e79 | 835 | MIPS_CPU_FPU | MIPS_CPU_32FPR | |
1da177e4 | 836 | MIPS_CPU_COUNTER | MIPS_CPU_WATCH | |
03751e79 | 837 | MIPS_CPU_LLSC; |
1da177e4 LT |
838 | c->tlbsize = 64; |
839 | break; | |
840 | case PRID_IMP_R12000: | |
841 | c->cputype = CPU_R12000; | |
cea7e2df | 842 | __cpu_name[cpu] = "R12000"; |
a96102be | 843 | set_isa(c, MIPS_CPU_ISA_IV); |
8b36612a | 844 | c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | |
03751e79 | 845 | MIPS_CPU_FPU | MIPS_CPU_32FPR | |
1da177e4 | 846 | MIPS_CPU_COUNTER | MIPS_CPU_WATCH | |
03751e79 | 847 | MIPS_CPU_LLSC; |
1da177e4 LT |
848 | c->tlbsize = 64; |
849 | break; | |
44d921b2 K |
850 | case PRID_IMP_R14000: |
851 | c->cputype = CPU_R14000; | |
cea7e2df | 852 | __cpu_name[cpu] = "R14000"; |
a96102be | 853 | set_isa(c, MIPS_CPU_ISA_IV); |
44d921b2 | 854 | c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | |
03751e79 | 855 | MIPS_CPU_FPU | MIPS_CPU_32FPR | |
44d921b2 | 856 | MIPS_CPU_COUNTER | MIPS_CPU_WATCH | |
03751e79 | 857 | MIPS_CPU_LLSC; |
44d921b2 K |
858 | c->tlbsize = 64; |
859 | break; | |
26859198 | 860 | case PRID_IMP_LOONGSON_64: /* Loongson-2/3 */ |
5aac1e8a RM |
861 | switch (c->processor_id & PRID_REV_MASK) { |
862 | case PRID_REV_LOONGSON2E: | |
c579d310 HC |
863 | c->cputype = CPU_LOONGSON2; |
864 | __cpu_name[cpu] = "ICT Loongson-2"; | |
5aac1e8a | 865 | set_elf_platform(cpu, "loongson2e"); |
7352c8b1 | 866 | set_isa(c, MIPS_CPU_ISA_III); |
5aac1e8a RM |
867 | break; |
868 | case PRID_REV_LOONGSON2F: | |
c579d310 HC |
869 | c->cputype = CPU_LOONGSON2; |
870 | __cpu_name[cpu] = "ICT Loongson-2"; | |
5aac1e8a | 871 | set_elf_platform(cpu, "loongson2f"); |
7352c8b1 | 872 | set_isa(c, MIPS_CPU_ISA_III); |
5aac1e8a | 873 | break; |
c579d310 HC |
874 | case PRID_REV_LOONGSON3A: |
875 | c->cputype = CPU_LOONGSON3; | |
876 | __cpu_name[cpu] = "ICT Loongson-3"; | |
877 | set_elf_platform(cpu, "loongson3a"); | |
7352c8b1 | 878 | set_isa(c, MIPS_CPU_ISA_M64R1); |
c579d310 | 879 | break; |
e7841be5 HC |
880 | case PRID_REV_LOONGSON3B_R1: |
881 | case PRID_REV_LOONGSON3B_R2: | |
882 | c->cputype = CPU_LOONGSON3; | |
883 | __cpu_name[cpu] = "ICT Loongson-3"; | |
884 | set_elf_platform(cpu, "loongson3b"); | |
7352c8b1 | 885 | set_isa(c, MIPS_CPU_ISA_M64R1); |
e7841be5 | 886 | break; |
5aac1e8a RM |
887 | } |
888 | ||
2a21c730 FZ |
889 | c->options = R4K_OPTS | |
890 | MIPS_CPU_FPU | MIPS_CPU_LLSC | | |
891 | MIPS_CPU_32FPR; | |
892 | c->tlbsize = 64; | |
cc94ea31 | 893 | c->writecombine = _CACHE_UNCACHED_ACCELERATED; |
2a21c730 | 894 | break; |
26859198 | 895 | case PRID_IMP_LOONGSON_32: /* Loongson-1 */ |
2fa36399 | 896 | decode_configs(c); |
b4672d37 | 897 | |
2fa36399 | 898 | c->cputype = CPU_LOONGSON1; |
1da177e4 | 899 | |
2fa36399 KC |
900 | switch (c->processor_id & PRID_REV_MASK) { |
901 | case PRID_REV_LOONGSON1B: | |
902 | __cpu_name[cpu] = "Loongson 1B"; | |
b4672d37 | 903 | break; |
b4672d37 | 904 | } |
4194318c | 905 | |
2fa36399 | 906 | break; |
1da177e4 | 907 | } |
1da177e4 LT |
908 | } |
909 | ||
cea7e2df | 910 | static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu) |
1da177e4 | 911 | { |
4f12b91d | 912 | c->writecombine = _CACHE_UNCACHED_ACCELERATED; |
8ff374b9 | 913 | switch (c->processor_id & PRID_IMP_MASK) { |
b2498af5 LY |
914 | case PRID_IMP_QEMU_GENERIC: |
915 | c->writecombine = _CACHE_UNCACHED; | |
916 | c->cputype = CPU_QEMU_GENERIC; | |
917 | __cpu_name[cpu] = "MIPS GENERIC QEMU"; | |
918 | break; | |
1da177e4 LT |
919 | case PRID_IMP_4KC: |
920 | c->cputype = CPU_4KC; | |
4f12b91d | 921 | c->writecombine = _CACHE_UNCACHED; |
cea7e2df | 922 | __cpu_name[cpu] = "MIPS 4Kc"; |
1da177e4 LT |
923 | break; |
924 | case PRID_IMP_4KEC: | |
2b07bd02 RB |
925 | case PRID_IMP_4KECR2: |
926 | c->cputype = CPU_4KEC; | |
4f12b91d | 927 | c->writecombine = _CACHE_UNCACHED; |
cea7e2df | 928 | __cpu_name[cpu] = "MIPS 4KEc"; |
2b07bd02 | 929 | break; |
1da177e4 | 930 | case PRID_IMP_4KSC: |
8afcb5d8 | 931 | case PRID_IMP_4KSD: |
1da177e4 | 932 | c->cputype = CPU_4KSC; |
4f12b91d | 933 | c->writecombine = _CACHE_UNCACHED; |
cea7e2df | 934 | __cpu_name[cpu] = "MIPS 4KSc"; |
1da177e4 LT |
935 | break; |
936 | case PRID_IMP_5KC: | |
937 | c->cputype = CPU_5KC; | |
4f12b91d | 938 | c->writecombine = _CACHE_UNCACHED; |
cea7e2df | 939 | __cpu_name[cpu] = "MIPS 5Kc"; |
1da177e4 | 940 | break; |
78d4803f LY |
941 | case PRID_IMP_5KE: |
942 | c->cputype = CPU_5KE; | |
4f12b91d | 943 | c->writecombine = _CACHE_UNCACHED; |
78d4803f LY |
944 | __cpu_name[cpu] = "MIPS 5KE"; |
945 | break; | |
1da177e4 LT |
946 | case PRID_IMP_20KC: |
947 | c->cputype = CPU_20KC; | |
4f12b91d | 948 | c->writecombine = _CACHE_UNCACHED; |
cea7e2df | 949 | __cpu_name[cpu] = "MIPS 20Kc"; |
1da177e4 LT |
950 | break; |
951 | case PRID_IMP_24K: | |
952 | c->cputype = CPU_24K; | |
4f12b91d | 953 | c->writecombine = _CACHE_UNCACHED; |
cea7e2df | 954 | __cpu_name[cpu] = "MIPS 24Kc"; |
1da177e4 | 955 | break; |
42f3caef JC |
956 | case PRID_IMP_24KE: |
957 | c->cputype = CPU_24K; | |
4f12b91d | 958 | c->writecombine = _CACHE_UNCACHED; |
42f3caef JC |
959 | __cpu_name[cpu] = "MIPS 24KEc"; |
960 | break; | |
1da177e4 LT |
961 | case PRID_IMP_25KF: |
962 | c->cputype = CPU_25KF; | |
4f12b91d | 963 | c->writecombine = _CACHE_UNCACHED; |
cea7e2df | 964 | __cpu_name[cpu] = "MIPS 25Kc"; |
1da177e4 | 965 | break; |
bbc7f22f RB |
966 | case PRID_IMP_34K: |
967 | c->cputype = CPU_34K; | |
4f12b91d | 968 | c->writecombine = _CACHE_UNCACHED; |
cea7e2df | 969 | __cpu_name[cpu] = "MIPS 34Kc"; |
bbc7f22f | 970 | break; |
c620953c CD |
971 | case PRID_IMP_74K: |
972 | c->cputype = CPU_74K; | |
4f12b91d | 973 | c->writecombine = _CACHE_UNCACHED; |
cea7e2df | 974 | __cpu_name[cpu] = "MIPS 74Kc"; |
c620953c | 975 | break; |
113c62d9 SH |
976 | case PRID_IMP_M14KC: |
977 | c->cputype = CPU_M14KC; | |
4f12b91d | 978 | c->writecombine = _CACHE_UNCACHED; |
113c62d9 SH |
979 | __cpu_name[cpu] = "MIPS M14Kc"; |
980 | break; | |
f8fa4811 SH |
981 | case PRID_IMP_M14KEC: |
982 | c->cputype = CPU_M14KEC; | |
4f12b91d | 983 | c->writecombine = _CACHE_UNCACHED; |
f8fa4811 SH |
984 | __cpu_name[cpu] = "MIPS M14KEc"; |
985 | break; | |
39b8d525 RB |
986 | case PRID_IMP_1004K: |
987 | c->cputype = CPU_1004K; | |
4f12b91d | 988 | c->writecombine = _CACHE_UNCACHED; |
cea7e2df | 989 | __cpu_name[cpu] = "MIPS 1004Kc"; |
39b8d525 | 990 | break; |
006a851b | 991 | case PRID_IMP_1074K: |
442e14a2 | 992 | c->cputype = CPU_1074K; |
4f12b91d | 993 | c->writecombine = _CACHE_UNCACHED; |
006a851b SH |
994 | __cpu_name[cpu] = "MIPS 1074Kc"; |
995 | break; | |
b5f065e7 LY |
996 | case PRID_IMP_INTERAPTIV_UP: |
997 | c->cputype = CPU_INTERAPTIV; | |
998 | __cpu_name[cpu] = "MIPS interAptiv"; | |
999 | break; | |
1000 | case PRID_IMP_INTERAPTIV_MP: | |
1001 | c->cputype = CPU_INTERAPTIV; | |
1002 | __cpu_name[cpu] = "MIPS interAptiv (multi)"; | |
1003 | break; | |
b0d4d300 LY |
1004 | case PRID_IMP_PROAPTIV_UP: |
1005 | c->cputype = CPU_PROAPTIV; | |
1006 | __cpu_name[cpu] = "MIPS proAptiv"; | |
1007 | break; | |
1008 | case PRID_IMP_PROAPTIV_MP: | |
1009 | c->cputype = CPU_PROAPTIV; | |
1010 | __cpu_name[cpu] = "MIPS proAptiv (multi)"; | |
1011 | break; | |
829dcc0a JH |
1012 | case PRID_IMP_P5600: |
1013 | c->cputype = CPU_P5600; | |
1014 | __cpu_name[cpu] = "MIPS P5600"; | |
1015 | break; | |
9943ed92 LY |
1016 | case PRID_IMP_M5150: |
1017 | c->cputype = CPU_M5150; | |
1018 | __cpu_name[cpu] = "MIPS M5150"; | |
1019 | break; | |
1da177e4 | 1020 | } |
0b6d497f | 1021 | |
75b5b5e0 LY |
1022 | decode_configs(c); |
1023 | ||
0b6d497f | 1024 | spram_config(); |
1da177e4 LT |
1025 | } |
1026 | ||
cea7e2df | 1027 | static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu) |
1da177e4 | 1028 | { |
4194318c | 1029 | decode_configs(c); |
8ff374b9 | 1030 | switch (c->processor_id & PRID_IMP_MASK) { |
1da177e4 LT |
1031 | case PRID_IMP_AU1_REV1: |
1032 | case PRID_IMP_AU1_REV2: | |
270717a8 | 1033 | c->cputype = CPU_ALCHEMY; |
1da177e4 LT |
1034 | switch ((c->processor_id >> 24) & 0xff) { |
1035 | case 0: | |
cea7e2df | 1036 | __cpu_name[cpu] = "Au1000"; |
1da177e4 LT |
1037 | break; |
1038 | case 1: | |
cea7e2df | 1039 | __cpu_name[cpu] = "Au1500"; |
1da177e4 LT |
1040 | break; |
1041 | case 2: | |
cea7e2df | 1042 | __cpu_name[cpu] = "Au1100"; |
1da177e4 LT |
1043 | break; |
1044 | case 3: | |
cea7e2df | 1045 | __cpu_name[cpu] = "Au1550"; |
1da177e4 | 1046 | break; |
e3ad1c23 | 1047 | case 4: |
cea7e2df | 1048 | __cpu_name[cpu] = "Au1200"; |
8ff374b9 | 1049 | if ((c->processor_id & PRID_REV_MASK) == 2) |
cea7e2df | 1050 | __cpu_name[cpu] = "Au1250"; |
237cfee1 ML |
1051 | break; |
1052 | case 5: | |
cea7e2df | 1053 | __cpu_name[cpu] = "Au1210"; |
e3ad1c23 | 1054 | break; |
1da177e4 | 1055 | default: |
270717a8 | 1056 | __cpu_name[cpu] = "Au1xxx"; |
1da177e4 LT |
1057 | break; |
1058 | } | |
1da177e4 LT |
1059 | break; |
1060 | } | |
1061 | } | |
1062 | ||
cea7e2df | 1063 | static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu) |
1da177e4 | 1064 | { |
4194318c | 1065 | decode_configs(c); |
02cf2119 | 1066 | |
4f12b91d | 1067 | c->writecombine = _CACHE_UNCACHED_ACCELERATED; |
8ff374b9 | 1068 | switch (c->processor_id & PRID_IMP_MASK) { |
1da177e4 LT |
1069 | case PRID_IMP_SB1: |
1070 | c->cputype = CPU_SB1; | |
cea7e2df | 1071 | __cpu_name[cpu] = "SiByte SB1"; |
1da177e4 | 1072 | /* FPU in pass1 is known to have issues. */ |
8ff374b9 | 1073 | if ((c->processor_id & PRID_REV_MASK) < 0x02) |
010b853b | 1074 | c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR); |
1da177e4 | 1075 | break; |
93ce2f52 AI |
1076 | case PRID_IMP_SB1A: |
1077 | c->cputype = CPU_SB1A; | |
cea7e2df | 1078 | __cpu_name[cpu] = "SiByte SB1A"; |
93ce2f52 | 1079 | break; |
1da177e4 LT |
1080 | } |
1081 | } | |
1082 | ||
cea7e2df | 1083 | static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu) |
1da177e4 | 1084 | { |
4194318c | 1085 | decode_configs(c); |
8ff374b9 | 1086 | switch (c->processor_id & PRID_IMP_MASK) { |
1da177e4 LT |
1087 | case PRID_IMP_SR71000: |
1088 | c->cputype = CPU_SR71000; | |
cea7e2df | 1089 | __cpu_name[cpu] = "Sandcraft SR71000"; |
1da177e4 LT |
1090 | c->scache.ways = 8; |
1091 | c->tlbsize = 64; | |
1092 | break; | |
1093 | } | |
1094 | } | |
1095 | ||
cea7e2df | 1096 | static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu) |
bdf21b18 PP |
1097 | { |
1098 | decode_configs(c); | |
8ff374b9 | 1099 | switch (c->processor_id & PRID_IMP_MASK) { |
bdf21b18 PP |
1100 | case PRID_IMP_PR4450: |
1101 | c->cputype = CPU_PR4450; | |
cea7e2df | 1102 | __cpu_name[cpu] = "Philips PR4450"; |
a96102be | 1103 | set_isa(c, MIPS_CPU_ISA_M32R1); |
bdf21b18 | 1104 | break; |
bdf21b18 PP |
1105 | } |
1106 | } | |
1107 | ||
cea7e2df | 1108 | static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu) |
1c0c13eb AJ |
1109 | { |
1110 | decode_configs(c); | |
8ff374b9 | 1111 | switch (c->processor_id & PRID_IMP_MASK) { |
190fca3e KC |
1112 | case PRID_IMP_BMIPS32_REV4: |
1113 | case PRID_IMP_BMIPS32_REV8: | |
602977b0 KC |
1114 | c->cputype = CPU_BMIPS32; |
1115 | __cpu_name[cpu] = "Broadcom BMIPS32"; | |
06785df0 | 1116 | set_elf_platform(cpu, "bmips32"); |
602977b0 KC |
1117 | break; |
1118 | case PRID_IMP_BMIPS3300: | |
1119 | case PRID_IMP_BMIPS3300_ALT: | |
1120 | case PRID_IMP_BMIPS3300_BUG: | |
1121 | c->cputype = CPU_BMIPS3300; | |
1122 | __cpu_name[cpu] = "Broadcom BMIPS3300"; | |
06785df0 | 1123 | set_elf_platform(cpu, "bmips3300"); |
602977b0 KC |
1124 | break; |
1125 | case PRID_IMP_BMIPS43XX: { | |
8ff374b9 | 1126 | int rev = c->processor_id & PRID_REV_MASK; |
602977b0 KC |
1127 | |
1128 | if (rev >= PRID_REV_BMIPS4380_LO && | |
1129 | rev <= PRID_REV_BMIPS4380_HI) { | |
1130 | c->cputype = CPU_BMIPS4380; | |
1131 | __cpu_name[cpu] = "Broadcom BMIPS4380"; | |
06785df0 | 1132 | set_elf_platform(cpu, "bmips4380"); |
602977b0 KC |
1133 | } else { |
1134 | c->cputype = CPU_BMIPS4350; | |
1135 | __cpu_name[cpu] = "Broadcom BMIPS4350"; | |
06785df0 | 1136 | set_elf_platform(cpu, "bmips4350"); |
602977b0 | 1137 | } |
0de663ef | 1138 | break; |
602977b0 KC |
1139 | } |
1140 | case PRID_IMP_BMIPS5000: | |
68e6a783 | 1141 | case PRID_IMP_BMIPS5200: |
602977b0 KC |
1142 | c->cputype = CPU_BMIPS5000; |
1143 | __cpu_name[cpu] = "Broadcom BMIPS5000"; | |
06785df0 | 1144 | set_elf_platform(cpu, "bmips5000"); |
602977b0 | 1145 | c->options |= MIPS_CPU_ULRI; |
0de663ef | 1146 | break; |
1c0c13eb AJ |
1147 | } |
1148 | } | |
1149 | ||
0dd4781b DD |
1150 | static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu) |
1151 | { | |
1152 | decode_configs(c); | |
8ff374b9 | 1153 | switch (c->processor_id & PRID_IMP_MASK) { |
0dd4781b DD |
1154 | case PRID_IMP_CAVIUM_CN38XX: |
1155 | case PRID_IMP_CAVIUM_CN31XX: | |
1156 | case PRID_IMP_CAVIUM_CN30XX: | |
6f329468 DD |
1157 | c->cputype = CPU_CAVIUM_OCTEON; |
1158 | __cpu_name[cpu] = "Cavium Octeon"; | |
1159 | goto platform; | |
0dd4781b DD |
1160 | case PRID_IMP_CAVIUM_CN58XX: |
1161 | case PRID_IMP_CAVIUM_CN56XX: | |
1162 | case PRID_IMP_CAVIUM_CN50XX: | |
1163 | case PRID_IMP_CAVIUM_CN52XX: | |
6f329468 DD |
1164 | c->cputype = CPU_CAVIUM_OCTEON_PLUS; |
1165 | __cpu_name[cpu] = "Cavium Octeon+"; | |
1166 | platform: | |
c094c99e | 1167 | set_elf_platform(cpu, "octeon"); |
0dd4781b | 1168 | break; |
a1431b61 | 1169 | case PRID_IMP_CAVIUM_CN61XX: |
0e56b385 | 1170 | case PRID_IMP_CAVIUM_CN63XX: |
a1431b61 DD |
1171 | case PRID_IMP_CAVIUM_CN66XX: |
1172 | case PRID_IMP_CAVIUM_CN68XX: | |
af04bb85 | 1173 | case PRID_IMP_CAVIUM_CNF71XX: |
0e56b385 DD |
1174 | c->cputype = CPU_CAVIUM_OCTEON2; |
1175 | __cpu_name[cpu] = "Cavium Octeon II"; | |
c094c99e | 1176 | set_elf_platform(cpu, "octeon2"); |
0e56b385 | 1177 | break; |
af04bb85 DD |
1178 | case PRID_IMP_CAVIUM_CN70XX: |
1179 | case PRID_IMP_CAVIUM_CN78XX: | |
1180 | c->cputype = CPU_CAVIUM_OCTEON3; | |
1181 | __cpu_name[cpu] = "Cavium Octeon III"; | |
1182 | set_elf_platform(cpu, "octeon3"); | |
1183 | break; | |
0dd4781b DD |
1184 | default: |
1185 | printk(KERN_INFO "Unknown Octeon chip!\n"); | |
1186 | c->cputype = CPU_UNKNOWN; | |
1187 | break; | |
1188 | } | |
1189 | } | |
1190 | ||
83ccf69d LPC |
1191 | static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu) |
1192 | { | |
1193 | decode_configs(c); | |
1194 | /* JZRISC does not implement the CP0 counter. */ | |
1195 | c->options &= ~MIPS_CPU_COUNTER; | |
06947aaa | 1196 | BUG_ON(!__builtin_constant_p(cpu_has_counter) || cpu_has_counter); |
8ff374b9 | 1197 | switch (c->processor_id & PRID_IMP_MASK) { |
83ccf69d LPC |
1198 | case PRID_IMP_JZRISC: |
1199 | c->cputype = CPU_JZRISC; | |
4f12b91d | 1200 | c->writecombine = _CACHE_UNCACHED_ACCELERATED; |
83ccf69d LPC |
1201 | __cpu_name[cpu] = "Ingenic JZRISC"; |
1202 | break; | |
1203 | default: | |
1204 | panic("Unknown Ingenic Processor ID!"); | |
1205 | break; | |
1206 | } | |
1207 | } | |
1208 | ||
a7117c6b J |
1209 | static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu) |
1210 | { | |
1211 | decode_configs(c); | |
1212 | ||
8ff374b9 | 1213 | if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_NETLOGIC_AU13XX) { |
809f36c6 ML |
1214 | c->cputype = CPU_ALCHEMY; |
1215 | __cpu_name[cpu] = "Au1300"; | |
1216 | /* following stuff is not for Alchemy */ | |
1217 | return; | |
1218 | } | |
1219 | ||
70342287 RB |
1220 | c->options = (MIPS_CPU_TLB | |
1221 | MIPS_CPU_4KEX | | |
a7117c6b | 1222 | MIPS_CPU_COUNTER | |
70342287 RB |
1223 | MIPS_CPU_DIVEC | |
1224 | MIPS_CPU_WATCH | | |
1225 | MIPS_CPU_EJTAG | | |
a7117c6b J |
1226 | MIPS_CPU_LLSC); |
1227 | ||
8ff374b9 | 1228 | switch (c->processor_id & PRID_IMP_MASK) { |
4ca86a2f | 1229 | case PRID_IMP_NETLOGIC_XLP2XX: |
8907c55e | 1230 | case PRID_IMP_NETLOGIC_XLP9XX: |
1c983986 | 1231 | case PRID_IMP_NETLOGIC_XLP5XX: |
4ca86a2f J |
1232 | c->cputype = CPU_XLP; |
1233 | __cpu_name[cpu] = "Broadcom XLPII"; | |
1234 | break; | |
1235 | ||
2aa54b20 J |
1236 | case PRID_IMP_NETLOGIC_XLP8XX: |
1237 | case PRID_IMP_NETLOGIC_XLP3XX: | |
a3d4fb2d J |
1238 | c->cputype = CPU_XLP; |
1239 | __cpu_name[cpu] = "Netlogic XLP"; | |
1240 | break; | |
1241 | ||
a7117c6b J |
1242 | case PRID_IMP_NETLOGIC_XLR732: |
1243 | case PRID_IMP_NETLOGIC_XLR716: | |
1244 | case PRID_IMP_NETLOGIC_XLR532: | |
1245 | case PRID_IMP_NETLOGIC_XLR308: | |
1246 | case PRID_IMP_NETLOGIC_XLR532C: | |
1247 | case PRID_IMP_NETLOGIC_XLR516C: | |
1248 | case PRID_IMP_NETLOGIC_XLR508C: | |
1249 | case PRID_IMP_NETLOGIC_XLR308C: | |
1250 | c->cputype = CPU_XLR; | |
1251 | __cpu_name[cpu] = "Netlogic XLR"; | |
1252 | break; | |
1253 | ||
1254 | case PRID_IMP_NETLOGIC_XLS608: | |
1255 | case PRID_IMP_NETLOGIC_XLS408: | |
1256 | case PRID_IMP_NETLOGIC_XLS404: | |
1257 | case PRID_IMP_NETLOGIC_XLS208: | |
1258 | case PRID_IMP_NETLOGIC_XLS204: | |
1259 | case PRID_IMP_NETLOGIC_XLS108: | |
1260 | case PRID_IMP_NETLOGIC_XLS104: | |
1261 | case PRID_IMP_NETLOGIC_XLS616B: | |
1262 | case PRID_IMP_NETLOGIC_XLS608B: | |
1263 | case PRID_IMP_NETLOGIC_XLS416B: | |
1264 | case PRID_IMP_NETLOGIC_XLS412B: | |
1265 | case PRID_IMP_NETLOGIC_XLS408B: | |
1266 | case PRID_IMP_NETLOGIC_XLS404B: | |
1267 | c->cputype = CPU_XLR; | |
1268 | __cpu_name[cpu] = "Netlogic XLS"; | |
1269 | break; | |
1270 | ||
1271 | default: | |
a3d4fb2d | 1272 | pr_info("Unknown Netlogic chip id [%02x]!\n", |
a7117c6b J |
1273 | c->processor_id); |
1274 | c->cputype = CPU_XLR; | |
1275 | break; | |
1276 | } | |
1277 | ||
a3d4fb2d | 1278 | if (c->cputype == CPU_XLP) { |
a96102be | 1279 | set_isa(c, MIPS_CPU_ISA_M64R2); |
a3d4fb2d J |
1280 | c->options |= (MIPS_CPU_FPU | MIPS_CPU_ULRI | MIPS_CPU_MCHECK); |
1281 | /* This will be updated again after all threads are woken up */ | |
1282 | c->tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1; | |
1283 | } else { | |
a96102be | 1284 | set_isa(c, MIPS_CPU_ISA_M64R1); |
a3d4fb2d J |
1285 | c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1; |
1286 | } | |
7777b939 | 1287 | c->kscratch_mask = 0xf; |
a7117c6b J |
1288 | } |
1289 | ||
949e51be DD |
1290 | #ifdef CONFIG_64BIT |
1291 | /* For use by uaccess.h */ | |
1292 | u64 __ua_limit; | |
1293 | EXPORT_SYMBOL(__ua_limit); | |
1294 | #endif | |
1295 | ||
9966db25 | 1296 | const char *__cpu_name[NR_CPUS]; |
874fd3b5 | 1297 | const char *__elf_platform; |
9966db25 | 1298 | |
078a55fc | 1299 | void cpu_probe(void) |
1da177e4 LT |
1300 | { |
1301 | struct cpuinfo_mips *c = ¤t_cpu_data; | |
9966db25 | 1302 | unsigned int cpu = smp_processor_id(); |
1da177e4 | 1303 | |
70342287 | 1304 | c->processor_id = PRID_IMP_UNKNOWN; |
1da177e4 LT |
1305 | c->fpu_id = FPIR_IMP_NONE; |
1306 | c->cputype = CPU_UNKNOWN; | |
4f12b91d | 1307 | c->writecombine = _CACHE_UNCACHED; |
1da177e4 LT |
1308 | |
1309 | c->processor_id = read_c0_prid(); | |
8ff374b9 | 1310 | switch (c->processor_id & PRID_COMP_MASK) { |
1da177e4 | 1311 | case PRID_COMP_LEGACY: |
cea7e2df | 1312 | cpu_probe_legacy(c, cpu); |
1da177e4 LT |
1313 | break; |
1314 | case PRID_COMP_MIPS: | |
cea7e2df | 1315 | cpu_probe_mips(c, cpu); |
1da177e4 LT |
1316 | break; |
1317 | case PRID_COMP_ALCHEMY: | |
cea7e2df | 1318 | cpu_probe_alchemy(c, cpu); |
1da177e4 LT |
1319 | break; |
1320 | case PRID_COMP_SIBYTE: | |
cea7e2df | 1321 | cpu_probe_sibyte(c, cpu); |
1da177e4 | 1322 | break; |
1c0c13eb | 1323 | case PRID_COMP_BROADCOM: |
cea7e2df | 1324 | cpu_probe_broadcom(c, cpu); |
1c0c13eb | 1325 | break; |
1da177e4 | 1326 | case PRID_COMP_SANDCRAFT: |
cea7e2df | 1327 | cpu_probe_sandcraft(c, cpu); |
1da177e4 | 1328 | break; |
a92b0588 | 1329 | case PRID_COMP_NXP: |
cea7e2df | 1330 | cpu_probe_nxp(c, cpu); |
a3dddd56 | 1331 | break; |
0dd4781b DD |
1332 | case PRID_COMP_CAVIUM: |
1333 | cpu_probe_cavium(c, cpu); | |
1334 | break; | |
83ccf69d LPC |
1335 | case PRID_COMP_INGENIC: |
1336 | cpu_probe_ingenic(c, cpu); | |
1337 | break; | |
a7117c6b J |
1338 | case PRID_COMP_NETLOGIC: |
1339 | cpu_probe_netlogic(c, cpu); | |
1340 | break; | |
1da177e4 | 1341 | } |
dec8b1ca | 1342 | |
cea7e2df RB |
1343 | BUG_ON(!__cpu_name[cpu]); |
1344 | BUG_ON(c->cputype == CPU_UNKNOWN); | |
1345 | ||
dec8b1ca FBH |
1346 | /* |
1347 | * Platform code can force the cpu type to optimize code | |
1348 | * generation. In that case be sure the cpu type is correctly | |
1349 | * manually setup otherwise it could trigger some nasty bugs. | |
1350 | */ | |
1351 | BUG_ON(current_cpu_type() != c->cputype); | |
1352 | ||
0103d23f KC |
1353 | if (mips_fpu_disabled) |
1354 | c->options &= ~MIPS_CPU_FPU; | |
1355 | ||
1356 | if (mips_dsp_disabled) | |
ee80f7c7 | 1357 | c->ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P); |
0103d23f | 1358 | |
3d528b32 MC |
1359 | if (mips_htw_disabled) { |
1360 | c->options &= ~MIPS_CPU_HTW; | |
1361 | write_c0_pwctl(read_c0_pwctl() & | |
1362 | ~(1 << MIPS_PWCTL_PWEN_SHIFT)); | |
1363 | } | |
1364 | ||
4194318c | 1365 | if (c->options & MIPS_CPU_FPU) { |
1da177e4 | 1366 | c->fpu_id = cpu_get_fpu_id(); |
4194318c | 1367 | |
8b8aa636 | 1368 | if (c->isa_level & cpu_has_mips_r) { |
4194318c RB |
1369 | if (c->fpu_id & MIPS_FPIR_3D) |
1370 | c->ases |= MIPS_ASE_MIPS3D; | |
adac5d53 PB |
1371 | if (c->fpu_id & MIPS_FPIR_FREP) |
1372 | c->options |= MIPS_CPU_FRE; | |
4194318c RB |
1373 | } |
1374 | } | |
9966db25 | 1375 | |
8b8aa636 | 1376 | if (cpu_has_mips_r2_r6) { |
f6771dbb | 1377 | c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1; |
da4b62cd AC |
1378 | /* R2 has Performance Counter Interrupt indicator */ |
1379 | c->options |= MIPS_CPU_PCI; | |
1380 | } | |
f6771dbb RB |
1381 | else |
1382 | c->srsets = 1; | |
91dfc423 | 1383 | |
a8ad1367 | 1384 | if (cpu_has_msa) { |
a5e9a69e | 1385 | c->msa_id = cpu_get_msa_id(); |
a8ad1367 PB |
1386 | WARN(c->msa_id & MSA_IR_WRPF, |
1387 | "Vector register partitioning unimplemented!"); | |
1388 | } | |
a5e9a69e | 1389 | |
91dfc423 | 1390 | cpu_probe_vmbits(c); |
949e51be DD |
1391 | |
1392 | #ifdef CONFIG_64BIT | |
1393 | if (cpu == 0) | |
1394 | __ua_limit = ~((1ull << cpu_vmbits) - 1); | |
1395 | #endif | |
1da177e4 LT |
1396 | } |
1397 | ||
078a55fc | 1398 | void cpu_report(void) |
1da177e4 LT |
1399 | { |
1400 | struct cpuinfo_mips *c = ¤t_cpu_data; | |
1401 | ||
d9f897c9 LY |
1402 | pr_info("CPU%d revision is: %08x (%s)\n", |
1403 | smp_processor_id(), c->processor_id, cpu_name_string()); | |
1da177e4 | 1404 | if (c->options & MIPS_CPU_FPU) |
9966db25 | 1405 | printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id); |
a5e9a69e PB |
1406 | if (cpu_has_msa) |
1407 | pr_info("MSA revision is: %08x\n", c->msa_id); | |
1da177e4 | 1408 | } |