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parisc: delete __cpuinit usage from all users
[mirror_ubuntu-zesty-kernel.git] / arch / mips / kernel / cpu-probe.c
CommitLineData
1da177e4
LT		 1/*
2 * Processor capabilities determination functions.
3 *
4 * Copyright (C) xxxx the Anonymous
010b853b 5 * Copyright (C) 1994 - 2006 Ralf Baechle
4194318c 6 * Copyright (C) 2003, 2004 Maciej W. Rozycki
70342287 7 * Copyright (C) 2001, 2004, 2011, 2012 MIPS Technologies, Inc.
1da177e4
LT		 8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
13 */
1da177e4
LT		 14#include <linux/init.h>
15#include <linux/kernel.h>
16#include <linux/ptrace.h>
631330f5 17#include <linux/smp.h>
1da177e4 18#include <linux/stddef.h>
73bc256d 19#include <linux/export.h>
1da177e4 20
5759906c 21#include <asm/bugs.h>
1da177e4
LT		 22#include <asm/cpu.h>
23#include <asm/fpu.h>
24#include <asm/mipsregs.h>
654f57bf 25#include <asm/watch.h>
06372a63 26#include <asm/elf.h>
a074f0e8 27#include <asm/spram.h>
949e51be
DD		 28#include <asm/uaccess.h>
29
0103d23f
KC		 30static int __cpuinitdata mips_fpu_disabled;
31
32static int __init fpu_disable(char *s)
33{
34 cpu_data[0].options &= ~MIPS_CPU_FPU;
35 mips_fpu_disabled = 1;
36
37 return 1;
38}
39
40__setup("nofpu", fpu_disable);
41
42int __cpuinitdata mips_dsp_disabled;
43
44static int __init dsp_disable(char *s)
45{
ee80f7c7 46 cpu_data[0].ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
0103d23f
KC		 47 mips_dsp_disabled = 1;
48
49 return 1;
50}
51
52__setup("nodsp", dsp_disable);
53
9267a30d
MSJ		 54static inline void check_errata(void)
55{
56 struct cpuinfo_mips *c = &current_cpu_data;
57
58 switch (c->cputype) {
59 case CPU_34K:
60 /*
61 * Erratum "RPS May Cause Incorrect Instruction Execution"
62 * This code only handles VPE0, any SMP/SMTC/RTOS code
63 * making use of VPE1 will be responsable for that VPE.
64 */
65 if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2)
66 write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS);
67 break;
68 default:
69 break;
70 }
71}
72
1da177e4
LT		 73void __init check_bugs32(void)
74{
9267a30d 75 check_errata();
1da177e4
LT		 76}
77
78/*
79 * Probe whether cpu has config register by trying to play with
80 * alternate cache bit and see whether it matters.
81 * It's used by cpu_probe to distinguish between R3000A and R3081.
82 */
83static inline int cpu_has_confreg(void)
84{
85#ifdef CONFIG_CPU_R3000
86 extern unsigned long r3k_cache_size(unsigned long);
87 unsigned long size1, size2;
88 unsigned long cfg = read_c0_conf();
89
90 size1 = r3k_cache_size(ST0_ISC);
91 write_c0_conf(cfg ^ R30XX_CONF_AC);
92 size2 = r3k_cache_size(ST0_ISC);
93 write_c0_conf(cfg);
94 return size1 != size2;
95#else
96 return 0;
97#endif
98}
99
c094c99e
RM		 100static inline void set_elf_platform(int cpu, const char *plat)
101{
102 if (cpu == 0)
103 __elf_platform = plat;
104}
105
1da177e4
LT		 106/*
107 * Get the FPU Implementation/Revision.
108 */
109static inline unsigned long cpu_get_fpu_id(void)
110{
111 unsigned long tmp, fpu_id;
112
113 tmp = read_c0_status();
114 __enable_fpu();
115 fpu_id = read_32bit_cp1_register(CP1_REVISION);
116 write_c0_status(tmp);
117 return fpu_id;
118}
119
120/*
121 * Check the CPU has an FPU the official way.
122 */
123static inline int __cpu_has_fpu(void)
124{
125 return ((cpu_get_fpu_id() & 0xff00) != FPIR_IMP_NONE);
126}
127
91dfc423
GR		 128static inline void cpu_probe_vmbits(struct cpuinfo_mips *c)
129{
130#ifdef __NEED_VMBITS_PROBE
5b7efa89 131 write_c0_entryhi(0x3fffffffffffe000ULL);
91dfc423 132 back_to_back_c0_hazard();
5b7efa89 133 c->vmbits = fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL);
91dfc423
GR		 134#endif
135}
136
a96102be
SH		 137static void __cpuinit set_isa(struct cpuinfo_mips *c, unsigned int isa)
138{
139 switch (isa) {
140 case MIPS_CPU_ISA_M64R2:
141 c->isa_level |= MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2;
142 case MIPS_CPU_ISA_M64R1:
143 c->isa_level |= MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1;
144 case MIPS_CPU_ISA_V:
145 c->isa_level |= MIPS_CPU_ISA_V;
146 case MIPS_CPU_ISA_IV:
147 c->isa_level |= MIPS_CPU_ISA_IV;
148 case MIPS_CPU_ISA_III:
1990e542 149 c->isa_level |= MIPS_CPU_ISA_II | MIPS_CPU_ISA_III;
a96102be
SH		 150 break;
151
152 case MIPS_CPU_ISA_M32R2:
153 c->isa_level |= MIPS_CPU_ISA_M32R2;
154 case MIPS_CPU_ISA_M32R1:
155 c->isa_level |= MIPS_CPU_ISA_M32R1;
156 case MIPS_CPU_ISA_II:
157 c->isa_level |= MIPS_CPU_ISA_II;
a96102be
SH		 158 break;
159 }
160}
161
2fa36399
KC		 162static char unknown_isa[] __cpuinitdata = KERN_ERR \
163 "Unsupported ISA type, c0.config0: %d.";
164
165static inline unsigned int decode_config0(struct cpuinfo_mips *c)
166{
167 unsigned int config0;
168 int isa;
169
170 config0 = read_c0_config();
171
172 if (((config0 & MIPS_CONF_MT) >> 7) == 1)
173 c->options |= MIPS_CPU_TLB;
174 isa = (config0 & MIPS_CONF_AT) >> 13;
175 switch (isa) {
176 case 0:
177 switch ((config0 & MIPS_CONF_AR) >> 10) {
178 case 0:
a96102be 179 set_isa(c, MIPS_CPU_ISA_M32R1);
2fa36399
KC		 180 break;
181 case 1:
a96102be 182 set_isa(c, MIPS_CPU_ISA_M32R2);
2fa36399
KC		 183 break;
184 default:
185 goto unknown;
186 }
187 break;
188 case 2:
189 switch ((config0 & MIPS_CONF_AR) >> 10) {
190 case 0:
a96102be 191 set_isa(c, MIPS_CPU_ISA_M64R1);
2fa36399
KC		 192 break;
193 case 1:
a96102be 194 set_isa(c, MIPS_CPU_ISA_M64R2);
2fa36399
KC		 195 break;
196 default:
197 goto unknown;
198 }
199 break;
200 default:
201 goto unknown;
202 }
203
204 return config0 & MIPS_CONF_M;
205
206unknown:
207 panic(unknown_isa, config0);
208}
209
210static inline unsigned int decode_config1(struct cpuinfo_mips *c)
211{
212 unsigned int config1;
213
214 config1 = read_c0_config1();
215
216 if (config1 & MIPS_CONF1_MD)
217 c->ases |= MIPS_ASE_MDMX;
218 if (config1 & MIPS_CONF1_WR)
219 c->options |= MIPS_CPU_WATCH;
220 if (config1 & MIPS_CONF1_CA)
221 c->ases |= MIPS_ASE_MIPS16;
222 if (config1 & MIPS_CONF1_EP)
223 c->options |= MIPS_CPU_EJTAG;
224 if (config1 & MIPS_CONF1_FP) {
225 c->options |= MIPS_CPU_FPU;
226 c->options |= MIPS_CPU_32FPR;
227 }
228 if (cpu_has_tlb)
229 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;
230
231 return config1 & MIPS_CONF_M;
232}
233
234static inline unsigned int decode_config2(struct cpuinfo_mips *c)
235{
236 unsigned int config2;
237
238 config2 = read_c0_config2();
239
240 if (config2 & MIPS_CONF2_SL)
241 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
242
243 return config2 & MIPS_CONF_M;
244}
245
246static inline unsigned int decode_config3(struct cpuinfo_mips *c)
247{
248 unsigned int config3;
249
250 config3 = read_c0_config3();
251
b2ab4f08 252 if (config3 & MIPS_CONF3_SM) {
2fa36399 253 c->ases |= MIPS_ASE_SMARTMIPS;
b2ab4f08
SH		 254 c->options |= MIPS_CPU_RIXI;
255 }
256 if (config3 & MIPS_CONF3_RXI)
257 c->options |= MIPS_CPU_RIXI;
2fa36399
KC		 258 if (config3 & MIPS_CONF3_DSP)
259 c->ases |= MIPS_ASE_DSP;
ee80f7c7
SH		 260 if (config3 & MIPS_CONF3_DSP2P)
261 c->ases |= MIPS_ASE_DSP2P;
2fa36399
KC		 262 if (config3 & MIPS_CONF3_VINT)
263 c->options |= MIPS_CPU_VINT;
264 if (config3 & MIPS_CONF3_VEIC)
265 c->options |= MIPS_CPU_VEIC;
266 if (config3 & MIPS_CONF3_MT)
267 c->ases |= MIPS_ASE_MIPSMT;
268 if (config3 & MIPS_CONF3_ULRI)
269 c->options |= MIPS_CPU_ULRI;
f8fa4811
SH		 270 if (config3 & MIPS_CONF3_ISA)
271 c->options |= MIPS_CPU_MICROMIPS;
1e7decdb
DD		 272 if (config3 & MIPS_CONF3_VZ)
273 c->ases |= MIPS_ASE_VZ;
2fa36399
KC		 274
275 return config3 & MIPS_CONF_M;
276}
277
278static inline unsigned int decode_config4(struct cpuinfo_mips *c)
279{
280 unsigned int config4;
281
282 config4 = read_c0_config4();
283
284 if ((config4 & MIPS_CONF4_MMUEXTDEF) == MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT
285 && cpu_has_tlb)
286 c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40;
287
288 c->kscratch_mask = (config4 >> 16) & 0xff;
289
290 return config4 & MIPS_CONF_M;
291}
292
293static void __cpuinit decode_configs(struct cpuinfo_mips *c)
294{
295 int ok;
296
297 /* MIPS32 or MIPS64 compliant CPU. */
298 c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
299 MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
300
301 c->scache.flags = MIPS_CACHE_NOT_PRESENT;
302
303 ok = decode_config0(c); /* Read Config registers. */
70342287 304 BUG_ON(!ok); /* Arch spec violation! */
2fa36399
KC		 305 if (ok)
306 ok = decode_config1(c);
307 if (ok)
308 ok = decode_config2(c);
309 if (ok)
310 ok = decode_config3(c);
311 if (ok)
312 ok = decode_config4(c);
313
314 mips_probe_watch_registers(c);
315
316 if (cpu_has_mips_r2)
317 c->core = read_c0_ebase() & 0x3ff;
318}
319
02cf2119 320#define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
1da177e4
LT		 321 | MIPS_CPU_COUNTER)
322
cea7e2df 323static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4
LT		 324{
325 switch (c->processor_id & 0xff00) {
326 case PRID_IMP_R2000:
327 c->cputype = CPU_R2000;
cea7e2df 328 __cpu_name[cpu] = "R2000";
02cf2119 329 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
03751e79 330 MIPS_CPU_NOFPUEX;
1da177e4
LT		 331 if (__cpu_has_fpu())
332 c->options |= MIPS_CPU_FPU;
333 c->tlbsize = 64;
334 break;
335 case PRID_IMP_R3000:
cea7e2df
RB		 336 if ((c->processor_id & 0xff) == PRID_REV_R3000A) {
337 if (cpu_has_confreg()) {
1da177e4 338 c->cputype = CPU_R3081E;
cea7e2df
RB		 339 __cpu_name[cpu] = "R3081";
340 } else {
1da177e4 341 c->cputype = CPU_R3000A;
cea7e2df
RB		 342 __cpu_name[cpu] = "R3000A";
343 }
cea7e2df 344 } else {
1da177e4 345 c->cputype = CPU_R3000;
cea7e2df
RB		 346 __cpu_name[cpu] = "R3000";
347 }
02cf2119 348 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
03751e79 349 MIPS_CPU_NOFPUEX;
1da177e4
LT		 350 if (__cpu_has_fpu())
351 c->options |= MIPS_CPU_FPU;
352 c->tlbsize = 64;
353 break;
354 case PRID_IMP_R4000:
355 if (read_c0_config() & CONF_SC) {
cea7e2df 356 if ((c->processor_id & 0xff) >= PRID_REV_R4400) {
1da177e4 357 c->cputype = CPU_R4400PC;
cea7e2df
RB		 358 __cpu_name[cpu] = "R4400PC";
359 } else {
1da177e4 360 c->cputype = CPU_R4000PC;
cea7e2df
RB		 361 __cpu_name[cpu] = "R4000PC";
362 }
1da177e4 363 } else {
cea7e2df 364 if ((c->processor_id & 0xff) >= PRID_REV_R4400) {
1da177e4 365 c->cputype = CPU_R4400SC;
cea7e2df
RB		 366 __cpu_name[cpu] = "R4400SC";
367 } else {
1da177e4 368 c->cputype = CPU_R4000SC;
cea7e2df
RB		 369 __cpu_name[cpu] = "R4000SC";
370 }
1da177e4
LT		 371 }
372
a96102be 373 set_isa(c, MIPS_CPU_ISA_III);
1da177e4 374 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79
SH		 375 MIPS_CPU_WATCH | MIPS_CPU_VCE |
376 MIPS_CPU_LLSC;
1da177e4
LT		 377 c->tlbsize = 48;
378 break;
379 case PRID_IMP_VR41XX:
9f91e506
YY		 380 set_isa(c, MIPS_CPU_ISA_III);
381 c->options = R4K_OPTS;
382 c->tlbsize = 32;
1da177e4 383 switch (c->processor_id & 0xf0) {
1da177e4
LT		 384 case PRID_REV_VR4111:
385 c->cputype = CPU_VR4111;
cea7e2df 386 __cpu_name[cpu] = "NEC VR4111";
1da177e4 387 break;
1da177e4
LT		 388 case PRID_REV_VR4121:
389 c->cputype = CPU_VR4121;
cea7e2df 390 __cpu_name[cpu] = "NEC VR4121";
1da177e4
LT		 391 break;
392 case PRID_REV_VR4122:
cea7e2df 393 if ((c->processor_id & 0xf) < 0x3) {
1da177e4 394 c->cputype = CPU_VR4122;
cea7e2df
RB		 395 __cpu_name[cpu] = "NEC VR4122";
396 } else {
1da177e4 397 c->cputype = CPU_VR4181A;
cea7e2df
RB		 398 __cpu_name[cpu] = "NEC VR4181A";
399 }
1da177e4
LT		 400 break;
401 case PRID_REV_VR4130:
cea7e2df 402 if ((c->processor_id & 0xf) < 0x4) {
1da177e4 403 c->cputype = CPU_VR4131;
cea7e2df
RB		 404 __cpu_name[cpu] = "NEC VR4131";
405 } else {
1da177e4 406 c->cputype = CPU_VR4133;
9f91e506 407 c->options |= MIPS_CPU_LLSC;
cea7e2df
RB		 408 __cpu_name[cpu] = "NEC VR4133";
409 }
1da177e4
LT		 410 break;
411 default:
412 printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
413 c->cputype = CPU_VR41XX;
cea7e2df 414 __cpu_name[cpu] = "NEC Vr41xx";
1da177e4
LT		 415 break;
416 }
1da177e4
LT		 417 break;
418 case PRID_IMP_R4300:
419 c->cputype = CPU_R4300;
cea7e2df 420 __cpu_name[cpu] = "R4300";
a96102be 421 set_isa(c, MIPS_CPU_ISA_III);
1da177e4 422 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 423 MIPS_CPU_LLSC;
1da177e4
LT		 424 c->tlbsize = 32;
425 break;
426 case PRID_IMP_R4600:
427 c->cputype = CPU_R4600;
cea7e2df 428 __cpu_name[cpu] = "R4600";
a96102be 429 set_isa(c, MIPS_CPU_ISA_III);
075e7502
TS		 430 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
431 MIPS_CPU_LLSC;
1da177e4
LT		 432 c->tlbsize = 48;
433 break;
434 #if 0
03751e79 435 case PRID_IMP_R4650:
1da177e4
LT		 436 /*
437 * This processor doesn't have an MMU, so it's not
438 * "real easy" to run Linux on it. It is left purely
439 * for documentation. Commented out because it shares
440 * it's c0_prid id number with the TX3900.
441 */
a3dddd56 442 c->cputype = CPU_R4650;
cea7e2df 443 __cpu_name[cpu] = "R4650";
a96102be 444 set_isa(c, MIPS_CPU_ISA_III);
1da177e4 445 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
03751e79 446 c->tlbsize = 48;
1da177e4
LT		 447 break;
448 #endif
449 case PRID_IMP_TX39:
02cf2119 450 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE;
1da177e4
LT		 451
452 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
453 c->cputype = CPU_TX3927;
cea7e2df 454 __cpu_name[cpu] = "TX3927";
1da177e4
LT		 455 c->tlbsize = 64;
456 } else {
457 switch (c->processor_id & 0xff) {
458 case PRID_REV_TX3912:
459 c->cputype = CPU_TX3912;
cea7e2df 460 __cpu_name[cpu] = "TX3912";
1da177e4
LT		 461 c->tlbsize = 32;
462 break;
463 case PRID_REV_TX3922:
464 c->cputype = CPU_TX3922;
cea7e2df 465 __cpu_name[cpu] = "TX3922";
1da177e4
LT		 466 c->tlbsize = 64;
467 break;
1da177e4
LT		 468 }
469 }
470 break;
471 case PRID_IMP_R4700:
472 c->cputype = CPU_R4700;
cea7e2df 473 __cpu_name[cpu] = "R4700";
a96102be 474 set_isa(c, MIPS_CPU_ISA_III);
1da177e4 475 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 476 MIPS_CPU_LLSC;
1da177e4
LT		 477 c->tlbsize = 48;
478 break;
479 case PRID_IMP_TX49:
480 c->cputype = CPU_TX49XX;
cea7e2df 481 __cpu_name[cpu] = "R49XX";
a96102be 482 set_isa(c, MIPS_CPU_ISA_III);
1da177e4
LT		 483 c->options = R4K_OPTS | MIPS_CPU_LLSC;
484 if (!(c->processor_id & 0x08))
485 c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
486 c->tlbsize = 48;
487 break;
488 case PRID_IMP_R5000:
489 c->cputype = CPU_R5000;
cea7e2df 490 __cpu_name[cpu] = "R5000";
a96102be 491 set_isa(c, MIPS_CPU_ISA_IV);
1da177e4 492 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 493 MIPS_CPU_LLSC;
1da177e4
LT		 494 c->tlbsize = 48;
495 break;
496 case PRID_IMP_R5432:
497 c->cputype = CPU_R5432;
cea7e2df 498 __cpu_name[cpu] = "R5432";
a96102be 499 set_isa(c, MIPS_CPU_ISA_IV);
1da177e4 500 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 501 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
1da177e4
LT		 502 c->tlbsize = 48;
503 break;
504 case PRID_IMP_R5500:
505 c->cputype = CPU_R5500;
cea7e2df 506 __cpu_name[cpu] = "R5500";
a96102be 507 set_isa(c, MIPS_CPU_ISA_IV);
1da177e4 508 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 509 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
1da177e4
LT		 510 c->tlbsize = 48;
511 break;
512 case PRID_IMP_NEVADA:
513 c->cputype = CPU_NEVADA;
cea7e2df 514 __cpu_name[cpu] = "Nevada";
a96102be 515 set_isa(c, MIPS_CPU_ISA_IV);
1da177e4 516 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 517 MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
1da177e4
LT		 518 c->tlbsize = 48;
519 break;
520 case PRID_IMP_R6000:
521 c->cputype = CPU_R6000;
cea7e2df 522 __cpu_name[cpu] = "R6000";
a96102be 523 set_isa(c, MIPS_CPU_ISA_II);
1da177e4 524 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
03751e79 525 MIPS_CPU_LLSC;
1da177e4
LT		 526 c->tlbsize = 32;
527 break;
528 case PRID_IMP_R6000A:
529 c->cputype = CPU_R6000A;
cea7e2df 530 __cpu_name[cpu] = "R6000A";
a96102be 531 set_isa(c, MIPS_CPU_ISA_II);
1da177e4 532 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
03751e79 533 MIPS_CPU_LLSC;
1da177e4
LT		 534 c->tlbsize = 32;
535 break;
536 case PRID_IMP_RM7000:
537 c->cputype = CPU_RM7000;
cea7e2df 538 __cpu_name[cpu] = "RM7000";
a96102be 539 set_isa(c, MIPS_CPU_ISA_IV);
1da177e4 540 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 541 MIPS_CPU_LLSC;
1da177e4 542 /*
70342287 543 * Undocumented RM7000: Bit 29 in the info register of
1da177e4
LT		 544 * the RM7000 v2.0 indicates if the TLB has 48 or 64
545 * entries.
546 *
70342287
RB		 547 * 29 1 => 64 entry JTLB
548 * 0 => 48 entry JTLB
1da177e4
LT		 549 */
550 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
551 break;
552 case PRID_IMP_RM9000:
553 c->cputype = CPU_RM9000;
cea7e2df 554 __cpu_name[cpu] = "RM9000";
a96102be 555 set_isa(c, MIPS_CPU_ISA_IV);
1da177e4 556 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 557 MIPS_CPU_LLSC;
1da177e4
LT		 558 /*
559 * Bit 29 in the info register of the RM9000
560 * indicates if the TLB has 48 or 64 entries.
561 *
70342287
RB		 562 * 29 1 => 64 entry JTLB
563 * 0 => 48 entry JTLB
1da177e4
LT		 564 */
565 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
566 break;
567 case PRID_IMP_R8000:
568 c->cputype = CPU_R8000;
cea7e2df 569 __cpu_name[cpu] = "RM8000";
a96102be 570 set_isa(c, MIPS_CPU_ISA_IV);
1da177e4 571 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
03751e79
SH		 572 MIPS_CPU_FPU | MIPS_CPU_32FPR |
573 MIPS_CPU_LLSC;
1da177e4
LT		 574 c->tlbsize = 384; /* has weird TLB: 3-way x 128 */
575 break;
576 case PRID_IMP_R10000:
577 c->cputype = CPU_R10000;
cea7e2df 578 __cpu_name[cpu] = "R10000";
a96102be 579 set_isa(c, MIPS_CPU_ISA_IV);
8b36612a 580 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
03751e79 581 MIPS_CPU_FPU | MIPS_CPU_32FPR |
1da177e4 582 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
03751e79 583 MIPS_CPU_LLSC;
1da177e4
LT		 584 c->tlbsize = 64;
585 break;
586 case PRID_IMP_R12000:
587 c->cputype = CPU_R12000;
cea7e2df 588 __cpu_name[cpu] = "R12000";
a96102be 589 set_isa(c, MIPS_CPU_ISA_IV);
8b36612a 590 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
03751e79 591 MIPS_CPU_FPU | MIPS_CPU_32FPR |
1da177e4 592 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
03751e79 593 MIPS_CPU_LLSC;
1da177e4
LT		 594 c->tlbsize = 64;
595 break;
44d921b2
K		 596 case PRID_IMP_R14000:
597 c->cputype = CPU_R14000;
cea7e2df 598 __cpu_name[cpu] = "R14000";
a96102be 599 set_isa(c, MIPS_CPU_ISA_IV);
44d921b2 600 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
03751e79 601 MIPS_CPU_FPU | MIPS_CPU_32FPR |
44d921b2 602 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
03751e79 603 MIPS_CPU_LLSC;
44d921b2
K		 604 c->tlbsize = 64;
605 break;
2a21c730
FZ		 606 case PRID_IMP_LOONGSON2:
607 c->cputype = CPU_LOONGSON2;
cea7e2df 608 __cpu_name[cpu] = "ICT Loongson-2";
5aac1e8a
RM		 609
610 switch (c->processor_id & PRID_REV_MASK) {
611 case PRID_REV_LOONGSON2E:
612 set_elf_platform(cpu, "loongson2e");
613 break;
614 case PRID_REV_LOONGSON2F:
615 set_elf_platform(cpu, "loongson2f");
616 break;
617 }
618
a96102be 619 set_isa(c, MIPS_CPU_ISA_III);
2a21c730
FZ		 620 c->options = R4K_OPTS |
621 MIPS_CPU_FPU | MIPS_CPU_LLSC |
622 MIPS_CPU_32FPR;
623 c->tlbsize = 64;
624 break;
2fa36399
KC		 625 case PRID_IMP_LOONGSON1:
626 decode_configs(c);
b4672d37 627
2fa36399 628 c->cputype = CPU_LOONGSON1;
1da177e4 629
2fa36399
KC		 630 switch (c->processor_id & PRID_REV_MASK) {
631 case PRID_REV_LOONGSON1B:
632 __cpu_name[cpu] = "Loongson 1B";
b4672d37 633 break;
b4672d37 634 }
4194318c 635
2fa36399 636 break;
1da177e4 637 }
1da177e4
LT		 638}
639
cea7e2df 640static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4 641{
4194318c 642 decode_configs(c);
1da177e4
LT		 643 switch (c->processor_id & 0xff00) {
644 case PRID_IMP_4KC:
645 c->cputype = CPU_4KC;
cea7e2df 646 __cpu_name[cpu] = "MIPS 4Kc";
1da177e4
LT		 647 break;
648 case PRID_IMP_4KEC:
2b07bd02
RB		 649 case PRID_IMP_4KECR2:
650 c->cputype = CPU_4KEC;
cea7e2df 651 __cpu_name[cpu] = "MIPS 4KEc";
2b07bd02 652 break;
1da177e4 653 case PRID_IMP_4KSC:
8afcb5d8 654 case PRID_IMP_4KSD:
1da177e4 655 c->cputype = CPU_4KSC;
cea7e2df 656 __cpu_name[cpu] = "MIPS 4KSc";
1da177e4
LT		 657 break;
658 case PRID_IMP_5KC:
659 c->cputype = CPU_5KC;
cea7e2df 660 __cpu_name[cpu] = "MIPS 5Kc";
1da177e4 661 break;
78d4803f
LY		 662 case PRID_IMP_5KE:
663 c->cputype = CPU_5KE;
664 __cpu_name[cpu] = "MIPS 5KE";
665 break;
1da177e4
LT		 666 case PRID_IMP_20KC:
667 c->cputype = CPU_20KC;
cea7e2df 668 __cpu_name[cpu] = "MIPS 20Kc";
1da177e4
LT		 669 break;
670 case PRID_IMP_24K:
671 c->cputype = CPU_24K;
cea7e2df 672 __cpu_name[cpu] = "MIPS 24Kc";
1da177e4 673 break;
42f3caef
JC		 674 case PRID_IMP_24KE:
675 c->cputype = CPU_24K;
676 __cpu_name[cpu] = "MIPS 24KEc";
677 break;
1da177e4
LT		 678 case PRID_IMP_25KF:
679 c->cputype = CPU_25KF;
cea7e2df 680 __cpu_name[cpu] = "MIPS 25Kc";
1da177e4 681 break;
bbc7f22f
RB		 682 case PRID_IMP_34K:
683 c->cputype = CPU_34K;
cea7e2df 684 __cpu_name[cpu] = "MIPS 34Kc";
bbc7f22f 685 break;
c620953c
CD		 686 case PRID_IMP_74K:
687 c->cputype = CPU_74K;
cea7e2df 688 __cpu_name[cpu] = "MIPS 74Kc";
c620953c 689 break;
113c62d9
SH		 690 case PRID_IMP_M14KC:
691 c->cputype = CPU_M14KC;
692 __cpu_name[cpu] = "MIPS M14Kc";
693 break;
f8fa4811
SH		 694 case PRID_IMP_M14KEC:
695 c->cputype = CPU_M14KEC;
696 __cpu_name[cpu] = "MIPS M14KEc";
697 break;
39b8d525
RB		 698 case PRID_IMP_1004K:
699 c->cputype = CPU_1004K;
cea7e2df 700 __cpu_name[cpu] = "MIPS 1004Kc";
39b8d525 701 break;
006a851b
SH		 702 case PRID_IMP_1074K:
703 c->cputype = CPU_74K;
704 __cpu_name[cpu] = "MIPS 1074Kc";
705 break;
1da177e4 706 }
0b6d497f
CD		 707
708 spram_config();
1da177e4
LT		 709}
710
cea7e2df 711static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4 712{
4194318c 713 decode_configs(c);
1da177e4
LT		 714 switch (c->processor_id & 0xff00) {
715 case PRID_IMP_AU1_REV1:
716 case PRID_IMP_AU1_REV2:
270717a8 717 c->cputype = CPU_ALCHEMY;
1da177e4
LT		 718 switch ((c->processor_id >> 24) & 0xff) {
719 case 0:
cea7e2df 720 __cpu_name[cpu] = "Au1000";
1da177e4
LT		 721 break;
722 case 1:
cea7e2df 723 __cpu_name[cpu] = "Au1500";
1da177e4
LT		 724 break;
725 case 2:
cea7e2df 726 __cpu_name[cpu] = "Au1100";
1da177e4
LT		 727 break;
728 case 3:
cea7e2df 729 __cpu_name[cpu] = "Au1550";
1da177e4 730 break;
e3ad1c23 731 case 4:
cea7e2df 732 __cpu_name[cpu] = "Au1200";
270717a8 733 if ((c->processor_id & 0xff) == 2)
cea7e2df 734 __cpu_name[cpu] = "Au1250";
237cfee1
ML		 735 break;
736 case 5:
cea7e2df 737 __cpu_name[cpu] = "Au1210";
e3ad1c23 738 break;
1da177e4 739 default:
270717a8 740 __cpu_name[cpu] = "Au1xxx";
1da177e4
LT		 741 break;
742 }
1da177e4
LT		 743 break;
744 }
745}
746
cea7e2df 747static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4 748{
4194318c 749 decode_configs(c);
02cf2119 750
1da177e4
LT		 751 switch (c->processor_id & 0xff00) {
752 case PRID_IMP_SB1:
753 c->cputype = CPU_SB1;
cea7e2df 754 __cpu_name[cpu] = "SiByte SB1";
1da177e4 755 /* FPU in pass1 is known to have issues. */
aa32374a 756 if ((c->processor_id & 0xff) < 0x02)
010b853b 757 c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
1da177e4 758 break;
93ce2f52
AI		 759 case PRID_IMP_SB1A:
760 c->cputype = CPU_SB1A;
cea7e2df 761 __cpu_name[cpu] = "SiByte SB1A";
93ce2f52 762 break;
1da177e4
LT		 763 }
764}
765
cea7e2df 766static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4 767{
4194318c 768 decode_configs(c);
1da177e4
LT		 769 switch (c->processor_id & 0xff00) {
770 case PRID_IMP_SR71000:
771 c->cputype = CPU_SR71000;
cea7e2df 772 __cpu_name[cpu] = "Sandcraft SR71000";
1da177e4
LT		 773 c->scache.ways = 8;
774 c->tlbsize = 64;
775 break;
776 }
777}
778
cea7e2df 779static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu)
bdf21b18
PP		 780{
781 decode_configs(c);
782 switch (c->processor_id & 0xff00) {
783 case PRID_IMP_PR4450:
784 c->cputype = CPU_PR4450;
cea7e2df 785 __cpu_name[cpu] = "Philips PR4450";
a96102be 786 set_isa(c, MIPS_CPU_ISA_M32R1);
bdf21b18 787 break;
bdf21b18
PP		 788 }
789}
790
cea7e2df 791static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
1c0c13eb
AJ		 792{
793 decode_configs(c);
794 switch (c->processor_id & 0xff00) {
190fca3e
KC		 795 case PRID_IMP_BMIPS32_REV4:
796 case PRID_IMP_BMIPS32_REV8:
602977b0
KC		 797 c->cputype = CPU_BMIPS32;
798 __cpu_name[cpu] = "Broadcom BMIPS32";
06785df0 799 set_elf_platform(cpu, "bmips32");
602977b0
KC		 800 break;
801 case PRID_IMP_BMIPS3300:
802 case PRID_IMP_BMIPS3300_ALT:
803 case PRID_IMP_BMIPS3300_BUG:
804 c->cputype = CPU_BMIPS3300;
805 __cpu_name[cpu] = "Broadcom BMIPS3300";
06785df0 806 set_elf_platform(cpu, "bmips3300");
602977b0
KC		 807 break;
808 case PRID_IMP_BMIPS43XX: {
809 int rev = c->processor_id & 0xff;
810
811 if (rev >= PRID_REV_BMIPS4380_LO &&
812 rev <= PRID_REV_BMIPS4380_HI) {
813 c->cputype = CPU_BMIPS4380;
814 __cpu_name[cpu] = "Broadcom BMIPS4380";
06785df0 815 set_elf_platform(cpu, "bmips4380");
602977b0
KC		 816 } else {
817 c->cputype = CPU_BMIPS4350;
818 __cpu_name[cpu] = "Broadcom BMIPS4350";
06785df0 819 set_elf_platform(cpu, "bmips4350");
602977b0 820 }
0de663ef 821 break;
602977b0
KC		 822 }
823 case PRID_IMP_BMIPS5000:
824 c->cputype = CPU_BMIPS5000;
825 __cpu_name[cpu] = "Broadcom BMIPS5000";
06785df0 826 set_elf_platform(cpu, "bmips5000");
602977b0 827 c->options |= MIPS_CPU_ULRI;
0de663ef 828 break;
1c0c13eb
AJ		 829 }
830}
831
0dd4781b
DD		 832static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu)
833{
834 decode_configs(c);
835 switch (c->processor_id & 0xff00) {
836 case PRID_IMP_CAVIUM_CN38XX:
837 case PRID_IMP_CAVIUM_CN31XX:
838 case PRID_IMP_CAVIUM_CN30XX:
6f329468
DD		 839 c->cputype = CPU_CAVIUM_OCTEON;
840 __cpu_name[cpu] = "Cavium Octeon";
841 goto platform;
0dd4781b
DD		 842 case PRID_IMP_CAVIUM_CN58XX:
843 case PRID_IMP_CAVIUM_CN56XX:
844 case PRID_IMP_CAVIUM_CN50XX:
845 case PRID_IMP_CAVIUM_CN52XX:
6f329468
DD		 846 c->cputype = CPU_CAVIUM_OCTEON_PLUS;
847 __cpu_name[cpu] = "Cavium Octeon+";
848platform:
c094c99e 849 set_elf_platform(cpu, "octeon");
0dd4781b 850 break;
a1431b61 851 case PRID_IMP_CAVIUM_CN61XX:
0e56b385 852 case PRID_IMP_CAVIUM_CN63XX:
a1431b61
DD		 853 case PRID_IMP_CAVIUM_CN66XX:
854 case PRID_IMP_CAVIUM_CN68XX:
0e56b385
DD		 855 c->cputype = CPU_CAVIUM_OCTEON2;
856 __cpu_name[cpu] = "Cavium Octeon II";
c094c99e 857 set_elf_platform(cpu, "octeon2");
0e56b385 858 break;
0dd4781b
DD		 859 default:
860 printk(KERN_INFO "Unknown Octeon chip!\n");
861 c->cputype = CPU_UNKNOWN;
862 break;
863 }
864}
865
83ccf69d
LPC		 866static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
867{
868 decode_configs(c);
869 /* JZRISC does not implement the CP0 counter. */
870 c->options &= ~MIPS_CPU_COUNTER;
871 switch (c->processor_id & 0xff00) {
872 case PRID_IMP_JZRISC:
873 c->cputype = CPU_JZRISC;
874 __cpu_name[cpu] = "Ingenic JZRISC";
875 break;
876 default:
877 panic("Unknown Ingenic Processor ID!");
878 break;
879 }
880}
881
a7117c6b
J		 882static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu)
883{
884 decode_configs(c);
885
809f36c6
ML		 886 if ((c->processor_id & 0xff00) == PRID_IMP_NETLOGIC_AU13XX) {
887 c->cputype = CPU_ALCHEMY;
888 __cpu_name[cpu] = "Au1300";
889 /* following stuff is not for Alchemy */
890 return;
891 }
892
70342287
RB		 893 c->options = (MIPS_CPU_TLB |
894 MIPS_CPU_4KEX |
a7117c6b 895 MIPS_CPU_COUNTER |
70342287
RB		 896 MIPS_CPU_DIVEC |
897 MIPS_CPU_WATCH |
898 MIPS_CPU_EJTAG |
a7117c6b
J		 899 MIPS_CPU_LLSC);
900
901 switch (c->processor_id & 0xff00) {
2aa54b20
J		 902 case PRID_IMP_NETLOGIC_XLP8XX:
903 case PRID_IMP_NETLOGIC_XLP3XX:
a3d4fb2d
J		 904 c->cputype = CPU_XLP;
905 __cpu_name[cpu] = "Netlogic XLP";
906 break;
907
a7117c6b
J		 908 case PRID_IMP_NETLOGIC_XLR732:
909 case PRID_IMP_NETLOGIC_XLR716:
910 case PRID_IMP_NETLOGIC_XLR532:
911 case PRID_IMP_NETLOGIC_XLR308:
912 case PRID_IMP_NETLOGIC_XLR532C:
913 case PRID_IMP_NETLOGIC_XLR516C:
914 case PRID_IMP_NETLOGIC_XLR508C:
915 case PRID_IMP_NETLOGIC_XLR308C:
916 c->cputype = CPU_XLR;
917 __cpu_name[cpu] = "Netlogic XLR";
918 break;
919
920 case PRID_IMP_NETLOGIC_XLS608:
921 case PRID_IMP_NETLOGIC_XLS408:
922 case PRID_IMP_NETLOGIC_XLS404:
923 case PRID_IMP_NETLOGIC_XLS208:
924 case PRID_IMP_NETLOGIC_XLS204:
925 case PRID_IMP_NETLOGIC_XLS108:
926 case PRID_IMP_NETLOGIC_XLS104:
927 case PRID_IMP_NETLOGIC_XLS616B:
928 case PRID_IMP_NETLOGIC_XLS608B:
929 case PRID_IMP_NETLOGIC_XLS416B:
930 case PRID_IMP_NETLOGIC_XLS412B:
931 case PRID_IMP_NETLOGIC_XLS408B:
932 case PRID_IMP_NETLOGIC_XLS404B:
933 c->cputype = CPU_XLR;
934 __cpu_name[cpu] = "Netlogic XLS";
935 break;
936
937 default:
a3d4fb2d 938 pr_info("Unknown Netlogic chip id [%02x]!\n",
a7117c6b
J		 939 c->processor_id);
940 c->cputype = CPU_XLR;
941 break;
942 }
943
a3d4fb2d 944 if (c->cputype == CPU_XLP) {
a96102be 945 set_isa(c, MIPS_CPU_ISA_M64R2);
a3d4fb2d
J		 946 c->options |= (MIPS_CPU_FPU | MIPS_CPU_ULRI | MIPS_CPU_MCHECK);
947 /* This will be updated again after all threads are woken up */
948 c->tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1;
949 } else {
a96102be 950 set_isa(c, MIPS_CPU_ISA_M64R1);
a3d4fb2d
J		 951 c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1;
952 }
7777b939 953 c->kscratch_mask = 0xf;
a7117c6b
J		 954}
955
949e51be
DD		 956#ifdef CONFIG_64BIT
957/* For use by uaccess.h */
958u64 __ua_limit;
959EXPORT_SYMBOL(__ua_limit);
960#endif
961
9966db25 962const char *__cpu_name[NR_CPUS];
874fd3b5 963const char *__elf_platform;
9966db25 964
234fcd14 965__cpuinit void cpu_probe(void)
1da177e4
LT		 966{
967 struct cpuinfo_mips *c = &current_cpu_data;
9966db25 968 unsigned int cpu = smp_processor_id();
1da177e4 969
70342287 970 c->processor_id = PRID_IMP_UNKNOWN;
1da177e4
LT		 971 c->fpu_id = FPIR_IMP_NONE;
972 c->cputype = CPU_UNKNOWN;
973
974 c->processor_id = read_c0_prid();
975 switch (c->processor_id & 0xff0000) {
976 case PRID_COMP_LEGACY:
cea7e2df 977 cpu_probe_legacy(c, cpu);
1da177e4
LT		 978 break;
979 case PRID_COMP_MIPS:
cea7e2df 980 cpu_probe_mips(c, cpu);
1da177e4
LT		 981 break;
982 case PRID_COMP_ALCHEMY:
cea7e2df 983 cpu_probe_alchemy(c, cpu);
1da177e4
LT		 984 break;
985 case PRID_COMP_SIBYTE:
cea7e2df 986 cpu_probe_sibyte(c, cpu);
1da177e4 987 break;
1c0c13eb 988 case PRID_COMP_BROADCOM:
cea7e2df 989 cpu_probe_broadcom(c, cpu);
1c0c13eb 990 break;
1da177e4 991 case PRID_COMP_SANDCRAFT:
cea7e2df 992 cpu_probe_sandcraft(c, cpu);
1da177e4 993 break;
a92b0588 994 case PRID_COMP_NXP:
cea7e2df 995 cpu_probe_nxp(c, cpu);
a3dddd56 996 break;
0dd4781b
DD		 997 case PRID_COMP_CAVIUM:
998 cpu_probe_cavium(c, cpu);
999 break;
83ccf69d
LPC		 1000 case PRID_COMP_INGENIC:
1001 cpu_probe_ingenic(c, cpu);
1002 break;
a7117c6b
J		 1003 case PRID_COMP_NETLOGIC:
1004 cpu_probe_netlogic(c, cpu);
1005 break;
1da177e4 1006 }
dec8b1ca 1007
cea7e2df
RB		 1008 BUG_ON(!__cpu_name[cpu]);
1009 BUG_ON(c->cputype == CPU_UNKNOWN);
1010
dec8b1ca
FBH		 1011 /*
1012 * Platform code can force the cpu type to optimize code
1013 * generation. In that case be sure the cpu type is correctly
1014 * manually setup otherwise it could trigger some nasty bugs.
1015 */
1016 BUG_ON(current_cpu_type() != c->cputype);
1017
0103d23f
KC		 1018 if (mips_fpu_disabled)
1019 c->options &= ~MIPS_CPU_FPU;
1020
1021 if (mips_dsp_disabled)
ee80f7c7 1022 c->ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
0103d23f 1023
4194318c 1024 if (c->options & MIPS_CPU_FPU) {
1da177e4 1025 c->fpu_id = cpu_get_fpu_id();
4194318c 1026
adb37892
DCZ		 1027 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 |
1028 MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2)) {
4194318c
RB		 1029 if (c->fpu_id & MIPS_FPIR_3D)
1030 c->ases |= MIPS_ASE_MIPS3D;
1031 }
1032 }
9966db25 1033
da4b62cd 1034 if (cpu_has_mips_r2) {
f6771dbb 1035 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
da4b62cd
AC		 1036 /* R2 has Performance Counter Interrupt indicator */
1037 c->options |= MIPS_CPU_PCI;
1038 }
f6771dbb
RB		 1039 else
1040 c->srsets = 1;
91dfc423
GR		 1041
1042 cpu_probe_vmbits(c);
949e51be
DD		 1043
1044#ifdef CONFIG_64BIT
1045 if (cpu == 0)
1046 __ua_limit = ~((1ull << cpu_vmbits) - 1);
1047#endif
1da177e4
LT		 1048}
1049
234fcd14 1050__cpuinit void cpu_report(void)
1da177e4
LT		 1051{
1052 struct cpuinfo_mips *c = &current_cpu_data;
1053
9966db25
RB		 1054 printk(KERN_INFO "CPU revision is: %08x (%s)\n",
1055 c->processor_id, cpu_name_string());
1da177e4 1056 if (c->options & MIPS_CPU_FPU)
9966db25 1057 printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id);
1da177e4 1058}
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