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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Processor capabilities determination functions. | |
3 | * | |
4 | * Copyright (C) xxxx the Anonymous | |
010b853b | 5 | * Copyright (C) 1994 - 2006 Ralf Baechle |
4194318c | 6 | * Copyright (C) 2003, 2004 Maciej W. Rozycki |
4194318c | 7 | * Copyright (C) 2001, 2004 MIPS Inc. |
1da177e4 LT |
8 | * |
9 | * This program is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License | |
11 | * as published by the Free Software Foundation; either version | |
12 | * 2 of the License, or (at your option) any later version. | |
13 | */ | |
1da177e4 LT |
14 | #include <linux/init.h> |
15 | #include <linux/kernel.h> | |
16 | #include <linux/ptrace.h> | |
17 | #include <linux/stddef.h> | |
18 | ||
5759906c | 19 | #include <asm/bugs.h> |
1da177e4 LT |
20 | #include <asm/cpu.h> |
21 | #include <asm/fpu.h> | |
22 | #include <asm/mipsregs.h> | |
23 | #include <asm/system.h> | |
24 | ||
25 | /* | |
26 | * Not all of the MIPS CPUs have the "wait" instruction available. Moreover, | |
27 | * the implementation of the "wait" feature differs between CPU families. This | |
28 | * points to the function that implements CPU specific wait. | |
29 | * The wait instruction stops the pipeline and reduces the power consumption of | |
30 | * the CPU very much. | |
31 | */ | |
32 | void (*cpu_wait)(void) = NULL; | |
33 | ||
34 | static void r3081_wait(void) | |
35 | { | |
36 | unsigned long cfg = read_c0_conf(); | |
37 | write_c0_conf(cfg | R30XX_CONF_HALT); | |
38 | } | |
39 | ||
40 | static void r39xx_wait(void) | |
41 | { | |
60a6c377 AN |
42 | local_irq_disable(); |
43 | if (!need_resched()) | |
44 | write_c0_conf(read_c0_conf() | TX39_CONF_HALT); | |
45 | local_irq_enable(); | |
1da177e4 LT |
46 | } |
47 | ||
c65a5480 | 48 | extern void r4k_wait(void); |
60a6c377 AN |
49 | |
50 | /* | |
51 | * This variant is preferable as it allows testing need_resched and going to | |
52 | * sleep depending on the outcome atomically. Unfortunately the "It is | |
53 | * implementation-dependent whether the pipeline restarts when a non-enabled | |
54 | * interrupt is requested" restriction in the MIPS32/MIPS64 architecture makes | |
55 | * using this version a gamble. | |
56 | */ | |
8531a35e | 57 | void r4k_wait_irqoff(void) |
60a6c377 AN |
58 | { |
59 | local_irq_disable(); | |
60 | if (!need_resched()) | |
8531a35e KK |
61 | __asm__(" .set push \n" |
62 | " .set mips3 \n" | |
60a6c377 | 63 | " wait \n" |
8531a35e | 64 | " .set pop \n"); |
60a6c377 | 65 | local_irq_enable(); |
8531a35e KK |
66 | __asm__(" .globl __pastwait \n" |
67 | "__pastwait: \n"); | |
68 | return; | |
1da177e4 LT |
69 | } |
70 | ||
5a812999 RB |
71 | /* |
72 | * The RM7000 variant has to handle erratum 38. The workaround is to not | |
73 | * have any pending stores when the WAIT instruction is executed. | |
74 | */ | |
75 | static void rm7k_wait_irqoff(void) | |
76 | { | |
77 | local_irq_disable(); | |
78 | if (!need_resched()) | |
79 | __asm__( | |
80 | " .set push \n" | |
81 | " .set mips3 \n" | |
82 | " .set noat \n" | |
83 | " mfc0 $1, $12 \n" | |
84 | " sync \n" | |
85 | " mtc0 $1, $12 # stalls until W stage \n" | |
86 | " wait \n" | |
87 | " mtc0 $1, $12 # stalls until W stage \n" | |
88 | " .set pop \n"); | |
89 | local_irq_enable(); | |
90 | } | |
91 | ||
494900af PP |
92 | /* The Au1xxx wait is available only if using 32khz counter or |
93 | * external timer source, but specifically not CP0 Counter. */ | |
fe359bf5 | 94 | int allow_au1k_wait; |
10f650db | 95 | |
494900af | 96 | static void au1k_wait(void) |
1da177e4 | 97 | { |
1da177e4 | 98 | /* using the wait instruction makes CP0 counter unusable */ |
60a6c377 AN |
99 | __asm__(" .set mips3 \n" |
100 | " cache 0x14, 0(%0) \n" | |
101 | " cache 0x14, 32(%0) \n" | |
102 | " sync \n" | |
103 | " nop \n" | |
104 | " wait \n" | |
105 | " nop \n" | |
106 | " nop \n" | |
107 | " nop \n" | |
108 | " nop \n" | |
109 | " .set mips0 \n" | |
10f650db | 110 | : : "r" (au1k_wait)); |
1da177e4 LT |
111 | } |
112 | ||
55d04dff RB |
113 | static int __initdata nowait = 0; |
114 | ||
f49a747c | 115 | static int __init wait_disable(char *s) |
55d04dff RB |
116 | { |
117 | nowait = 1; | |
118 | ||
119 | return 1; | |
120 | } | |
121 | ||
122 | __setup("nowait", wait_disable); | |
123 | ||
c65a5480 | 124 | void __init check_wait(void) |
1da177e4 LT |
125 | { |
126 | struct cpuinfo_mips *c = ¤t_cpu_data; | |
127 | ||
55d04dff | 128 | if (nowait) { |
c2379230 | 129 | printk("Wait instruction disabled.\n"); |
55d04dff RB |
130 | return; |
131 | } | |
132 | ||
1da177e4 LT |
133 | switch (c->cputype) { |
134 | case CPU_R3081: | |
135 | case CPU_R3081E: | |
136 | cpu_wait = r3081_wait; | |
1da177e4 LT |
137 | break; |
138 | case CPU_TX3927: | |
139 | cpu_wait = r39xx_wait; | |
1da177e4 LT |
140 | break; |
141 | case CPU_R4200: | |
142 | /* case CPU_R4300: */ | |
143 | case CPU_R4600: | |
144 | case CPU_R4640: | |
145 | case CPU_R4650: | |
146 | case CPU_R4700: | |
147 | case CPU_R5000: | |
148 | case CPU_NEVADA: | |
1da177e4 LT |
149 | case CPU_4KC: |
150 | case CPU_4KEC: | |
151 | case CPU_4KSC: | |
152 | case CPU_5KC: | |
1da177e4 | 153 | case CPU_25KF: |
4b3e975e | 154 | case CPU_PR4450: |
1c0c13eb | 155 | case CPU_BCM3302: |
4b3e975e RB |
156 | cpu_wait = r4k_wait; |
157 | break; | |
158 | ||
5a812999 RB |
159 | case CPU_RM7000: |
160 | cpu_wait = rm7k_wait_irqoff; | |
161 | break; | |
162 | ||
4b3e975e | 163 | case CPU_24K: |
bbc7f22f | 164 | case CPU_34K: |
39b8d525 | 165 | case CPU_1004K: |
4b3e975e RB |
166 | cpu_wait = r4k_wait; |
167 | if (read_c0_config7() & MIPS_CONF7_WII) | |
168 | cpu_wait = r4k_wait_irqoff; | |
169 | break; | |
170 | ||
c620953c | 171 | case CPU_74K: |
1da177e4 | 172 | cpu_wait = r4k_wait; |
4b3e975e RB |
173 | if ((c->processor_id & 0xff) >= PRID_REV_ENCODE_332(2, 1, 0)) |
174 | cpu_wait = r4k_wait_irqoff; | |
1da177e4 | 175 | break; |
4b3e975e | 176 | |
60a6c377 AN |
177 | case CPU_TX49XX: |
178 | cpu_wait = r4k_wait_irqoff; | |
60a6c377 | 179 | break; |
1da177e4 LT |
180 | case CPU_AU1000: |
181 | case CPU_AU1100: | |
182 | case CPU_AU1500: | |
e3ad1c23 PP |
183 | case CPU_AU1550: |
184 | case CPU_AU1200: | |
237cfee1 ML |
185 | case CPU_AU1210: |
186 | case CPU_AU1250: | |
c2379230 | 187 | if (allow_au1k_wait) |
fe359bf5 | 188 | cpu_wait = au1k_wait; |
1da177e4 | 189 | break; |
c8eae71d RB |
190 | case CPU_20KC: |
191 | /* | |
192 | * WAIT on Rev1.0 has E1, E2, E3 and E16. | |
193 | * WAIT on Rev2.0 and Rev3.0 has E16. | |
194 | * Rev3.1 WAIT is nop, why bother | |
195 | */ | |
196 | if ((c->processor_id & 0xff) <= 0x64) | |
197 | break; | |
198 | ||
50da469a RB |
199 | /* |
200 | * Another rev is incremeting c0_count at a reduced clock | |
201 | * rate while in WAIT mode. So we basically have the choice | |
202 | * between using the cp0 timer as clocksource or avoiding | |
203 | * the WAIT instruction. Until more details are known, | |
204 | * disable the use of WAIT for 20Kc entirely. | |
205 | cpu_wait = r4k_wait; | |
206 | */ | |
c8eae71d | 207 | break; |
441ee341 | 208 | case CPU_RM9000: |
c2379230 | 209 | if ((c->processor_id & 0x00ff) >= 0x40) |
441ee341 | 210 | cpu_wait = r4k_wait; |
441ee341 | 211 | break; |
1da177e4 | 212 | default: |
1da177e4 LT |
213 | break; |
214 | } | |
215 | } | |
216 | ||
9267a30d MSJ |
217 | static inline void check_errata(void) |
218 | { | |
219 | struct cpuinfo_mips *c = ¤t_cpu_data; | |
220 | ||
221 | switch (c->cputype) { | |
222 | case CPU_34K: | |
223 | /* | |
224 | * Erratum "RPS May Cause Incorrect Instruction Execution" | |
225 | * This code only handles VPE0, any SMP/SMTC/RTOS code | |
226 | * making use of VPE1 will be responsable for that VPE. | |
227 | */ | |
228 | if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2) | |
229 | write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS); | |
230 | break; | |
231 | default: | |
232 | break; | |
233 | } | |
234 | } | |
235 | ||
1da177e4 LT |
236 | void __init check_bugs32(void) |
237 | { | |
9267a30d | 238 | check_errata(); |
1da177e4 LT |
239 | } |
240 | ||
241 | /* | |
242 | * Probe whether cpu has config register by trying to play with | |
243 | * alternate cache bit and see whether it matters. | |
244 | * It's used by cpu_probe to distinguish between R3000A and R3081. | |
245 | */ | |
246 | static inline int cpu_has_confreg(void) | |
247 | { | |
248 | #ifdef CONFIG_CPU_R3000 | |
249 | extern unsigned long r3k_cache_size(unsigned long); | |
250 | unsigned long size1, size2; | |
251 | unsigned long cfg = read_c0_conf(); | |
252 | ||
253 | size1 = r3k_cache_size(ST0_ISC); | |
254 | write_c0_conf(cfg ^ R30XX_CONF_AC); | |
255 | size2 = r3k_cache_size(ST0_ISC); | |
256 | write_c0_conf(cfg); | |
257 | return size1 != size2; | |
258 | #else | |
259 | return 0; | |
260 | #endif | |
261 | } | |
262 | ||
263 | /* | |
264 | * Get the FPU Implementation/Revision. | |
265 | */ | |
266 | static inline unsigned long cpu_get_fpu_id(void) | |
267 | { | |
268 | unsigned long tmp, fpu_id; | |
269 | ||
270 | tmp = read_c0_status(); | |
271 | __enable_fpu(); | |
272 | fpu_id = read_32bit_cp1_register(CP1_REVISION); | |
273 | write_c0_status(tmp); | |
274 | return fpu_id; | |
275 | } | |
276 | ||
277 | /* | |
278 | * Check the CPU has an FPU the official way. | |
279 | */ | |
280 | static inline int __cpu_has_fpu(void) | |
281 | { | |
282 | return ((cpu_get_fpu_id() & 0xff00) != FPIR_IMP_NONE); | |
283 | } | |
284 | ||
02cf2119 | 285 | #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \ |
1da177e4 LT |
286 | | MIPS_CPU_COUNTER) |
287 | ||
288 | static inline void cpu_probe_legacy(struct cpuinfo_mips *c) | |
289 | { | |
290 | switch (c->processor_id & 0xff00) { | |
291 | case PRID_IMP_R2000: | |
292 | c->cputype = CPU_R2000; | |
293 | c->isa_level = MIPS_CPU_ISA_I; | |
02cf2119 RB |
294 | c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE | |
295 | MIPS_CPU_NOFPUEX; | |
1da177e4 LT |
296 | if (__cpu_has_fpu()) |
297 | c->options |= MIPS_CPU_FPU; | |
298 | c->tlbsize = 64; | |
299 | break; | |
300 | case PRID_IMP_R3000: | |
301 | if ((c->processor_id & 0xff) == PRID_REV_R3000A) | |
302 | if (cpu_has_confreg()) | |
303 | c->cputype = CPU_R3081E; | |
304 | else | |
305 | c->cputype = CPU_R3000A; | |
306 | else | |
307 | c->cputype = CPU_R3000; | |
308 | c->isa_level = MIPS_CPU_ISA_I; | |
02cf2119 RB |
309 | c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE | |
310 | MIPS_CPU_NOFPUEX; | |
1da177e4 LT |
311 | if (__cpu_has_fpu()) |
312 | c->options |= MIPS_CPU_FPU; | |
313 | c->tlbsize = 64; | |
314 | break; | |
315 | case PRID_IMP_R4000: | |
316 | if (read_c0_config() & CONF_SC) { | |
317 | if ((c->processor_id & 0xff) >= PRID_REV_R4400) | |
318 | c->cputype = CPU_R4400PC; | |
319 | else | |
320 | c->cputype = CPU_R4000PC; | |
321 | } else { | |
322 | if ((c->processor_id & 0xff) >= PRID_REV_R4400) | |
323 | c->cputype = CPU_R4400SC; | |
324 | else | |
325 | c->cputype = CPU_R4000SC; | |
326 | } | |
327 | ||
328 | c->isa_level = MIPS_CPU_ISA_III; | |
329 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | | |
330 | MIPS_CPU_WATCH | MIPS_CPU_VCE | | |
331 | MIPS_CPU_LLSC; | |
332 | c->tlbsize = 48; | |
333 | break; | |
334 | case PRID_IMP_VR41XX: | |
335 | switch (c->processor_id & 0xf0) { | |
1da177e4 LT |
336 | case PRID_REV_VR4111: |
337 | c->cputype = CPU_VR4111; | |
338 | break; | |
1da177e4 LT |
339 | case PRID_REV_VR4121: |
340 | c->cputype = CPU_VR4121; | |
341 | break; | |
342 | case PRID_REV_VR4122: | |
343 | if ((c->processor_id & 0xf) < 0x3) | |
344 | c->cputype = CPU_VR4122; | |
345 | else | |
346 | c->cputype = CPU_VR4181A; | |
347 | break; | |
348 | case PRID_REV_VR4130: | |
349 | if ((c->processor_id & 0xf) < 0x4) | |
350 | c->cputype = CPU_VR4131; | |
351 | else | |
352 | c->cputype = CPU_VR4133; | |
353 | break; | |
354 | default: | |
355 | printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n"); | |
356 | c->cputype = CPU_VR41XX; | |
357 | break; | |
358 | } | |
359 | c->isa_level = MIPS_CPU_ISA_III; | |
360 | c->options = R4K_OPTS; | |
361 | c->tlbsize = 32; | |
362 | break; | |
363 | case PRID_IMP_R4300: | |
364 | c->cputype = CPU_R4300; | |
365 | c->isa_level = MIPS_CPU_ISA_III; | |
366 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | | |
367 | MIPS_CPU_LLSC; | |
368 | c->tlbsize = 32; | |
369 | break; | |
370 | case PRID_IMP_R4600: | |
371 | c->cputype = CPU_R4600; | |
372 | c->isa_level = MIPS_CPU_ISA_III; | |
075e7502 TS |
373 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | |
374 | MIPS_CPU_LLSC; | |
1da177e4 LT |
375 | c->tlbsize = 48; |
376 | break; | |
377 | #if 0 | |
378 | case PRID_IMP_R4650: | |
379 | /* | |
380 | * This processor doesn't have an MMU, so it's not | |
381 | * "real easy" to run Linux on it. It is left purely | |
382 | * for documentation. Commented out because it shares | |
383 | * it's c0_prid id number with the TX3900. | |
384 | */ | |
a3dddd56 | 385 | c->cputype = CPU_R4650; |
1da177e4 LT |
386 | c->isa_level = MIPS_CPU_ISA_III; |
387 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC; | |
388 | c->tlbsize = 48; | |
389 | break; | |
390 | #endif | |
391 | case PRID_IMP_TX39: | |
392 | c->isa_level = MIPS_CPU_ISA_I; | |
02cf2119 | 393 | c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE; |
1da177e4 LT |
394 | |
395 | if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) { | |
396 | c->cputype = CPU_TX3927; | |
397 | c->tlbsize = 64; | |
398 | } else { | |
399 | switch (c->processor_id & 0xff) { | |
400 | case PRID_REV_TX3912: | |
401 | c->cputype = CPU_TX3912; | |
402 | c->tlbsize = 32; | |
403 | break; | |
404 | case PRID_REV_TX3922: | |
405 | c->cputype = CPU_TX3922; | |
406 | c->tlbsize = 64; | |
407 | break; | |
408 | default: | |
409 | c->cputype = CPU_UNKNOWN; | |
410 | break; | |
411 | } | |
412 | } | |
413 | break; | |
414 | case PRID_IMP_R4700: | |
415 | c->cputype = CPU_R4700; | |
416 | c->isa_level = MIPS_CPU_ISA_III; | |
417 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | | |
418 | MIPS_CPU_LLSC; | |
419 | c->tlbsize = 48; | |
420 | break; | |
421 | case PRID_IMP_TX49: | |
422 | c->cputype = CPU_TX49XX; | |
423 | c->isa_level = MIPS_CPU_ISA_III; | |
424 | c->options = R4K_OPTS | MIPS_CPU_LLSC; | |
425 | if (!(c->processor_id & 0x08)) | |
426 | c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR; | |
427 | c->tlbsize = 48; | |
428 | break; | |
429 | case PRID_IMP_R5000: | |
430 | c->cputype = CPU_R5000; | |
431 | c->isa_level = MIPS_CPU_ISA_IV; | |
432 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | | |
433 | MIPS_CPU_LLSC; | |
434 | c->tlbsize = 48; | |
435 | break; | |
436 | case PRID_IMP_R5432: | |
437 | c->cputype = CPU_R5432; | |
438 | c->isa_level = MIPS_CPU_ISA_IV; | |
439 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | | |
440 | MIPS_CPU_WATCH | MIPS_CPU_LLSC; | |
441 | c->tlbsize = 48; | |
442 | break; | |
443 | case PRID_IMP_R5500: | |
444 | c->cputype = CPU_R5500; | |
445 | c->isa_level = MIPS_CPU_ISA_IV; | |
446 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | | |
447 | MIPS_CPU_WATCH | MIPS_CPU_LLSC; | |
448 | c->tlbsize = 48; | |
449 | break; | |
450 | case PRID_IMP_NEVADA: | |
451 | c->cputype = CPU_NEVADA; | |
452 | c->isa_level = MIPS_CPU_ISA_IV; | |
453 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | | |
454 | MIPS_CPU_DIVEC | MIPS_CPU_LLSC; | |
455 | c->tlbsize = 48; | |
456 | break; | |
457 | case PRID_IMP_R6000: | |
458 | c->cputype = CPU_R6000; | |
459 | c->isa_level = MIPS_CPU_ISA_II; | |
460 | c->options = MIPS_CPU_TLB | MIPS_CPU_FPU | | |
461 | MIPS_CPU_LLSC; | |
462 | c->tlbsize = 32; | |
463 | break; | |
464 | case PRID_IMP_R6000A: | |
465 | c->cputype = CPU_R6000A; | |
466 | c->isa_level = MIPS_CPU_ISA_II; | |
467 | c->options = MIPS_CPU_TLB | MIPS_CPU_FPU | | |
468 | MIPS_CPU_LLSC; | |
469 | c->tlbsize = 32; | |
470 | break; | |
471 | case PRID_IMP_RM7000: | |
472 | c->cputype = CPU_RM7000; | |
473 | c->isa_level = MIPS_CPU_ISA_IV; | |
474 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | | |
475 | MIPS_CPU_LLSC; | |
476 | /* | |
477 | * Undocumented RM7000: Bit 29 in the info register of | |
478 | * the RM7000 v2.0 indicates if the TLB has 48 or 64 | |
479 | * entries. | |
480 | * | |
481 | * 29 1 => 64 entry JTLB | |
482 | * 0 => 48 entry JTLB | |
483 | */ | |
484 | c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48; | |
485 | break; | |
486 | case PRID_IMP_RM9000: | |
487 | c->cputype = CPU_RM9000; | |
488 | c->isa_level = MIPS_CPU_ISA_IV; | |
489 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | | |
490 | MIPS_CPU_LLSC; | |
491 | /* | |
492 | * Bit 29 in the info register of the RM9000 | |
493 | * indicates if the TLB has 48 or 64 entries. | |
494 | * | |
495 | * 29 1 => 64 entry JTLB | |
496 | * 0 => 48 entry JTLB | |
497 | */ | |
498 | c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48; | |
499 | break; | |
500 | case PRID_IMP_R8000: | |
501 | c->cputype = CPU_R8000; | |
502 | c->isa_level = MIPS_CPU_ISA_IV; | |
503 | c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX | | |
504 | MIPS_CPU_FPU | MIPS_CPU_32FPR | | |
505 | MIPS_CPU_LLSC; | |
506 | c->tlbsize = 384; /* has weird TLB: 3-way x 128 */ | |
507 | break; | |
508 | case PRID_IMP_R10000: | |
509 | c->cputype = CPU_R10000; | |
510 | c->isa_level = MIPS_CPU_ISA_IV; | |
8b36612a | 511 | c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | |
1da177e4 LT |
512 | MIPS_CPU_FPU | MIPS_CPU_32FPR | |
513 | MIPS_CPU_COUNTER | MIPS_CPU_WATCH | | |
514 | MIPS_CPU_LLSC; | |
515 | c->tlbsize = 64; | |
516 | break; | |
517 | case PRID_IMP_R12000: | |
518 | c->cputype = CPU_R12000; | |
519 | c->isa_level = MIPS_CPU_ISA_IV; | |
8b36612a | 520 | c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | |
1da177e4 LT |
521 | MIPS_CPU_FPU | MIPS_CPU_32FPR | |
522 | MIPS_CPU_COUNTER | MIPS_CPU_WATCH | | |
523 | MIPS_CPU_LLSC; | |
524 | c->tlbsize = 64; | |
525 | break; | |
44d921b2 K |
526 | case PRID_IMP_R14000: |
527 | c->cputype = CPU_R14000; | |
528 | c->isa_level = MIPS_CPU_ISA_IV; | |
529 | c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | | |
530 | MIPS_CPU_FPU | MIPS_CPU_32FPR | | |
531 | MIPS_CPU_COUNTER | MIPS_CPU_WATCH | | |
532 | MIPS_CPU_LLSC; | |
533 | c->tlbsize = 64; | |
534 | break; | |
2a21c730 FZ |
535 | case PRID_IMP_LOONGSON2: |
536 | c->cputype = CPU_LOONGSON2; | |
537 | c->isa_level = MIPS_CPU_ISA_III; | |
538 | c->options = R4K_OPTS | | |
539 | MIPS_CPU_FPU | MIPS_CPU_LLSC | | |
540 | MIPS_CPU_32FPR; | |
541 | c->tlbsize = 64; | |
542 | break; | |
1da177e4 LT |
543 | } |
544 | } | |
545 | ||
234fcd14 | 546 | static char unknown_isa[] __cpuinitdata = KERN_ERR \ |
b4672d37 RB |
547 | "Unsupported ISA type, c0.config0: %d."; |
548 | ||
4194318c | 549 | static inline unsigned int decode_config0(struct cpuinfo_mips *c) |
1da177e4 | 550 | { |
4194318c RB |
551 | unsigned int config0; |
552 | int isa; | |
1da177e4 | 553 | |
4194318c RB |
554 | config0 = read_c0_config(); |
555 | ||
556 | if (((config0 & MIPS_CONF_MT) >> 7) == 1) | |
02cf2119 | 557 | c->options |= MIPS_CPU_TLB; |
4194318c RB |
558 | isa = (config0 & MIPS_CONF_AT) >> 13; |
559 | switch (isa) { | |
560 | case 0: | |
3a01c49a | 561 | switch ((config0 & MIPS_CONF_AR) >> 10) { |
b4672d37 RB |
562 | case 0: |
563 | c->isa_level = MIPS_CPU_ISA_M32R1; | |
564 | break; | |
565 | case 1: | |
566 | c->isa_level = MIPS_CPU_ISA_M32R2; | |
567 | break; | |
568 | default: | |
569 | goto unknown; | |
570 | } | |
4194318c RB |
571 | break; |
572 | case 2: | |
3a01c49a | 573 | switch ((config0 & MIPS_CONF_AR) >> 10) { |
b4672d37 RB |
574 | case 0: |
575 | c->isa_level = MIPS_CPU_ISA_M64R1; | |
576 | break; | |
577 | case 1: | |
578 | c->isa_level = MIPS_CPU_ISA_M64R2; | |
579 | break; | |
580 | default: | |
581 | goto unknown; | |
582 | } | |
4194318c RB |
583 | break; |
584 | default: | |
b4672d37 | 585 | goto unknown; |
4194318c RB |
586 | } |
587 | ||
588 | return config0 & MIPS_CONF_M; | |
b4672d37 RB |
589 | |
590 | unknown: | |
591 | panic(unknown_isa, config0); | |
4194318c RB |
592 | } |
593 | ||
594 | static inline unsigned int decode_config1(struct cpuinfo_mips *c) | |
595 | { | |
596 | unsigned int config1; | |
1da177e4 | 597 | |
1da177e4 | 598 | config1 = read_c0_config1(); |
4194318c RB |
599 | |
600 | if (config1 & MIPS_CONF1_MD) | |
601 | c->ases |= MIPS_ASE_MDMX; | |
602 | if (config1 & MIPS_CONF1_WR) | |
1da177e4 | 603 | c->options |= MIPS_CPU_WATCH; |
4194318c RB |
604 | if (config1 & MIPS_CONF1_CA) |
605 | c->ases |= MIPS_ASE_MIPS16; | |
606 | if (config1 & MIPS_CONF1_EP) | |
1da177e4 | 607 | c->options |= MIPS_CPU_EJTAG; |
4194318c | 608 | if (config1 & MIPS_CONF1_FP) { |
1da177e4 LT |
609 | c->options |= MIPS_CPU_FPU; |
610 | c->options |= MIPS_CPU_32FPR; | |
611 | } | |
4194318c RB |
612 | if (cpu_has_tlb) |
613 | c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1; | |
614 | ||
615 | return config1 & MIPS_CONF_M; | |
616 | } | |
617 | ||
618 | static inline unsigned int decode_config2(struct cpuinfo_mips *c) | |
619 | { | |
620 | unsigned int config2; | |
621 | ||
622 | config2 = read_c0_config2(); | |
623 | ||
624 | if (config2 & MIPS_CONF2_SL) | |
625 | c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT; | |
626 | ||
627 | return config2 & MIPS_CONF_M; | |
628 | } | |
629 | ||
630 | static inline unsigned int decode_config3(struct cpuinfo_mips *c) | |
631 | { | |
632 | unsigned int config3; | |
633 | ||
634 | config3 = read_c0_config3(); | |
635 | ||
636 | if (config3 & MIPS_CONF3_SM) | |
637 | c->ases |= MIPS_ASE_SMARTMIPS; | |
e50c0a8f RB |
638 | if (config3 & MIPS_CONF3_DSP) |
639 | c->ases |= MIPS_ASE_DSP; | |
8f40611d RB |
640 | if (config3 & MIPS_CONF3_VINT) |
641 | c->options |= MIPS_CPU_VINT; | |
642 | if (config3 & MIPS_CONF3_VEIC) | |
643 | c->options |= MIPS_CPU_VEIC; | |
644 | if (config3 & MIPS_CONF3_MT) | |
e0daad44 | 645 | c->ases |= MIPS_ASE_MIPSMT; |
a3692020 RB |
646 | if (config3 & MIPS_CONF3_ULRI) |
647 | c->options |= MIPS_CPU_ULRI; | |
4194318c RB |
648 | |
649 | return config3 & MIPS_CONF_M; | |
650 | } | |
651 | ||
234fcd14 | 652 | static void __cpuinit decode_configs(struct cpuinfo_mips *c) |
4194318c RB |
653 | { |
654 | /* MIPS32 or MIPS64 compliant CPU. */ | |
02cf2119 RB |
655 | c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER | |
656 | MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK; | |
4194318c | 657 | |
1da177e4 LT |
658 | c->scache.flags = MIPS_CACHE_NOT_PRESENT; |
659 | ||
4194318c RB |
660 | /* Read Config registers. */ |
661 | if (!decode_config0(c)) | |
662 | return; /* actually worth a panic() */ | |
663 | if (!decode_config1(c)) | |
664 | return; | |
665 | if (!decode_config2(c)) | |
666 | return; | |
667 | if (!decode_config3(c)) | |
668 | return; | |
1da177e4 LT |
669 | } |
670 | ||
0b6d497f CD |
671 | #ifdef CONFIG_CPU_MIPSR2 |
672 | extern void spram_config(void); | |
673 | #else | |
674 | static inline void spram_config(void) {} | |
675 | #endif | |
676 | ||
1da177e4 LT |
677 | static inline void cpu_probe_mips(struct cpuinfo_mips *c) |
678 | { | |
4194318c | 679 | decode_configs(c); |
1da177e4 LT |
680 | switch (c->processor_id & 0xff00) { |
681 | case PRID_IMP_4KC: | |
682 | c->cputype = CPU_4KC; | |
1da177e4 LT |
683 | break; |
684 | case PRID_IMP_4KEC: | |
685 | c->cputype = CPU_4KEC; | |
1da177e4 | 686 | break; |
2b07bd02 RB |
687 | case PRID_IMP_4KECR2: |
688 | c->cputype = CPU_4KEC; | |
2b07bd02 | 689 | break; |
1da177e4 | 690 | case PRID_IMP_4KSC: |
8afcb5d8 | 691 | case PRID_IMP_4KSD: |
1da177e4 | 692 | c->cputype = CPU_4KSC; |
1da177e4 LT |
693 | break; |
694 | case PRID_IMP_5KC: | |
695 | c->cputype = CPU_5KC; | |
1da177e4 LT |
696 | break; |
697 | case PRID_IMP_20KC: | |
698 | c->cputype = CPU_20KC; | |
1da177e4 LT |
699 | break; |
700 | case PRID_IMP_24K: | |
e50c0a8f | 701 | case PRID_IMP_24KE: |
1da177e4 | 702 | c->cputype = CPU_24K; |
1da177e4 LT |
703 | break; |
704 | case PRID_IMP_25KF: | |
705 | c->cputype = CPU_25KF; | |
1da177e4 | 706 | break; |
bbc7f22f RB |
707 | case PRID_IMP_34K: |
708 | c->cputype = CPU_34K; | |
bbc7f22f | 709 | break; |
c620953c CD |
710 | case PRID_IMP_74K: |
711 | c->cputype = CPU_74K; | |
712 | break; | |
39b8d525 RB |
713 | case PRID_IMP_1004K: |
714 | c->cputype = CPU_1004K; | |
715 | break; | |
1da177e4 | 716 | } |
0b6d497f CD |
717 | |
718 | spram_config(); | |
1da177e4 LT |
719 | } |
720 | ||
721 | static inline void cpu_probe_alchemy(struct cpuinfo_mips *c) | |
722 | { | |
4194318c | 723 | decode_configs(c); |
1da177e4 LT |
724 | switch (c->processor_id & 0xff00) { |
725 | case PRID_IMP_AU1_REV1: | |
726 | case PRID_IMP_AU1_REV2: | |
727 | switch ((c->processor_id >> 24) & 0xff) { | |
728 | case 0: | |
a3dddd56 | 729 | c->cputype = CPU_AU1000; |
1da177e4 LT |
730 | break; |
731 | case 1: | |
732 | c->cputype = CPU_AU1500; | |
733 | break; | |
734 | case 2: | |
735 | c->cputype = CPU_AU1100; | |
736 | break; | |
737 | case 3: | |
738 | c->cputype = CPU_AU1550; | |
739 | break; | |
e3ad1c23 PP |
740 | case 4: |
741 | c->cputype = CPU_AU1200; | |
237cfee1 ML |
742 | if (2 == (c->processor_id & 0xff)) |
743 | c->cputype = CPU_AU1250; | |
744 | break; | |
745 | case 5: | |
746 | c->cputype = CPU_AU1210; | |
e3ad1c23 | 747 | break; |
1da177e4 LT |
748 | default: |
749 | panic("Unknown Au Core!"); | |
750 | break; | |
751 | } | |
1da177e4 LT |
752 | break; |
753 | } | |
754 | } | |
755 | ||
756 | static inline void cpu_probe_sibyte(struct cpuinfo_mips *c) | |
757 | { | |
4194318c | 758 | decode_configs(c); |
02cf2119 | 759 | |
1da177e4 LT |
760 | switch (c->processor_id & 0xff00) { |
761 | case PRID_IMP_SB1: | |
762 | c->cputype = CPU_SB1; | |
1da177e4 | 763 | /* FPU in pass1 is known to have issues. */ |
aa32374a | 764 | if ((c->processor_id & 0xff) < 0x02) |
010b853b | 765 | c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR); |
1da177e4 | 766 | break; |
93ce2f52 AI |
767 | case PRID_IMP_SB1A: |
768 | c->cputype = CPU_SB1A; | |
769 | break; | |
1da177e4 LT |
770 | } |
771 | } | |
772 | ||
773 | static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c) | |
774 | { | |
4194318c | 775 | decode_configs(c); |
1da177e4 LT |
776 | switch (c->processor_id & 0xff00) { |
777 | case PRID_IMP_SR71000: | |
778 | c->cputype = CPU_SR71000; | |
1da177e4 LT |
779 | c->scache.ways = 8; |
780 | c->tlbsize = 64; | |
781 | break; | |
782 | } | |
783 | } | |
784 | ||
a92b0588 | 785 | static inline void cpu_probe_nxp(struct cpuinfo_mips *c) |
bdf21b18 PP |
786 | { |
787 | decode_configs(c); | |
788 | switch (c->processor_id & 0xff00) { | |
789 | case PRID_IMP_PR4450: | |
790 | c->cputype = CPU_PR4450; | |
e7958bb9 | 791 | c->isa_level = MIPS_CPU_ISA_M32R1; |
bdf21b18 PP |
792 | break; |
793 | default: | |
a92b0588 | 794 | panic("Unknown NXP Core!"); /* REVISIT: die? */ |
bdf21b18 PP |
795 | break; |
796 | } | |
797 | } | |
798 | ||
799 | ||
1c0c13eb AJ |
800 | static inline void cpu_probe_broadcom(struct cpuinfo_mips *c) |
801 | { | |
802 | decode_configs(c); | |
803 | switch (c->processor_id & 0xff00) { | |
804 | case PRID_IMP_BCM3302: | |
805 | c->cputype = CPU_BCM3302; | |
806 | break; | |
807 | case PRID_IMP_BCM4710: | |
808 | c->cputype = CPU_BCM4710; | |
809 | break; | |
810 | default: | |
811 | c->cputype = CPU_UNKNOWN; | |
812 | break; | |
813 | } | |
814 | } | |
815 | ||
9966db25 RB |
816 | const char *__cpu_name[NR_CPUS]; |
817 | ||
818 | /* | |
819 | * Name a CPU | |
820 | */ | |
234fcd14 | 821 | static __cpuinit const char *cpu_to_name(struct cpuinfo_mips *c) |
9966db25 RB |
822 | { |
823 | const char *name = NULL; | |
824 | ||
825 | switch (c->cputype) { | |
826 | case CPU_UNKNOWN: name = "unknown"; break; | |
827 | case CPU_R2000: name = "R2000"; break; | |
828 | case CPU_R3000: name = "R3000"; break; | |
829 | case CPU_R3000A: name = "R3000A"; break; | |
830 | case CPU_R3041: name = "R3041"; break; | |
831 | case CPU_R3051: name = "R3051"; break; | |
832 | case CPU_R3052: name = "R3052"; break; | |
833 | case CPU_R3081: name = "R3081"; break; | |
834 | case CPU_R3081E: name = "R3081E"; break; | |
835 | case CPU_R4000PC: name = "R4000PC"; break; | |
836 | case CPU_R4000SC: name = "R4000SC"; break; | |
837 | case CPU_R4000MC: name = "R4000MC"; break; | |
838 | case CPU_R4200: name = "R4200"; break; | |
839 | case CPU_R4400PC: name = "R4400PC"; break; | |
840 | case CPU_R4400SC: name = "R4400SC"; break; | |
841 | case CPU_R4400MC: name = "R4400MC"; break; | |
842 | case CPU_R4600: name = "R4600"; break; | |
843 | case CPU_R6000: name = "R6000"; break; | |
844 | case CPU_R6000A: name = "R6000A"; break; | |
845 | case CPU_R8000: name = "R8000"; break; | |
846 | case CPU_R10000: name = "R10000"; break; | |
847 | case CPU_R12000: name = "R12000"; break; | |
848 | case CPU_R14000: name = "R14000"; break; | |
849 | case CPU_R4300: name = "R4300"; break; | |
850 | case CPU_R4650: name = "R4650"; break; | |
851 | case CPU_R4700: name = "R4700"; break; | |
852 | case CPU_R5000: name = "R5000"; break; | |
853 | case CPU_R5000A: name = "R5000A"; break; | |
854 | case CPU_R4640: name = "R4640"; break; | |
855 | case CPU_NEVADA: name = "Nevada"; break; | |
856 | case CPU_RM7000: name = "RM7000"; break; | |
857 | case CPU_RM9000: name = "RM9000"; break; | |
858 | case CPU_R5432: name = "R5432"; break; | |
859 | case CPU_4KC: name = "MIPS 4Kc"; break; | |
860 | case CPU_5KC: name = "MIPS 5Kc"; break; | |
861 | case CPU_R4310: name = "R4310"; break; | |
862 | case CPU_SB1: name = "SiByte SB1"; break; | |
863 | case CPU_SB1A: name = "SiByte SB1A"; break; | |
864 | case CPU_TX3912: name = "TX3912"; break; | |
865 | case CPU_TX3922: name = "TX3922"; break; | |
866 | case CPU_TX3927: name = "TX3927"; break; | |
867 | case CPU_AU1000: name = "Au1000"; break; | |
868 | case CPU_AU1500: name = "Au1500"; break; | |
869 | case CPU_AU1100: name = "Au1100"; break; | |
870 | case CPU_AU1550: name = "Au1550"; break; | |
871 | case CPU_AU1200: name = "Au1200"; break; | |
237cfee1 ML |
872 | case CPU_AU1210: name = "Au1210"; break; |
873 | case CPU_AU1250: name = "Au1250"; break; | |
9966db25 RB |
874 | case CPU_4KEC: name = "MIPS 4KEc"; break; |
875 | case CPU_4KSC: name = "MIPS 4KSc"; break; | |
876 | case CPU_VR41XX: name = "NEC Vr41xx"; break; | |
877 | case CPU_R5500: name = "R5500"; break; | |
878 | case CPU_TX49XX: name = "TX49xx"; break; | |
879 | case CPU_20KC: name = "MIPS 20Kc"; break; | |
880 | case CPU_24K: name = "MIPS 24K"; break; | |
881 | case CPU_25KF: name = "MIPS 25Kf"; break; | |
882 | case CPU_34K: name = "MIPS 34K"; break; | |
39b8d525 | 883 | case CPU_1004K: name = "MIPS 1004K"; break; |
9966db25 RB |
884 | case CPU_74K: name = "MIPS 74K"; break; |
885 | case CPU_VR4111: name = "NEC VR4111"; break; | |
886 | case CPU_VR4121: name = "NEC VR4121"; break; | |
887 | case CPU_VR4122: name = "NEC VR4122"; break; | |
888 | case CPU_VR4131: name = "NEC VR4131"; break; | |
889 | case CPU_VR4133: name = "NEC VR4133"; break; | |
890 | case CPU_VR4181: name = "NEC VR4181"; break; | |
891 | case CPU_VR4181A: name = "NEC VR4181A"; break; | |
892 | case CPU_SR71000: name = "Sandcraft SR71000"; break; | |
893 | case CPU_BCM3302: name = "Broadcom BCM3302"; break; | |
894 | case CPU_BCM4710: name = "Broadcom BCM4710"; break; | |
895 | case CPU_PR4450: name = "Philips PR4450"; break; | |
896 | case CPU_LOONGSON2: name = "ICT Loongson-2"; break; | |
897 | default: | |
898 | BUG(); | |
899 | } | |
900 | ||
901 | return name; | |
902 | } | |
903 | ||
234fcd14 | 904 | __cpuinit void cpu_probe(void) |
1da177e4 LT |
905 | { |
906 | struct cpuinfo_mips *c = ¤t_cpu_data; | |
9966db25 | 907 | unsigned int cpu = smp_processor_id(); |
1da177e4 LT |
908 | |
909 | c->processor_id = PRID_IMP_UNKNOWN; | |
910 | c->fpu_id = FPIR_IMP_NONE; | |
911 | c->cputype = CPU_UNKNOWN; | |
912 | ||
913 | c->processor_id = read_c0_prid(); | |
914 | switch (c->processor_id & 0xff0000) { | |
915 | case PRID_COMP_LEGACY: | |
916 | cpu_probe_legacy(c); | |
917 | break; | |
918 | case PRID_COMP_MIPS: | |
919 | cpu_probe_mips(c); | |
920 | break; | |
921 | case PRID_COMP_ALCHEMY: | |
922 | cpu_probe_alchemy(c); | |
923 | break; | |
924 | case PRID_COMP_SIBYTE: | |
925 | cpu_probe_sibyte(c); | |
926 | break; | |
1c0c13eb AJ |
927 | case PRID_COMP_BROADCOM: |
928 | cpu_probe_broadcom(c); | |
929 | break; | |
1da177e4 LT |
930 | case PRID_COMP_SANDCRAFT: |
931 | cpu_probe_sandcraft(c); | |
932 | break; | |
a92b0588 DL |
933 | case PRID_COMP_NXP: |
934 | cpu_probe_nxp(c); | |
a3dddd56 | 935 | break; |
1da177e4 LT |
936 | default: |
937 | c->cputype = CPU_UNKNOWN; | |
938 | } | |
dec8b1ca FBH |
939 | |
940 | /* | |
941 | * Platform code can force the cpu type to optimize code | |
942 | * generation. In that case be sure the cpu type is correctly | |
943 | * manually setup otherwise it could trigger some nasty bugs. | |
944 | */ | |
945 | BUG_ON(current_cpu_type() != c->cputype); | |
946 | ||
4194318c | 947 | if (c->options & MIPS_CPU_FPU) { |
1da177e4 | 948 | c->fpu_id = cpu_get_fpu_id(); |
4194318c | 949 | |
e7958bb9 | 950 | if (c->isa_level == MIPS_CPU_ISA_M32R1 || |
b4672d37 RB |
951 | c->isa_level == MIPS_CPU_ISA_M32R2 || |
952 | c->isa_level == MIPS_CPU_ISA_M64R1 || | |
953 | c->isa_level == MIPS_CPU_ISA_M64R2) { | |
4194318c RB |
954 | if (c->fpu_id & MIPS_FPIR_3D) |
955 | c->ases |= MIPS_ASE_MIPS3D; | |
956 | } | |
957 | } | |
9966db25 RB |
958 | |
959 | __cpu_name[cpu] = cpu_to_name(c); | |
f6771dbb RB |
960 | |
961 | if (cpu_has_mips_r2) | |
962 | c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1; | |
963 | else | |
964 | c->srsets = 1; | |
1da177e4 LT |
965 | } |
966 | ||
234fcd14 | 967 | __cpuinit void cpu_report(void) |
1da177e4 LT |
968 | { |
969 | struct cpuinfo_mips *c = ¤t_cpu_data; | |
970 | ||
9966db25 RB |
971 | printk(KERN_INFO "CPU revision is: %08x (%s)\n", |
972 | c->processor_id, cpu_name_string()); | |
1da177e4 | 973 | if (c->options & MIPS_CPU_FPU) |
9966db25 | 974 | printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id); |
1da177e4 | 975 | } |