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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Processor capabilities determination functions. | |
3 | * | |
4 | * Copyright (C) xxxx the Anonymous | |
010b853b | 5 | * Copyright (C) 1994 - 2006 Ralf Baechle |
4194318c | 6 | * Copyright (C) 2003, 2004 Maciej W. Rozycki |
4194318c | 7 | * Copyright (C) 2001, 2004 MIPS Inc. |
1da177e4 LT |
8 | * |
9 | * This program is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License | |
11 | * as published by the Free Software Foundation; either version | |
12 | * 2 of the License, or (at your option) any later version. | |
13 | */ | |
1da177e4 LT |
14 | #include <linux/init.h> |
15 | #include <linux/kernel.h> | |
16 | #include <linux/ptrace.h> | |
631330f5 | 17 | #include <linux/smp.h> |
1da177e4 | 18 | #include <linux/stddef.h> |
f8ede0f7 | 19 | #include <linux/module.h> |
1da177e4 | 20 | |
5759906c | 21 | #include <asm/bugs.h> |
1da177e4 LT |
22 | #include <asm/cpu.h> |
23 | #include <asm/fpu.h> | |
24 | #include <asm/mipsregs.h> | |
25 | #include <asm/system.h> | |
654f57bf | 26 | #include <asm/watch.h> |
a074f0e8 | 27 | #include <asm/spram.h> |
1da177e4 LT |
28 | /* |
29 | * Not all of the MIPS CPUs have the "wait" instruction available. Moreover, | |
30 | * the implementation of the "wait" feature differs between CPU families. This | |
31 | * points to the function that implements CPU specific wait. | |
32 | * The wait instruction stops the pipeline and reduces the power consumption of | |
33 | * the CPU very much. | |
34 | */ | |
982f6ffe | 35 | void (*cpu_wait)(void); |
f8ede0f7 | 36 | EXPORT_SYMBOL(cpu_wait); |
1da177e4 LT |
37 | |
38 | static void r3081_wait(void) | |
39 | { | |
40 | unsigned long cfg = read_c0_conf(); | |
41 | write_c0_conf(cfg | R30XX_CONF_HALT); | |
42 | } | |
43 | ||
44 | static void r39xx_wait(void) | |
45 | { | |
60a6c377 AN |
46 | local_irq_disable(); |
47 | if (!need_resched()) | |
48 | write_c0_conf(read_c0_conf() | TX39_CONF_HALT); | |
49 | local_irq_enable(); | |
1da177e4 LT |
50 | } |
51 | ||
c65a5480 | 52 | extern void r4k_wait(void); |
60a6c377 AN |
53 | |
54 | /* | |
55 | * This variant is preferable as it allows testing need_resched and going to | |
56 | * sleep depending on the outcome atomically. Unfortunately the "It is | |
57 | * implementation-dependent whether the pipeline restarts when a non-enabled | |
58 | * interrupt is requested" restriction in the MIPS32/MIPS64 architecture makes | |
59 | * using this version a gamble. | |
60 | */ | |
8531a35e | 61 | void r4k_wait_irqoff(void) |
60a6c377 AN |
62 | { |
63 | local_irq_disable(); | |
64 | if (!need_resched()) | |
8531a35e KK |
65 | __asm__(" .set push \n" |
66 | " .set mips3 \n" | |
60a6c377 | 67 | " wait \n" |
8531a35e | 68 | " .set pop \n"); |
60a6c377 | 69 | local_irq_enable(); |
8531a35e KK |
70 | __asm__(" .globl __pastwait \n" |
71 | "__pastwait: \n"); | |
72 | return; | |
1da177e4 LT |
73 | } |
74 | ||
5a812999 RB |
75 | /* |
76 | * The RM7000 variant has to handle erratum 38. The workaround is to not | |
77 | * have any pending stores when the WAIT instruction is executed. | |
78 | */ | |
79 | static void rm7k_wait_irqoff(void) | |
80 | { | |
81 | local_irq_disable(); | |
82 | if (!need_resched()) | |
83 | __asm__( | |
84 | " .set push \n" | |
85 | " .set mips3 \n" | |
86 | " .set noat \n" | |
87 | " mfc0 $1, $12 \n" | |
88 | " sync \n" | |
89 | " mtc0 $1, $12 # stalls until W stage \n" | |
90 | " wait \n" | |
91 | " mtc0 $1, $12 # stalls until W stage \n" | |
92 | " .set pop \n"); | |
93 | local_irq_enable(); | |
94 | } | |
95 | ||
2882b0c6 ML |
96 | /* |
97 | * The Au1xxx wait is available only if using 32khz counter or | |
98 | * external timer source, but specifically not CP0 Counter. | |
99 | * alchemy/common/time.c may override cpu_wait! | |
100 | */ | |
494900af | 101 | static void au1k_wait(void) |
1da177e4 | 102 | { |
60a6c377 AN |
103 | __asm__(" .set mips3 \n" |
104 | " cache 0x14, 0(%0) \n" | |
105 | " cache 0x14, 32(%0) \n" | |
106 | " sync \n" | |
107 | " nop \n" | |
108 | " wait \n" | |
109 | " nop \n" | |
110 | " nop \n" | |
111 | " nop \n" | |
112 | " nop \n" | |
113 | " .set mips0 \n" | |
10f650db | 114 | : : "r" (au1k_wait)); |
1da177e4 LT |
115 | } |
116 | ||
982f6ffe | 117 | static int __initdata nowait; |
55d04dff | 118 | |
f49a747c | 119 | static int __init wait_disable(char *s) |
55d04dff RB |
120 | { |
121 | nowait = 1; | |
122 | ||
123 | return 1; | |
124 | } | |
125 | ||
126 | __setup("nowait", wait_disable); | |
127 | ||
c65a5480 | 128 | void __init check_wait(void) |
1da177e4 LT |
129 | { |
130 | struct cpuinfo_mips *c = ¤t_cpu_data; | |
131 | ||
55d04dff | 132 | if (nowait) { |
c2379230 | 133 | printk("Wait instruction disabled.\n"); |
55d04dff RB |
134 | return; |
135 | } | |
136 | ||
1da177e4 LT |
137 | switch (c->cputype) { |
138 | case CPU_R3081: | |
139 | case CPU_R3081E: | |
140 | cpu_wait = r3081_wait; | |
1da177e4 LT |
141 | break; |
142 | case CPU_TX3927: | |
143 | cpu_wait = r39xx_wait; | |
1da177e4 LT |
144 | break; |
145 | case CPU_R4200: | |
146 | /* case CPU_R4300: */ | |
147 | case CPU_R4600: | |
148 | case CPU_R4640: | |
149 | case CPU_R4650: | |
150 | case CPU_R4700: | |
151 | case CPU_R5000: | |
a644b277 | 152 | case CPU_R5500: |
1da177e4 | 153 | case CPU_NEVADA: |
1da177e4 LT |
154 | case CPU_4KC: |
155 | case CPU_4KEC: | |
156 | case CPU_4KSC: | |
157 | case CPU_5KC: | |
1da177e4 | 158 | case CPU_25KF: |
4b3e975e | 159 | case CPU_PR4450: |
1c0c13eb | 160 | case CPU_BCM3302: |
0de663ef MB |
161 | case CPU_BCM6338: |
162 | case CPU_BCM6348: | |
163 | case CPU_BCM6358: | |
0dd4781b | 164 | case CPU_CAVIUM_OCTEON: |
4b3e975e RB |
165 | cpu_wait = r4k_wait; |
166 | break; | |
167 | ||
5a812999 RB |
168 | case CPU_RM7000: |
169 | cpu_wait = rm7k_wait_irqoff; | |
170 | break; | |
171 | ||
4b3e975e | 172 | case CPU_24K: |
bbc7f22f | 173 | case CPU_34K: |
39b8d525 | 174 | case CPU_1004K: |
4b3e975e RB |
175 | cpu_wait = r4k_wait; |
176 | if (read_c0_config7() & MIPS_CONF7_WII) | |
177 | cpu_wait = r4k_wait_irqoff; | |
178 | break; | |
179 | ||
c620953c | 180 | case CPU_74K: |
1da177e4 | 181 | cpu_wait = r4k_wait; |
4b3e975e RB |
182 | if ((c->processor_id & 0xff) >= PRID_REV_ENCODE_332(2, 1, 0)) |
183 | cpu_wait = r4k_wait_irqoff; | |
1da177e4 | 184 | break; |
4b3e975e | 185 | |
60a6c377 AN |
186 | case CPU_TX49XX: |
187 | cpu_wait = r4k_wait_irqoff; | |
60a6c377 | 188 | break; |
270717a8 | 189 | case CPU_ALCHEMY: |
0c694de1 | 190 | cpu_wait = au1k_wait; |
1da177e4 | 191 | break; |
c8eae71d RB |
192 | case CPU_20KC: |
193 | /* | |
194 | * WAIT on Rev1.0 has E1, E2, E3 and E16. | |
195 | * WAIT on Rev2.0 and Rev3.0 has E16. | |
196 | * Rev3.1 WAIT is nop, why bother | |
197 | */ | |
198 | if ((c->processor_id & 0xff) <= 0x64) | |
199 | break; | |
200 | ||
50da469a RB |
201 | /* |
202 | * Another rev is incremeting c0_count at a reduced clock | |
203 | * rate while in WAIT mode. So we basically have the choice | |
204 | * between using the cp0 timer as clocksource or avoiding | |
205 | * the WAIT instruction. Until more details are known, | |
206 | * disable the use of WAIT for 20Kc entirely. | |
207 | cpu_wait = r4k_wait; | |
208 | */ | |
c8eae71d | 209 | break; |
441ee341 | 210 | case CPU_RM9000: |
c2379230 | 211 | if ((c->processor_id & 0x00ff) >= 0x40) |
441ee341 | 212 | cpu_wait = r4k_wait; |
441ee341 | 213 | break; |
1da177e4 | 214 | default: |
1da177e4 LT |
215 | break; |
216 | } | |
217 | } | |
218 | ||
9267a30d MSJ |
219 | static inline void check_errata(void) |
220 | { | |
221 | struct cpuinfo_mips *c = ¤t_cpu_data; | |
222 | ||
223 | switch (c->cputype) { | |
224 | case CPU_34K: | |
225 | /* | |
226 | * Erratum "RPS May Cause Incorrect Instruction Execution" | |
227 | * This code only handles VPE0, any SMP/SMTC/RTOS code | |
228 | * making use of VPE1 will be responsable for that VPE. | |
229 | */ | |
230 | if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2) | |
231 | write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS); | |
232 | break; | |
233 | default: | |
234 | break; | |
235 | } | |
236 | } | |
237 | ||
1da177e4 LT |
238 | void __init check_bugs32(void) |
239 | { | |
9267a30d | 240 | check_errata(); |
1da177e4 LT |
241 | } |
242 | ||
243 | /* | |
244 | * Probe whether cpu has config register by trying to play with | |
245 | * alternate cache bit and see whether it matters. | |
246 | * It's used by cpu_probe to distinguish between R3000A and R3081. | |
247 | */ | |
248 | static inline int cpu_has_confreg(void) | |
249 | { | |
250 | #ifdef CONFIG_CPU_R3000 | |
251 | extern unsigned long r3k_cache_size(unsigned long); | |
252 | unsigned long size1, size2; | |
253 | unsigned long cfg = read_c0_conf(); | |
254 | ||
255 | size1 = r3k_cache_size(ST0_ISC); | |
256 | write_c0_conf(cfg ^ R30XX_CONF_AC); | |
257 | size2 = r3k_cache_size(ST0_ISC); | |
258 | write_c0_conf(cfg); | |
259 | return size1 != size2; | |
260 | #else | |
261 | return 0; | |
262 | #endif | |
263 | } | |
264 | ||
265 | /* | |
266 | * Get the FPU Implementation/Revision. | |
267 | */ | |
268 | static inline unsigned long cpu_get_fpu_id(void) | |
269 | { | |
270 | unsigned long tmp, fpu_id; | |
271 | ||
272 | tmp = read_c0_status(); | |
273 | __enable_fpu(); | |
274 | fpu_id = read_32bit_cp1_register(CP1_REVISION); | |
275 | write_c0_status(tmp); | |
276 | return fpu_id; | |
277 | } | |
278 | ||
279 | /* | |
280 | * Check the CPU has an FPU the official way. | |
281 | */ | |
282 | static inline int __cpu_has_fpu(void) | |
283 | { | |
284 | return ((cpu_get_fpu_id() & 0xff00) != FPIR_IMP_NONE); | |
285 | } | |
286 | ||
91dfc423 GR |
287 | static inline void cpu_probe_vmbits(struct cpuinfo_mips *c) |
288 | { | |
289 | #ifdef __NEED_VMBITS_PROBE | |
5b7efa89 | 290 | write_c0_entryhi(0x3fffffffffffe000ULL); |
91dfc423 | 291 | back_to_back_c0_hazard(); |
5b7efa89 | 292 | c->vmbits = fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL); |
91dfc423 GR |
293 | #endif |
294 | } | |
295 | ||
02cf2119 | 296 | #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \ |
1da177e4 LT |
297 | | MIPS_CPU_COUNTER) |
298 | ||
cea7e2df | 299 | static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu) |
1da177e4 LT |
300 | { |
301 | switch (c->processor_id & 0xff00) { | |
302 | case PRID_IMP_R2000: | |
303 | c->cputype = CPU_R2000; | |
cea7e2df | 304 | __cpu_name[cpu] = "R2000"; |
1da177e4 | 305 | c->isa_level = MIPS_CPU_ISA_I; |
02cf2119 RB |
306 | c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE | |
307 | MIPS_CPU_NOFPUEX; | |
1da177e4 LT |
308 | if (__cpu_has_fpu()) |
309 | c->options |= MIPS_CPU_FPU; | |
310 | c->tlbsize = 64; | |
311 | break; | |
312 | case PRID_IMP_R3000: | |
cea7e2df RB |
313 | if ((c->processor_id & 0xff) == PRID_REV_R3000A) { |
314 | if (cpu_has_confreg()) { | |
1da177e4 | 315 | c->cputype = CPU_R3081E; |
cea7e2df RB |
316 | __cpu_name[cpu] = "R3081"; |
317 | } else { | |
1da177e4 | 318 | c->cputype = CPU_R3000A; |
cea7e2df RB |
319 | __cpu_name[cpu] = "R3000A"; |
320 | } | |
321 | break; | |
322 | } else { | |
1da177e4 | 323 | c->cputype = CPU_R3000; |
cea7e2df RB |
324 | __cpu_name[cpu] = "R3000"; |
325 | } | |
1da177e4 | 326 | c->isa_level = MIPS_CPU_ISA_I; |
02cf2119 RB |
327 | c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE | |
328 | MIPS_CPU_NOFPUEX; | |
1da177e4 LT |
329 | if (__cpu_has_fpu()) |
330 | c->options |= MIPS_CPU_FPU; | |
331 | c->tlbsize = 64; | |
332 | break; | |
333 | case PRID_IMP_R4000: | |
334 | if (read_c0_config() & CONF_SC) { | |
cea7e2df | 335 | if ((c->processor_id & 0xff) >= PRID_REV_R4400) { |
1da177e4 | 336 | c->cputype = CPU_R4400PC; |
cea7e2df RB |
337 | __cpu_name[cpu] = "R4400PC"; |
338 | } else { | |
1da177e4 | 339 | c->cputype = CPU_R4000PC; |
cea7e2df RB |
340 | __cpu_name[cpu] = "R4000PC"; |
341 | } | |
1da177e4 | 342 | } else { |
cea7e2df | 343 | if ((c->processor_id & 0xff) >= PRID_REV_R4400) { |
1da177e4 | 344 | c->cputype = CPU_R4400SC; |
cea7e2df RB |
345 | __cpu_name[cpu] = "R4400SC"; |
346 | } else { | |
1da177e4 | 347 | c->cputype = CPU_R4000SC; |
cea7e2df RB |
348 | __cpu_name[cpu] = "R4000SC"; |
349 | } | |
1da177e4 LT |
350 | } |
351 | ||
352 | c->isa_level = MIPS_CPU_ISA_III; | |
353 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | | |
354 | MIPS_CPU_WATCH | MIPS_CPU_VCE | | |
355 | MIPS_CPU_LLSC; | |
356 | c->tlbsize = 48; | |
357 | break; | |
358 | case PRID_IMP_VR41XX: | |
359 | switch (c->processor_id & 0xf0) { | |
1da177e4 LT |
360 | case PRID_REV_VR4111: |
361 | c->cputype = CPU_VR4111; | |
cea7e2df | 362 | __cpu_name[cpu] = "NEC VR4111"; |
1da177e4 | 363 | break; |
1da177e4 LT |
364 | case PRID_REV_VR4121: |
365 | c->cputype = CPU_VR4121; | |
cea7e2df | 366 | __cpu_name[cpu] = "NEC VR4121"; |
1da177e4 LT |
367 | break; |
368 | case PRID_REV_VR4122: | |
cea7e2df | 369 | if ((c->processor_id & 0xf) < 0x3) { |
1da177e4 | 370 | c->cputype = CPU_VR4122; |
cea7e2df RB |
371 | __cpu_name[cpu] = "NEC VR4122"; |
372 | } else { | |
1da177e4 | 373 | c->cputype = CPU_VR4181A; |
cea7e2df RB |
374 | __cpu_name[cpu] = "NEC VR4181A"; |
375 | } | |
1da177e4 LT |
376 | break; |
377 | case PRID_REV_VR4130: | |
cea7e2df | 378 | if ((c->processor_id & 0xf) < 0x4) { |
1da177e4 | 379 | c->cputype = CPU_VR4131; |
cea7e2df RB |
380 | __cpu_name[cpu] = "NEC VR4131"; |
381 | } else { | |
1da177e4 | 382 | c->cputype = CPU_VR4133; |
cea7e2df RB |
383 | __cpu_name[cpu] = "NEC VR4133"; |
384 | } | |
1da177e4 LT |
385 | break; |
386 | default: | |
387 | printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n"); | |
388 | c->cputype = CPU_VR41XX; | |
cea7e2df | 389 | __cpu_name[cpu] = "NEC Vr41xx"; |
1da177e4 LT |
390 | break; |
391 | } | |
392 | c->isa_level = MIPS_CPU_ISA_III; | |
393 | c->options = R4K_OPTS; | |
394 | c->tlbsize = 32; | |
395 | break; | |
396 | case PRID_IMP_R4300: | |
397 | c->cputype = CPU_R4300; | |
cea7e2df | 398 | __cpu_name[cpu] = "R4300"; |
1da177e4 LT |
399 | c->isa_level = MIPS_CPU_ISA_III; |
400 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | | |
401 | MIPS_CPU_LLSC; | |
402 | c->tlbsize = 32; | |
403 | break; | |
404 | case PRID_IMP_R4600: | |
405 | c->cputype = CPU_R4600; | |
cea7e2df | 406 | __cpu_name[cpu] = "R4600"; |
1da177e4 | 407 | c->isa_level = MIPS_CPU_ISA_III; |
075e7502 TS |
408 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | |
409 | MIPS_CPU_LLSC; | |
1da177e4 LT |
410 | c->tlbsize = 48; |
411 | break; | |
412 | #if 0 | |
413 | case PRID_IMP_R4650: | |
414 | /* | |
415 | * This processor doesn't have an MMU, so it's not | |
416 | * "real easy" to run Linux on it. It is left purely | |
417 | * for documentation. Commented out because it shares | |
418 | * it's c0_prid id number with the TX3900. | |
419 | */ | |
a3dddd56 | 420 | c->cputype = CPU_R4650; |
cea7e2df | 421 | __cpu_name[cpu] = "R4650"; |
1da177e4 LT |
422 | c->isa_level = MIPS_CPU_ISA_III; |
423 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC; | |
424 | c->tlbsize = 48; | |
425 | break; | |
426 | #endif | |
427 | case PRID_IMP_TX39: | |
428 | c->isa_level = MIPS_CPU_ISA_I; | |
02cf2119 | 429 | c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE; |
1da177e4 LT |
430 | |
431 | if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) { | |
432 | c->cputype = CPU_TX3927; | |
cea7e2df | 433 | __cpu_name[cpu] = "TX3927"; |
1da177e4 LT |
434 | c->tlbsize = 64; |
435 | } else { | |
436 | switch (c->processor_id & 0xff) { | |
437 | case PRID_REV_TX3912: | |
438 | c->cputype = CPU_TX3912; | |
cea7e2df | 439 | __cpu_name[cpu] = "TX3912"; |
1da177e4 LT |
440 | c->tlbsize = 32; |
441 | break; | |
442 | case PRID_REV_TX3922: | |
443 | c->cputype = CPU_TX3922; | |
cea7e2df | 444 | __cpu_name[cpu] = "TX3922"; |
1da177e4 LT |
445 | c->tlbsize = 64; |
446 | break; | |
1da177e4 LT |
447 | } |
448 | } | |
449 | break; | |
450 | case PRID_IMP_R4700: | |
451 | c->cputype = CPU_R4700; | |
cea7e2df | 452 | __cpu_name[cpu] = "R4700"; |
1da177e4 LT |
453 | c->isa_level = MIPS_CPU_ISA_III; |
454 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | | |
455 | MIPS_CPU_LLSC; | |
456 | c->tlbsize = 48; | |
457 | break; | |
458 | case PRID_IMP_TX49: | |
459 | c->cputype = CPU_TX49XX; | |
cea7e2df | 460 | __cpu_name[cpu] = "R49XX"; |
1da177e4 LT |
461 | c->isa_level = MIPS_CPU_ISA_III; |
462 | c->options = R4K_OPTS | MIPS_CPU_LLSC; | |
463 | if (!(c->processor_id & 0x08)) | |
464 | c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR; | |
465 | c->tlbsize = 48; | |
466 | break; | |
467 | case PRID_IMP_R5000: | |
468 | c->cputype = CPU_R5000; | |
cea7e2df | 469 | __cpu_name[cpu] = "R5000"; |
1da177e4 LT |
470 | c->isa_level = MIPS_CPU_ISA_IV; |
471 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | | |
472 | MIPS_CPU_LLSC; | |
473 | c->tlbsize = 48; | |
474 | break; | |
475 | case PRID_IMP_R5432: | |
476 | c->cputype = CPU_R5432; | |
cea7e2df | 477 | __cpu_name[cpu] = "R5432"; |
1da177e4 LT |
478 | c->isa_level = MIPS_CPU_ISA_IV; |
479 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | | |
480 | MIPS_CPU_WATCH | MIPS_CPU_LLSC; | |
481 | c->tlbsize = 48; | |
482 | break; | |
483 | case PRID_IMP_R5500: | |
484 | c->cputype = CPU_R5500; | |
cea7e2df | 485 | __cpu_name[cpu] = "R5500"; |
1da177e4 LT |
486 | c->isa_level = MIPS_CPU_ISA_IV; |
487 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | | |
488 | MIPS_CPU_WATCH | MIPS_CPU_LLSC; | |
489 | c->tlbsize = 48; | |
490 | break; | |
491 | case PRID_IMP_NEVADA: | |
492 | c->cputype = CPU_NEVADA; | |
cea7e2df | 493 | __cpu_name[cpu] = "Nevada"; |
1da177e4 LT |
494 | c->isa_level = MIPS_CPU_ISA_IV; |
495 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | | |
496 | MIPS_CPU_DIVEC | MIPS_CPU_LLSC; | |
497 | c->tlbsize = 48; | |
498 | break; | |
499 | case PRID_IMP_R6000: | |
500 | c->cputype = CPU_R6000; | |
cea7e2df | 501 | __cpu_name[cpu] = "R6000"; |
1da177e4 LT |
502 | c->isa_level = MIPS_CPU_ISA_II; |
503 | c->options = MIPS_CPU_TLB | MIPS_CPU_FPU | | |
504 | MIPS_CPU_LLSC; | |
505 | c->tlbsize = 32; | |
506 | break; | |
507 | case PRID_IMP_R6000A: | |
508 | c->cputype = CPU_R6000A; | |
cea7e2df | 509 | __cpu_name[cpu] = "R6000A"; |
1da177e4 LT |
510 | c->isa_level = MIPS_CPU_ISA_II; |
511 | c->options = MIPS_CPU_TLB | MIPS_CPU_FPU | | |
512 | MIPS_CPU_LLSC; | |
513 | c->tlbsize = 32; | |
514 | break; | |
515 | case PRID_IMP_RM7000: | |
516 | c->cputype = CPU_RM7000; | |
cea7e2df | 517 | __cpu_name[cpu] = "RM7000"; |
1da177e4 LT |
518 | c->isa_level = MIPS_CPU_ISA_IV; |
519 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | | |
520 | MIPS_CPU_LLSC; | |
521 | /* | |
522 | * Undocumented RM7000: Bit 29 in the info register of | |
523 | * the RM7000 v2.0 indicates if the TLB has 48 or 64 | |
524 | * entries. | |
525 | * | |
526 | * 29 1 => 64 entry JTLB | |
527 | * 0 => 48 entry JTLB | |
528 | */ | |
529 | c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48; | |
530 | break; | |
531 | case PRID_IMP_RM9000: | |
532 | c->cputype = CPU_RM9000; | |
cea7e2df | 533 | __cpu_name[cpu] = "RM9000"; |
1da177e4 LT |
534 | c->isa_level = MIPS_CPU_ISA_IV; |
535 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | | |
536 | MIPS_CPU_LLSC; | |
537 | /* | |
538 | * Bit 29 in the info register of the RM9000 | |
539 | * indicates if the TLB has 48 or 64 entries. | |
540 | * | |
541 | * 29 1 => 64 entry JTLB | |
542 | * 0 => 48 entry JTLB | |
543 | */ | |
544 | c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48; | |
545 | break; | |
546 | case PRID_IMP_R8000: | |
547 | c->cputype = CPU_R8000; | |
cea7e2df | 548 | __cpu_name[cpu] = "RM8000"; |
1da177e4 LT |
549 | c->isa_level = MIPS_CPU_ISA_IV; |
550 | c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX | | |
551 | MIPS_CPU_FPU | MIPS_CPU_32FPR | | |
552 | MIPS_CPU_LLSC; | |
553 | c->tlbsize = 384; /* has weird TLB: 3-way x 128 */ | |
554 | break; | |
555 | case PRID_IMP_R10000: | |
556 | c->cputype = CPU_R10000; | |
cea7e2df | 557 | __cpu_name[cpu] = "R10000"; |
1da177e4 | 558 | c->isa_level = MIPS_CPU_ISA_IV; |
8b36612a | 559 | c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | |
1da177e4 LT |
560 | MIPS_CPU_FPU | MIPS_CPU_32FPR | |
561 | MIPS_CPU_COUNTER | MIPS_CPU_WATCH | | |
562 | MIPS_CPU_LLSC; | |
563 | c->tlbsize = 64; | |
564 | break; | |
565 | case PRID_IMP_R12000: | |
566 | c->cputype = CPU_R12000; | |
cea7e2df | 567 | __cpu_name[cpu] = "R12000"; |
1da177e4 | 568 | c->isa_level = MIPS_CPU_ISA_IV; |
8b36612a | 569 | c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | |
1da177e4 LT |
570 | MIPS_CPU_FPU | MIPS_CPU_32FPR | |
571 | MIPS_CPU_COUNTER | MIPS_CPU_WATCH | | |
572 | MIPS_CPU_LLSC; | |
573 | c->tlbsize = 64; | |
574 | break; | |
44d921b2 K |
575 | case PRID_IMP_R14000: |
576 | c->cputype = CPU_R14000; | |
cea7e2df | 577 | __cpu_name[cpu] = "R14000"; |
44d921b2 K |
578 | c->isa_level = MIPS_CPU_ISA_IV; |
579 | c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | | |
580 | MIPS_CPU_FPU | MIPS_CPU_32FPR | | |
581 | MIPS_CPU_COUNTER | MIPS_CPU_WATCH | | |
582 | MIPS_CPU_LLSC; | |
583 | c->tlbsize = 64; | |
584 | break; | |
2a21c730 FZ |
585 | case PRID_IMP_LOONGSON2: |
586 | c->cputype = CPU_LOONGSON2; | |
cea7e2df | 587 | __cpu_name[cpu] = "ICT Loongson-2"; |
2a21c730 FZ |
588 | c->isa_level = MIPS_CPU_ISA_III; |
589 | c->options = R4K_OPTS | | |
590 | MIPS_CPU_FPU | MIPS_CPU_LLSC | | |
591 | MIPS_CPU_32FPR; | |
592 | c->tlbsize = 64; | |
593 | break; | |
1da177e4 LT |
594 | } |
595 | } | |
596 | ||
234fcd14 | 597 | static char unknown_isa[] __cpuinitdata = KERN_ERR \ |
b4672d37 RB |
598 | "Unsupported ISA type, c0.config0: %d."; |
599 | ||
4194318c | 600 | static inline unsigned int decode_config0(struct cpuinfo_mips *c) |
1da177e4 | 601 | { |
4194318c RB |
602 | unsigned int config0; |
603 | int isa; | |
1da177e4 | 604 | |
4194318c RB |
605 | config0 = read_c0_config(); |
606 | ||
607 | if (((config0 & MIPS_CONF_MT) >> 7) == 1) | |
02cf2119 | 608 | c->options |= MIPS_CPU_TLB; |
4194318c RB |
609 | isa = (config0 & MIPS_CONF_AT) >> 13; |
610 | switch (isa) { | |
611 | case 0: | |
3a01c49a | 612 | switch ((config0 & MIPS_CONF_AR) >> 10) { |
b4672d37 RB |
613 | case 0: |
614 | c->isa_level = MIPS_CPU_ISA_M32R1; | |
615 | break; | |
616 | case 1: | |
617 | c->isa_level = MIPS_CPU_ISA_M32R2; | |
618 | break; | |
619 | default: | |
620 | goto unknown; | |
621 | } | |
4194318c RB |
622 | break; |
623 | case 2: | |
3a01c49a | 624 | switch ((config0 & MIPS_CONF_AR) >> 10) { |
b4672d37 RB |
625 | case 0: |
626 | c->isa_level = MIPS_CPU_ISA_M64R1; | |
627 | break; | |
628 | case 1: | |
629 | c->isa_level = MIPS_CPU_ISA_M64R2; | |
630 | break; | |
631 | default: | |
632 | goto unknown; | |
633 | } | |
4194318c RB |
634 | break; |
635 | default: | |
b4672d37 | 636 | goto unknown; |
4194318c RB |
637 | } |
638 | ||
639 | return config0 & MIPS_CONF_M; | |
b4672d37 RB |
640 | |
641 | unknown: | |
642 | panic(unknown_isa, config0); | |
4194318c RB |
643 | } |
644 | ||
645 | static inline unsigned int decode_config1(struct cpuinfo_mips *c) | |
646 | { | |
647 | unsigned int config1; | |
1da177e4 | 648 | |
1da177e4 | 649 | config1 = read_c0_config1(); |
4194318c RB |
650 | |
651 | if (config1 & MIPS_CONF1_MD) | |
652 | c->ases |= MIPS_ASE_MDMX; | |
653 | if (config1 & MIPS_CONF1_WR) | |
1da177e4 | 654 | c->options |= MIPS_CPU_WATCH; |
4194318c RB |
655 | if (config1 & MIPS_CONF1_CA) |
656 | c->ases |= MIPS_ASE_MIPS16; | |
657 | if (config1 & MIPS_CONF1_EP) | |
1da177e4 | 658 | c->options |= MIPS_CPU_EJTAG; |
4194318c | 659 | if (config1 & MIPS_CONF1_FP) { |
1da177e4 LT |
660 | c->options |= MIPS_CPU_FPU; |
661 | c->options |= MIPS_CPU_32FPR; | |
662 | } | |
4194318c RB |
663 | if (cpu_has_tlb) |
664 | c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1; | |
665 | ||
666 | return config1 & MIPS_CONF_M; | |
667 | } | |
668 | ||
669 | static inline unsigned int decode_config2(struct cpuinfo_mips *c) | |
670 | { | |
671 | unsigned int config2; | |
672 | ||
673 | config2 = read_c0_config2(); | |
674 | ||
675 | if (config2 & MIPS_CONF2_SL) | |
676 | c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT; | |
677 | ||
678 | return config2 & MIPS_CONF_M; | |
679 | } | |
680 | ||
681 | static inline unsigned int decode_config3(struct cpuinfo_mips *c) | |
682 | { | |
683 | unsigned int config3; | |
684 | ||
685 | config3 = read_c0_config3(); | |
686 | ||
687 | if (config3 & MIPS_CONF3_SM) | |
688 | c->ases |= MIPS_ASE_SMARTMIPS; | |
e50c0a8f RB |
689 | if (config3 & MIPS_CONF3_DSP) |
690 | c->ases |= MIPS_ASE_DSP; | |
8f40611d RB |
691 | if (config3 & MIPS_CONF3_VINT) |
692 | c->options |= MIPS_CPU_VINT; | |
693 | if (config3 & MIPS_CONF3_VEIC) | |
694 | c->options |= MIPS_CPU_VEIC; | |
695 | if (config3 & MIPS_CONF3_MT) | |
e0daad44 | 696 | c->ases |= MIPS_ASE_MIPSMT; |
a3692020 RB |
697 | if (config3 & MIPS_CONF3_ULRI) |
698 | c->options |= MIPS_CPU_ULRI; | |
4194318c RB |
699 | |
700 | return config3 & MIPS_CONF_M; | |
701 | } | |
702 | ||
1b362e3e DD |
703 | static inline unsigned int decode_config4(struct cpuinfo_mips *c) |
704 | { | |
705 | unsigned int config4; | |
706 | ||
707 | config4 = read_c0_config4(); | |
708 | ||
709 | if ((config4 & MIPS_CONF4_MMUEXTDEF) == MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT | |
710 | && cpu_has_tlb) | |
711 | c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40; | |
712 | ||
713 | return config4 & MIPS_CONF_M; | |
714 | } | |
715 | ||
234fcd14 | 716 | static void __cpuinit decode_configs(struct cpuinfo_mips *c) |
4194318c | 717 | { |
558ce124 RB |
718 | int ok; |
719 | ||
4194318c | 720 | /* MIPS32 or MIPS64 compliant CPU. */ |
02cf2119 RB |
721 | c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER | |
722 | MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK; | |
4194318c | 723 | |
1da177e4 LT |
724 | c->scache.flags = MIPS_CACHE_NOT_PRESENT; |
725 | ||
558ce124 RB |
726 | ok = decode_config0(c); /* Read Config registers. */ |
727 | BUG_ON(!ok); /* Arch spec violation! */ | |
728 | if (ok) | |
729 | ok = decode_config1(c); | |
730 | if (ok) | |
731 | ok = decode_config2(c); | |
732 | if (ok) | |
733 | ok = decode_config3(c); | |
1b362e3e DD |
734 | if (ok) |
735 | ok = decode_config4(c); | |
558ce124 RB |
736 | |
737 | mips_probe_watch_registers(c); | |
1da177e4 LT |
738 | } |
739 | ||
cea7e2df | 740 | static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu) |
1da177e4 | 741 | { |
4194318c | 742 | decode_configs(c); |
1da177e4 LT |
743 | switch (c->processor_id & 0xff00) { |
744 | case PRID_IMP_4KC: | |
745 | c->cputype = CPU_4KC; | |
cea7e2df | 746 | __cpu_name[cpu] = "MIPS 4Kc"; |
1da177e4 LT |
747 | break; |
748 | case PRID_IMP_4KEC: | |
2b07bd02 RB |
749 | case PRID_IMP_4KECR2: |
750 | c->cputype = CPU_4KEC; | |
cea7e2df | 751 | __cpu_name[cpu] = "MIPS 4KEc"; |
2b07bd02 | 752 | break; |
1da177e4 | 753 | case PRID_IMP_4KSC: |
8afcb5d8 | 754 | case PRID_IMP_4KSD: |
1da177e4 | 755 | c->cputype = CPU_4KSC; |
cea7e2df | 756 | __cpu_name[cpu] = "MIPS 4KSc"; |
1da177e4 LT |
757 | break; |
758 | case PRID_IMP_5KC: | |
759 | c->cputype = CPU_5KC; | |
cea7e2df | 760 | __cpu_name[cpu] = "MIPS 5Kc"; |
1da177e4 LT |
761 | break; |
762 | case PRID_IMP_20KC: | |
763 | c->cputype = CPU_20KC; | |
cea7e2df | 764 | __cpu_name[cpu] = "MIPS 20Kc"; |
1da177e4 LT |
765 | break; |
766 | case PRID_IMP_24K: | |
e50c0a8f | 767 | case PRID_IMP_24KE: |
1da177e4 | 768 | c->cputype = CPU_24K; |
cea7e2df | 769 | __cpu_name[cpu] = "MIPS 24Kc"; |
1da177e4 LT |
770 | break; |
771 | case PRID_IMP_25KF: | |
772 | c->cputype = CPU_25KF; | |
cea7e2df | 773 | __cpu_name[cpu] = "MIPS 25Kc"; |
1da177e4 | 774 | break; |
bbc7f22f RB |
775 | case PRID_IMP_34K: |
776 | c->cputype = CPU_34K; | |
cea7e2df | 777 | __cpu_name[cpu] = "MIPS 34Kc"; |
bbc7f22f | 778 | break; |
c620953c CD |
779 | case PRID_IMP_74K: |
780 | c->cputype = CPU_74K; | |
cea7e2df | 781 | __cpu_name[cpu] = "MIPS 74Kc"; |
c620953c | 782 | break; |
39b8d525 RB |
783 | case PRID_IMP_1004K: |
784 | c->cputype = CPU_1004K; | |
cea7e2df | 785 | __cpu_name[cpu] = "MIPS 1004Kc"; |
39b8d525 | 786 | break; |
1da177e4 | 787 | } |
0b6d497f CD |
788 | |
789 | spram_config(); | |
1da177e4 LT |
790 | } |
791 | ||
cea7e2df | 792 | static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu) |
1da177e4 | 793 | { |
4194318c | 794 | decode_configs(c); |
1da177e4 LT |
795 | switch (c->processor_id & 0xff00) { |
796 | case PRID_IMP_AU1_REV1: | |
797 | case PRID_IMP_AU1_REV2: | |
270717a8 | 798 | c->cputype = CPU_ALCHEMY; |
1da177e4 LT |
799 | switch ((c->processor_id >> 24) & 0xff) { |
800 | case 0: | |
cea7e2df | 801 | __cpu_name[cpu] = "Au1000"; |
1da177e4 LT |
802 | break; |
803 | case 1: | |
cea7e2df | 804 | __cpu_name[cpu] = "Au1500"; |
1da177e4 LT |
805 | break; |
806 | case 2: | |
cea7e2df | 807 | __cpu_name[cpu] = "Au1100"; |
1da177e4 LT |
808 | break; |
809 | case 3: | |
cea7e2df | 810 | __cpu_name[cpu] = "Au1550"; |
1da177e4 | 811 | break; |
e3ad1c23 | 812 | case 4: |
cea7e2df | 813 | __cpu_name[cpu] = "Au1200"; |
270717a8 | 814 | if ((c->processor_id & 0xff) == 2) |
cea7e2df | 815 | __cpu_name[cpu] = "Au1250"; |
237cfee1 ML |
816 | break; |
817 | case 5: | |
cea7e2df | 818 | __cpu_name[cpu] = "Au1210"; |
e3ad1c23 | 819 | break; |
1da177e4 | 820 | default: |
270717a8 | 821 | __cpu_name[cpu] = "Au1xxx"; |
1da177e4 LT |
822 | break; |
823 | } | |
1da177e4 LT |
824 | break; |
825 | } | |
826 | } | |
827 | ||
cea7e2df | 828 | static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu) |
1da177e4 | 829 | { |
4194318c | 830 | decode_configs(c); |
02cf2119 | 831 | |
1da177e4 LT |
832 | switch (c->processor_id & 0xff00) { |
833 | case PRID_IMP_SB1: | |
834 | c->cputype = CPU_SB1; | |
cea7e2df | 835 | __cpu_name[cpu] = "SiByte SB1"; |
1da177e4 | 836 | /* FPU in pass1 is known to have issues. */ |
aa32374a | 837 | if ((c->processor_id & 0xff) < 0x02) |
010b853b | 838 | c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR); |
1da177e4 | 839 | break; |
93ce2f52 AI |
840 | case PRID_IMP_SB1A: |
841 | c->cputype = CPU_SB1A; | |
cea7e2df | 842 | __cpu_name[cpu] = "SiByte SB1A"; |
93ce2f52 | 843 | break; |
1da177e4 LT |
844 | } |
845 | } | |
846 | ||
cea7e2df | 847 | static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu) |
1da177e4 | 848 | { |
4194318c | 849 | decode_configs(c); |
1da177e4 LT |
850 | switch (c->processor_id & 0xff00) { |
851 | case PRID_IMP_SR71000: | |
852 | c->cputype = CPU_SR71000; | |
cea7e2df | 853 | __cpu_name[cpu] = "Sandcraft SR71000"; |
1da177e4 LT |
854 | c->scache.ways = 8; |
855 | c->tlbsize = 64; | |
856 | break; | |
857 | } | |
858 | } | |
859 | ||
cea7e2df | 860 | static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu) |
bdf21b18 PP |
861 | { |
862 | decode_configs(c); | |
863 | switch (c->processor_id & 0xff00) { | |
864 | case PRID_IMP_PR4450: | |
865 | c->cputype = CPU_PR4450; | |
cea7e2df | 866 | __cpu_name[cpu] = "Philips PR4450"; |
e7958bb9 | 867 | c->isa_level = MIPS_CPU_ISA_M32R1; |
bdf21b18 | 868 | break; |
bdf21b18 PP |
869 | } |
870 | } | |
871 | ||
cea7e2df | 872 | static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu) |
1c0c13eb AJ |
873 | { |
874 | decode_configs(c); | |
875 | switch (c->processor_id & 0xff00) { | |
876 | case PRID_IMP_BCM3302: | |
0de663ef | 877 | /* same as PRID_IMP_BCM6338 */ |
1c0c13eb | 878 | c->cputype = CPU_BCM3302; |
cea7e2df | 879 | __cpu_name[cpu] = "Broadcom BCM3302"; |
1c0c13eb AJ |
880 | break; |
881 | case PRID_IMP_BCM4710: | |
882 | c->cputype = CPU_BCM4710; | |
cea7e2df | 883 | __cpu_name[cpu] = "Broadcom BCM4710"; |
1c0c13eb | 884 | break; |
0de663ef MB |
885 | case PRID_IMP_BCM6345: |
886 | c->cputype = CPU_BCM6345; | |
887 | __cpu_name[cpu] = "Broadcom BCM6345"; | |
888 | break; | |
889 | case PRID_IMP_BCM6348: | |
890 | c->cputype = CPU_BCM6348; | |
891 | __cpu_name[cpu] = "Broadcom BCM6348"; | |
892 | break; | |
893 | case PRID_IMP_BCM4350: | |
894 | switch (c->processor_id & 0xf0) { | |
895 | case PRID_REV_BCM6358: | |
896 | c->cputype = CPU_BCM6358; | |
897 | __cpu_name[cpu] = "Broadcom BCM6358"; | |
898 | break; | |
899 | default: | |
900 | c->cputype = CPU_UNKNOWN; | |
901 | break; | |
902 | } | |
903 | break; | |
1c0c13eb AJ |
904 | } |
905 | } | |
906 | ||
0dd4781b DD |
907 | static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu) |
908 | { | |
909 | decode_configs(c); | |
910 | switch (c->processor_id & 0xff00) { | |
911 | case PRID_IMP_CAVIUM_CN38XX: | |
912 | case PRID_IMP_CAVIUM_CN31XX: | |
913 | case PRID_IMP_CAVIUM_CN30XX: | |
914 | case PRID_IMP_CAVIUM_CN58XX: | |
915 | case PRID_IMP_CAVIUM_CN56XX: | |
916 | case PRID_IMP_CAVIUM_CN50XX: | |
917 | case PRID_IMP_CAVIUM_CN52XX: | |
918 | c->cputype = CPU_CAVIUM_OCTEON; | |
919 | __cpu_name[cpu] = "Cavium Octeon"; | |
368bf8ef DD |
920 | if (cpu == 0) |
921 | __elf_platform = "octeon"; | |
0dd4781b DD |
922 | break; |
923 | default: | |
924 | printk(KERN_INFO "Unknown Octeon chip!\n"); | |
925 | c->cputype = CPU_UNKNOWN; | |
926 | break; | |
927 | } | |
928 | } | |
929 | ||
9966db25 | 930 | const char *__cpu_name[NR_CPUS]; |
874fd3b5 | 931 | const char *__elf_platform; |
9966db25 | 932 | |
234fcd14 | 933 | __cpuinit void cpu_probe(void) |
1da177e4 LT |
934 | { |
935 | struct cpuinfo_mips *c = ¤t_cpu_data; | |
9966db25 | 936 | unsigned int cpu = smp_processor_id(); |
1da177e4 LT |
937 | |
938 | c->processor_id = PRID_IMP_UNKNOWN; | |
939 | c->fpu_id = FPIR_IMP_NONE; | |
940 | c->cputype = CPU_UNKNOWN; | |
941 | ||
942 | c->processor_id = read_c0_prid(); | |
943 | switch (c->processor_id & 0xff0000) { | |
944 | case PRID_COMP_LEGACY: | |
cea7e2df | 945 | cpu_probe_legacy(c, cpu); |
1da177e4 LT |
946 | break; |
947 | case PRID_COMP_MIPS: | |
cea7e2df | 948 | cpu_probe_mips(c, cpu); |
1da177e4 LT |
949 | break; |
950 | case PRID_COMP_ALCHEMY: | |
cea7e2df | 951 | cpu_probe_alchemy(c, cpu); |
1da177e4 LT |
952 | break; |
953 | case PRID_COMP_SIBYTE: | |
cea7e2df | 954 | cpu_probe_sibyte(c, cpu); |
1da177e4 | 955 | break; |
1c0c13eb | 956 | case PRID_COMP_BROADCOM: |
cea7e2df | 957 | cpu_probe_broadcom(c, cpu); |
1c0c13eb | 958 | break; |
1da177e4 | 959 | case PRID_COMP_SANDCRAFT: |
cea7e2df | 960 | cpu_probe_sandcraft(c, cpu); |
1da177e4 | 961 | break; |
a92b0588 | 962 | case PRID_COMP_NXP: |
cea7e2df | 963 | cpu_probe_nxp(c, cpu); |
a3dddd56 | 964 | break; |
0dd4781b DD |
965 | case PRID_COMP_CAVIUM: |
966 | cpu_probe_cavium(c, cpu); | |
967 | break; | |
1da177e4 | 968 | } |
dec8b1ca | 969 | |
cea7e2df RB |
970 | BUG_ON(!__cpu_name[cpu]); |
971 | BUG_ON(c->cputype == CPU_UNKNOWN); | |
972 | ||
dec8b1ca FBH |
973 | /* |
974 | * Platform code can force the cpu type to optimize code | |
975 | * generation. In that case be sure the cpu type is correctly | |
976 | * manually setup otherwise it could trigger some nasty bugs. | |
977 | */ | |
978 | BUG_ON(current_cpu_type() != c->cputype); | |
979 | ||
4194318c | 980 | if (c->options & MIPS_CPU_FPU) { |
1da177e4 | 981 | c->fpu_id = cpu_get_fpu_id(); |
4194318c | 982 | |
e7958bb9 | 983 | if (c->isa_level == MIPS_CPU_ISA_M32R1 || |
b4672d37 RB |
984 | c->isa_level == MIPS_CPU_ISA_M32R2 || |
985 | c->isa_level == MIPS_CPU_ISA_M64R1 || | |
986 | c->isa_level == MIPS_CPU_ISA_M64R2) { | |
4194318c RB |
987 | if (c->fpu_id & MIPS_FPIR_3D) |
988 | c->ases |= MIPS_ASE_MIPS3D; | |
989 | } | |
990 | } | |
9966db25 | 991 | |
f6771dbb RB |
992 | if (cpu_has_mips_r2) |
993 | c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1; | |
994 | else | |
995 | c->srsets = 1; | |
91dfc423 GR |
996 | |
997 | cpu_probe_vmbits(c); | |
1da177e4 LT |
998 | } |
999 | ||
234fcd14 | 1000 | __cpuinit void cpu_report(void) |
1da177e4 LT |
1001 | { |
1002 | struct cpuinfo_mips *c = ¤t_cpu_data; | |
1003 | ||
9966db25 RB |
1004 | printk(KERN_INFO "CPU revision is: %08x (%s)\n", |
1005 | c->processor_id, cpu_name_string()); | |
1da177e4 | 1006 | if (c->options & MIPS_CPU_FPU) |
9966db25 | 1007 | printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id); |
1da177e4 | 1008 | } |