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MIPS: Add guest CP0 accessors
[mirror_ubuntu-eoan-kernel.git] / arch / mips / kernel / cpu-probe.c
CommitLineData
1da177e4
LT		 1/*
2 * Processor capabilities determination functions.
3 *
4 * Copyright (C) xxxx the Anonymous
010b853b 5 * Copyright (C) 1994 - 2006 Ralf Baechle
4194318c 6 * Copyright (C) 2003, 2004 Maciej W. Rozycki
70342287 7 * Copyright (C) 2001, 2004, 2011, 2012 MIPS Technologies, Inc.
1da177e4
LT		 8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
13 */
1da177e4
LT		 14#include <linux/init.h>
15#include <linux/kernel.h>
16#include <linux/ptrace.h>
631330f5 17#include <linux/smp.h>
1da177e4 18#include <linux/stddef.h>
73bc256d 19#include <linux/export.h>
1da177e4 20
5759906c 21#include <asm/bugs.h>
1da177e4 22#include <asm/cpu.h>
f6843626 23#include <asm/cpu-features.h>
69f24d17 24#include <asm/cpu-type.h>
1da177e4
LT		 25#include <asm/fpu.h>
26#include <asm/mipsregs.h>
30ee615b 27#include <asm/mipsmtregs.h>
a5e9a69e 28#include <asm/msa.h>
654f57bf 29#include <asm/watch.h>
06372a63 30#include <asm/elf.h>
4f12b91d 31#include <asm/pgtable-bits.h>
a074f0e8 32#include <asm/spram.h>
949e51be
DD		 33#include <asm/uaccess.h>
34
e14f1db7
PB		 35/* Hardware capabilities */
36unsigned int elf_hwcap __read_mostly;
37
7aecd5ca
MR		 38/*
39 * Get the FPU Implementation/Revision.
40 */
41static inline unsigned long cpu_get_fpu_id(void)
42{
43 unsigned long tmp, fpu_id;
44
45 tmp = read_c0_status();
46 __enable_fpu(FPU_AS_IS);
47 fpu_id = read_32bit_cp1_register(CP1_REVISION);
48 write_c0_status(tmp);
49 return fpu_id;
50}
51
52/*
53 * Check if the CPU has an external FPU.
54 */
55static inline int __cpu_has_fpu(void)
56{
57 return (cpu_get_fpu_id() & FPIR_IMP_MASK) != FPIR_IMP_NONE;
58}
59
60static inline unsigned long cpu_get_msa_id(void)
61{
62 unsigned long status, msa_id;
63
64 status = read_c0_status();
65 __enable_fpu(FPU_64BIT);
66 enable_msa();
67 msa_id = read_msa_ir();
68 disable_msa();
69 write_c0_status(status);
70 return msa_id;
71}
72
9b26616c
MR		 73/*
74 * Determine the FCSR mask for FPU hardware.
75 */
76static inline void cpu_set_fpu_fcsr_mask(struct cpuinfo_mips *c)
77{
78 unsigned long sr, mask, fcsr, fcsr0, fcsr1;
79
90b712dd 80 fcsr = c->fpu_csr31;
9b26616c
MR		 81 mask = FPU_CSR_ALL_X | FPU_CSR_ALL_E | FPU_CSR_ALL_S | FPU_CSR_RM;
82
83 sr = read_c0_status();
84 __enable_fpu(FPU_AS_IS);
85
9b26616c
MR		 86 fcsr0 = fcsr & mask;
87 write_32bit_cp1_register(CP1_STATUS, fcsr0);
88 fcsr0 = read_32bit_cp1_register(CP1_STATUS);
89
90 fcsr1 = fcsr | ~mask;
91 write_32bit_cp1_register(CP1_STATUS, fcsr1);
92 fcsr1 = read_32bit_cp1_register(CP1_STATUS);
93
94 write_32bit_cp1_register(CP1_STATUS, fcsr);
95
96 write_c0_status(sr);
97
98 c->fpu_msk31 = ~(fcsr0 ^ fcsr1) & ~mask;
99}
100
93adeaf6
MR		 101/*
102 * Determine the IEEE 754 NaN encodings and ABS.fmt/NEG.fmt execution modes
103 * supported by FPU hardware.
104 */
105static void cpu_set_fpu_2008(struct cpuinfo_mips *c)
106{
107 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
108 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
109 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) {
110 unsigned long sr, fir, fcsr, fcsr0, fcsr1;
111
112 sr = read_c0_status();
113 __enable_fpu(FPU_AS_IS);
114
115 fir = read_32bit_cp1_register(CP1_REVISION);
116 if (fir & MIPS_FPIR_HAS2008) {
117 fcsr = read_32bit_cp1_register(CP1_STATUS);
118
119 fcsr0 = fcsr & ~(FPU_CSR_ABS2008 | FPU_CSR_NAN2008);
120 write_32bit_cp1_register(CP1_STATUS, fcsr0);
121 fcsr0 = read_32bit_cp1_register(CP1_STATUS);
122
123 fcsr1 = fcsr | FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
124 write_32bit_cp1_register(CP1_STATUS, fcsr1);
125 fcsr1 = read_32bit_cp1_register(CP1_STATUS);
126
127 write_32bit_cp1_register(CP1_STATUS, fcsr);
128
129 if (!(fcsr0 & FPU_CSR_NAN2008))
130 c->options |= MIPS_CPU_NAN_LEGACY;
131 if (fcsr1 & FPU_CSR_NAN2008)
132 c->options |= MIPS_CPU_NAN_2008;
133
134 if ((fcsr0 ^ fcsr1) & FPU_CSR_ABS2008)
135 c->fpu_msk31 &= ~FPU_CSR_ABS2008;
136 else
137 c->fpu_csr31 |= fcsr & FPU_CSR_ABS2008;
138
139 if ((fcsr0 ^ fcsr1) & FPU_CSR_NAN2008)
140 c->fpu_msk31 &= ~FPU_CSR_NAN2008;
141 else
142 c->fpu_csr31 |= fcsr & FPU_CSR_NAN2008;
143 } else {
144 c->options |= MIPS_CPU_NAN_LEGACY;
145 }
146
147 write_c0_status(sr);
148 } else {
149 c->options |= MIPS_CPU_NAN_LEGACY;
150 }
151}
152
153/*
503943e0
MR		 154 * IEEE 754 conformance mode to use. Affects the NaN encoding and the
155 * ABS.fmt/NEG.fmt execution mode.
156 */
157static enum { STRICT, LEGACY, STD2008, RELAXED } ieee754 = STRICT;
158
159/*
160 * Set the IEEE 754 NaN encodings and the ABS.fmt/NEG.fmt execution modes
161 * to support by the FPU emulator according to the IEEE 754 conformance
162 * mode selected. Note that "relaxed" straps the emulator so that it
163 * allows 2008-NaN binaries even for legacy processors.
93adeaf6
MR		 164 */
165static void cpu_set_nofpu_2008(struct cpuinfo_mips *c)
166{
503943e0 167 c->options &= ~(MIPS_CPU_NAN_2008 | MIPS_CPU_NAN_LEGACY);
93adeaf6 168 c->fpu_csr31 &= ~(FPU_CSR_ABS2008 | FPU_CSR_NAN2008);
503943e0
MR		 169 c->fpu_msk31 &= ~(FPU_CSR_ABS2008 | FPU_CSR_NAN2008);
170
171 switch (ieee754) {
172 case STRICT:
173 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
174 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
175 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) {
176 c->options |= MIPS_CPU_NAN_2008 | MIPS_CPU_NAN_LEGACY;
177 } else {
178 c->options |= MIPS_CPU_NAN_LEGACY;
179 c->fpu_msk31 |= FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
180 }
181 break;
182 case LEGACY:
93adeaf6
MR		 183 c->options |= MIPS_CPU_NAN_LEGACY;
184 c->fpu_msk31 |= FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
503943e0
MR		 185 break;
186 case STD2008:
187 c->options |= MIPS_CPU_NAN_2008;
188 c->fpu_csr31 |= FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
189 c->fpu_msk31 |= FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
190 break;
191 case RELAXED:
192 c->options |= MIPS_CPU_NAN_2008 | MIPS_CPU_NAN_LEGACY;
193 break;
93adeaf6
MR		 194 }
195}
196
503943e0
MR		 197/*
198 * Override the IEEE 754 NaN encoding and ABS.fmt/NEG.fmt execution mode
199 * according to the "ieee754=" parameter.
200 */
201static void cpu_set_nan_2008(struct cpuinfo_mips *c)
202{
203 switch (ieee754) {
204 case STRICT:
205 mips_use_nan_legacy = !!cpu_has_nan_legacy;
206 mips_use_nan_2008 = !!cpu_has_nan_2008;
207 break;
208 case LEGACY:
209 mips_use_nan_legacy = !!cpu_has_nan_legacy;
210 mips_use_nan_2008 = !cpu_has_nan_legacy;
211 break;
212 case STD2008:
213 mips_use_nan_legacy = !cpu_has_nan_2008;
214 mips_use_nan_2008 = !!cpu_has_nan_2008;
215 break;
216 case RELAXED:
217 mips_use_nan_legacy = true;
218 mips_use_nan_2008 = true;
219 break;
220 }
221}
222
223/*
224 * IEEE 754 NaN encoding and ABS.fmt/NEG.fmt execution mode override
225 * settings:
226 *
227 * strict: accept binaries that request a NaN encoding supported by the FPU
228 * legacy: only accept legacy-NaN binaries
229 * 2008: only accept 2008-NaN binaries
230 * relaxed: accept any binaries regardless of whether supported by the FPU
231 */
232static int __init ieee754_setup(char *s)
233{
234 if (!s)
235 return -1;
236 else if (!strcmp(s, "strict"))
237 ieee754 = STRICT;
238 else if (!strcmp(s, "legacy"))
239 ieee754 = LEGACY;
240 else if (!strcmp(s, "2008"))
241 ieee754 = STD2008;
242 else if (!strcmp(s, "relaxed"))
243 ieee754 = RELAXED;
244 else
245 return -1;
246
247 if (!(boot_cpu_data.options & MIPS_CPU_FPU))
248 cpu_set_nofpu_2008(&boot_cpu_data);
249 cpu_set_nan_2008(&boot_cpu_data);
250
251 return 0;
252}
253
254early_param("ieee754", ieee754_setup);
255
f6843626
MR		 256/*
257 * Set the FIR feature flags for the FPU emulator.
258 */
259static void cpu_set_nofpu_id(struct cpuinfo_mips *c)
260{
261 u32 value;
262
263 value = 0;
264 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
265 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
266 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6))
267 value |= MIPS_FPIR_D | MIPS_FPIR_S;
268 if (c->isa_level & (MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
269 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6))
270 value |= MIPS_FPIR_F64 | MIPS_FPIR_L | MIPS_FPIR_W;
90d53a91
MR		 271 if (c->options & MIPS_CPU_NAN_2008)
272 value |= MIPS_FPIR_HAS2008;
f6843626
MR		 273 c->fpu_id = value;
274}
275
9b26616c
MR		 276/* Determined FPU emulator mask to use for the boot CPU with "nofpu". */
277static unsigned int mips_nofpu_msk31;
278
7aecd5ca
MR		 279/*
280 * Set options for FPU hardware.
281 */
282static void cpu_set_fpu_opts(struct cpuinfo_mips *c)
283{
284 c->fpu_id = cpu_get_fpu_id();
285 mips_nofpu_msk31 = c->fpu_msk31;
286
287 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
288 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
289 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) {
290 if (c->fpu_id & MIPS_FPIR_3D)
291 c->ases |= MIPS_ASE_MIPS3D;
292 if (c->fpu_id & MIPS_FPIR_FREP)
293 c->options |= MIPS_CPU_FRE;
294 }
295
296 cpu_set_fpu_fcsr_mask(c);
93adeaf6 297 cpu_set_fpu_2008(c);
503943e0 298 cpu_set_nan_2008(c);
7aecd5ca
MR		 299}
300
301/*
302 * Set options for the FPU emulator.
303 */
304static void cpu_set_nofpu_opts(struct cpuinfo_mips *c)
305{
306 c->options &= ~MIPS_CPU_FPU;
307 c->fpu_msk31 = mips_nofpu_msk31;
308
93adeaf6 309 cpu_set_nofpu_2008(c);
503943e0 310 cpu_set_nan_2008(c);
7aecd5ca
MR		 311 cpu_set_nofpu_id(c);
312}
313
078a55fc 314static int mips_fpu_disabled;
0103d23f
KC		 315
316static int __init fpu_disable(char *s)
317{
7aecd5ca 318 cpu_set_nofpu_opts(&boot_cpu_data);
0103d23f
KC		 319 mips_fpu_disabled = 1;
320
321 return 1;
322}
323
324__setup("nofpu", fpu_disable);
325
078a55fc 326int mips_dsp_disabled;
0103d23f
KC		 327
328static int __init dsp_disable(char *s)
329{
ee80f7c7 330 cpu_data[0].ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
0103d23f
KC		 331 mips_dsp_disabled = 1;
332
333 return 1;
334}
335
336__setup("nodsp", dsp_disable);
337
3d528b32
MC		 338static int mips_htw_disabled;
339
340static int __init htw_disable(char *s)
341{
342 mips_htw_disabled = 1;
343 cpu_data[0].options &= ~MIPS_CPU_HTW;
344 write_c0_pwctl(read_c0_pwctl() &
345 ~(1 << MIPS_PWCTL_PWEN_SHIFT));
346
347 return 1;
348}
349
350__setup("nohtw", htw_disable);
351
97f4ad29
MC		 352static int mips_ftlb_disabled;
353static int mips_has_ftlb_configured;
354
912708c2 355static int set_ftlb_enable(struct cpuinfo_mips *c, int enable);
97f4ad29
MC		 356
357static int __init ftlb_disable(char *s)
358{
359 unsigned int config4, mmuextdef;
360
361 /*
362 * If the core hasn't done any FTLB configuration, there is nothing
363 * for us to do here.
364 */
365 if (!mips_has_ftlb_configured)
366 return 1;
367
368 /* Disable it in the boot cpu */
912708c2
MC		 369 if (set_ftlb_enable(&cpu_data[0], 0)) {
370 pr_warn("Can't turn FTLB off\n");
371 return 1;
372 }
97f4ad29
MC		 373
374 back_to_back_c0_hazard();
375
376 config4 = read_c0_config4();
377
378 /* Check that FTLB has been disabled */
379 mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF;
380 /* MMUSIZEEXT == VTLB ON, FTLB OFF */
381 if (mmuextdef == MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT) {
382 /* This should never happen */
383 pr_warn("FTLB could not be disabled!\n");
384 return 1;
385 }
386
387 mips_ftlb_disabled = 1;
388 mips_has_ftlb_configured = 0;
389
390 /*
391 * noftlb is mainly used for debug purposes so print
392 * an informative message instead of using pr_debug()
393 */
394 pr_info("FTLB has been disabled\n");
395
396 /*
397 * Some of these bits are duplicated in the decode_config4.
398 * MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT is the only possible case
399 * once FTLB has been disabled so undo what decode_config4 did.
400 */
401 cpu_data[0].tlbsize -= cpu_data[0].tlbsizeftlbways *
402 cpu_data[0].tlbsizeftlbsets;
403 cpu_data[0].tlbsizeftlbsets = 0;
404 cpu_data[0].tlbsizeftlbways = 0;
405
406 return 1;
407}
408
409__setup("noftlb", ftlb_disable);
410
411
9267a30d
MSJ		 412static inline void check_errata(void)
413{
414 struct cpuinfo_mips *c = &current_cpu_data;
415
69f24d17 416 switch (current_cpu_type()) {
9267a30d
MSJ		 417 case CPU_34K:
418 /*
419 * Erratum "RPS May Cause Incorrect Instruction Execution"
b633648c 420 * This code only handles VPE0, any SMP/RTOS code
9267a30d
MSJ		 421 * making use of VPE1 will be responsable for that VPE.
422 */
423 if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2)
424 write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS);
425 break;
426 default:
427 break;
428 }
429}
430
1da177e4
LT		 431void __init check_bugs32(void)
432{
9267a30d 433 check_errata();
1da177e4
LT		 434}
435
436/*
437 * Probe whether cpu has config register by trying to play with
438 * alternate cache bit and see whether it matters.
439 * It's used by cpu_probe to distinguish between R3000A and R3081.
440 */
441static inline int cpu_has_confreg(void)
442{
443#ifdef CONFIG_CPU_R3000
444 extern unsigned long r3k_cache_size(unsigned long);
445 unsigned long size1, size2;
446 unsigned long cfg = read_c0_conf();
447
448 size1 = r3k_cache_size(ST0_ISC);
449 write_c0_conf(cfg ^ R30XX_CONF_AC);
450 size2 = r3k_cache_size(ST0_ISC);
451 write_c0_conf(cfg);
452 return size1 != size2;
453#else
454 return 0;
455#endif
456}
457
c094c99e
RM		 458static inline void set_elf_platform(int cpu, const char *plat)
459{
460 if (cpu == 0)
461 __elf_platform = plat;
462}
463
91dfc423
GR		 464static inline void cpu_probe_vmbits(struct cpuinfo_mips *c)
465{
466#ifdef __NEED_VMBITS_PROBE
5b7efa89 467 write_c0_entryhi(0x3fffffffffffe000ULL);
91dfc423 468 back_to_back_c0_hazard();
5b7efa89 469 c->vmbits = fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL);
91dfc423
GR		 470#endif
471}
472
078a55fc 473static void set_isa(struct cpuinfo_mips *c, unsigned int isa)
a96102be
SH		 474{
475 switch (isa) {
476 case MIPS_CPU_ISA_M64R2:
477 c->isa_level |= MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2;
478 case MIPS_CPU_ISA_M64R1:
479 c->isa_level |= MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1;
480 case MIPS_CPU_ISA_V:
481 c->isa_level |= MIPS_CPU_ISA_V;
482 case MIPS_CPU_ISA_IV:
483 c->isa_level |= MIPS_CPU_ISA_IV;
484 case MIPS_CPU_ISA_III:
1990e542 485 c->isa_level |= MIPS_CPU_ISA_II | MIPS_CPU_ISA_III;
a96102be
SH		 486 break;
487
8b8aa636
LY		 488 /* R6 incompatible with everything else */
489 case MIPS_CPU_ISA_M64R6:
490 c->isa_level |= MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6;
491 case MIPS_CPU_ISA_M32R6:
492 c->isa_level |= MIPS_CPU_ISA_M32R6;
493 /* Break here so we don't add incompatible ISAs */
494 break;
a96102be
SH		 495 case MIPS_CPU_ISA_M32R2:
496 c->isa_level |= MIPS_CPU_ISA_M32R2;
497 case MIPS_CPU_ISA_M32R1:
498 c->isa_level |= MIPS_CPU_ISA_M32R1;
499 case MIPS_CPU_ISA_II:
500 c->isa_level |= MIPS_CPU_ISA_II;
a96102be
SH		 501 break;
502 }
503}
504
078a55fc 505static char unknown_isa[] = KERN_ERR \
2fa36399
KC		 506 "Unsupported ISA type, c0.config0: %d.";
507
cf0a8aa0
MC		 508static unsigned int calculate_ftlb_probability(struct cpuinfo_mips *c)
509{
510
511 unsigned int probability = c->tlbsize / c->tlbsizevtlb;
512
513 /*
514 * 0 = All TLBWR instructions go to FTLB
515 * 1 = 15:1: For every 16 TBLWR instructions, 15 go to the
516 * FTLB and 1 goes to the VTLB.
517 * 2 = 7:1: As above with 7:1 ratio.
518 * 3 = 3:1: As above with 3:1 ratio.
519 *
520 * Use the linear midpoint as the probability threshold.
521 */
522 if (probability >= 12)
523 return 1;
524 else if (probability >= 6)
525 return 2;
526 else
527 /*
528 * So FTLB is less than 4 times bigger than VTLB.
529 * A 3:1 ratio can still be useful though.
530 */
531 return 3;
532}
533
912708c2 534static int set_ftlb_enable(struct cpuinfo_mips *c, int enable)
75b5b5e0 535{
20a7f7e5 536 unsigned int config;
d83b0e82
JH		 537
538 /* It's implementation dependent how the FTLB can be enabled */
539 switch (c->cputype) {
540 case CPU_PROAPTIV:
541 case CPU_P5600:
1091bfa2 542 case CPU_P6600:
d83b0e82 543 /* proAptiv & related cores use Config6 to enable the FTLB */
20a7f7e5 544 config = read_c0_config6();
cf0a8aa0 545 /* Clear the old probability value */
20a7f7e5 546 config &= ~(3 << MIPS_CONF6_FTLBP_SHIFT);
75b5b5e0
LY		 547 if (enable)
548 /* Enable FTLB */
20a7f7e5 549 write_c0_config6(config |
cf0a8aa0
MC		 550 (calculate_ftlb_probability(c)
551 << MIPS_CONF6_FTLBP_SHIFT)
552 | MIPS_CONF6_FTLBEN);
75b5b5e0
LY		 553 else
554 /* Disable FTLB */
20a7f7e5
MC		 555 write_c0_config6(config & ~MIPS_CONF6_FTLBEN);
556 break;
557 case CPU_I6400:
558 /* I6400 & related cores use Config7 to configure FTLB */
559 config = read_c0_config7();
560 /* Clear the old probability value */
561 config &= ~(3 << MIPS_CONF7_FTLBP_SHIFT);
562 write_c0_config7(config | (calculate_ftlb_probability(c)
563 << MIPS_CONF7_FTLBP_SHIFT));
d83b0e82 564 break;
b2edcfc8 565 case CPU_LOONGSON3:
06e4814e
HC		 566 /* Flush ITLB, DTLB, VTLB and FTLB */
567 write_c0_diag(LOONGSON_DIAG_ITLB | LOONGSON_DIAG_DTLB |
568 LOONGSON_DIAG_VTLB | LOONGSON_DIAG_FTLB);
b2edcfc8
HC		 569 /* Loongson-3 cores use Config6 to enable the FTLB */
570 config = read_c0_config6();
571 if (enable)
572 /* Enable FTLB */
573 write_c0_config6(config & ~MIPS_CONF6_FTLBDIS);
574 else
575 /* Disable FTLB */
576 write_c0_config6(config | MIPS_CONF6_FTLBDIS);
577 break;
912708c2
MC		 578 default:
579 return 1;
75b5b5e0 580 }
912708c2
MC		 581
582 return 0;
75b5b5e0
LY		 583}
584
2fa36399
KC		 585static inline unsigned int decode_config0(struct cpuinfo_mips *c)
586{
587 unsigned int config0;
2f6f3136 588 int isa, mt;
2fa36399
KC		 589
590 config0 = read_c0_config();
591
75b5b5e0
LY		 592 /*
593 * Look for Standard TLB or Dual VTLB and FTLB
594 */
2f6f3136
JH		 595 mt = config0 & MIPS_CONF_MT;
596 if (mt == MIPS_CONF_MT_TLB)
2fa36399 597 c->options |= MIPS_CPU_TLB;
2f6f3136
JH		 598 else if (mt == MIPS_CONF_MT_FTLB)
599 c->options |= MIPS_CPU_TLB | MIPS_CPU_FTLB;
75b5b5e0 600
2fa36399
KC		 601 isa = (config0 & MIPS_CONF_AT) >> 13;
602 switch (isa) {
603 case 0:
604 switch ((config0 & MIPS_CONF_AR) >> 10) {
605 case 0:
a96102be 606 set_isa(c, MIPS_CPU_ISA_M32R1);
2fa36399
KC		 607 break;
608 case 1:
a96102be 609 set_isa(c, MIPS_CPU_ISA_M32R2);
2fa36399 610 break;
8b8aa636
LY		 611 case 2:
612 set_isa(c, MIPS_CPU_ISA_M32R6);
613 break;
2fa36399
KC		 614 default:
615 goto unknown;
616 }
617 break;
618 case 2:
619 switch ((config0 & MIPS_CONF_AR) >> 10) {
620 case 0:
a96102be 621 set_isa(c, MIPS_CPU_ISA_M64R1);
2fa36399
KC		 622 break;
623 case 1:
a96102be 624 set_isa(c, MIPS_CPU_ISA_M64R2);
2fa36399 625 break;
8b8aa636
LY		 626 case 2:
627 set_isa(c, MIPS_CPU_ISA_M64R6);
628 break;
2fa36399
KC		 629 default:
630 goto unknown;
631 }
632 break;
633 default:
634 goto unknown;
635 }
636
637 return config0 & MIPS_CONF_M;
638
639unknown:
640 panic(unknown_isa, config0);
641}
642
643static inline unsigned int decode_config1(struct cpuinfo_mips *c)
644{
645 unsigned int config1;
646
647 config1 = read_c0_config1();
648
649 if (config1 & MIPS_CONF1_MD)
650 c->ases |= MIPS_ASE_MDMX;
30228c40
JH		 651 if (config1 & MIPS_CONF1_PC)
652 c->options |= MIPS_CPU_PERF;
2fa36399
KC		 653 if (config1 & MIPS_CONF1_WR)
654 c->options |= MIPS_CPU_WATCH;
655 if (config1 & MIPS_CONF1_CA)
656 c->ases |= MIPS_ASE_MIPS16;
657 if (config1 & MIPS_CONF1_EP)
658 c->options |= MIPS_CPU_EJTAG;
659 if (config1 & MIPS_CONF1_FP) {
660 c->options |= MIPS_CPU_FPU;
661 c->options |= MIPS_CPU_32FPR;
662 }
75b5b5e0 663 if (cpu_has_tlb) {
2fa36399 664 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;
75b5b5e0
LY		 665 c->tlbsizevtlb = c->tlbsize;
666 c->tlbsizeftlbsets = 0;
667 }
2fa36399
KC		 668
669 return config1 & MIPS_CONF_M;
670}
671
672static inline unsigned int decode_config2(struct cpuinfo_mips *c)
673{
674 unsigned int config2;
675
676 config2 = read_c0_config2();
677
678 if (config2 & MIPS_CONF2_SL)
679 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
680
681 return config2 & MIPS_CONF_M;
682}
683
684static inline unsigned int decode_config3(struct cpuinfo_mips *c)
685{
686 unsigned int config3;
687
688 config3 = read_c0_config3();
689
b2ab4f08 690 if (config3 & MIPS_CONF3_SM) {
2fa36399 691 c->ases |= MIPS_ASE_SMARTMIPS;
f18bdfa1 692 c->options |= MIPS_CPU_RIXI | MIPS_CPU_CTXTC;
b2ab4f08
SH		 693 }
694 if (config3 & MIPS_CONF3_RXI)
695 c->options |= MIPS_CPU_RIXI;
f18bdfa1
JH		 696 if (config3 & MIPS_CONF3_CTXTC)
697 c->options |= MIPS_CPU_CTXTC;
2fa36399
KC		 698 if (config3 & MIPS_CONF3_DSP)
699 c->ases |= MIPS_ASE_DSP;
b5a6455c 700 if (config3 & MIPS_CONF3_DSP2P) {
ee80f7c7 701 c->ases |= MIPS_ASE_DSP2P;
b5a6455c
ZLK		 702 if (cpu_has_mips_r6)
703 c->ases |= MIPS_ASE_DSP3;
704 }
2fa36399
KC		 705 if (config3 & MIPS_CONF3_VINT)
706 c->options |= MIPS_CPU_VINT;
707 if (config3 & MIPS_CONF3_VEIC)
708 c->options |= MIPS_CPU_VEIC;
12822570
JH		 709 if (config3 & MIPS_CONF3_LPA)
710 c->options |= MIPS_CPU_LPA;
2fa36399
KC		 711 if (config3 & MIPS_CONF3_MT)
712 c->ases |= MIPS_ASE_MIPSMT;
713 if (config3 & MIPS_CONF3_ULRI)
714 c->options |= MIPS_CPU_ULRI;
f8fa4811
SH		 715 if (config3 & MIPS_CONF3_ISA)
716 c->options |= MIPS_CPU_MICROMIPS;
1e7decdb
DD		 717 if (config3 & MIPS_CONF3_VZ)
718 c->ases |= MIPS_ASE_VZ;
4a0156fb
SH		 719 if (config3 & MIPS_CONF3_SC)
720 c->options |= MIPS_CPU_SEGMENTS;
e06a1548
JH		 721 if (config3 & MIPS_CONF3_BI)
722 c->options |= MIPS_CPU_BADINSTR;
723 if (config3 & MIPS_CONF3_BP)
724 c->options |= MIPS_CPU_BADINSTRP;
a5e9a69e
PB		 725 if (config3 & MIPS_CONF3_MSA)
726 c->ases |= MIPS_ASE_MSA;
cab25bc7 727 if (config3 & MIPS_CONF3_PW) {
ed4cbc81 728 c->htw_seq = 0;
3d528b32 729 c->options |= MIPS_CPU_HTW;
ed4cbc81 730 }
9b3274bd
JH		 731 if (config3 & MIPS_CONF3_CDMM)
732 c->options |= MIPS_CPU_CDMM;
aaa7be48
JH		 733 if (config3 & MIPS_CONF3_SP)
734 c->options |= MIPS_CPU_SP;
2fa36399
KC		 735
736 return config3 & MIPS_CONF_M;
737}
738
739static inline unsigned int decode_config4(struct cpuinfo_mips *c)
740{
741 unsigned int config4;
75b5b5e0
LY		 742 unsigned int newcf4;
743 unsigned int mmuextdef;
744 unsigned int ftlb_page = MIPS_CONF4_FTLBPAGESIZE;
2db003a5 745 unsigned long asid_mask;
2fa36399
KC		 746
747 config4 = read_c0_config4();
748
1745c1ef
LY		 749 if (cpu_has_tlb) {
750 if (((config4 & MIPS_CONF4_IE) >> 29) == 2)
751 c->options |= MIPS_CPU_TLBINV;
43d104db 752
e87569cd 753 /*
43d104db
JH		 754 * R6 has dropped the MMUExtDef field from config4.
755 * On R6 the fields always describe the FTLB, and only if it is
756 * present according to Config.MT.
e87569cd 757 */
43d104db
JH		 758 if (!cpu_has_mips_r6)
759 mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF;
760 else if (cpu_has_ftlb)
e87569cd
MC		 761 mmuextdef = MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT;
762 else
43d104db 763 mmuextdef = 0;
e87569cd 764
75b5b5e0
LY		 765 switch (mmuextdef) {
766 case MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT:
767 c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40;
768 c->tlbsizevtlb = c->tlbsize;
769 break;
770 case MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT:
771 c->tlbsizevtlb +=
772 ((config4 & MIPS_CONF4_VTLBSIZEEXT) >>
773 MIPS_CONF4_VTLBSIZEEXT_SHIFT) * 0x40;
774 c->tlbsize = c->tlbsizevtlb;
775 ftlb_page = MIPS_CONF4_VFTLBPAGESIZE;
776 /* fall through */
777 case MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT:
97f4ad29
MC		 778 if (mips_ftlb_disabled)
779 break;
75b5b5e0
LY		 780 newcf4 = (config4 & ~ftlb_page) |
781 (page_size_ftlb(mmuextdef) <<
782 MIPS_CONF4_FTLBPAGESIZE_SHIFT);
783 write_c0_config4(newcf4);
784 back_to_back_c0_hazard();
785 config4 = read_c0_config4();
786 if (config4 != newcf4) {
787 pr_err("PAGE_SIZE 0x%lx is not supported by FTLB (config4=0x%x)\n",
788 PAGE_SIZE, config4);
789 /* Switch FTLB off */
790 set_ftlb_enable(c, 0);
791 break;
792 }
793 c->tlbsizeftlbsets = 1 <<
794 ((config4 & MIPS_CONF4_FTLBSETS) >>
795 MIPS_CONF4_FTLBSETS_SHIFT);
796 c->tlbsizeftlbways = ((config4 & MIPS_CONF4_FTLBWAYS) >>
797 MIPS_CONF4_FTLBWAYS_SHIFT) + 2;
798 c->tlbsize += c->tlbsizeftlbways * c->tlbsizeftlbsets;
97f4ad29 799 mips_has_ftlb_configured = 1;
75b5b5e0
LY		 800 break;
801 }
1745c1ef
LY		 802 }
803
9e575f75
JH		 804 c->kscratch_mask = (config4 & MIPS_CONF4_KSCREXIST)
805 >> MIPS_CONF4_KSCREXIST_SHIFT;
2fa36399 806
2db003a5
PB		 807 asid_mask = MIPS_ENTRYHI_ASID;
808 if (config4 & MIPS_CONF4_AE)
809 asid_mask |= MIPS_ENTRYHI_ASIDX;
810 set_cpu_asid_mask(c, asid_mask);
811
812 /*
813 * Warn if the computed ASID mask doesn't match the mask the kernel
814 * is built for. This may indicate either a serious problem or an
815 * easy optimisation opportunity, but either way should be addressed.
816 */
817 WARN_ON(asid_mask != cpu_asid_mask(c));
818
2fa36399
KC		 819 return config4 & MIPS_CONF_M;
820}
821
8b8a7634
RB		 822static inline unsigned int decode_config5(struct cpuinfo_mips *c)
823{
824 unsigned int config5;
825
826 config5 = read_c0_config5();
d175ed2b 827 config5 &= ~(MIPS_CONF5_UFR | MIPS_CONF5_UFE);
8b8a7634
RB		 828 write_c0_config5(config5);
829
49016748
MC		 830 if (config5 & MIPS_CONF5_EVA)
831 c->options |= MIPS_CPU_EVA;
1f6c52ff
PB		 832 if (config5 & MIPS_CONF5_MRP)
833 c->options |= MIPS_CPU_MAAR;
5aed9da1
MC		 834 if (config5 & MIPS_CONF5_LLB)
835 c->options |= MIPS_CPU_RW_LLB;
c5b36783
SH		 836#ifdef CONFIG_XPA
837 if (config5 & MIPS_CONF5_MVH)
838 c->options |= MIPS_CPU_XPA;
839#endif
f270d881
PB		 840 if (cpu_has_mips_r6 && (config5 & MIPS_CONF5_VP))
841 c->options |= MIPS_CPU_VP;
49016748 842
8b8a7634
RB		 843 return config5 & MIPS_CONF_M;
844}
845
078a55fc 846static void decode_configs(struct cpuinfo_mips *c)
2fa36399
KC		 847{
848 int ok;
849
850 /* MIPS32 or MIPS64 compliant CPU. */
851 c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
852 MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
853
854 c->scache.flags = MIPS_CACHE_NOT_PRESENT;
855
97f4ad29
MC		 856 /* Enable FTLB if present and not disabled */
857 set_ftlb_enable(c, !mips_ftlb_disabled);
75b5b5e0 858
2fa36399 859 ok = decode_config0(c); /* Read Config registers. */
70342287 860 BUG_ON(!ok); /* Arch spec violation! */
2fa36399
KC		 861 if (ok)
862 ok = decode_config1(c);
863 if (ok)
864 ok = decode_config2(c);
865 if (ok)
866 ok = decode_config3(c);
867 if (ok)
868 ok = decode_config4(c);
8b8a7634
RB		 869 if (ok)
870 ok = decode_config5(c);
2fa36399 871
37fb60f8
JH		 872 /* Probe the EBase.WG bit */
873 if (cpu_has_mips_r2_r6) {
874 u64 ebase;
875 unsigned int status;
876
877 /* {read,write}_c0_ebase_64() may be UNDEFINED prior to r6 */
878 ebase = cpu_has_mips64r6 ? read_c0_ebase_64()
879 : (s32)read_c0_ebase();
880 if (ebase & MIPS_EBASE_WG) {
881 /* WG bit already set, we can avoid the clumsy probe */
882 c->options |= MIPS_CPU_EBASE_WG;
883 } else {
884 /* Its UNDEFINED to change EBase while BEV=0 */
885 status = read_c0_status();
886 write_c0_status(status | ST0_BEV);
887 irq_enable_hazard();
888 /*
889 * On pre-r6 cores, this may well clobber the upper bits
890 * of EBase. This is hard to avoid without potentially
891 * hitting UNDEFINED dm*c0 behaviour if EBase is 32-bit.
892 */
893 if (cpu_has_mips64r6)
894 write_c0_ebase_64(ebase | MIPS_EBASE_WG);
895 else
896 write_c0_ebase(ebase | MIPS_EBASE_WG);
897 back_to_back_c0_hazard();
898 /* Restore BEV */
899 write_c0_status(status);
900 if (read_c0_ebase() & MIPS_EBASE_WG) {
901 c->options |= MIPS_CPU_EBASE_WG;
902 write_c0_ebase(ebase);
903 }
904 }
905 }
906
2fa36399
KC		 907 mips_probe_watch_registers(c);
908
0ee958e1 909#ifndef CONFIG_MIPS_CPS
8b8aa636 910 if (cpu_has_mips_r2_r6) {
45b585c8 911 c->core = get_ebase_cpunum();
30ee615b
PB		 912 if (cpu_has_mipsmt)
913 c->core >>= fls(core_nvpes()) - 1;
914 }
0ee958e1 915#endif
2fa36399
KC		 916}
917
02cf2119 918#define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
1da177e4
LT		 919 | MIPS_CPU_COUNTER)
920
cea7e2df 921static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4 922{
8ff374b9 923 switch (c->processor_id & PRID_IMP_MASK) {
1da177e4
LT		 924 case PRID_IMP_R2000:
925 c->cputype = CPU_R2000;
cea7e2df 926 __cpu_name[cpu] = "R2000";
9b26616c 927 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
02cf2119 928 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
03751e79 929 MIPS_CPU_NOFPUEX;
1da177e4
LT		 930 if (__cpu_has_fpu())
931 c->options |= MIPS_CPU_FPU;
932 c->tlbsize = 64;
933 break;
934 case PRID_IMP_R3000:
8ff374b9 935 if ((c->processor_id & PRID_REV_MASK) == PRID_REV_R3000A) {
cea7e2df 936 if (cpu_has_confreg()) {
1da177e4 937 c->cputype = CPU_R3081E;
cea7e2df
RB		 938 __cpu_name[cpu] = "R3081";
939 } else {
1da177e4 940 c->cputype = CPU_R3000A;
cea7e2df
RB		 941 __cpu_name[cpu] = "R3000A";
942 }
cea7e2df 943 } else {
1da177e4 944 c->cputype = CPU_R3000;
cea7e2df
RB		 945 __cpu_name[cpu] = "R3000";
946 }
9b26616c 947 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
02cf2119 948 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
03751e79 949 MIPS_CPU_NOFPUEX;
1da177e4
LT		 950 if (__cpu_has_fpu())
951 c->options |= MIPS_CPU_FPU;
952 c->tlbsize = 64;
953 break;
954 case PRID_IMP_R4000:
955 if (read_c0_config() & CONF_SC) {
8ff374b9
MR		 956 if ((c->processor_id & PRID_REV_MASK) >=
957 PRID_REV_R4400) {
1da177e4 958 c->cputype = CPU_R4400PC;
cea7e2df
RB		 959 __cpu_name[cpu] = "R4400PC";
960 } else {
1da177e4 961 c->cputype = CPU_R4000PC;
cea7e2df
RB		 962 __cpu_name[cpu] = "R4000PC";
963 }
1da177e4 964 } else {
7f177a52
MR		 965 int cca = read_c0_config() & CONF_CM_CMASK;
966 int mc;
967
968 /*
969 * SC and MC versions can't be reliably told apart,
970 * but only the latter support coherent caching
971 * modes so assume the firmware has set the KSEG0
972 * coherency attribute reasonably (if uncached, we
973 * assume SC).
974 */
975 switch (cca) {
976 case CONF_CM_CACHABLE_CE:
977 case CONF_CM_CACHABLE_COW:
978 case CONF_CM_CACHABLE_CUW:
979 mc = 1;
980 break;
981 default:
982 mc = 0;
983 break;
984 }
8ff374b9
MR		 985 if ((c->processor_id & PRID_REV_MASK) >=
986 PRID_REV_R4400) {
7f177a52
MR		 987 c->cputype = mc ? CPU_R4400MC : CPU_R4400SC;
988 __cpu_name[cpu] = mc ? "R4400MC" : "R4400SC";
cea7e2df 989 } else {
7f177a52
MR		 990 c->cputype = mc ? CPU_R4000MC : CPU_R4000SC;
991 __cpu_name[cpu] = mc ? "R4000MC" : "R4000SC";
cea7e2df 992 }
1da177e4
LT		 993 }
994
a96102be 995 set_isa(c, MIPS_CPU_ISA_III);
9b26616c 996 c->fpu_msk31 |= FPU_CSR_CONDX;
1da177e4 997 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79
SH		 998 MIPS_CPU_WATCH | MIPS_CPU_VCE |
999 MIPS_CPU_LLSC;
1da177e4
LT		 1000 c->tlbsize = 48;
1001 break;
1002 case PRID_IMP_VR41XX:
9f91e506 1003 set_isa(c, MIPS_CPU_ISA_III);
9b26616c 1004 c->fpu_msk31 |= FPU_CSR_CONDX;
9f91e506
YY		 1005 c->options = R4K_OPTS;
1006 c->tlbsize = 32;
1da177e4 1007 switch (c->processor_id & 0xf0) {
1da177e4
LT		 1008 case PRID_REV_VR4111:
1009 c->cputype = CPU_VR4111;
cea7e2df 1010 __cpu_name[cpu] = "NEC VR4111";
1da177e4 1011 break;
1da177e4
LT		 1012 case PRID_REV_VR4121:
1013 c->cputype = CPU_VR4121;
cea7e2df 1014 __cpu_name[cpu] = "NEC VR4121";
1da177e4
LT		 1015 break;
1016 case PRID_REV_VR4122:
cea7e2df 1017 if ((c->processor_id & 0xf) < 0x3) {
1da177e4 1018 c->cputype = CPU_VR4122;
cea7e2df
RB		 1019 __cpu_name[cpu] = "NEC VR4122";
1020 } else {
1da177e4 1021 c->cputype = CPU_VR4181A;
cea7e2df
RB		 1022 __cpu_name[cpu] = "NEC VR4181A";
1023 }
1da177e4
LT		 1024 break;
1025 case PRID_REV_VR4130:
cea7e2df 1026 if ((c->processor_id & 0xf) < 0x4) {
1da177e4 1027 c->cputype = CPU_VR4131;
cea7e2df
RB		 1028 __cpu_name[cpu] = "NEC VR4131";
1029 } else {
1da177e4 1030 c->cputype = CPU_VR4133;
9f91e506 1031 c->options |= MIPS_CPU_LLSC;
cea7e2df
RB		 1032 __cpu_name[cpu] = "NEC VR4133";
1033 }
1da177e4
LT		 1034 break;
1035 default:
1036 printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
1037 c->cputype = CPU_VR41XX;
cea7e2df 1038 __cpu_name[cpu] = "NEC Vr41xx";
1da177e4
LT		 1039 break;
1040 }
1da177e4
LT		 1041 break;
1042 case PRID_IMP_R4300:
1043 c->cputype = CPU_R4300;
cea7e2df 1044 __cpu_name[cpu] = "R4300";
a96102be 1045 set_isa(c, MIPS_CPU_ISA_III);
9b26616c 1046 c->fpu_msk31 |= FPU_CSR_CONDX;
1da177e4 1047 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 1048 MIPS_CPU_LLSC;
1da177e4
LT		 1049 c->tlbsize = 32;
1050 break;
1051 case PRID_IMP_R4600:
1052 c->cputype = CPU_R4600;
cea7e2df 1053 __cpu_name[cpu] = "R4600";
a96102be 1054 set_isa(c, MIPS_CPU_ISA_III);
9b26616c 1055 c->fpu_msk31 |= FPU_CSR_CONDX;
075e7502
TS		 1056 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1057 MIPS_CPU_LLSC;
1da177e4
LT		 1058 c->tlbsize = 48;
1059 break;
1060 #if 0
03751e79 1061 case PRID_IMP_R4650:
1da177e4
LT		 1062 /*
1063 * This processor doesn't have an MMU, so it's not
1064 * "real easy" to run Linux on it. It is left purely
1065 * for documentation. Commented out because it shares
1066 * it's c0_prid id number with the TX3900.
1067 */
a3dddd56 1068 c->cputype = CPU_R4650;
cea7e2df 1069 __cpu_name[cpu] = "R4650";
a96102be 1070 set_isa(c, MIPS_CPU_ISA_III);
9b26616c 1071 c->fpu_msk31 |= FPU_CSR_CONDX;
1da177e4 1072 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
03751e79 1073 c->tlbsize = 48;
1da177e4
LT		 1074 break;
1075 #endif
1076 case PRID_IMP_TX39:
9b26616c 1077 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
02cf2119 1078 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE;
1da177e4
LT		 1079
1080 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
1081 c->cputype = CPU_TX3927;
cea7e2df 1082 __cpu_name[cpu] = "TX3927";
1da177e4
LT		 1083 c->tlbsize = 64;
1084 } else {
8ff374b9 1085 switch (c->processor_id & PRID_REV_MASK) {
1da177e4
LT		 1086 case PRID_REV_TX3912:
1087 c->cputype = CPU_TX3912;
cea7e2df 1088 __cpu_name[cpu] = "TX3912";
1da177e4
LT		 1089 c->tlbsize = 32;
1090 break;
1091 case PRID_REV_TX3922:
1092 c->cputype = CPU_TX3922;
cea7e2df 1093 __cpu_name[cpu] = "TX3922";
1da177e4
LT		 1094 c->tlbsize = 64;
1095 break;
1da177e4
LT		 1096 }
1097 }
1098 break;
1099 case PRID_IMP_R4700:
1100 c->cputype = CPU_R4700;
cea7e2df 1101 __cpu_name[cpu] = "R4700";
a96102be 1102 set_isa(c, MIPS_CPU_ISA_III);
9b26616c 1103 c->fpu_msk31 |= FPU_CSR_CONDX;
1da177e4 1104 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 1105 MIPS_CPU_LLSC;
1da177e4
LT		 1106 c->tlbsize = 48;
1107 break;
1108 case PRID_IMP_TX49:
1109 c->cputype = CPU_TX49XX;
cea7e2df 1110 __cpu_name[cpu] = "R49XX";
a96102be 1111 set_isa(c, MIPS_CPU_ISA_III);
9b26616c 1112 c->fpu_msk31 |= FPU_CSR_CONDX;
1da177e4
LT		 1113 c->options = R4K_OPTS | MIPS_CPU_LLSC;
1114 if (!(c->processor_id & 0x08))
1115 c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
1116 c->tlbsize = 48;
1117 break;
1118 case PRID_IMP_R5000:
1119 c->cputype = CPU_R5000;
cea7e2df 1120 __cpu_name[cpu] = "R5000";
a96102be 1121 set_isa(c, MIPS_CPU_ISA_IV);
1da177e4 1122 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 1123 MIPS_CPU_LLSC;
1da177e4
LT		 1124 c->tlbsize = 48;
1125 break;
1126 case PRID_IMP_R5432:
1127 c->cputype = CPU_R5432;
cea7e2df 1128 __cpu_name[cpu] = "R5432";
a96102be 1129 set_isa(c, MIPS_CPU_ISA_IV);
1da177e4 1130 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 1131 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
1da177e4
LT		 1132 c->tlbsize = 48;
1133 break;
1134 case PRID_IMP_R5500:
1135 c->cputype = CPU_R5500;
cea7e2df 1136 __cpu_name[cpu] = "R5500";
a96102be 1137 set_isa(c, MIPS_CPU_ISA_IV);
1da177e4 1138 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 1139 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
1da177e4
LT		 1140 c->tlbsize = 48;
1141 break;
1142 case PRID_IMP_NEVADA:
1143 c->cputype = CPU_NEVADA;
cea7e2df 1144 __cpu_name[cpu] = "Nevada";
a96102be 1145 set_isa(c, MIPS_CPU_ISA_IV);
1da177e4 1146 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 1147 MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
1da177e4
LT		 1148 c->tlbsize = 48;
1149 break;
1150 case PRID_IMP_R6000:
1151 c->cputype = CPU_R6000;
cea7e2df 1152 __cpu_name[cpu] = "R6000";
a96102be 1153 set_isa(c, MIPS_CPU_ISA_II);
9b26616c 1154 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
1da177e4 1155 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
03751e79 1156 MIPS_CPU_LLSC;
1da177e4
LT		 1157 c->tlbsize = 32;
1158 break;
1159 case PRID_IMP_R6000A:
1160 c->cputype = CPU_R6000A;
cea7e2df 1161 __cpu_name[cpu] = "R6000A";
a96102be 1162 set_isa(c, MIPS_CPU_ISA_II);
9b26616c 1163 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
1da177e4 1164 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
03751e79 1165 MIPS_CPU_LLSC;
1da177e4
LT		 1166 c->tlbsize = 32;
1167 break;
1168 case PRID_IMP_RM7000:
1169 c->cputype = CPU_RM7000;
cea7e2df 1170 __cpu_name[cpu] = "RM7000";
a96102be 1171 set_isa(c, MIPS_CPU_ISA_IV);
1da177e4 1172 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 1173 MIPS_CPU_LLSC;
1da177e4 1174 /*
70342287 1175 * Undocumented RM7000: Bit 29 in the info register of
1da177e4
LT		 1176 * the RM7000 v2.0 indicates if the TLB has 48 or 64
1177 * entries.
1178 *
70342287
RB		 1179 * 29 1 => 64 entry JTLB
1180 * 0 => 48 entry JTLB
1da177e4
LT		 1181 */
1182 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
1da177e4
LT		 1183 break;
1184 case PRID_IMP_R8000:
1185 c->cputype = CPU_R8000;
cea7e2df 1186 __cpu_name[cpu] = "RM8000";
a96102be 1187 set_isa(c, MIPS_CPU_ISA_IV);
1da177e4 1188 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
03751e79
SH		 1189 MIPS_CPU_FPU | MIPS_CPU_32FPR |
1190 MIPS_CPU_LLSC;
1da177e4
LT		 1191 c->tlbsize = 384; /* has weird TLB: 3-way x 128 */
1192 break;
1193 case PRID_IMP_R10000:
1194 c->cputype = CPU_R10000;
cea7e2df 1195 __cpu_name[cpu] = "R10000";
a96102be 1196 set_isa(c, MIPS_CPU_ISA_IV);
8b36612a 1197 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
03751e79 1198 MIPS_CPU_FPU | MIPS_CPU_32FPR |
1da177e4 1199 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
03751e79 1200 MIPS_CPU_LLSC;
1da177e4
LT		 1201 c->tlbsize = 64;
1202 break;
1203 case PRID_IMP_R12000:
1204 c->cputype = CPU_R12000;
cea7e2df 1205 __cpu_name[cpu] = "R12000";
a96102be 1206 set_isa(c, MIPS_CPU_ISA_IV);
8b36612a 1207 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
03751e79 1208 MIPS_CPU_FPU | MIPS_CPU_32FPR |
1da177e4 1209 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
8d5ded16 1210 MIPS_CPU_LLSC | MIPS_CPU_BP_GHIST;
1da177e4
LT		 1211 c->tlbsize = 64;
1212 break;
44d921b2 1213 case PRID_IMP_R14000:
30577391
JK		 1214 if (((c->processor_id >> 4) & 0x0f) > 2) {
1215 c->cputype = CPU_R16000;
1216 __cpu_name[cpu] = "R16000";
1217 } else {
1218 c->cputype = CPU_R14000;
1219 __cpu_name[cpu] = "R14000";
1220 }
a96102be 1221 set_isa(c, MIPS_CPU_ISA_IV);
44d921b2 1222 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
03751e79 1223 MIPS_CPU_FPU | MIPS_CPU_32FPR |
44d921b2 1224 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
8d5ded16 1225 MIPS_CPU_LLSC | MIPS_CPU_BP_GHIST;
44d921b2
K		 1226 c->tlbsize = 64;
1227 break;
26859198 1228 case PRID_IMP_LOONGSON_64: /* Loongson-2/3 */
5aac1e8a
RM		 1229 switch (c->processor_id & PRID_REV_MASK) {
1230 case PRID_REV_LOONGSON2E:
c579d310
HC		 1231 c->cputype = CPU_LOONGSON2;
1232 __cpu_name[cpu] = "ICT Loongson-2";
5aac1e8a 1233 set_elf_platform(cpu, "loongson2e");
7352c8b1 1234 set_isa(c, MIPS_CPU_ISA_III);
9b26616c 1235 c->fpu_msk31 |= FPU_CSR_CONDX;
5aac1e8a
RM		 1236 break;
1237 case PRID_REV_LOONGSON2F:
c579d310
HC		 1238 c->cputype = CPU_LOONGSON2;
1239 __cpu_name[cpu] = "ICT Loongson-2";
5aac1e8a 1240 set_elf_platform(cpu, "loongson2f");
7352c8b1 1241 set_isa(c, MIPS_CPU_ISA_III);
9b26616c 1242 c->fpu_msk31 |= FPU_CSR_CONDX;
5aac1e8a 1243 break;
b2edcfc8 1244 case PRID_REV_LOONGSON3A_R1:
c579d310
HC		 1245 c->cputype = CPU_LOONGSON3;
1246 __cpu_name[cpu] = "ICT Loongson-3";
1247 set_elf_platform(cpu, "loongson3a");
7352c8b1 1248 set_isa(c, MIPS_CPU_ISA_M64R1);
c579d310 1249 break;
e7841be5
HC		 1250 case PRID_REV_LOONGSON3B_R1:
1251 case PRID_REV_LOONGSON3B_R2:
1252 c->cputype = CPU_LOONGSON3;
1253 __cpu_name[cpu] = "ICT Loongson-3";
1254 set_elf_platform(cpu, "loongson3b");
7352c8b1 1255 set_isa(c, MIPS_CPU_ISA_M64R1);
e7841be5 1256 break;
5aac1e8a
RM		 1257 }
1258
2a21c730
FZ		 1259 c->options = R4K_OPTS |
1260 MIPS_CPU_FPU | MIPS_CPU_LLSC |
1261 MIPS_CPU_32FPR;
1262 c->tlbsize = 64;
cc94ea31 1263 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
2a21c730 1264 break;
26859198 1265 case PRID_IMP_LOONGSON_32: /* Loongson-1 */
2fa36399 1266 decode_configs(c);
b4672d37 1267
2fa36399 1268 c->cputype = CPU_LOONGSON1;
1da177e4 1269
2fa36399
KC		 1270 switch (c->processor_id & PRID_REV_MASK) {
1271 case PRID_REV_LOONGSON1B:
1272 __cpu_name[cpu] = "Loongson 1B";
b4672d37 1273 break;
b4672d37 1274 }
4194318c 1275
2fa36399 1276 break;
1da177e4 1277 }
1da177e4
LT		 1278}
1279
cea7e2df 1280static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4 1281{
4f12b91d 1282 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
8ff374b9 1283 switch (c->processor_id & PRID_IMP_MASK) {
b2498af5
LY		 1284 case PRID_IMP_QEMU_GENERIC:
1285 c->writecombine = _CACHE_UNCACHED;
1286 c->cputype = CPU_QEMU_GENERIC;
1287 __cpu_name[cpu] = "MIPS GENERIC QEMU";
1288 break;
1da177e4
LT		 1289 case PRID_IMP_4KC:
1290 c->cputype = CPU_4KC;
4f12b91d 1291 c->writecombine = _CACHE_UNCACHED;
cea7e2df 1292 __cpu_name[cpu] = "MIPS 4Kc";
1da177e4
LT		 1293 break;
1294 case PRID_IMP_4KEC:
2b07bd02
RB		 1295 case PRID_IMP_4KECR2:
1296 c->cputype = CPU_4KEC;
4f12b91d 1297 c->writecombine = _CACHE_UNCACHED;
cea7e2df 1298 __cpu_name[cpu] = "MIPS 4KEc";
2b07bd02 1299 break;
1da177e4 1300 case PRID_IMP_4KSC:
8afcb5d8 1301 case PRID_IMP_4KSD:
1da177e4 1302 c->cputype = CPU_4KSC;
4f12b91d 1303 c->writecombine = _CACHE_UNCACHED;
cea7e2df 1304 __cpu_name[cpu] = "MIPS 4KSc";
1da177e4
LT		 1305 break;
1306 case PRID_IMP_5KC:
1307 c->cputype = CPU_5KC;
4f12b91d 1308 c->writecombine = _CACHE_UNCACHED;
cea7e2df 1309 __cpu_name[cpu] = "MIPS 5Kc";
1da177e4 1310 break;
78d4803f
LY		 1311 case PRID_IMP_5KE:
1312 c->cputype = CPU_5KE;
4f12b91d 1313 c->writecombine = _CACHE_UNCACHED;
78d4803f
LY		 1314 __cpu_name[cpu] = "MIPS 5KE";
1315 break;
1da177e4
LT		 1316 case PRID_IMP_20KC:
1317 c->cputype = CPU_20KC;
4f12b91d 1318 c->writecombine = _CACHE_UNCACHED;
cea7e2df 1319 __cpu_name[cpu] = "MIPS 20Kc";
1da177e4
LT		 1320 break;
1321 case PRID_IMP_24K:
1322 c->cputype = CPU_24K;
4f12b91d 1323 c->writecombine = _CACHE_UNCACHED;
cea7e2df 1324 __cpu_name[cpu] = "MIPS 24Kc";
1da177e4 1325 break;
42f3caef
JC		 1326 case PRID_IMP_24KE:
1327 c->cputype = CPU_24K;
4f12b91d 1328 c->writecombine = _CACHE_UNCACHED;
42f3caef
JC		 1329 __cpu_name[cpu] = "MIPS 24KEc";
1330 break;
1da177e4
LT		 1331 case PRID_IMP_25KF:
1332 c->cputype = CPU_25KF;
4f12b91d 1333 c->writecombine = _CACHE_UNCACHED;
cea7e2df 1334 __cpu_name[cpu] = "MIPS 25Kc";
1da177e4 1335 break;
bbc7f22f
RB		 1336 case PRID_IMP_34K:
1337 c->cputype = CPU_34K;
4f12b91d 1338 c->writecombine = _CACHE_UNCACHED;
cea7e2df 1339 __cpu_name[cpu] = "MIPS 34Kc";
bbc7f22f 1340 break;
c620953c
CD		 1341 case PRID_IMP_74K:
1342 c->cputype = CPU_74K;
4f12b91d 1343 c->writecombine = _CACHE_UNCACHED;
cea7e2df 1344 __cpu_name[cpu] = "MIPS 74Kc";
c620953c 1345 break;
113c62d9
SH		 1346 case PRID_IMP_M14KC:
1347 c->cputype = CPU_M14KC;
4f12b91d 1348 c->writecombine = _CACHE_UNCACHED;
113c62d9
SH		 1349 __cpu_name[cpu] = "MIPS M14Kc";
1350 break;
f8fa4811
SH		 1351 case PRID_IMP_M14KEC:
1352 c->cputype = CPU_M14KEC;
4f12b91d 1353 c->writecombine = _CACHE_UNCACHED;
f8fa4811
SH		 1354 __cpu_name[cpu] = "MIPS M14KEc";
1355 break;
39b8d525
RB		 1356 case PRID_IMP_1004K:
1357 c->cputype = CPU_1004K;
4f12b91d 1358 c->writecombine = _CACHE_UNCACHED;
cea7e2df 1359 __cpu_name[cpu] = "MIPS 1004Kc";
39b8d525 1360 break;
006a851b 1361 case PRID_IMP_1074K:
442e14a2 1362 c->cputype = CPU_1074K;
4f12b91d 1363 c->writecombine = _CACHE_UNCACHED;
006a851b
SH		 1364 __cpu_name[cpu] = "MIPS 1074Kc";
1365 break;
b5f065e7
LY		 1366 case PRID_IMP_INTERAPTIV_UP:
1367 c->cputype = CPU_INTERAPTIV;
1368 __cpu_name[cpu] = "MIPS interAptiv";
1369 break;
1370 case PRID_IMP_INTERAPTIV_MP:
1371 c->cputype = CPU_INTERAPTIV;
1372 __cpu_name[cpu] = "MIPS interAptiv (multi)";
1373 break;
b0d4d300
LY		 1374 case PRID_IMP_PROAPTIV_UP:
1375 c->cputype = CPU_PROAPTIV;
1376 __cpu_name[cpu] = "MIPS proAptiv";
1377 break;
1378 case PRID_IMP_PROAPTIV_MP:
1379 c->cputype = CPU_PROAPTIV;
1380 __cpu_name[cpu] = "MIPS proAptiv (multi)";
1381 break;
829dcc0a
JH		 1382 case PRID_IMP_P5600:
1383 c->cputype = CPU_P5600;
1384 __cpu_name[cpu] = "MIPS P5600";
1385 break;
eba20a3a
PB		 1386 case PRID_IMP_P6600:
1387 c->cputype = CPU_P6600;
1388 __cpu_name[cpu] = "MIPS P6600";
1389 break;
e57f9a2d
MC		 1390 case PRID_IMP_I6400:
1391 c->cputype = CPU_I6400;
1392 __cpu_name[cpu] = "MIPS I6400";
1393 break;
9943ed92
LY		 1394 case PRID_IMP_M5150:
1395 c->cputype = CPU_M5150;
1396 __cpu_name[cpu] = "MIPS M5150";
1397 break;
43aff742
PB		 1398 case PRID_IMP_M6250:
1399 c->cputype = CPU_M6250;
1400 __cpu_name[cpu] = "MIPS M6250";
1401 break;
1da177e4 1402 }
0b6d497f 1403
75b5b5e0
LY		 1404 decode_configs(c);
1405
0b6d497f 1406 spram_config();
1da177e4
LT		 1407}
1408
cea7e2df 1409static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4 1410{
4194318c 1411 decode_configs(c);
8ff374b9 1412 switch (c->processor_id & PRID_IMP_MASK) {
1da177e4
LT		 1413 case PRID_IMP_AU1_REV1:
1414 case PRID_IMP_AU1_REV2:
270717a8 1415 c->cputype = CPU_ALCHEMY;
1da177e4
LT		 1416 switch ((c->processor_id >> 24) & 0xff) {
1417 case 0:
cea7e2df 1418 __cpu_name[cpu] = "Au1000";
1da177e4
LT		 1419 break;
1420 case 1:
cea7e2df 1421 __cpu_name[cpu] = "Au1500";
1da177e4
LT		 1422 break;
1423 case 2:
cea7e2df 1424 __cpu_name[cpu] = "Au1100";
1da177e4
LT		 1425 break;
1426 case 3:
cea7e2df 1427 __cpu_name[cpu] = "Au1550";
1da177e4 1428 break;
e3ad1c23 1429 case 4:
cea7e2df 1430 __cpu_name[cpu] = "Au1200";
8ff374b9 1431 if ((c->processor_id & PRID_REV_MASK) == 2)
cea7e2df 1432 __cpu_name[cpu] = "Au1250";
237cfee1
ML		 1433 break;
1434 case 5:
cea7e2df 1435 __cpu_name[cpu] = "Au1210";
e3ad1c23 1436 break;
1da177e4 1437 default:
270717a8 1438 __cpu_name[cpu] = "Au1xxx";
1da177e4
LT		 1439 break;
1440 }
1da177e4
LT		 1441 break;
1442 }
1443}
1444
cea7e2df 1445static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4 1446{
4194318c 1447 decode_configs(c);
02cf2119 1448
4f12b91d 1449 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
8ff374b9 1450 switch (c->processor_id & PRID_IMP_MASK) {
1da177e4
LT		 1451 case PRID_IMP_SB1:
1452 c->cputype = CPU_SB1;
cea7e2df 1453 __cpu_name[cpu] = "SiByte SB1";
1da177e4 1454 /* FPU in pass1 is known to have issues. */
8ff374b9 1455 if ((c->processor_id & PRID_REV_MASK) < 0x02)
010b853b 1456 c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
1da177e4 1457 break;
93ce2f52
AI		 1458 case PRID_IMP_SB1A:
1459 c->cputype = CPU_SB1A;
cea7e2df 1460 __cpu_name[cpu] = "SiByte SB1A";
93ce2f52 1461 break;
1da177e4
LT		 1462 }
1463}
1464
cea7e2df 1465static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4 1466{
4194318c 1467 decode_configs(c);
8ff374b9 1468 switch (c->processor_id & PRID_IMP_MASK) {
1da177e4
LT		 1469 case PRID_IMP_SR71000:
1470 c->cputype = CPU_SR71000;
cea7e2df 1471 __cpu_name[cpu] = "Sandcraft SR71000";
1da177e4
LT		 1472 c->scache.ways = 8;
1473 c->tlbsize = 64;
1474 break;
1475 }
1476}
1477
cea7e2df 1478static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu)
bdf21b18
PP		 1479{
1480 decode_configs(c);
8ff374b9 1481 switch (c->processor_id & PRID_IMP_MASK) {
bdf21b18
PP		 1482 case PRID_IMP_PR4450:
1483 c->cputype = CPU_PR4450;
cea7e2df 1484 __cpu_name[cpu] = "Philips PR4450";
a96102be 1485 set_isa(c, MIPS_CPU_ISA_M32R1);
bdf21b18 1486 break;
bdf21b18
PP		 1487 }
1488}
1489
cea7e2df 1490static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
1c0c13eb
AJ		 1491{
1492 decode_configs(c);
8ff374b9 1493 switch (c->processor_id & PRID_IMP_MASK) {
190fca3e
KC		 1494 case PRID_IMP_BMIPS32_REV4:
1495 case PRID_IMP_BMIPS32_REV8:
602977b0
KC		 1496 c->cputype = CPU_BMIPS32;
1497 __cpu_name[cpu] = "Broadcom BMIPS32";
06785df0 1498 set_elf_platform(cpu, "bmips32");
602977b0
KC		 1499 break;
1500 case PRID_IMP_BMIPS3300:
1501 case PRID_IMP_BMIPS3300_ALT:
1502 case PRID_IMP_BMIPS3300_BUG:
1503 c->cputype = CPU_BMIPS3300;
1504 __cpu_name[cpu] = "Broadcom BMIPS3300";
06785df0 1505 set_elf_platform(cpu, "bmips3300");
602977b0
KC		 1506 break;
1507 case PRID_IMP_BMIPS43XX: {
8ff374b9 1508 int rev = c->processor_id & PRID_REV_MASK;
602977b0
KC		 1509
1510 if (rev >= PRID_REV_BMIPS4380_LO &&
1511 rev <= PRID_REV_BMIPS4380_HI) {
1512 c->cputype = CPU_BMIPS4380;
1513 __cpu_name[cpu] = "Broadcom BMIPS4380";
06785df0 1514 set_elf_platform(cpu, "bmips4380");
b4720809 1515 c->options |= MIPS_CPU_RIXI;
602977b0
KC		 1516 } else {
1517 c->cputype = CPU_BMIPS4350;
1518 __cpu_name[cpu] = "Broadcom BMIPS4350";
06785df0 1519 set_elf_platform(cpu, "bmips4350");
602977b0 1520 }
0de663ef 1521 break;
602977b0
KC		 1522 }
1523 case PRID_IMP_BMIPS5000:
68e6a783 1524 case PRID_IMP_BMIPS5200:
602977b0 1525 c->cputype = CPU_BMIPS5000;
37808d62
FF		 1526 if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_BMIPS5200)
1527 __cpu_name[cpu] = "Broadcom BMIPS5200";
1528 else
1529 __cpu_name[cpu] = "Broadcom BMIPS5000";
06785df0 1530 set_elf_platform(cpu, "bmips5000");
b4720809 1531 c->options |= MIPS_CPU_ULRI | MIPS_CPU_RIXI;
0de663ef 1532 break;
1c0c13eb
AJ		 1533 }
1534}
1535
0dd4781b
DD		 1536static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu)
1537{
1538 decode_configs(c);
8ff374b9 1539 switch (c->processor_id & PRID_IMP_MASK) {
0dd4781b
DD		 1540 case PRID_IMP_CAVIUM_CN38XX:
1541 case PRID_IMP_CAVIUM_CN31XX:
1542 case PRID_IMP_CAVIUM_CN30XX:
6f329468
DD		 1543 c->cputype = CPU_CAVIUM_OCTEON;
1544 __cpu_name[cpu] = "Cavium Octeon";
1545 goto platform;
0dd4781b
DD		 1546 case PRID_IMP_CAVIUM_CN58XX:
1547 case PRID_IMP_CAVIUM_CN56XX:
1548 case PRID_IMP_CAVIUM_CN50XX:
1549 case PRID_IMP_CAVIUM_CN52XX:
6f329468
DD		 1550 c->cputype = CPU_CAVIUM_OCTEON_PLUS;
1551 __cpu_name[cpu] = "Cavium Octeon+";
1552platform:
c094c99e 1553 set_elf_platform(cpu, "octeon");
0dd4781b 1554 break;
a1431b61 1555 case PRID_IMP_CAVIUM_CN61XX:
0e56b385 1556 case PRID_IMP_CAVIUM_CN63XX:
a1431b61
DD		 1557 case PRID_IMP_CAVIUM_CN66XX:
1558 case PRID_IMP_CAVIUM_CN68XX:
af04bb85 1559 case PRID_IMP_CAVIUM_CNF71XX:
0e56b385
DD		 1560 c->cputype = CPU_CAVIUM_OCTEON2;
1561 __cpu_name[cpu] = "Cavium Octeon II";
c094c99e 1562 set_elf_platform(cpu, "octeon2");
0e56b385 1563 break;
af04bb85 1564 case PRID_IMP_CAVIUM_CN70XX:
b8c8f665
DD		 1565 case PRID_IMP_CAVIUM_CN73XX:
1566 case PRID_IMP_CAVIUM_CNF75XX:
af04bb85
DD		 1567 case PRID_IMP_CAVIUM_CN78XX:
1568 c->cputype = CPU_CAVIUM_OCTEON3;
1569 __cpu_name[cpu] = "Cavium Octeon III";
1570 set_elf_platform(cpu, "octeon3");
1571 break;
0dd4781b
DD		 1572 default:
1573 printk(KERN_INFO "Unknown Octeon chip!\n");
1574 c->cputype = CPU_UNKNOWN;
1575 break;
1576 }
1577}
1578
b2edcfc8
HC		 1579static inline void cpu_probe_loongson(struct cpuinfo_mips *c, unsigned int cpu)
1580{
1581 switch (c->processor_id & PRID_IMP_MASK) {
1582 case PRID_IMP_LOONGSON_64: /* Loongson-2/3 */
1583 switch (c->processor_id & PRID_REV_MASK) {
1584 case PRID_REV_LOONGSON3A_R2:
1585 c->cputype = CPU_LOONGSON3;
1586 __cpu_name[cpu] = "ICT Loongson-3";
1587 set_elf_platform(cpu, "loongson3a");
1588 set_isa(c, MIPS_CPU_ISA_M64R2);
1589 break;
1590 }
1591
1592 decode_configs(c);
380cd582 1593 c->options |= MIPS_CPU_TLBINV | MIPS_CPU_LDPTE;
b2edcfc8
HC		 1594 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1595 break;
1596 default:
1597 panic("Unknown Loongson Processor ID!");
1598 break;
1599 }
1600}
1601
83ccf69d
LPC		 1602static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
1603{
1604 decode_configs(c);
1605 /* JZRISC does not implement the CP0 counter. */
1606 c->options &= ~MIPS_CPU_COUNTER;
06947aaa 1607 BUG_ON(!__builtin_constant_p(cpu_has_counter) || cpu_has_counter);
8ff374b9 1608 switch (c->processor_id & PRID_IMP_MASK) {
83ccf69d
LPC		 1609 case PRID_IMP_JZRISC:
1610 c->cputype = CPU_JZRISC;
4f12b91d 1611 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
83ccf69d
LPC		 1612 __cpu_name[cpu] = "Ingenic JZRISC";
1613 break;
1614 default:
1615 panic("Unknown Ingenic Processor ID!");
1616 break;
1617 }
1618}
1619
a7117c6b
J		 1620static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu)
1621{
1622 decode_configs(c);
1623
8ff374b9 1624 if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_NETLOGIC_AU13XX) {
809f36c6
ML		 1625 c->cputype = CPU_ALCHEMY;
1626 __cpu_name[cpu] = "Au1300";
1627 /* following stuff is not for Alchemy */
1628 return;
1629 }
1630
70342287
RB		 1631 c->options = (MIPS_CPU_TLB |
1632 MIPS_CPU_4KEX |
a7117c6b 1633 MIPS_CPU_COUNTER |
70342287
RB		 1634 MIPS_CPU_DIVEC |
1635 MIPS_CPU_WATCH |
1636 MIPS_CPU_EJTAG |
a7117c6b
J		 1637 MIPS_CPU_LLSC);
1638
8ff374b9 1639 switch (c->processor_id & PRID_IMP_MASK) {
4ca86a2f 1640 case PRID_IMP_NETLOGIC_XLP2XX:
8907c55e 1641 case PRID_IMP_NETLOGIC_XLP9XX:
1c983986 1642 case PRID_IMP_NETLOGIC_XLP5XX:
4ca86a2f
J		 1643 c->cputype = CPU_XLP;
1644 __cpu_name[cpu] = "Broadcom XLPII";
1645 break;
1646
2aa54b20
J		 1647 case PRID_IMP_NETLOGIC_XLP8XX:
1648 case PRID_IMP_NETLOGIC_XLP3XX:
a3d4fb2d
J		 1649 c->cputype = CPU_XLP;
1650 __cpu_name[cpu] = "Netlogic XLP";
1651 break;
1652
a7117c6b
J		 1653 case PRID_IMP_NETLOGIC_XLR732:
1654 case PRID_IMP_NETLOGIC_XLR716:
1655 case PRID_IMP_NETLOGIC_XLR532:
1656 case PRID_IMP_NETLOGIC_XLR308:
1657 case PRID_IMP_NETLOGIC_XLR532C:
1658 case PRID_IMP_NETLOGIC_XLR516C:
1659 case PRID_IMP_NETLOGIC_XLR508C:
1660 case PRID_IMP_NETLOGIC_XLR308C:
1661 c->cputype = CPU_XLR;
1662 __cpu_name[cpu] = "Netlogic XLR";
1663 break;
1664
1665 case PRID_IMP_NETLOGIC_XLS608:
1666 case PRID_IMP_NETLOGIC_XLS408:
1667 case PRID_IMP_NETLOGIC_XLS404:
1668 case PRID_IMP_NETLOGIC_XLS208:
1669 case PRID_IMP_NETLOGIC_XLS204:
1670 case PRID_IMP_NETLOGIC_XLS108:
1671 case PRID_IMP_NETLOGIC_XLS104:
1672 case PRID_IMP_NETLOGIC_XLS616B:
1673 case PRID_IMP_NETLOGIC_XLS608B:
1674 case PRID_IMP_NETLOGIC_XLS416B:
1675 case PRID_IMP_NETLOGIC_XLS412B:
1676 case PRID_IMP_NETLOGIC_XLS408B:
1677 case PRID_IMP_NETLOGIC_XLS404B:
1678 c->cputype = CPU_XLR;
1679 __cpu_name[cpu] = "Netlogic XLS";
1680 break;
1681
1682 default:
a3d4fb2d 1683 pr_info("Unknown Netlogic chip id [%02x]!\n",
a7117c6b
J		 1684 c->processor_id);
1685 c->cputype = CPU_XLR;
1686 break;
1687 }
1688
a3d4fb2d 1689 if (c->cputype == CPU_XLP) {
a96102be 1690 set_isa(c, MIPS_CPU_ISA_M64R2);
a3d4fb2d
J		 1691 c->options |= (MIPS_CPU_FPU | MIPS_CPU_ULRI | MIPS_CPU_MCHECK);
1692 /* This will be updated again after all threads are woken up */
1693 c->tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1;
1694 } else {
a96102be 1695 set_isa(c, MIPS_CPU_ISA_M64R1);
a3d4fb2d
J		 1696 c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1;
1697 }
7777b939 1698 c->kscratch_mask = 0xf;
a7117c6b
J		 1699}
1700
949e51be
DD		 1701#ifdef CONFIG_64BIT
1702/* For use by uaccess.h */
1703u64 __ua_limit;
1704EXPORT_SYMBOL(__ua_limit);
1705#endif
1706
9966db25 1707const char *__cpu_name[NR_CPUS];
874fd3b5 1708const char *__elf_platform;
9966db25 1709
078a55fc 1710void cpu_probe(void)
1da177e4
LT		 1711{
1712 struct cpuinfo_mips *c = &current_cpu_data;
9966db25 1713 unsigned int cpu = smp_processor_id();
1da177e4 1714
70342287 1715 c->processor_id = PRID_IMP_UNKNOWN;
1da177e4
LT		 1716 c->fpu_id = FPIR_IMP_NONE;
1717 c->cputype = CPU_UNKNOWN;
4f12b91d 1718 c->writecombine = _CACHE_UNCACHED;
1da177e4 1719
9b26616c
MR		 1720 c->fpu_csr31 = FPU_CSR_RN;
1721 c->fpu_msk31 = FPU_CSR_RSVD | FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
1722
1da177e4 1723 c->processor_id = read_c0_prid();
8ff374b9 1724 switch (c->processor_id & PRID_COMP_MASK) {
1da177e4 1725 case PRID_COMP_LEGACY:
cea7e2df 1726 cpu_probe_legacy(c, cpu);
1da177e4
LT		 1727 break;
1728 case PRID_COMP_MIPS:
cea7e2df 1729 cpu_probe_mips(c, cpu);
1da177e4
LT		 1730 break;
1731 case PRID_COMP_ALCHEMY:
cea7e2df 1732 cpu_probe_alchemy(c, cpu);
1da177e4
LT		 1733 break;
1734 case PRID_COMP_SIBYTE:
cea7e2df 1735 cpu_probe_sibyte(c, cpu);
1da177e4 1736 break;
1c0c13eb 1737 case PRID_COMP_BROADCOM:
cea7e2df 1738 cpu_probe_broadcom(c, cpu);
1c0c13eb 1739 break;
1da177e4 1740 case PRID_COMP_SANDCRAFT:
cea7e2df 1741 cpu_probe_sandcraft(c, cpu);
1da177e4 1742 break;
a92b0588 1743 case PRID_COMP_NXP:
cea7e2df 1744 cpu_probe_nxp(c, cpu);
a3dddd56 1745 break;
0dd4781b
DD		 1746 case PRID_COMP_CAVIUM:
1747 cpu_probe_cavium(c, cpu);
1748 break;
b2edcfc8
HC		 1749 case PRID_COMP_LOONGSON:
1750 cpu_probe_loongson(c, cpu);
1751 break;
252617a4
PB		 1752 case PRID_COMP_INGENIC_D0:
1753 case PRID_COMP_INGENIC_D1:
1754 case PRID_COMP_INGENIC_E1:
83ccf69d
LPC		 1755 cpu_probe_ingenic(c, cpu);
1756 break;
a7117c6b
J		 1757 case PRID_COMP_NETLOGIC:
1758 cpu_probe_netlogic(c, cpu);
1759 break;
1da177e4 1760 }
dec8b1ca 1761
cea7e2df
RB		 1762 BUG_ON(!__cpu_name[cpu]);
1763 BUG_ON(c->cputype == CPU_UNKNOWN);
1764
dec8b1ca
FBH		 1765 /*
1766 * Platform code can force the cpu type to optimize code
1767 * generation. In that case be sure the cpu type is correctly
1768 * manually setup otherwise it could trigger some nasty bugs.
1769 */
1770 BUG_ON(current_cpu_type() != c->cputype);
1771
2e274768
FF		 1772 if (cpu_has_rixi) {
1773 /* Enable the RIXI exceptions */
1774 set_c0_pagegrain(PG_IEC);
1775 back_to_back_c0_hazard();
1776 /* Verify the IEC bit is set */
1777 if (read_c0_pagegrain() & PG_IEC)
1778 c->options |= MIPS_CPU_RIXIEX;
1779 }
1780
0103d23f
KC		 1781 if (mips_fpu_disabled)
1782 c->options &= ~MIPS_CPU_FPU;
1783
1784 if (mips_dsp_disabled)
ee80f7c7 1785 c->ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
0103d23f 1786
3d528b32
MC		 1787 if (mips_htw_disabled) {
1788 c->options &= ~MIPS_CPU_HTW;
1789 write_c0_pwctl(read_c0_pwctl() &
1790 ~(1 << MIPS_PWCTL_PWEN_SHIFT));
1791 }
1792
7aecd5ca
MR		 1793 if (c->options & MIPS_CPU_FPU)
1794 cpu_set_fpu_opts(c);
1795 else
1796 cpu_set_nofpu_opts(c);
9966db25 1797
8d5ded16
JK		 1798 if (cpu_has_bp_ghist)
1799 write_c0_r10k_diag(read_c0_r10k_diag() |
1800 R10K_DIAG_E_GHIST);
1801
8b8aa636 1802 if (cpu_has_mips_r2_r6) {
f6771dbb 1803 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
da4b62cd
AC		 1804 /* R2 has Performance Counter Interrupt indicator */
1805 c->options |= MIPS_CPU_PCI;
1806 }
f6771dbb
RB		 1807 else
1808 c->srsets = 1;
91dfc423 1809
4c063034
PB		 1810 if (cpu_has_mips_r6)
1811 elf_hwcap |= HWCAP_MIPS_R6;
1812
a8ad1367 1813 if (cpu_has_msa) {
a5e9a69e 1814 c->msa_id = cpu_get_msa_id();
a8ad1367
PB		 1815 WARN(c->msa_id & MSA_IR_WRPF,
1816 "Vector register partitioning unimplemented!");
3cc9fa7f 1817 elf_hwcap |= HWCAP_MIPS_MSA;
a8ad1367 1818 }
a5e9a69e 1819
91dfc423 1820 cpu_probe_vmbits(c);
949e51be
DD		 1821
1822#ifdef CONFIG_64BIT
1823 if (cpu == 0)
1824 __ua_limit = ~((1ull << cpu_vmbits) - 1);
1825#endif
1da177e4
LT		 1826}
1827
078a55fc 1828void cpu_report(void)
1da177e4
LT		 1829{
1830 struct cpuinfo_mips *c = &current_cpu_data;
1831
d9f897c9
LY		 1832 pr_info("CPU%d revision is: %08x (%s)\n",
1833 smp_processor_id(), c->processor_id, cpu_name_string());
1da177e4 1834 if (c->options & MIPS_CPU_FPU)
9966db25 1835 printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id);
a5e9a69e
PB		 1836 if (cpu_has_msa)
1837 pr_info("MSA revision is: %08x\n", c->msa_id);
1da177e4 1838}
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