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MIPS: Fix a typo error in AUDIT_ARCH definition
[mirror_ubuntu-zesty-kernel.git] / arch / mips / kernel / cpu-probe.c
CommitLineData
1da177e4
LT		 1/*
2 * Processor capabilities determination functions.
3 *
4 * Copyright (C) xxxx the Anonymous
010b853b 5 * Copyright (C) 1994 - 2006 Ralf Baechle
4194318c 6 * Copyright (C) 2003, 2004 Maciej W. Rozycki
70342287 7 * Copyright (C) 2001, 2004, 2011, 2012 MIPS Technologies, Inc.
1da177e4
LT		 8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
13 */
1da177e4
LT		 14#include <linux/init.h>
15#include <linux/kernel.h>
16#include <linux/ptrace.h>
631330f5 17#include <linux/smp.h>
1da177e4 18#include <linux/stddef.h>
73bc256d 19#include <linux/export.h>
1da177e4 20
5759906c 21#include <asm/bugs.h>
1da177e4 22#include <asm/cpu.h>
69f24d17 23#include <asm/cpu-type.h>
1da177e4
LT		 24#include <asm/fpu.h>
25#include <asm/mipsregs.h>
30ee615b 26#include <asm/mipsmtregs.h>
a5e9a69e 27#include <asm/msa.h>
654f57bf 28#include <asm/watch.h>
06372a63 29#include <asm/elf.h>
a074f0e8 30#include <asm/spram.h>
949e51be
DD		 31#include <asm/uaccess.h>
32
078a55fc 33static int mips_fpu_disabled;
0103d23f
KC		 34
35static int __init fpu_disable(char *s)
36{
37 cpu_data[0].options &= ~MIPS_CPU_FPU;
38 mips_fpu_disabled = 1;
39
40 return 1;
41}
42
43__setup("nofpu", fpu_disable);
44
078a55fc 45int mips_dsp_disabled;
0103d23f
KC		 46
47static int __init dsp_disable(char *s)
48{
ee80f7c7 49 cpu_data[0].ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
0103d23f
KC		 50 mips_dsp_disabled = 1;
51
52 return 1;
53}
54
55__setup("nodsp", dsp_disable);
56
9267a30d
MSJ		 57static inline void check_errata(void)
58{
59 struct cpuinfo_mips *c = &current_cpu_data;
60
69f24d17 61 switch (current_cpu_type()) {
9267a30d
MSJ		 62 case CPU_34K:
63 /*
64 * Erratum "RPS May Cause Incorrect Instruction Execution"
65 * This code only handles VPE0, any SMP/SMTC/RTOS code
66 * making use of VPE1 will be responsable for that VPE.
67 */
68 if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2)
69 write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS);
70 break;
71 default:
72 break;
73 }
74}
75
1da177e4
LT		 76void __init check_bugs32(void)
77{
9267a30d 78 check_errata();
1da177e4
LT		 79}
80
81/*
82 * Probe whether cpu has config register by trying to play with
83 * alternate cache bit and see whether it matters.
84 * It's used by cpu_probe to distinguish between R3000A and R3081.
85 */
86static inline int cpu_has_confreg(void)
87{
88#ifdef CONFIG_CPU_R3000
89 extern unsigned long r3k_cache_size(unsigned long);
90 unsigned long size1, size2;
91 unsigned long cfg = read_c0_conf();
92
93 size1 = r3k_cache_size(ST0_ISC);
94 write_c0_conf(cfg ^ R30XX_CONF_AC);
95 size2 = r3k_cache_size(ST0_ISC);
96 write_c0_conf(cfg);
97 return size1 != size2;
98#else
99 return 0;
100#endif
101}
102
c094c99e
RM		 103static inline void set_elf_platform(int cpu, const char *plat)
104{
105 if (cpu == 0)
106 __elf_platform = plat;
107}
108
1da177e4
LT		 109/*
110 * Get the FPU Implementation/Revision.
111 */
112static inline unsigned long cpu_get_fpu_id(void)
113{
114 unsigned long tmp, fpu_id;
115
116 tmp = read_c0_status();
597ce172 117 __enable_fpu(FPU_AS_IS);
1da177e4
LT		 118 fpu_id = read_32bit_cp1_register(CP1_REVISION);
119 write_c0_status(tmp);
120 return fpu_id;
121}
122
123/*
124 * Check the CPU has an FPU the official way.
125 */
126static inline int __cpu_has_fpu(void)
127{
8ff374b9 128 return ((cpu_get_fpu_id() & FPIR_IMP_MASK) != FPIR_IMP_NONE);
1da177e4
LT		 129}
130
a5e9a69e
PB		 131static inline unsigned long cpu_get_msa_id(void)
132{
133 unsigned long status, conf5, msa_id;
134
135 status = read_c0_status();
136 __enable_fpu(FPU_64BIT);
137 conf5 = read_c0_config5();
138 enable_msa();
139 msa_id = read_msa_ir();
140 write_c0_config5(conf5);
141 write_c0_status(status);
142 return msa_id;
143}
144
91dfc423
GR		 145static inline void cpu_probe_vmbits(struct cpuinfo_mips *c)
146{
147#ifdef __NEED_VMBITS_PROBE
5b7efa89 148 write_c0_entryhi(0x3fffffffffffe000ULL);
91dfc423 149 back_to_back_c0_hazard();
5b7efa89 150 c->vmbits = fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL);
91dfc423
GR		 151#endif
152}
153
078a55fc 154static void set_isa(struct cpuinfo_mips *c, unsigned int isa)
a96102be
SH		 155{
156 switch (isa) {
157 case MIPS_CPU_ISA_M64R2:
158 c->isa_level |= MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2;
159 case MIPS_CPU_ISA_M64R1:
160 c->isa_level |= MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1;
161 case MIPS_CPU_ISA_V:
162 c->isa_level |= MIPS_CPU_ISA_V;
163 case MIPS_CPU_ISA_IV:
164 c->isa_level |= MIPS_CPU_ISA_IV;
165 case MIPS_CPU_ISA_III:
1990e542 166 c->isa_level |= MIPS_CPU_ISA_II | MIPS_CPU_ISA_III;
a96102be
SH		 167 break;
168
169 case MIPS_CPU_ISA_M32R2:
170 c->isa_level |= MIPS_CPU_ISA_M32R2;
171 case MIPS_CPU_ISA_M32R1:
172 c->isa_level |= MIPS_CPU_ISA_M32R1;
173 case MIPS_CPU_ISA_II:
174 c->isa_level |= MIPS_CPU_ISA_II;
a96102be
SH		 175 break;
176 }
177}
178
078a55fc 179static char unknown_isa[] = KERN_ERR \
2fa36399
KC		 180 "Unsupported ISA type, c0.config0: %d.";
181
75b5b5e0
LY		 182static void set_ftlb_enable(struct cpuinfo_mips *c, int enable)
183{
184 unsigned int config6;
d83b0e82
JH		 185
186 /* It's implementation dependent how the FTLB can be enabled */
187 switch (c->cputype) {
188 case CPU_PROAPTIV:
189 case CPU_P5600:
190 /* proAptiv & related cores use Config6 to enable the FTLB */
75b5b5e0
LY		 191 config6 = read_c0_config6();
192 if (enable)
193 /* Enable FTLB */
194 write_c0_config6(config6 | MIPS_CONF6_FTLBEN);
195 else
196 /* Disable FTLB */
197 write_c0_config6(config6 & ~MIPS_CONF6_FTLBEN);
198 back_to_back_c0_hazard();
d83b0e82 199 break;
75b5b5e0
LY		 200 }
201}
202
2fa36399
KC		 203static inline unsigned int decode_config0(struct cpuinfo_mips *c)
204{
205 unsigned int config0;
206 int isa;
207
208 config0 = read_c0_config();
209
75b5b5e0
LY		 210 /*
211 * Look for Standard TLB or Dual VTLB and FTLB
212 */
213 if ((((config0 & MIPS_CONF_MT) >> 7) == 1) ||
214 (((config0 & MIPS_CONF_MT) >> 7) == 4))
2fa36399 215 c->options |= MIPS_CPU_TLB;
75b5b5e0 216
2fa36399
KC		 217 isa = (config0 & MIPS_CONF_AT) >> 13;
218 switch (isa) {
219 case 0:
220 switch ((config0 & MIPS_CONF_AR) >> 10) {
221 case 0:
a96102be 222 set_isa(c, MIPS_CPU_ISA_M32R1);
2fa36399
KC		 223 break;
224 case 1:
a96102be 225 set_isa(c, MIPS_CPU_ISA_M32R2);
2fa36399
KC		 226 break;
227 default:
228 goto unknown;
229 }
230 break;
231 case 2:
232 switch ((config0 & MIPS_CONF_AR) >> 10) {
233 case 0:
a96102be 234 set_isa(c, MIPS_CPU_ISA_M64R1);
2fa36399
KC		 235 break;
236 case 1:
a96102be 237 set_isa(c, MIPS_CPU_ISA_M64R2);
2fa36399
KC		 238 break;
239 default:
240 goto unknown;
241 }
242 break;
243 default:
244 goto unknown;
245 }
246
247 return config0 & MIPS_CONF_M;
248
249unknown:
250 panic(unknown_isa, config0);
251}
252
253static inline unsigned int decode_config1(struct cpuinfo_mips *c)
254{
255 unsigned int config1;
256
257 config1 = read_c0_config1();
258
259 if (config1 & MIPS_CONF1_MD)
260 c->ases |= MIPS_ASE_MDMX;
261 if (config1 & MIPS_CONF1_WR)
262 c->options |= MIPS_CPU_WATCH;
263 if (config1 & MIPS_CONF1_CA)
264 c->ases |= MIPS_ASE_MIPS16;
265 if (config1 & MIPS_CONF1_EP)
266 c->options |= MIPS_CPU_EJTAG;
267 if (config1 & MIPS_CONF1_FP) {
268 c->options |= MIPS_CPU_FPU;
269 c->options |= MIPS_CPU_32FPR;
270 }
75b5b5e0 271 if (cpu_has_tlb) {
2fa36399 272 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;
75b5b5e0
LY		 273 c->tlbsizevtlb = c->tlbsize;
274 c->tlbsizeftlbsets = 0;
275 }
2fa36399
KC		 276
277 return config1 & MIPS_CONF_M;
278}
279
280static inline unsigned int decode_config2(struct cpuinfo_mips *c)
281{
282 unsigned int config2;
283
284 config2 = read_c0_config2();
285
286 if (config2 & MIPS_CONF2_SL)
287 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
288
289 return config2 & MIPS_CONF_M;
290}
291
292static inline unsigned int decode_config3(struct cpuinfo_mips *c)
293{
294 unsigned int config3;
295
296 config3 = read_c0_config3();
297
b2ab4f08 298 if (config3 & MIPS_CONF3_SM) {
2fa36399 299 c->ases |= MIPS_ASE_SMARTMIPS;
b2ab4f08
SH		 300 c->options |= MIPS_CPU_RIXI;
301 }
302 if (config3 & MIPS_CONF3_RXI)
303 c->options |= MIPS_CPU_RIXI;
2fa36399
KC		 304 if (config3 & MIPS_CONF3_DSP)
305 c->ases |= MIPS_ASE_DSP;
ee80f7c7
SH		 306 if (config3 & MIPS_CONF3_DSP2P)
307 c->ases |= MIPS_ASE_DSP2P;
2fa36399
KC		 308 if (config3 & MIPS_CONF3_VINT)
309 c->options |= MIPS_CPU_VINT;
310 if (config3 & MIPS_CONF3_VEIC)
311 c->options |= MIPS_CPU_VEIC;
312 if (config3 & MIPS_CONF3_MT)
313 c->ases |= MIPS_ASE_MIPSMT;
314 if (config3 & MIPS_CONF3_ULRI)
315 c->options |= MIPS_CPU_ULRI;
f8fa4811
SH		 316 if (config3 & MIPS_CONF3_ISA)
317 c->options |= MIPS_CPU_MICROMIPS;
1e7decdb
DD		 318 if (config3 & MIPS_CONF3_VZ)
319 c->ases |= MIPS_ASE_VZ;
4a0156fb
SH		 320 if (config3 & MIPS_CONF3_SC)
321 c->options |= MIPS_CPU_SEGMENTS;
a5e9a69e
PB		 322 if (config3 & MIPS_CONF3_MSA)
323 c->ases |= MIPS_ASE_MSA;
2fa36399
KC		 324
325 return config3 & MIPS_CONF_M;
326}
327
328static inline unsigned int decode_config4(struct cpuinfo_mips *c)
329{
330 unsigned int config4;
75b5b5e0
LY		 331 unsigned int newcf4;
332 unsigned int mmuextdef;
333 unsigned int ftlb_page = MIPS_CONF4_FTLBPAGESIZE;
2fa36399
KC		 334
335 config4 = read_c0_config4();
336
1745c1ef
LY		 337 if (cpu_has_tlb) {
338 if (((config4 & MIPS_CONF4_IE) >> 29) == 2)
339 c->options |= MIPS_CPU_TLBINV;
75b5b5e0
LY		 340 mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF;
341 switch (mmuextdef) {
342 case MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT:
343 c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40;
344 c->tlbsizevtlb = c->tlbsize;
345 break;
346 case MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT:
347 c->tlbsizevtlb +=
348 ((config4 & MIPS_CONF4_VTLBSIZEEXT) >>
349 MIPS_CONF4_VTLBSIZEEXT_SHIFT) * 0x40;
350 c->tlbsize = c->tlbsizevtlb;
351 ftlb_page = MIPS_CONF4_VFTLBPAGESIZE;
352 /* fall through */
353 case MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT:
354 newcf4 = (config4 & ~ftlb_page) |
355 (page_size_ftlb(mmuextdef) <<
356 MIPS_CONF4_FTLBPAGESIZE_SHIFT);
357 write_c0_config4(newcf4);
358 back_to_back_c0_hazard();
359 config4 = read_c0_config4();
360 if (config4 != newcf4) {
361 pr_err("PAGE_SIZE 0x%lx is not supported by FTLB (config4=0x%x)\n",
362 PAGE_SIZE, config4);
363 /* Switch FTLB off */
364 set_ftlb_enable(c, 0);
365 break;
366 }
367 c->tlbsizeftlbsets = 1 <<
368 ((config4 & MIPS_CONF4_FTLBSETS) >>
369 MIPS_CONF4_FTLBSETS_SHIFT);
370 c->tlbsizeftlbways = ((config4 & MIPS_CONF4_FTLBWAYS) >>
371 MIPS_CONF4_FTLBWAYS_SHIFT) + 2;
372 c->tlbsize += c->tlbsizeftlbways * c->tlbsizeftlbsets;
373 break;
374 }
1745c1ef
LY		 375 }
376
2fa36399
KC		 377 c->kscratch_mask = (config4 >> 16) & 0xff;
378
379 return config4 & MIPS_CONF_M;
380}
381
8b8a7634
RB		 382static inline unsigned int decode_config5(struct cpuinfo_mips *c)
383{
384 unsigned int config5;
385
386 config5 = read_c0_config5();
387 config5 &= ~MIPS_CONF5_UFR;
388 write_c0_config5(config5);
389
49016748
MC		 390 if (config5 & MIPS_CONF5_EVA)
391 c->options |= MIPS_CPU_EVA;
392
8b8a7634
RB		 393 return config5 & MIPS_CONF_M;
394}
395
078a55fc 396static void decode_configs(struct cpuinfo_mips *c)
2fa36399
KC		 397{
398 int ok;
399
400 /* MIPS32 or MIPS64 compliant CPU. */
401 c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
402 MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
403
404 c->scache.flags = MIPS_CACHE_NOT_PRESENT;
405
75b5b5e0
LY		 406 /* Enable FTLB if present */
407 set_ftlb_enable(c, 1);
408
2fa36399 409 ok = decode_config0(c); /* Read Config registers. */
70342287 410 BUG_ON(!ok); /* Arch spec violation! */
2fa36399
KC		 411 if (ok)
412 ok = decode_config1(c);
413 if (ok)
414 ok = decode_config2(c);
415 if (ok)
416 ok = decode_config3(c);
417 if (ok)
418 ok = decode_config4(c);
8b8a7634
RB		 419 if (ok)
420 ok = decode_config5(c);
2fa36399
KC		 421
422 mips_probe_watch_registers(c);
423
0ee958e1 424#ifndef CONFIG_MIPS_CPS
30ee615b 425 if (cpu_has_mips_r2) {
2fa36399 426 c->core = read_c0_ebase() & 0x3ff;
30ee615b
PB		 427 if (cpu_has_mipsmt)
428 c->core >>= fls(core_nvpes()) - 1;
429 }
0ee958e1 430#endif
2fa36399
KC		 431}
432
02cf2119 433#define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
1da177e4
LT		 434 | MIPS_CPU_COUNTER)
435
cea7e2df 436static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4 437{
8ff374b9 438 switch (c->processor_id & PRID_IMP_MASK) {
1da177e4
LT		 439 case PRID_IMP_R2000:
440 c->cputype = CPU_R2000;
cea7e2df 441 __cpu_name[cpu] = "R2000";
02cf2119 442 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
03751e79 443 MIPS_CPU_NOFPUEX;
1da177e4
LT		 444 if (__cpu_has_fpu())
445 c->options |= MIPS_CPU_FPU;
446 c->tlbsize = 64;
447 break;
448 case PRID_IMP_R3000:
8ff374b9 449 if ((c->processor_id & PRID_REV_MASK) == PRID_REV_R3000A) {
cea7e2df 450 if (cpu_has_confreg()) {
1da177e4 451 c->cputype = CPU_R3081E;
cea7e2df
RB		 452 __cpu_name[cpu] = "R3081";
453 } else {
1da177e4 454 c->cputype = CPU_R3000A;
cea7e2df
RB		 455 __cpu_name[cpu] = "R3000A";
456 }
cea7e2df 457 } else {
1da177e4 458 c->cputype = CPU_R3000;
cea7e2df
RB		 459 __cpu_name[cpu] = "R3000";
460 }
02cf2119 461 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
03751e79 462 MIPS_CPU_NOFPUEX;
1da177e4
LT		 463 if (__cpu_has_fpu())
464 c->options |= MIPS_CPU_FPU;
465 c->tlbsize = 64;
466 break;
467 case PRID_IMP_R4000:
468 if (read_c0_config() & CONF_SC) {
8ff374b9
MR		 469 if ((c->processor_id & PRID_REV_MASK) >=
470 PRID_REV_R4400) {
1da177e4 471 c->cputype = CPU_R4400PC;
cea7e2df
RB		 472 __cpu_name[cpu] = "R4400PC";
473 } else {
1da177e4 474 c->cputype = CPU_R4000PC;
cea7e2df
RB		 475 __cpu_name[cpu] = "R4000PC";
476 }
1da177e4 477 } else {
7f177a52
MR		 478 int cca = read_c0_config() & CONF_CM_CMASK;
479 int mc;
480
481 /*
482 * SC and MC versions can't be reliably told apart,
483 * but only the latter support coherent caching
484 * modes so assume the firmware has set the KSEG0
485 * coherency attribute reasonably (if uncached, we
486 * assume SC).
487 */
488 switch (cca) {
489 case CONF_CM_CACHABLE_CE:
490 case CONF_CM_CACHABLE_COW:
491 case CONF_CM_CACHABLE_CUW:
492 mc = 1;
493 break;
494 default:
495 mc = 0;
496 break;
497 }
8ff374b9
MR		 498 if ((c->processor_id & PRID_REV_MASK) >=
499 PRID_REV_R4400) {
7f177a52
MR		 500 c->cputype = mc ? CPU_R4400MC : CPU_R4400SC;
501 __cpu_name[cpu] = mc ? "R4400MC" : "R4400SC";
cea7e2df 502 } else {
7f177a52
MR		 503 c->cputype = mc ? CPU_R4000MC : CPU_R4000SC;
504 __cpu_name[cpu] = mc ? "R4000MC" : "R4000SC";
cea7e2df 505 }
1da177e4
LT		 506 }
507
a96102be 508 set_isa(c, MIPS_CPU_ISA_III);
1da177e4 509 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79
SH		 510 MIPS_CPU_WATCH | MIPS_CPU_VCE |
511 MIPS_CPU_LLSC;
1da177e4
LT		 512 c->tlbsize = 48;
513 break;
514 case PRID_IMP_VR41XX:
9f91e506
YY		 515 set_isa(c, MIPS_CPU_ISA_III);
516 c->options = R4K_OPTS;
517 c->tlbsize = 32;
1da177e4 518 switch (c->processor_id & 0xf0) {
1da177e4
LT		 519 case PRID_REV_VR4111:
520 c->cputype = CPU_VR4111;
cea7e2df 521 __cpu_name[cpu] = "NEC VR4111";
1da177e4 522 break;
1da177e4
LT		 523 case PRID_REV_VR4121:
524 c->cputype = CPU_VR4121;
cea7e2df 525 __cpu_name[cpu] = "NEC VR4121";
1da177e4
LT		 526 break;
527 case PRID_REV_VR4122:
cea7e2df 528 if ((c->processor_id & 0xf) < 0x3) {
1da177e4 529 c->cputype = CPU_VR4122;
cea7e2df
RB		 530 __cpu_name[cpu] = "NEC VR4122";
531 } else {
1da177e4 532 c->cputype = CPU_VR4181A;
cea7e2df
RB		 533 __cpu_name[cpu] = "NEC VR4181A";
534 }
1da177e4
LT		 535 break;
536 case PRID_REV_VR4130:
cea7e2df 537 if ((c->processor_id & 0xf) < 0x4) {
1da177e4 538 c->cputype = CPU_VR4131;
cea7e2df
RB		 539 __cpu_name[cpu] = "NEC VR4131";
540 } else {
1da177e4 541 c->cputype = CPU_VR4133;
9f91e506 542 c->options |= MIPS_CPU_LLSC;
cea7e2df
RB		 543 __cpu_name[cpu] = "NEC VR4133";
544 }
1da177e4
LT		 545 break;
546 default:
547 printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
548 c->cputype = CPU_VR41XX;
cea7e2df 549 __cpu_name[cpu] = "NEC Vr41xx";
1da177e4
LT		 550 break;
551 }
1da177e4
LT		 552 break;
553 case PRID_IMP_R4300:
554 c->cputype = CPU_R4300;
cea7e2df 555 __cpu_name[cpu] = "R4300";
a96102be 556 set_isa(c, MIPS_CPU_ISA_III);
1da177e4 557 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 558 MIPS_CPU_LLSC;
1da177e4
LT		 559 c->tlbsize = 32;
560 break;
561 case PRID_IMP_R4600:
562 c->cputype = CPU_R4600;
cea7e2df 563 __cpu_name[cpu] = "R4600";
a96102be 564 set_isa(c, MIPS_CPU_ISA_III);
075e7502
TS		 565 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
566 MIPS_CPU_LLSC;
1da177e4
LT		 567 c->tlbsize = 48;
568 break;
569 #if 0
03751e79 570 case PRID_IMP_R4650:
1da177e4
LT		 571 /*
572 * This processor doesn't have an MMU, so it's not
573 * "real easy" to run Linux on it. It is left purely
574 * for documentation. Commented out because it shares
575 * it's c0_prid id number with the TX3900.
576 */
a3dddd56 577 c->cputype = CPU_R4650;
cea7e2df 578 __cpu_name[cpu] = "R4650";
a96102be 579 set_isa(c, MIPS_CPU_ISA_III);
1da177e4 580 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
03751e79 581 c->tlbsize = 48;
1da177e4
LT		 582 break;
583 #endif
584 case PRID_IMP_TX39:
02cf2119 585 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE;
1da177e4
LT		 586
587 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
588 c->cputype = CPU_TX3927;
cea7e2df 589 __cpu_name[cpu] = "TX3927";
1da177e4
LT		 590 c->tlbsize = 64;
591 } else {
8ff374b9 592 switch (c->processor_id & PRID_REV_MASK) {
1da177e4
LT		 593 case PRID_REV_TX3912:
594 c->cputype = CPU_TX3912;
cea7e2df 595 __cpu_name[cpu] = "TX3912";
1da177e4
LT		 596 c->tlbsize = 32;
597 break;
598 case PRID_REV_TX3922:
599 c->cputype = CPU_TX3922;
cea7e2df 600 __cpu_name[cpu] = "TX3922";
1da177e4
LT		 601 c->tlbsize = 64;
602 break;
1da177e4
LT		 603 }
604 }
605 break;
606 case PRID_IMP_R4700:
607 c->cputype = CPU_R4700;
cea7e2df 608 __cpu_name[cpu] = "R4700";
a96102be 609 set_isa(c, MIPS_CPU_ISA_III);
1da177e4 610 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 611 MIPS_CPU_LLSC;
1da177e4
LT		 612 c->tlbsize = 48;
613 break;
614 case PRID_IMP_TX49:
615 c->cputype = CPU_TX49XX;
cea7e2df 616 __cpu_name[cpu] = "R49XX";
a96102be 617 set_isa(c, MIPS_CPU_ISA_III);
1da177e4
LT		 618 c->options = R4K_OPTS | MIPS_CPU_LLSC;
619 if (!(c->processor_id & 0x08))
620 c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
621 c->tlbsize = 48;
622 break;
623 case PRID_IMP_R5000:
624 c->cputype = CPU_R5000;
cea7e2df 625 __cpu_name[cpu] = "R5000";
a96102be 626 set_isa(c, MIPS_CPU_ISA_IV);
1da177e4 627 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 628 MIPS_CPU_LLSC;
1da177e4
LT		 629 c->tlbsize = 48;
630 break;
631 case PRID_IMP_R5432:
632 c->cputype = CPU_R5432;
cea7e2df 633 __cpu_name[cpu] = "R5432";
a96102be 634 set_isa(c, MIPS_CPU_ISA_IV);
1da177e4 635 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 636 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
1da177e4
LT		 637 c->tlbsize = 48;
638 break;
639 case PRID_IMP_R5500:
640 c->cputype = CPU_R5500;
cea7e2df 641 __cpu_name[cpu] = "R5500";
a96102be 642 set_isa(c, MIPS_CPU_ISA_IV);
1da177e4 643 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 644 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
1da177e4
LT		 645 c->tlbsize = 48;
646 break;
647 case PRID_IMP_NEVADA:
648 c->cputype = CPU_NEVADA;
cea7e2df 649 __cpu_name[cpu] = "Nevada";
a96102be 650 set_isa(c, MIPS_CPU_ISA_IV);
1da177e4 651 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 652 MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
1da177e4
LT		 653 c->tlbsize = 48;
654 break;
655 case PRID_IMP_R6000:
656 c->cputype = CPU_R6000;
cea7e2df 657 __cpu_name[cpu] = "R6000";
a96102be 658 set_isa(c, MIPS_CPU_ISA_II);
1da177e4 659 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
03751e79 660 MIPS_CPU_LLSC;
1da177e4
LT		 661 c->tlbsize = 32;
662 break;
663 case PRID_IMP_R6000A:
664 c->cputype = CPU_R6000A;
cea7e2df 665 __cpu_name[cpu] = "R6000A";
a96102be 666 set_isa(c, MIPS_CPU_ISA_II);
1da177e4 667 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
03751e79 668 MIPS_CPU_LLSC;
1da177e4
LT		 669 c->tlbsize = 32;
670 break;
671 case PRID_IMP_RM7000:
672 c->cputype = CPU_RM7000;
cea7e2df 673 __cpu_name[cpu] = "RM7000";
a96102be 674 set_isa(c, MIPS_CPU_ISA_IV);
1da177e4 675 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 676 MIPS_CPU_LLSC;
1da177e4 677 /*
70342287 678 * Undocumented RM7000: Bit 29 in the info register of
1da177e4
LT		 679 * the RM7000 v2.0 indicates if the TLB has 48 or 64
680 * entries.
681 *
70342287
RB		 682 * 29 1 => 64 entry JTLB
683 * 0 => 48 entry JTLB
1da177e4
LT		 684 */
685 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
1da177e4
LT		 686 break;
687 case PRID_IMP_R8000:
688 c->cputype = CPU_R8000;
cea7e2df 689 __cpu_name[cpu] = "RM8000";
a96102be 690 set_isa(c, MIPS_CPU_ISA_IV);
1da177e4 691 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
03751e79
SH		 692 MIPS_CPU_FPU | MIPS_CPU_32FPR |
693 MIPS_CPU_LLSC;
1da177e4
LT		 694 c->tlbsize = 384; /* has weird TLB: 3-way x 128 */
695 break;
696 case PRID_IMP_R10000:
697 c->cputype = CPU_R10000;
cea7e2df 698 __cpu_name[cpu] = "R10000";
a96102be 699 set_isa(c, MIPS_CPU_ISA_IV);
8b36612a 700 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
03751e79 701 MIPS_CPU_FPU | MIPS_CPU_32FPR |
1da177e4 702 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
03751e79 703 MIPS_CPU_LLSC;
1da177e4
LT		 704 c->tlbsize = 64;
705 break;
706 case PRID_IMP_R12000:
707 c->cputype = CPU_R12000;
cea7e2df 708 __cpu_name[cpu] = "R12000";
a96102be 709 set_isa(c, MIPS_CPU_ISA_IV);
8b36612a 710 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
03751e79 711 MIPS_CPU_FPU | MIPS_CPU_32FPR |
1da177e4 712 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
03751e79 713 MIPS_CPU_LLSC;
1da177e4
LT		 714 c->tlbsize = 64;
715 break;
44d921b2
K		 716 case PRID_IMP_R14000:
717 c->cputype = CPU_R14000;
cea7e2df 718 __cpu_name[cpu] = "R14000";
a96102be 719 set_isa(c, MIPS_CPU_ISA_IV);
44d921b2 720 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
03751e79 721 MIPS_CPU_FPU | MIPS_CPU_32FPR |
44d921b2 722 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
03751e79 723 MIPS_CPU_LLSC;
44d921b2
K		 724 c->tlbsize = 64;
725 break;
26859198 726 case PRID_IMP_LOONGSON_64: /* Loongson-2/3 */
5aac1e8a
RM		 727 switch (c->processor_id & PRID_REV_MASK) {
728 case PRID_REV_LOONGSON2E:
c579d310
HC		 729 c->cputype = CPU_LOONGSON2;
730 __cpu_name[cpu] = "ICT Loongson-2";
5aac1e8a
RM		 731 set_elf_platform(cpu, "loongson2e");
732 break;
733 case PRID_REV_LOONGSON2F:
c579d310
HC		 734 c->cputype = CPU_LOONGSON2;
735 __cpu_name[cpu] = "ICT Loongson-2";
5aac1e8a
RM		 736 set_elf_platform(cpu, "loongson2f");
737 break;
c579d310
HC		 738 case PRID_REV_LOONGSON3A:
739 c->cputype = CPU_LOONGSON3;
740 __cpu_name[cpu] = "ICT Loongson-3";
741 set_elf_platform(cpu, "loongson3a");
742 break;
5aac1e8a
RM		 743 }
744
a96102be 745 set_isa(c, MIPS_CPU_ISA_III);
2a21c730
FZ		 746 c->options = R4K_OPTS |
747 MIPS_CPU_FPU | MIPS_CPU_LLSC |
748 MIPS_CPU_32FPR;
749 c->tlbsize = 64;
750 break;
26859198 751 case PRID_IMP_LOONGSON_32: /* Loongson-1 */
2fa36399 752 decode_configs(c);
b4672d37 753
2fa36399 754 c->cputype = CPU_LOONGSON1;
1da177e4 755
2fa36399
KC		 756 switch (c->processor_id & PRID_REV_MASK) {
757 case PRID_REV_LOONGSON1B:
758 __cpu_name[cpu] = "Loongson 1B";
b4672d37 759 break;
b4672d37 760 }
4194318c 761
2fa36399 762 break;
1da177e4 763 }
1da177e4
LT		 764}
765
cea7e2df 766static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4 767{
8ff374b9 768 switch (c->processor_id & PRID_IMP_MASK) {
1da177e4
LT		 769 case PRID_IMP_4KC:
770 c->cputype = CPU_4KC;
cea7e2df 771 __cpu_name[cpu] = "MIPS 4Kc";
1da177e4
LT		 772 break;
773 case PRID_IMP_4KEC:
2b07bd02
RB		 774 case PRID_IMP_4KECR2:
775 c->cputype = CPU_4KEC;
cea7e2df 776 __cpu_name[cpu] = "MIPS 4KEc";
2b07bd02 777 break;
1da177e4 778 case PRID_IMP_4KSC:
8afcb5d8 779 case PRID_IMP_4KSD:
1da177e4 780 c->cputype = CPU_4KSC;
cea7e2df 781 __cpu_name[cpu] = "MIPS 4KSc";
1da177e4
LT		 782 break;
783 case PRID_IMP_5KC:
784 c->cputype = CPU_5KC;
cea7e2df 785 __cpu_name[cpu] = "MIPS 5Kc";
1da177e4 786 break;
78d4803f
LY		 787 case PRID_IMP_5KE:
788 c->cputype = CPU_5KE;
789 __cpu_name[cpu] = "MIPS 5KE";
790 break;
1da177e4
LT		 791 case PRID_IMP_20KC:
792 c->cputype = CPU_20KC;
cea7e2df 793 __cpu_name[cpu] = "MIPS 20Kc";
1da177e4
LT		 794 break;
795 case PRID_IMP_24K:
796 c->cputype = CPU_24K;
cea7e2df 797 __cpu_name[cpu] = "MIPS 24Kc";
1da177e4 798 break;
42f3caef
JC		 799 case PRID_IMP_24KE:
800 c->cputype = CPU_24K;
801 __cpu_name[cpu] = "MIPS 24KEc";
802 break;
1da177e4
LT		 803 case PRID_IMP_25KF:
804 c->cputype = CPU_25KF;
cea7e2df 805 __cpu_name[cpu] = "MIPS 25Kc";
1da177e4 806 break;
bbc7f22f
RB		 807 case PRID_IMP_34K:
808 c->cputype = CPU_34K;
cea7e2df 809 __cpu_name[cpu] = "MIPS 34Kc";
bbc7f22f 810 break;
c620953c
CD		 811 case PRID_IMP_74K:
812 c->cputype = CPU_74K;
cea7e2df 813 __cpu_name[cpu] = "MIPS 74Kc";
c620953c 814 break;
113c62d9
SH		 815 case PRID_IMP_M14KC:
816 c->cputype = CPU_M14KC;
817 __cpu_name[cpu] = "MIPS M14Kc";
818 break;
f8fa4811
SH		 819 case PRID_IMP_M14KEC:
820 c->cputype = CPU_M14KEC;
821 __cpu_name[cpu] = "MIPS M14KEc";
822 break;
39b8d525
RB		 823 case PRID_IMP_1004K:
824 c->cputype = CPU_1004K;
cea7e2df 825 __cpu_name[cpu] = "MIPS 1004Kc";
39b8d525 826 break;
006a851b 827 case PRID_IMP_1074K:
442e14a2 828 c->cputype = CPU_1074K;
006a851b
SH		 829 __cpu_name[cpu] = "MIPS 1074Kc";
830 break;
b5f065e7
LY		 831 case PRID_IMP_INTERAPTIV_UP:
832 c->cputype = CPU_INTERAPTIV;
833 __cpu_name[cpu] = "MIPS interAptiv";
834 break;
835 case PRID_IMP_INTERAPTIV_MP:
836 c->cputype = CPU_INTERAPTIV;
837 __cpu_name[cpu] = "MIPS interAptiv (multi)";
838 break;
b0d4d300
LY		 839 case PRID_IMP_PROAPTIV_UP:
840 c->cputype = CPU_PROAPTIV;
841 __cpu_name[cpu] = "MIPS proAptiv";
842 break;
843 case PRID_IMP_PROAPTIV_MP:
844 c->cputype = CPU_PROAPTIV;
845 __cpu_name[cpu] = "MIPS proAptiv (multi)";
846 break;
829dcc0a
JH		 847 case PRID_IMP_P5600:
848 c->cputype = CPU_P5600;
849 __cpu_name[cpu] = "MIPS P5600";
850 break;
9943ed92
LY		 851 case PRID_IMP_M5150:
852 c->cputype = CPU_M5150;
853 __cpu_name[cpu] = "MIPS M5150";
854 break;
1da177e4 855 }
0b6d497f 856
75b5b5e0
LY		 857 decode_configs(c);
858
0b6d497f 859 spram_config();
1da177e4
LT		 860}
861
cea7e2df 862static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4 863{
4194318c 864 decode_configs(c);
8ff374b9 865 switch (c->processor_id & PRID_IMP_MASK) {
1da177e4
LT		 866 case PRID_IMP_AU1_REV1:
867 case PRID_IMP_AU1_REV2:
270717a8 868 c->cputype = CPU_ALCHEMY;
1da177e4
LT		 869 switch ((c->processor_id >> 24) & 0xff) {
870 case 0:
cea7e2df 871 __cpu_name[cpu] = "Au1000";
1da177e4
LT		 872 break;
873 case 1:
cea7e2df 874 __cpu_name[cpu] = "Au1500";
1da177e4
LT		 875 break;
876 case 2:
cea7e2df 877 __cpu_name[cpu] = "Au1100";
1da177e4
LT		 878 break;
879 case 3:
cea7e2df 880 __cpu_name[cpu] = "Au1550";
1da177e4 881 break;
e3ad1c23 882 case 4:
cea7e2df 883 __cpu_name[cpu] = "Au1200";
8ff374b9 884 if ((c->processor_id & PRID_REV_MASK) == 2)
cea7e2df 885 __cpu_name[cpu] = "Au1250";
237cfee1
ML		 886 break;
887 case 5:
cea7e2df 888 __cpu_name[cpu] = "Au1210";
e3ad1c23 889 break;
1da177e4 890 default:
270717a8 891 __cpu_name[cpu] = "Au1xxx";
1da177e4
LT		 892 break;
893 }
1da177e4
LT		 894 break;
895 }
896}
897
cea7e2df 898static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4 899{
4194318c 900 decode_configs(c);
02cf2119 901
8ff374b9 902 switch (c->processor_id & PRID_IMP_MASK) {
1da177e4
LT		 903 case PRID_IMP_SB1:
904 c->cputype = CPU_SB1;
cea7e2df 905 __cpu_name[cpu] = "SiByte SB1";
1da177e4 906 /* FPU in pass1 is known to have issues. */
8ff374b9 907 if ((c->processor_id & PRID_REV_MASK) < 0x02)
010b853b 908 c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
1da177e4 909 break;
93ce2f52
AI		 910 case PRID_IMP_SB1A:
911 c->cputype = CPU_SB1A;
cea7e2df 912 __cpu_name[cpu] = "SiByte SB1A";
93ce2f52 913 break;
1da177e4
LT		 914 }
915}
916
cea7e2df 917static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4 918{
4194318c 919 decode_configs(c);
8ff374b9 920 switch (c->processor_id & PRID_IMP_MASK) {
1da177e4
LT		 921 case PRID_IMP_SR71000:
922 c->cputype = CPU_SR71000;
cea7e2df 923 __cpu_name[cpu] = "Sandcraft SR71000";
1da177e4
LT		 924 c->scache.ways = 8;
925 c->tlbsize = 64;
926 break;
927 }
928}
929
cea7e2df 930static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu)
bdf21b18
PP		 931{
932 decode_configs(c);
8ff374b9 933 switch (c->processor_id & PRID_IMP_MASK) {
bdf21b18
PP		 934 case PRID_IMP_PR4450:
935 c->cputype = CPU_PR4450;
cea7e2df 936 __cpu_name[cpu] = "Philips PR4450";
a96102be 937 set_isa(c, MIPS_CPU_ISA_M32R1);
bdf21b18 938 break;
bdf21b18
PP		 939 }
940}
941
cea7e2df 942static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
1c0c13eb
AJ		 943{
944 decode_configs(c);
8ff374b9 945 switch (c->processor_id & PRID_IMP_MASK) {
190fca3e
KC		 946 case PRID_IMP_BMIPS32_REV4:
947 case PRID_IMP_BMIPS32_REV8:
602977b0
KC		 948 c->cputype = CPU_BMIPS32;
949 __cpu_name[cpu] = "Broadcom BMIPS32";
06785df0 950 set_elf_platform(cpu, "bmips32");
602977b0
KC		 951 break;
952 case PRID_IMP_BMIPS3300:
953 case PRID_IMP_BMIPS3300_ALT:
954 case PRID_IMP_BMIPS3300_BUG:
955 c->cputype = CPU_BMIPS3300;
956 __cpu_name[cpu] = "Broadcom BMIPS3300";
06785df0 957 set_elf_platform(cpu, "bmips3300");
602977b0
KC		 958 break;
959 case PRID_IMP_BMIPS43XX: {
8ff374b9 960 int rev = c->processor_id & PRID_REV_MASK;
602977b0
KC		 961
962 if (rev >= PRID_REV_BMIPS4380_LO &&
963 rev <= PRID_REV_BMIPS4380_HI) {
964 c->cputype = CPU_BMIPS4380;
965 __cpu_name[cpu] = "Broadcom BMIPS4380";
06785df0 966 set_elf_platform(cpu, "bmips4380");
602977b0
KC		 967 } else {
968 c->cputype = CPU_BMIPS4350;
969 __cpu_name[cpu] = "Broadcom BMIPS4350";
06785df0 970 set_elf_platform(cpu, "bmips4350");
602977b0 971 }
0de663ef 972 break;
602977b0
KC		 973 }
974 case PRID_IMP_BMIPS5000:
975 c->cputype = CPU_BMIPS5000;
976 __cpu_name[cpu] = "Broadcom BMIPS5000";
06785df0 977 set_elf_platform(cpu, "bmips5000");
602977b0 978 c->options |= MIPS_CPU_ULRI;
0de663ef 979 break;
1c0c13eb
AJ		 980 }
981}
982
0dd4781b
DD		 983static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu)
984{
985 decode_configs(c);
8ff374b9 986 switch (c->processor_id & PRID_IMP_MASK) {
0dd4781b
DD		 987 case PRID_IMP_CAVIUM_CN38XX:
988 case PRID_IMP_CAVIUM_CN31XX:
989 case PRID_IMP_CAVIUM_CN30XX:
6f329468
DD		 990 c->cputype = CPU_CAVIUM_OCTEON;
991 __cpu_name[cpu] = "Cavium Octeon";
992 goto platform;
0dd4781b
DD		 993 case PRID_IMP_CAVIUM_CN58XX:
994 case PRID_IMP_CAVIUM_CN56XX:
995 case PRID_IMP_CAVIUM_CN50XX:
996 case PRID_IMP_CAVIUM_CN52XX:
6f329468
DD		 997 c->cputype = CPU_CAVIUM_OCTEON_PLUS;
998 __cpu_name[cpu] = "Cavium Octeon+";
999platform:
c094c99e 1000 set_elf_platform(cpu, "octeon");
0dd4781b 1001 break;
a1431b61 1002 case PRID_IMP_CAVIUM_CN61XX:
0e56b385 1003 case PRID_IMP_CAVIUM_CN63XX:
a1431b61
DD		 1004 case PRID_IMP_CAVIUM_CN66XX:
1005 case PRID_IMP_CAVIUM_CN68XX:
af04bb85 1006 case PRID_IMP_CAVIUM_CNF71XX:
0e56b385
DD		 1007 c->cputype = CPU_CAVIUM_OCTEON2;
1008 __cpu_name[cpu] = "Cavium Octeon II";
c094c99e 1009 set_elf_platform(cpu, "octeon2");
0e56b385 1010 break;
af04bb85
DD		 1011 case PRID_IMP_CAVIUM_CN70XX:
1012 case PRID_IMP_CAVIUM_CN78XX:
1013 c->cputype = CPU_CAVIUM_OCTEON3;
1014 __cpu_name[cpu] = "Cavium Octeon III";
1015 set_elf_platform(cpu, "octeon3");
1016 break;
0dd4781b
DD		 1017 default:
1018 printk(KERN_INFO "Unknown Octeon chip!\n");
1019 c->cputype = CPU_UNKNOWN;
1020 break;
1021 }
1022}
1023
83ccf69d
LPC		 1024static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
1025{
1026 decode_configs(c);
1027 /* JZRISC does not implement the CP0 counter. */
1028 c->options &= ~MIPS_CPU_COUNTER;
8ff374b9 1029 switch (c->processor_id & PRID_IMP_MASK) {
83ccf69d
LPC		 1030 case PRID_IMP_JZRISC:
1031 c->cputype = CPU_JZRISC;
1032 __cpu_name[cpu] = "Ingenic JZRISC";
1033 break;
1034 default:
1035 panic("Unknown Ingenic Processor ID!");
1036 break;
1037 }
1038}
1039
a7117c6b
J		 1040static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu)
1041{
1042 decode_configs(c);
1043
8ff374b9 1044 if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_NETLOGIC_AU13XX) {
809f36c6
ML		 1045 c->cputype = CPU_ALCHEMY;
1046 __cpu_name[cpu] = "Au1300";
1047 /* following stuff is not for Alchemy */
1048 return;
1049 }
1050
70342287
RB		 1051 c->options = (MIPS_CPU_TLB |
1052 MIPS_CPU_4KEX |
a7117c6b 1053 MIPS_CPU_COUNTER |
70342287
RB		 1054 MIPS_CPU_DIVEC |
1055 MIPS_CPU_WATCH |
1056 MIPS_CPU_EJTAG |
a7117c6b
J		 1057 MIPS_CPU_LLSC);
1058
8ff374b9 1059 switch (c->processor_id & PRID_IMP_MASK) {
4ca86a2f 1060 case PRID_IMP_NETLOGIC_XLP2XX:
8907c55e 1061 case PRID_IMP_NETLOGIC_XLP9XX:
4ca86a2f
J		 1062 c->cputype = CPU_XLP;
1063 __cpu_name[cpu] = "Broadcom XLPII";
1064 break;
1065
2aa54b20
J		 1066 case PRID_IMP_NETLOGIC_XLP8XX:
1067 case PRID_IMP_NETLOGIC_XLP3XX:
a3d4fb2d
J		 1068 c->cputype = CPU_XLP;
1069 __cpu_name[cpu] = "Netlogic XLP";
1070 break;
1071
a7117c6b
J		 1072 case PRID_IMP_NETLOGIC_XLR732:
1073 case PRID_IMP_NETLOGIC_XLR716:
1074 case PRID_IMP_NETLOGIC_XLR532:
1075 case PRID_IMP_NETLOGIC_XLR308:
1076 case PRID_IMP_NETLOGIC_XLR532C:
1077 case PRID_IMP_NETLOGIC_XLR516C:
1078 case PRID_IMP_NETLOGIC_XLR508C:
1079 case PRID_IMP_NETLOGIC_XLR308C:
1080 c->cputype = CPU_XLR;
1081 __cpu_name[cpu] = "Netlogic XLR";
1082 break;
1083
1084 case PRID_IMP_NETLOGIC_XLS608:
1085 case PRID_IMP_NETLOGIC_XLS408:
1086 case PRID_IMP_NETLOGIC_XLS404:
1087 case PRID_IMP_NETLOGIC_XLS208:
1088 case PRID_IMP_NETLOGIC_XLS204:
1089 case PRID_IMP_NETLOGIC_XLS108:
1090 case PRID_IMP_NETLOGIC_XLS104:
1091 case PRID_IMP_NETLOGIC_XLS616B:
1092 case PRID_IMP_NETLOGIC_XLS608B:
1093 case PRID_IMP_NETLOGIC_XLS416B:
1094 case PRID_IMP_NETLOGIC_XLS412B:
1095 case PRID_IMP_NETLOGIC_XLS408B:
1096 case PRID_IMP_NETLOGIC_XLS404B:
1097 c->cputype = CPU_XLR;
1098 __cpu_name[cpu] = "Netlogic XLS";
1099 break;
1100
1101 default:
a3d4fb2d 1102 pr_info("Unknown Netlogic chip id [%02x]!\n",
a7117c6b
J		 1103 c->processor_id);
1104 c->cputype = CPU_XLR;
1105 break;
1106 }
1107
a3d4fb2d 1108 if (c->cputype == CPU_XLP) {
a96102be 1109 set_isa(c, MIPS_CPU_ISA_M64R2);
a3d4fb2d
J		 1110 c->options |= (MIPS_CPU_FPU | MIPS_CPU_ULRI | MIPS_CPU_MCHECK);
1111 /* This will be updated again after all threads are woken up */
1112 c->tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1;
1113 } else {
a96102be 1114 set_isa(c, MIPS_CPU_ISA_M64R1);
a3d4fb2d
J		 1115 c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1;
1116 }
7777b939 1117 c->kscratch_mask = 0xf;
a7117c6b
J		 1118}
1119
949e51be
DD		 1120#ifdef CONFIG_64BIT
1121/* For use by uaccess.h */
1122u64 __ua_limit;
1123EXPORT_SYMBOL(__ua_limit);
1124#endif
1125
9966db25 1126const char *__cpu_name[NR_CPUS];
874fd3b5 1127const char *__elf_platform;
9966db25 1128
078a55fc 1129void cpu_probe(void)
1da177e4
LT		 1130{
1131 struct cpuinfo_mips *c = &current_cpu_data;
9966db25 1132 unsigned int cpu = smp_processor_id();
1da177e4 1133
70342287 1134 c->processor_id = PRID_IMP_UNKNOWN;
1da177e4
LT		 1135 c->fpu_id = FPIR_IMP_NONE;
1136 c->cputype = CPU_UNKNOWN;
1137
1138 c->processor_id = read_c0_prid();
8ff374b9 1139 switch (c->processor_id & PRID_COMP_MASK) {
1da177e4 1140 case PRID_COMP_LEGACY:
cea7e2df 1141 cpu_probe_legacy(c, cpu);
1da177e4
LT		 1142 break;
1143 case PRID_COMP_MIPS:
cea7e2df 1144 cpu_probe_mips(c, cpu);
1da177e4
LT		 1145 break;
1146 case PRID_COMP_ALCHEMY:
cea7e2df 1147 cpu_probe_alchemy(c, cpu);
1da177e4
LT		 1148 break;
1149 case PRID_COMP_SIBYTE:
cea7e2df 1150 cpu_probe_sibyte(c, cpu);
1da177e4 1151 break;
1c0c13eb 1152 case PRID_COMP_BROADCOM:
cea7e2df 1153 cpu_probe_broadcom(c, cpu);
1c0c13eb 1154 break;
1da177e4 1155 case PRID_COMP_SANDCRAFT:
cea7e2df 1156 cpu_probe_sandcraft(c, cpu);
1da177e4 1157 break;
a92b0588 1158 case PRID_COMP_NXP:
cea7e2df 1159 cpu_probe_nxp(c, cpu);
a3dddd56 1160 break;
0dd4781b
DD		 1161 case PRID_COMP_CAVIUM:
1162 cpu_probe_cavium(c, cpu);
1163 break;
83ccf69d
LPC		 1164 case PRID_COMP_INGENIC:
1165 cpu_probe_ingenic(c, cpu);
1166 break;
a7117c6b
J		 1167 case PRID_COMP_NETLOGIC:
1168 cpu_probe_netlogic(c, cpu);
1169 break;
1da177e4 1170 }
dec8b1ca 1171
cea7e2df
RB		 1172 BUG_ON(!__cpu_name[cpu]);
1173 BUG_ON(c->cputype == CPU_UNKNOWN);
1174
dec8b1ca
FBH		 1175 /*
1176 * Platform code can force the cpu type to optimize code
1177 * generation. In that case be sure the cpu type is correctly
1178 * manually setup otherwise it could trigger some nasty bugs.
1179 */
1180 BUG_ON(current_cpu_type() != c->cputype);
1181
0103d23f
KC		 1182 if (mips_fpu_disabled)
1183 c->options &= ~MIPS_CPU_FPU;
1184
1185 if (mips_dsp_disabled)
ee80f7c7 1186 c->ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
0103d23f 1187
4194318c 1188 if (c->options & MIPS_CPU_FPU) {
1da177e4 1189 c->fpu_id = cpu_get_fpu_id();
4194318c 1190
adb37892
DCZ		 1191 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 |
1192 MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2)) {
4194318c
RB		 1193 if (c->fpu_id & MIPS_FPIR_3D)
1194 c->ases |= MIPS_ASE_MIPS3D;
1195 }
1196 }
9966db25 1197
da4b62cd 1198 if (cpu_has_mips_r2) {
f6771dbb 1199 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
da4b62cd
AC		 1200 /* R2 has Performance Counter Interrupt indicator */
1201 c->options |= MIPS_CPU_PCI;
1202 }
f6771dbb
RB		 1203 else
1204 c->srsets = 1;
91dfc423 1205
a8ad1367 1206 if (cpu_has_msa) {
a5e9a69e 1207 c->msa_id = cpu_get_msa_id();
a8ad1367
PB		 1208 WARN(c->msa_id & MSA_IR_WRPF,
1209 "Vector register partitioning unimplemented!");
1210 }
a5e9a69e 1211
91dfc423 1212 cpu_probe_vmbits(c);
949e51be
DD		 1213
1214#ifdef CONFIG_64BIT
1215 if (cpu == 0)
1216 __ua_limit = ~((1ull << cpu_vmbits) - 1);
1217#endif
1da177e4
LT		 1218}
1219
078a55fc 1220void cpu_report(void)
1da177e4
LT		 1221{
1222 struct cpuinfo_mips *c = &current_cpu_data;
1223
d9f897c9
LY		 1224 pr_info("CPU%d revision is: %08x (%s)\n",
1225 smp_processor_id(), c->processor_id, cpu_name_string());
1da177e4 1226 if (c->options & MIPS_CPU_FPU)
9966db25 1227 printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id);
a5e9a69e
PB		 1228 if (cpu_has_msa)
1229 pr_info("MSA revision is: %08x\n", c->msa_id);
1da177e4 1230}
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