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MIPS: Respect the ISA level in FCSR handling
[mirror_ubuntu-zesty-kernel.git] / arch / mips / kernel / cpu-probe.c
CommitLineData
1da177e4
LT		 1/*
2 * Processor capabilities determination functions.
3 *
4 * Copyright (C) xxxx the Anonymous
010b853b 5 * Copyright (C) 1994 - 2006 Ralf Baechle
4194318c 6 * Copyright (C) 2003, 2004 Maciej W. Rozycki
70342287 7 * Copyright (C) 2001, 2004, 2011, 2012 MIPS Technologies, Inc.
1da177e4
LT		 8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
13 */
1da177e4
LT		 14#include <linux/init.h>
15#include <linux/kernel.h>
16#include <linux/ptrace.h>
631330f5 17#include <linux/smp.h>
1da177e4 18#include <linux/stddef.h>
73bc256d 19#include <linux/export.h>
1da177e4 20
5759906c 21#include <asm/bugs.h>
1da177e4 22#include <asm/cpu.h>
f6843626 23#include <asm/cpu-features.h>
69f24d17 24#include <asm/cpu-type.h>
1da177e4
LT		 25#include <asm/fpu.h>
26#include <asm/mipsregs.h>
30ee615b 27#include <asm/mipsmtregs.h>
a5e9a69e 28#include <asm/msa.h>
654f57bf 29#include <asm/watch.h>
06372a63 30#include <asm/elf.h>
4f12b91d 31#include <asm/pgtable-bits.h>
a074f0e8 32#include <asm/spram.h>
949e51be
DD		 33#include <asm/uaccess.h>
34
9b26616c
MR		 35/*
36 * Determine the FCSR mask for FPU hardware.
37 */
38static inline void cpu_set_fpu_fcsr_mask(struct cpuinfo_mips *c)
39{
40 unsigned long sr, mask, fcsr, fcsr0, fcsr1;
41
42 mask = FPU_CSR_ALL_X | FPU_CSR_ALL_E | FPU_CSR_ALL_S | FPU_CSR_RM;
43
44 sr = read_c0_status();
45 __enable_fpu(FPU_AS_IS);
46
47 fcsr = read_32bit_cp1_register(CP1_STATUS);
48
49 fcsr0 = fcsr & mask;
50 write_32bit_cp1_register(CP1_STATUS, fcsr0);
51 fcsr0 = read_32bit_cp1_register(CP1_STATUS);
52
53 fcsr1 = fcsr | ~mask;
54 write_32bit_cp1_register(CP1_STATUS, fcsr1);
55 fcsr1 = read_32bit_cp1_register(CP1_STATUS);
56
57 write_32bit_cp1_register(CP1_STATUS, fcsr);
58
59 write_c0_status(sr);
60
61 c->fpu_msk31 = ~(fcsr0 ^ fcsr1) & ~mask;
62}
63
f6843626
MR		 64/*
65 * Set the FIR feature flags for the FPU emulator.
66 */
67static void cpu_set_nofpu_id(struct cpuinfo_mips *c)
68{
69 u32 value;
70
71 value = 0;
72 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
73 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
74 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6))
75 value |= MIPS_FPIR_D | MIPS_FPIR_S;
76 if (c->isa_level & (MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
77 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6))
78 value |= MIPS_FPIR_F64 | MIPS_FPIR_L | MIPS_FPIR_W;
79 c->fpu_id = value;
80}
81
9b26616c
MR		 82/* Determined FPU emulator mask to use for the boot CPU with "nofpu". */
83static unsigned int mips_nofpu_msk31;
84
078a55fc 85static int mips_fpu_disabled;
0103d23f
KC		 86
87static int __init fpu_disable(char *s)
88{
f6843626 89 boot_cpu_data.options &= ~MIPS_CPU_FPU;
9b26616c 90 boot_cpu_data.fpu_msk31 = mips_nofpu_msk31;
f6843626 91 cpu_set_nofpu_id(&boot_cpu_data);
0103d23f
KC		 92 mips_fpu_disabled = 1;
93
94 return 1;
95}
96
97__setup("nofpu", fpu_disable);
98
078a55fc 99int mips_dsp_disabled;
0103d23f
KC		 100
101static int __init dsp_disable(char *s)
102{
ee80f7c7 103 cpu_data[0].ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
0103d23f
KC		 104 mips_dsp_disabled = 1;
105
106 return 1;
107}
108
109__setup("nodsp", dsp_disable);
110
3d528b32
MC		 111static int mips_htw_disabled;
112
113static int __init htw_disable(char *s)
114{
115 mips_htw_disabled = 1;
116 cpu_data[0].options &= ~MIPS_CPU_HTW;
117 write_c0_pwctl(read_c0_pwctl() &
118 ~(1 << MIPS_PWCTL_PWEN_SHIFT));
119
120 return 1;
121}
122
123__setup("nohtw", htw_disable);
124
97f4ad29
MC		 125static int mips_ftlb_disabled;
126static int mips_has_ftlb_configured;
127
128static void set_ftlb_enable(struct cpuinfo_mips *c, int enable);
129
130static int __init ftlb_disable(char *s)
131{
132 unsigned int config4, mmuextdef;
133
134 /*
135 * If the core hasn't done any FTLB configuration, there is nothing
136 * for us to do here.
137 */
138 if (!mips_has_ftlb_configured)
139 return 1;
140
141 /* Disable it in the boot cpu */
142 set_ftlb_enable(&cpu_data[0], 0);
143
144 back_to_back_c0_hazard();
145
146 config4 = read_c0_config4();
147
148 /* Check that FTLB has been disabled */
149 mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF;
150 /* MMUSIZEEXT == VTLB ON, FTLB OFF */
151 if (mmuextdef == MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT) {
152 /* This should never happen */
153 pr_warn("FTLB could not be disabled!\n");
154 return 1;
155 }
156
157 mips_ftlb_disabled = 1;
158 mips_has_ftlb_configured = 0;
159
160 /*
161 * noftlb is mainly used for debug purposes so print
162 * an informative message instead of using pr_debug()
163 */
164 pr_info("FTLB has been disabled\n");
165
166 /*
167 * Some of these bits are duplicated in the decode_config4.
168 * MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT is the only possible case
169 * once FTLB has been disabled so undo what decode_config4 did.
170 */
171 cpu_data[0].tlbsize -= cpu_data[0].tlbsizeftlbways *
172 cpu_data[0].tlbsizeftlbsets;
173 cpu_data[0].tlbsizeftlbsets = 0;
174 cpu_data[0].tlbsizeftlbways = 0;
175
176 return 1;
177}
178
179__setup("noftlb", ftlb_disable);
180
181
9267a30d
MSJ		 182static inline void check_errata(void)
183{
184 struct cpuinfo_mips *c = &current_cpu_data;
185
69f24d17 186 switch (current_cpu_type()) {
9267a30d
MSJ		 187 case CPU_34K:
188 /*
189 * Erratum "RPS May Cause Incorrect Instruction Execution"
b633648c 190 * This code only handles VPE0, any SMP/RTOS code
9267a30d
MSJ		 191 * making use of VPE1 will be responsable for that VPE.
192 */
193 if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2)
194 write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS);
195 break;
196 default:
197 break;
198 }
199}
200
1da177e4
LT		 201void __init check_bugs32(void)
202{
9267a30d 203 check_errata();
1da177e4
LT		 204}
205
206/*
207 * Probe whether cpu has config register by trying to play with
208 * alternate cache bit and see whether it matters.
209 * It's used by cpu_probe to distinguish between R3000A and R3081.
210 */
211static inline int cpu_has_confreg(void)
212{
213#ifdef CONFIG_CPU_R3000
214 extern unsigned long r3k_cache_size(unsigned long);
215 unsigned long size1, size2;
216 unsigned long cfg = read_c0_conf();
217
218 size1 = r3k_cache_size(ST0_ISC);
219 write_c0_conf(cfg ^ R30XX_CONF_AC);
220 size2 = r3k_cache_size(ST0_ISC);
221 write_c0_conf(cfg);
222 return size1 != size2;
223#else
224 return 0;
225#endif
226}
227
c094c99e
RM		 228static inline void set_elf_platform(int cpu, const char *plat)
229{
230 if (cpu == 0)
231 __elf_platform = plat;
232}
233
1da177e4
LT		 234/*
235 * Get the FPU Implementation/Revision.
236 */
237static inline unsigned long cpu_get_fpu_id(void)
238{
239 unsigned long tmp, fpu_id;
240
241 tmp = read_c0_status();
597ce172 242 __enable_fpu(FPU_AS_IS);
1da177e4
LT		 243 fpu_id = read_32bit_cp1_register(CP1_REVISION);
244 write_c0_status(tmp);
245 return fpu_id;
246}
247
248/*
f6c70ff4 249 * Check if the CPU has an external FPU.
1da177e4
LT		 250 */
251static inline int __cpu_has_fpu(void)
252{
635c9907 253 return (cpu_get_fpu_id() & FPIR_IMP_MASK) != FPIR_IMP_NONE;
1da177e4
LT		 254}
255
a5e9a69e
PB		 256static inline unsigned long cpu_get_msa_id(void)
257{
3587ea88 258 unsigned long status, msa_id;
a5e9a69e
PB		 259
260 status = read_c0_status();
261 __enable_fpu(FPU_64BIT);
a5e9a69e
PB		 262 enable_msa();
263 msa_id = read_msa_ir();
3587ea88 264 disable_msa();
a5e9a69e
PB		 265 write_c0_status(status);
266 return msa_id;
267}
268
91dfc423
GR		 269static inline void cpu_probe_vmbits(struct cpuinfo_mips *c)
270{
271#ifdef __NEED_VMBITS_PROBE
5b7efa89 272 write_c0_entryhi(0x3fffffffffffe000ULL);
91dfc423 273 back_to_back_c0_hazard();
5b7efa89 274 c->vmbits = fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL);
91dfc423
GR		 275#endif
276}
277
078a55fc 278static void set_isa(struct cpuinfo_mips *c, unsigned int isa)
a96102be
SH		 279{
280 switch (isa) {
281 case MIPS_CPU_ISA_M64R2:
282 c->isa_level |= MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2;
283 case MIPS_CPU_ISA_M64R1:
284 c->isa_level |= MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1;
285 case MIPS_CPU_ISA_V:
286 c->isa_level |= MIPS_CPU_ISA_V;
287 case MIPS_CPU_ISA_IV:
288 c->isa_level |= MIPS_CPU_ISA_IV;
289 case MIPS_CPU_ISA_III:
1990e542 290 c->isa_level |= MIPS_CPU_ISA_II | MIPS_CPU_ISA_III;
a96102be
SH		 291 break;
292
8b8aa636
LY		 293 /* R6 incompatible with everything else */
294 case MIPS_CPU_ISA_M64R6:
295 c->isa_level |= MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6;
296 case MIPS_CPU_ISA_M32R6:
297 c->isa_level |= MIPS_CPU_ISA_M32R6;
298 /* Break here so we don't add incompatible ISAs */
299 break;
a96102be
SH		 300 case MIPS_CPU_ISA_M32R2:
301 c->isa_level |= MIPS_CPU_ISA_M32R2;
302 case MIPS_CPU_ISA_M32R1:
303 c->isa_level |= MIPS_CPU_ISA_M32R1;
304 case MIPS_CPU_ISA_II:
305 c->isa_level |= MIPS_CPU_ISA_II;
a96102be
SH		 306 break;
307 }
308}
309
078a55fc 310static char unknown_isa[] = KERN_ERR \
2fa36399
KC		 311 "Unsupported ISA type, c0.config0: %d.";
312
cf0a8aa0
MC		 313static unsigned int calculate_ftlb_probability(struct cpuinfo_mips *c)
314{
315
316 unsigned int probability = c->tlbsize / c->tlbsizevtlb;
317
318 /*
319 * 0 = All TLBWR instructions go to FTLB
320 * 1 = 15:1: For every 16 TBLWR instructions, 15 go to the
321 * FTLB and 1 goes to the VTLB.
322 * 2 = 7:1: As above with 7:1 ratio.
323 * 3 = 3:1: As above with 3:1 ratio.
324 *
325 * Use the linear midpoint as the probability threshold.
326 */
327 if (probability >= 12)
328 return 1;
329 else if (probability >= 6)
330 return 2;
331 else
332 /*
333 * So FTLB is less than 4 times bigger than VTLB.
334 * A 3:1 ratio can still be useful though.
335 */
336 return 3;
337}
338
75b5b5e0
LY		 339static void set_ftlb_enable(struct cpuinfo_mips *c, int enable)
340{
341 unsigned int config6;
d83b0e82
JH		 342
343 /* It's implementation dependent how the FTLB can be enabled */
344 switch (c->cputype) {
345 case CPU_PROAPTIV:
346 case CPU_P5600:
347 /* proAptiv & related cores use Config6 to enable the FTLB */
75b5b5e0 348 config6 = read_c0_config6();
cf0a8aa0
MC		 349 /* Clear the old probability value */
350 config6 &= ~(3 << MIPS_CONF6_FTLBP_SHIFT);
75b5b5e0
LY		 351 if (enable)
352 /* Enable FTLB */
cf0a8aa0
MC		 353 write_c0_config6(config6 |
354 (calculate_ftlb_probability(c)
355 << MIPS_CONF6_FTLBP_SHIFT)
356 | MIPS_CONF6_FTLBEN);
75b5b5e0
LY		 357 else
358 /* Disable FTLB */
359 write_c0_config6(config6 & ~MIPS_CONF6_FTLBEN);
360 back_to_back_c0_hazard();
d83b0e82 361 break;
75b5b5e0
LY		 362 }
363}
364
2fa36399
KC		 365static inline unsigned int decode_config0(struct cpuinfo_mips *c)
366{
367 unsigned int config0;
368 int isa;
369
370 config0 = read_c0_config();
371
75b5b5e0
LY		 372 /*
373 * Look for Standard TLB or Dual VTLB and FTLB
374 */
375 if ((((config0 & MIPS_CONF_MT) >> 7) == 1) ||
376 (((config0 & MIPS_CONF_MT) >> 7) == 4))
2fa36399 377 c->options |= MIPS_CPU_TLB;
75b5b5e0 378
2fa36399
KC		 379 isa = (config0 & MIPS_CONF_AT) >> 13;
380 switch (isa) {
381 case 0:
382 switch ((config0 & MIPS_CONF_AR) >> 10) {
383 case 0:
a96102be 384 set_isa(c, MIPS_CPU_ISA_M32R1);
2fa36399
KC		 385 break;
386 case 1:
a96102be 387 set_isa(c, MIPS_CPU_ISA_M32R2);
2fa36399 388 break;
8b8aa636
LY		 389 case 2:
390 set_isa(c, MIPS_CPU_ISA_M32R6);
391 break;
2fa36399
KC		 392 default:
393 goto unknown;
394 }
395 break;
396 case 2:
397 switch ((config0 & MIPS_CONF_AR) >> 10) {
398 case 0:
a96102be 399 set_isa(c, MIPS_CPU_ISA_M64R1);
2fa36399
KC		 400 break;
401 case 1:
a96102be 402 set_isa(c, MIPS_CPU_ISA_M64R2);
2fa36399 403 break;
8b8aa636
LY		 404 case 2:
405 set_isa(c, MIPS_CPU_ISA_M64R6);
406 break;
2fa36399
KC		 407 default:
408 goto unknown;
409 }
410 break;
411 default:
412 goto unknown;
413 }
414
415 return config0 & MIPS_CONF_M;
416
417unknown:
418 panic(unknown_isa, config0);
419}
420
421static inline unsigned int decode_config1(struct cpuinfo_mips *c)
422{
423 unsigned int config1;
424
425 config1 = read_c0_config1();
426
427 if (config1 & MIPS_CONF1_MD)
428 c->ases |= MIPS_ASE_MDMX;
429 if (config1 & MIPS_CONF1_WR)
430 c->options |= MIPS_CPU_WATCH;
431 if (config1 & MIPS_CONF1_CA)
432 c->ases |= MIPS_ASE_MIPS16;
433 if (config1 & MIPS_CONF1_EP)
434 c->options |= MIPS_CPU_EJTAG;
435 if (config1 & MIPS_CONF1_FP) {
436 c->options |= MIPS_CPU_FPU;
437 c->options |= MIPS_CPU_32FPR;
438 }
75b5b5e0 439 if (cpu_has_tlb) {
2fa36399 440 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;
75b5b5e0
LY		 441 c->tlbsizevtlb = c->tlbsize;
442 c->tlbsizeftlbsets = 0;
443 }
2fa36399
KC		 444
445 return config1 & MIPS_CONF_M;
446}
447
448static inline unsigned int decode_config2(struct cpuinfo_mips *c)
449{
450 unsigned int config2;
451
452 config2 = read_c0_config2();
453
454 if (config2 & MIPS_CONF2_SL)
455 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
456
457 return config2 & MIPS_CONF_M;
458}
459
460static inline unsigned int decode_config3(struct cpuinfo_mips *c)
461{
462 unsigned int config3;
463
464 config3 = read_c0_config3();
465
b2ab4f08 466 if (config3 & MIPS_CONF3_SM) {
2fa36399 467 c->ases |= MIPS_ASE_SMARTMIPS;
b2ab4f08
SH		 468 c->options |= MIPS_CPU_RIXI;
469 }
470 if (config3 & MIPS_CONF3_RXI)
471 c->options |= MIPS_CPU_RIXI;
2fa36399
KC		 472 if (config3 & MIPS_CONF3_DSP)
473 c->ases |= MIPS_ASE_DSP;
ee80f7c7
SH		 474 if (config3 & MIPS_CONF3_DSP2P)
475 c->ases |= MIPS_ASE_DSP2P;
2fa36399
KC		 476 if (config3 & MIPS_CONF3_VINT)
477 c->options |= MIPS_CPU_VINT;
478 if (config3 & MIPS_CONF3_VEIC)
479 c->options |= MIPS_CPU_VEIC;
480 if (config3 & MIPS_CONF3_MT)
481 c->ases |= MIPS_ASE_MIPSMT;
482 if (config3 & MIPS_CONF3_ULRI)
483 c->options |= MIPS_CPU_ULRI;
f8fa4811
SH		 484 if (config3 & MIPS_CONF3_ISA)
485 c->options |= MIPS_CPU_MICROMIPS;
1e7decdb
DD		 486 if (config3 & MIPS_CONF3_VZ)
487 c->ases |= MIPS_ASE_VZ;
4a0156fb
SH		 488 if (config3 & MIPS_CONF3_SC)
489 c->options |= MIPS_CPU_SEGMENTS;
a5e9a69e
PB		 490 if (config3 & MIPS_CONF3_MSA)
491 c->ases |= MIPS_ASE_MSA;
3d528b32 492 /* Only tested on 32-bit cores */
ed4cbc81
MC		 493 if ((config3 & MIPS_CONF3_PW) && config_enabled(CONFIG_32BIT)) {
494 c->htw_seq = 0;
3d528b32 495 c->options |= MIPS_CPU_HTW;
ed4cbc81 496 }
9b3274bd
JH		 497 if (config3 & MIPS_CONF3_CDMM)
498 c->options |= MIPS_CPU_CDMM;
2fa36399
KC		 499
500 return config3 & MIPS_CONF_M;
501}
502
503static inline unsigned int decode_config4(struct cpuinfo_mips *c)
504{
505 unsigned int config4;
75b5b5e0
LY		 506 unsigned int newcf4;
507 unsigned int mmuextdef;
508 unsigned int ftlb_page = MIPS_CONF4_FTLBPAGESIZE;
2fa36399
KC		 509
510 config4 = read_c0_config4();
511
1745c1ef
LY		 512 if (cpu_has_tlb) {
513 if (((config4 & MIPS_CONF4_IE) >> 29) == 2)
514 c->options |= MIPS_CPU_TLBINV;
75b5b5e0
LY		 515 mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF;
516 switch (mmuextdef) {
517 case MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT:
518 c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40;
519 c->tlbsizevtlb = c->tlbsize;
520 break;
521 case MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT:
522 c->tlbsizevtlb +=
523 ((config4 & MIPS_CONF4_VTLBSIZEEXT) >>
524 MIPS_CONF4_VTLBSIZEEXT_SHIFT) * 0x40;
525 c->tlbsize = c->tlbsizevtlb;
526 ftlb_page = MIPS_CONF4_VFTLBPAGESIZE;
527 /* fall through */
528 case MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT:
97f4ad29
MC		 529 if (mips_ftlb_disabled)
530 break;
75b5b5e0
LY		 531 newcf4 = (config4 & ~ftlb_page) |
532 (page_size_ftlb(mmuextdef) <<
533 MIPS_CONF4_FTLBPAGESIZE_SHIFT);
534 write_c0_config4(newcf4);
535 back_to_back_c0_hazard();
536 config4 = read_c0_config4();
537 if (config4 != newcf4) {
538 pr_err("PAGE_SIZE 0x%lx is not supported by FTLB (config4=0x%x)\n",
539 PAGE_SIZE, config4);
540 /* Switch FTLB off */
541 set_ftlb_enable(c, 0);
542 break;
543 }
544 c->tlbsizeftlbsets = 1 <<
545 ((config4 & MIPS_CONF4_FTLBSETS) >>
546 MIPS_CONF4_FTLBSETS_SHIFT);
547 c->tlbsizeftlbways = ((config4 & MIPS_CONF4_FTLBWAYS) >>
548 MIPS_CONF4_FTLBWAYS_SHIFT) + 2;
549 c->tlbsize += c->tlbsizeftlbways * c->tlbsizeftlbsets;
97f4ad29 550 mips_has_ftlb_configured = 1;
75b5b5e0
LY		 551 break;
552 }
1745c1ef
LY		 553 }
554
2fa36399
KC		 555 c->kscratch_mask = (config4 >> 16) & 0xff;
556
557 return config4 & MIPS_CONF_M;
558}
559
8b8a7634
RB		 560static inline unsigned int decode_config5(struct cpuinfo_mips *c)
561{
562 unsigned int config5;
563
564 config5 = read_c0_config5();
d175ed2b 565 config5 &= ~(MIPS_CONF5_UFR | MIPS_CONF5_UFE);
8b8a7634
RB		 566 write_c0_config5(config5);
567
49016748
MC		 568 if (config5 & MIPS_CONF5_EVA)
569 c->options |= MIPS_CPU_EVA;
1f6c52ff
PB		 570 if (config5 & MIPS_CONF5_MRP)
571 c->options |= MIPS_CPU_MAAR;
5aed9da1
MC		 572 if (config5 & MIPS_CONF5_LLB)
573 c->options |= MIPS_CPU_RW_LLB;
49016748 574
8b8a7634
RB		 575 return config5 & MIPS_CONF_M;
576}
577
078a55fc 578static void decode_configs(struct cpuinfo_mips *c)
2fa36399
KC		 579{
580 int ok;
581
582 /* MIPS32 or MIPS64 compliant CPU. */
583 c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
584 MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
585
586 c->scache.flags = MIPS_CACHE_NOT_PRESENT;
587
97f4ad29
MC		 588 /* Enable FTLB if present and not disabled */
589 set_ftlb_enable(c, !mips_ftlb_disabled);
75b5b5e0 590
2fa36399 591 ok = decode_config0(c); /* Read Config registers. */
70342287 592 BUG_ON(!ok); /* Arch spec violation! */
2fa36399
KC		 593 if (ok)
594 ok = decode_config1(c);
595 if (ok)
596 ok = decode_config2(c);
597 if (ok)
598 ok = decode_config3(c);
599 if (ok)
600 ok = decode_config4(c);
8b8a7634
RB		 601 if (ok)
602 ok = decode_config5(c);
2fa36399
KC		 603
604 mips_probe_watch_registers(c);
605
6575b1d4
LY		 606 if (cpu_has_rixi) {
607 /* Enable the RIXI exceptions */
a5770df0 608 set_c0_pagegrain(PG_IEC);
6575b1d4
LY		 609 back_to_back_c0_hazard();
610 /* Verify the IEC bit is set */
611 if (read_c0_pagegrain() & PG_IEC)
612 c->options |= MIPS_CPU_RIXIEX;
613 }
614
0ee958e1 615#ifndef CONFIG_MIPS_CPS
8b8aa636 616 if (cpu_has_mips_r2_r6) {
45b585c8 617 c->core = get_ebase_cpunum();
30ee615b
PB		 618 if (cpu_has_mipsmt)
619 c->core >>= fls(core_nvpes()) - 1;
620 }
0ee958e1 621#endif
2fa36399
KC		 622}
623
02cf2119 624#define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
1da177e4
LT		 625 | MIPS_CPU_COUNTER)
626
cea7e2df 627static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4 628{
8ff374b9 629 switch (c->processor_id & PRID_IMP_MASK) {
1da177e4
LT		 630 case PRID_IMP_R2000:
631 c->cputype = CPU_R2000;
cea7e2df 632 __cpu_name[cpu] = "R2000";
9b26616c 633 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
02cf2119 634 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
03751e79 635 MIPS_CPU_NOFPUEX;
1da177e4
LT		 636 if (__cpu_has_fpu())
637 c->options |= MIPS_CPU_FPU;
638 c->tlbsize = 64;
639 break;
640 case PRID_IMP_R3000:
8ff374b9 641 if ((c->processor_id & PRID_REV_MASK) == PRID_REV_R3000A) {
cea7e2df 642 if (cpu_has_confreg()) {
1da177e4 643 c->cputype = CPU_R3081E;
cea7e2df
RB		 644 __cpu_name[cpu] = "R3081";
645 } else {
1da177e4 646 c->cputype = CPU_R3000A;
cea7e2df
RB		 647 __cpu_name[cpu] = "R3000A";
648 }
cea7e2df 649 } else {
1da177e4 650 c->cputype = CPU_R3000;
cea7e2df
RB		 651 __cpu_name[cpu] = "R3000";
652 }
9b26616c 653 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
02cf2119 654 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
03751e79 655 MIPS_CPU_NOFPUEX;
1da177e4
LT		 656 if (__cpu_has_fpu())
657 c->options |= MIPS_CPU_FPU;
658 c->tlbsize = 64;
659 break;
660 case PRID_IMP_R4000:
661 if (read_c0_config() & CONF_SC) {
8ff374b9
MR		 662 if ((c->processor_id & PRID_REV_MASK) >=
663 PRID_REV_R4400) {
1da177e4 664 c->cputype = CPU_R4400PC;
cea7e2df
RB		 665 __cpu_name[cpu] = "R4400PC";
666 } else {
1da177e4 667 c->cputype = CPU_R4000PC;
cea7e2df
RB		 668 __cpu_name[cpu] = "R4000PC";
669 }
1da177e4 670 } else {
7f177a52
MR		 671 int cca = read_c0_config() & CONF_CM_CMASK;
672 int mc;
673
674 /*
675 * SC and MC versions can't be reliably told apart,
676 * but only the latter support coherent caching
677 * modes so assume the firmware has set the KSEG0
678 * coherency attribute reasonably (if uncached, we
679 * assume SC).
680 */
681 switch (cca) {
682 case CONF_CM_CACHABLE_CE:
683 case CONF_CM_CACHABLE_COW:
684 case CONF_CM_CACHABLE_CUW:
685 mc = 1;
686 break;
687 default:
688 mc = 0;
689 break;
690 }
8ff374b9
MR		 691 if ((c->processor_id & PRID_REV_MASK) >=
692 PRID_REV_R4400) {
7f177a52
MR		 693 c->cputype = mc ? CPU_R4400MC : CPU_R4400SC;
694 __cpu_name[cpu] = mc ? "R4400MC" : "R4400SC";
cea7e2df 695 } else {
7f177a52
MR		 696 c->cputype = mc ? CPU_R4000MC : CPU_R4000SC;
697 __cpu_name[cpu] = mc ? "R4000MC" : "R4000SC";
cea7e2df 698 }
1da177e4
LT		 699 }
700
a96102be 701 set_isa(c, MIPS_CPU_ISA_III);
9b26616c 702 c->fpu_msk31 |= FPU_CSR_CONDX;
1da177e4 703 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79
SH		 704 MIPS_CPU_WATCH | MIPS_CPU_VCE |
705 MIPS_CPU_LLSC;
1da177e4
LT		 706 c->tlbsize = 48;
707 break;
708 case PRID_IMP_VR41XX:
9f91e506 709 set_isa(c, MIPS_CPU_ISA_III);
9b26616c 710 c->fpu_msk31 |= FPU_CSR_CONDX;
9f91e506
YY		 711 c->options = R4K_OPTS;
712 c->tlbsize = 32;
1da177e4 713 switch (c->processor_id & 0xf0) {
1da177e4
LT		 714 case PRID_REV_VR4111:
715 c->cputype = CPU_VR4111;
cea7e2df 716 __cpu_name[cpu] = "NEC VR4111";
1da177e4 717 break;
1da177e4
LT		 718 case PRID_REV_VR4121:
719 c->cputype = CPU_VR4121;
cea7e2df 720 __cpu_name[cpu] = "NEC VR4121";
1da177e4
LT		 721 break;
722 case PRID_REV_VR4122:
cea7e2df 723 if ((c->processor_id & 0xf) < 0x3) {
1da177e4 724 c->cputype = CPU_VR4122;
cea7e2df
RB		 725 __cpu_name[cpu] = "NEC VR4122";
726 } else {
1da177e4 727 c->cputype = CPU_VR4181A;
cea7e2df
RB		 728 __cpu_name[cpu] = "NEC VR4181A";
729 }
1da177e4
LT		 730 break;
731 case PRID_REV_VR4130:
cea7e2df 732 if ((c->processor_id & 0xf) < 0x4) {
1da177e4 733 c->cputype = CPU_VR4131;
cea7e2df
RB		 734 __cpu_name[cpu] = "NEC VR4131";
735 } else {
1da177e4 736 c->cputype = CPU_VR4133;
9f91e506 737 c->options |= MIPS_CPU_LLSC;
cea7e2df
RB		 738 __cpu_name[cpu] = "NEC VR4133";
739 }
1da177e4
LT		 740 break;
741 default:
742 printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
743 c->cputype = CPU_VR41XX;
cea7e2df 744 __cpu_name[cpu] = "NEC Vr41xx";
1da177e4
LT		 745 break;
746 }
1da177e4
LT		 747 break;
748 case PRID_IMP_R4300:
749 c->cputype = CPU_R4300;
cea7e2df 750 __cpu_name[cpu] = "R4300";
a96102be 751 set_isa(c, MIPS_CPU_ISA_III);
9b26616c 752 c->fpu_msk31 |= FPU_CSR_CONDX;
1da177e4 753 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 754 MIPS_CPU_LLSC;
1da177e4
LT		 755 c->tlbsize = 32;
756 break;
757 case PRID_IMP_R4600:
758 c->cputype = CPU_R4600;
cea7e2df 759 __cpu_name[cpu] = "R4600";
a96102be 760 set_isa(c, MIPS_CPU_ISA_III);
9b26616c 761 c->fpu_msk31 |= FPU_CSR_CONDX;
075e7502
TS		 762 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
763 MIPS_CPU_LLSC;
1da177e4
LT		 764 c->tlbsize = 48;
765 break;
766 #if 0
03751e79 767 case PRID_IMP_R4650:
1da177e4
LT		 768 /*
769 * This processor doesn't have an MMU, so it's not
770 * "real easy" to run Linux on it. It is left purely
771 * for documentation. Commented out because it shares
772 * it's c0_prid id number with the TX3900.
773 */
a3dddd56 774 c->cputype = CPU_R4650;
cea7e2df 775 __cpu_name[cpu] = "R4650";
a96102be 776 set_isa(c, MIPS_CPU_ISA_III);
9b26616c 777 c->fpu_msk31 |= FPU_CSR_CONDX;
1da177e4 778 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
03751e79 779 c->tlbsize = 48;
1da177e4
LT		 780 break;
781 #endif
782 case PRID_IMP_TX39:
9b26616c 783 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
02cf2119 784 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE;
1da177e4
LT		 785
786 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
787 c->cputype = CPU_TX3927;
cea7e2df 788 __cpu_name[cpu] = "TX3927";
1da177e4
LT		 789 c->tlbsize = 64;
790 } else {
8ff374b9 791 switch (c->processor_id & PRID_REV_MASK) {
1da177e4
LT		 792 case PRID_REV_TX3912:
793 c->cputype = CPU_TX3912;
cea7e2df 794 __cpu_name[cpu] = "TX3912";
1da177e4
LT		 795 c->tlbsize = 32;
796 break;
797 case PRID_REV_TX3922:
798 c->cputype = CPU_TX3922;
cea7e2df 799 __cpu_name[cpu] = "TX3922";
1da177e4
LT		 800 c->tlbsize = 64;
801 break;
1da177e4
LT		 802 }
803 }
804 break;
805 case PRID_IMP_R4700:
806 c->cputype = CPU_R4700;
cea7e2df 807 __cpu_name[cpu] = "R4700";
a96102be 808 set_isa(c, MIPS_CPU_ISA_III);
9b26616c 809 c->fpu_msk31 |= FPU_CSR_CONDX;
1da177e4 810 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 811 MIPS_CPU_LLSC;
1da177e4
LT		 812 c->tlbsize = 48;
813 break;
814 case PRID_IMP_TX49:
815 c->cputype = CPU_TX49XX;
cea7e2df 816 __cpu_name[cpu] = "R49XX";
a96102be 817 set_isa(c, MIPS_CPU_ISA_III);
9b26616c 818 c->fpu_msk31 |= FPU_CSR_CONDX;
1da177e4
LT		 819 c->options = R4K_OPTS | MIPS_CPU_LLSC;
820 if (!(c->processor_id & 0x08))
821 c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
822 c->tlbsize = 48;
823 break;
824 case PRID_IMP_R5000:
825 c->cputype = CPU_R5000;
cea7e2df 826 __cpu_name[cpu] = "R5000";
a96102be 827 set_isa(c, MIPS_CPU_ISA_IV);
1da177e4 828 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 829 MIPS_CPU_LLSC;
1da177e4
LT		 830 c->tlbsize = 48;
831 break;
832 case PRID_IMP_R5432:
833 c->cputype = CPU_R5432;
cea7e2df 834 __cpu_name[cpu] = "R5432";
a96102be 835 set_isa(c, MIPS_CPU_ISA_IV);
1da177e4 836 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 837 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
1da177e4
LT		 838 c->tlbsize = 48;
839 break;
840 case PRID_IMP_R5500:
841 c->cputype = CPU_R5500;
cea7e2df 842 __cpu_name[cpu] = "R5500";
a96102be 843 set_isa(c, MIPS_CPU_ISA_IV);
1da177e4 844 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 845 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
1da177e4
LT		 846 c->tlbsize = 48;
847 break;
848 case PRID_IMP_NEVADA:
849 c->cputype = CPU_NEVADA;
cea7e2df 850 __cpu_name[cpu] = "Nevada";
a96102be 851 set_isa(c, MIPS_CPU_ISA_IV);
1da177e4 852 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 853 MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
1da177e4
LT		 854 c->tlbsize = 48;
855 break;
856 case PRID_IMP_R6000:
857 c->cputype = CPU_R6000;
cea7e2df 858 __cpu_name[cpu] = "R6000";
a96102be 859 set_isa(c, MIPS_CPU_ISA_II);
9b26616c 860 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
1da177e4 861 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
03751e79 862 MIPS_CPU_LLSC;
1da177e4
LT		 863 c->tlbsize = 32;
864 break;
865 case PRID_IMP_R6000A:
866 c->cputype = CPU_R6000A;
cea7e2df 867 __cpu_name[cpu] = "R6000A";
a96102be 868 set_isa(c, MIPS_CPU_ISA_II);
9b26616c 869 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
1da177e4 870 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
03751e79 871 MIPS_CPU_LLSC;
1da177e4
LT		 872 c->tlbsize = 32;
873 break;
874 case PRID_IMP_RM7000:
875 c->cputype = CPU_RM7000;
cea7e2df 876 __cpu_name[cpu] = "RM7000";
a96102be 877 set_isa(c, MIPS_CPU_ISA_IV);
1da177e4 878 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 879 MIPS_CPU_LLSC;
1da177e4 880 /*
70342287 881 * Undocumented RM7000: Bit 29 in the info register of
1da177e4
LT		 882 * the RM7000 v2.0 indicates if the TLB has 48 or 64
883 * entries.
884 *
70342287
RB		 885 * 29 1 => 64 entry JTLB
886 * 0 => 48 entry JTLB
1da177e4
LT		 887 */
888 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
1da177e4
LT		 889 break;
890 case PRID_IMP_R8000:
891 c->cputype = CPU_R8000;
cea7e2df 892 __cpu_name[cpu] = "RM8000";
a96102be 893 set_isa(c, MIPS_CPU_ISA_IV);
1da177e4 894 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
03751e79
SH		 895 MIPS_CPU_FPU | MIPS_CPU_32FPR |
896 MIPS_CPU_LLSC;
1da177e4
LT		 897 c->tlbsize = 384; /* has weird TLB: 3-way x 128 */
898 break;
899 case PRID_IMP_R10000:
900 c->cputype = CPU_R10000;
cea7e2df 901 __cpu_name[cpu] = "R10000";
a96102be 902 set_isa(c, MIPS_CPU_ISA_IV);
8b36612a 903 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
03751e79 904 MIPS_CPU_FPU | MIPS_CPU_32FPR |
1da177e4 905 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
03751e79 906 MIPS_CPU_LLSC;
1da177e4
LT		 907 c->tlbsize = 64;
908 break;
909 case PRID_IMP_R12000:
910 c->cputype = CPU_R12000;
cea7e2df 911 __cpu_name[cpu] = "R12000";
a96102be 912 set_isa(c, MIPS_CPU_ISA_IV);
8b36612a 913 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
03751e79 914 MIPS_CPU_FPU | MIPS_CPU_32FPR |
1da177e4 915 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
03751e79 916 MIPS_CPU_LLSC;
1da177e4
LT		 917 c->tlbsize = 64;
918 break;
44d921b2 919 case PRID_IMP_R14000:
30577391
JK		 920 if (((c->processor_id >> 4) & 0x0f) > 2) {
921 c->cputype = CPU_R16000;
922 __cpu_name[cpu] = "R16000";
923 } else {
924 c->cputype = CPU_R14000;
925 __cpu_name[cpu] = "R14000";
926 }
a96102be 927 set_isa(c, MIPS_CPU_ISA_IV);
44d921b2 928 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
03751e79 929 MIPS_CPU_FPU | MIPS_CPU_32FPR |
44d921b2 930 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
03751e79 931 MIPS_CPU_LLSC;
44d921b2
K		 932 c->tlbsize = 64;
933 break;
26859198 934 case PRID_IMP_LOONGSON_64: /* Loongson-2/3 */
5aac1e8a
RM		 935 switch (c->processor_id & PRID_REV_MASK) {
936 case PRID_REV_LOONGSON2E:
c579d310
HC		 937 c->cputype = CPU_LOONGSON2;
938 __cpu_name[cpu] = "ICT Loongson-2";
5aac1e8a 939 set_elf_platform(cpu, "loongson2e");
7352c8b1 940 set_isa(c, MIPS_CPU_ISA_III);
9b26616c 941 c->fpu_msk31 |= FPU_CSR_CONDX;
5aac1e8a
RM		 942 break;
943 case PRID_REV_LOONGSON2F:
c579d310
HC		 944 c->cputype = CPU_LOONGSON2;
945 __cpu_name[cpu] = "ICT Loongson-2";
5aac1e8a 946 set_elf_platform(cpu, "loongson2f");
7352c8b1 947 set_isa(c, MIPS_CPU_ISA_III);
9b26616c 948 c->fpu_msk31 |= FPU_CSR_CONDX;
5aac1e8a 949 break;
c579d310
HC		 950 case PRID_REV_LOONGSON3A:
951 c->cputype = CPU_LOONGSON3;
952 __cpu_name[cpu] = "ICT Loongson-3";
953 set_elf_platform(cpu, "loongson3a");
7352c8b1 954 set_isa(c, MIPS_CPU_ISA_M64R1);
c579d310 955 break;
e7841be5
HC		 956 case PRID_REV_LOONGSON3B_R1:
957 case PRID_REV_LOONGSON3B_R2:
958 c->cputype = CPU_LOONGSON3;
959 __cpu_name[cpu] = "ICT Loongson-3";
960 set_elf_platform(cpu, "loongson3b");
7352c8b1 961 set_isa(c, MIPS_CPU_ISA_M64R1);
e7841be5 962 break;
5aac1e8a
RM		 963 }
964
2a21c730
FZ		 965 c->options = R4K_OPTS |
966 MIPS_CPU_FPU | MIPS_CPU_LLSC |
967 MIPS_CPU_32FPR;
968 c->tlbsize = 64;
cc94ea31 969 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
2a21c730 970 break;
26859198 971 case PRID_IMP_LOONGSON_32: /* Loongson-1 */
2fa36399 972 decode_configs(c);
b4672d37 973
2fa36399 974 c->cputype = CPU_LOONGSON1;
1da177e4 975
2fa36399
KC		 976 switch (c->processor_id & PRID_REV_MASK) {
977 case PRID_REV_LOONGSON1B:
978 __cpu_name[cpu] = "Loongson 1B";
b4672d37 979 break;
b4672d37 980 }
4194318c 981
2fa36399 982 break;
1da177e4 983 }
1da177e4
LT		 984}
985
cea7e2df 986static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4 987{
4f12b91d 988 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
8ff374b9 989 switch (c->processor_id & PRID_IMP_MASK) {
b2498af5
LY		 990 case PRID_IMP_QEMU_GENERIC:
991 c->writecombine = _CACHE_UNCACHED;
992 c->cputype = CPU_QEMU_GENERIC;
993 __cpu_name[cpu] = "MIPS GENERIC QEMU";
994 break;
1da177e4
LT		 995 case PRID_IMP_4KC:
996 c->cputype = CPU_4KC;
4f12b91d 997 c->writecombine = _CACHE_UNCACHED;
cea7e2df 998 __cpu_name[cpu] = "MIPS 4Kc";
1da177e4
LT		 999 break;
1000 case PRID_IMP_4KEC:
2b07bd02
RB		 1001 case PRID_IMP_4KECR2:
1002 c->cputype = CPU_4KEC;
4f12b91d 1003 c->writecombine = _CACHE_UNCACHED;
cea7e2df 1004 __cpu_name[cpu] = "MIPS 4KEc";
2b07bd02 1005 break;
1da177e4 1006 case PRID_IMP_4KSC:
8afcb5d8 1007 case PRID_IMP_4KSD:
1da177e4 1008 c->cputype = CPU_4KSC;
4f12b91d 1009 c->writecombine = _CACHE_UNCACHED;
cea7e2df 1010 __cpu_name[cpu] = "MIPS 4KSc";
1da177e4
LT		 1011 break;
1012 case PRID_IMP_5KC:
1013 c->cputype = CPU_5KC;
4f12b91d 1014 c->writecombine = _CACHE_UNCACHED;
cea7e2df 1015 __cpu_name[cpu] = "MIPS 5Kc";
1da177e4 1016 break;
78d4803f
LY		 1017 case PRID_IMP_5KE:
1018 c->cputype = CPU_5KE;
4f12b91d 1019 c->writecombine = _CACHE_UNCACHED;
78d4803f
LY		 1020 __cpu_name[cpu] = "MIPS 5KE";
1021 break;
1da177e4
LT		 1022 case PRID_IMP_20KC:
1023 c->cputype = CPU_20KC;
4f12b91d 1024 c->writecombine = _CACHE_UNCACHED;
cea7e2df 1025 __cpu_name[cpu] = "MIPS 20Kc";
1da177e4
LT		 1026 break;
1027 case PRID_IMP_24K:
1028 c->cputype = CPU_24K;
4f12b91d 1029 c->writecombine = _CACHE_UNCACHED;
cea7e2df 1030 __cpu_name[cpu] = "MIPS 24Kc";
1da177e4 1031 break;
42f3caef
JC		 1032 case PRID_IMP_24KE:
1033 c->cputype = CPU_24K;
4f12b91d 1034 c->writecombine = _CACHE_UNCACHED;
42f3caef
JC		 1035 __cpu_name[cpu] = "MIPS 24KEc";
1036 break;
1da177e4
LT		 1037 case PRID_IMP_25KF:
1038 c->cputype = CPU_25KF;
4f12b91d 1039 c->writecombine = _CACHE_UNCACHED;
cea7e2df 1040 __cpu_name[cpu] = "MIPS 25Kc";
1da177e4 1041 break;
bbc7f22f
RB		 1042 case PRID_IMP_34K:
1043 c->cputype = CPU_34K;
4f12b91d 1044 c->writecombine = _CACHE_UNCACHED;
cea7e2df 1045 __cpu_name[cpu] = "MIPS 34Kc";
bbc7f22f 1046 break;
c620953c
CD		 1047 case PRID_IMP_74K:
1048 c->cputype = CPU_74K;
4f12b91d 1049 c->writecombine = _CACHE_UNCACHED;
cea7e2df 1050 __cpu_name[cpu] = "MIPS 74Kc";
c620953c 1051 break;
113c62d9
SH		 1052 case PRID_IMP_M14KC:
1053 c->cputype = CPU_M14KC;
4f12b91d 1054 c->writecombine = _CACHE_UNCACHED;
113c62d9
SH		 1055 __cpu_name[cpu] = "MIPS M14Kc";
1056 break;
f8fa4811
SH		 1057 case PRID_IMP_M14KEC:
1058 c->cputype = CPU_M14KEC;
4f12b91d 1059 c->writecombine = _CACHE_UNCACHED;
f8fa4811
SH		 1060 __cpu_name[cpu] = "MIPS M14KEc";
1061 break;
39b8d525
RB		 1062 case PRID_IMP_1004K:
1063 c->cputype = CPU_1004K;
4f12b91d 1064 c->writecombine = _CACHE_UNCACHED;
cea7e2df 1065 __cpu_name[cpu] = "MIPS 1004Kc";
39b8d525 1066 break;
006a851b 1067 case PRID_IMP_1074K:
442e14a2 1068 c->cputype = CPU_1074K;
4f12b91d 1069 c->writecombine = _CACHE_UNCACHED;
006a851b
SH		 1070 __cpu_name[cpu] = "MIPS 1074Kc";
1071 break;
b5f065e7
LY		 1072 case PRID_IMP_INTERAPTIV_UP:
1073 c->cputype = CPU_INTERAPTIV;
1074 __cpu_name[cpu] = "MIPS interAptiv";
1075 break;
1076 case PRID_IMP_INTERAPTIV_MP:
1077 c->cputype = CPU_INTERAPTIV;
1078 __cpu_name[cpu] = "MIPS interAptiv (multi)";
1079 break;
b0d4d300
LY		 1080 case PRID_IMP_PROAPTIV_UP:
1081 c->cputype = CPU_PROAPTIV;
1082 __cpu_name[cpu] = "MIPS proAptiv";
1083 break;
1084 case PRID_IMP_PROAPTIV_MP:
1085 c->cputype = CPU_PROAPTIV;
1086 __cpu_name[cpu] = "MIPS proAptiv (multi)";
1087 break;
829dcc0a
JH		 1088 case PRID_IMP_P5600:
1089 c->cputype = CPU_P5600;
1090 __cpu_name[cpu] = "MIPS P5600";
1091 break;
9943ed92
LY		 1092 case PRID_IMP_M5150:
1093 c->cputype = CPU_M5150;
1094 __cpu_name[cpu] = "MIPS M5150";
1095 break;
1da177e4 1096 }
0b6d497f 1097
75b5b5e0
LY		 1098 decode_configs(c);
1099
0b6d497f 1100 spram_config();
1da177e4
LT		 1101}
1102
cea7e2df 1103static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4 1104{
4194318c 1105 decode_configs(c);
8ff374b9 1106 switch (c->processor_id & PRID_IMP_MASK) {
1da177e4
LT		 1107 case PRID_IMP_AU1_REV1:
1108 case PRID_IMP_AU1_REV2:
270717a8 1109 c->cputype = CPU_ALCHEMY;
1da177e4
LT		 1110 switch ((c->processor_id >> 24) & 0xff) {
1111 case 0:
cea7e2df 1112 __cpu_name[cpu] = "Au1000";
1da177e4
LT		 1113 break;
1114 case 1:
cea7e2df 1115 __cpu_name[cpu] = "Au1500";
1da177e4
LT		 1116 break;
1117 case 2:
cea7e2df 1118 __cpu_name[cpu] = "Au1100";
1da177e4
LT		 1119 break;
1120 case 3:
cea7e2df 1121 __cpu_name[cpu] = "Au1550";
1da177e4 1122 break;
e3ad1c23 1123 case 4:
cea7e2df 1124 __cpu_name[cpu] = "Au1200";
8ff374b9 1125 if ((c->processor_id & PRID_REV_MASK) == 2)
cea7e2df 1126 __cpu_name[cpu] = "Au1250";
237cfee1
ML		 1127 break;
1128 case 5:
cea7e2df 1129 __cpu_name[cpu] = "Au1210";
e3ad1c23 1130 break;
1da177e4 1131 default:
270717a8 1132 __cpu_name[cpu] = "Au1xxx";
1da177e4
LT		 1133 break;
1134 }
1da177e4
LT		 1135 break;
1136 }
1137}
1138
cea7e2df 1139static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4 1140{
4194318c 1141 decode_configs(c);
02cf2119 1142
4f12b91d 1143 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
8ff374b9 1144 switch (c->processor_id & PRID_IMP_MASK) {
1da177e4
LT		 1145 case PRID_IMP_SB1:
1146 c->cputype = CPU_SB1;
cea7e2df 1147 __cpu_name[cpu] = "SiByte SB1";
1da177e4 1148 /* FPU in pass1 is known to have issues. */
8ff374b9 1149 if ((c->processor_id & PRID_REV_MASK) < 0x02)
010b853b 1150 c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
1da177e4 1151 break;
93ce2f52
AI		 1152 case PRID_IMP_SB1A:
1153 c->cputype = CPU_SB1A;
cea7e2df 1154 __cpu_name[cpu] = "SiByte SB1A";
93ce2f52 1155 break;
1da177e4
LT		 1156 }
1157}
1158
cea7e2df 1159static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4 1160{
4194318c 1161 decode_configs(c);
8ff374b9 1162 switch (c->processor_id & PRID_IMP_MASK) {
1da177e4
LT		 1163 case PRID_IMP_SR71000:
1164 c->cputype = CPU_SR71000;
cea7e2df 1165 __cpu_name[cpu] = "Sandcraft SR71000";
1da177e4
LT		 1166 c->scache.ways = 8;
1167 c->tlbsize = 64;
1168 break;
1169 }
1170}
1171
cea7e2df 1172static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu)
bdf21b18
PP		 1173{
1174 decode_configs(c);
8ff374b9 1175 switch (c->processor_id & PRID_IMP_MASK) {
bdf21b18
PP		 1176 case PRID_IMP_PR4450:
1177 c->cputype = CPU_PR4450;
cea7e2df 1178 __cpu_name[cpu] = "Philips PR4450";
a96102be 1179 set_isa(c, MIPS_CPU_ISA_M32R1);
bdf21b18 1180 break;
bdf21b18
PP		 1181 }
1182}
1183
cea7e2df 1184static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
1c0c13eb
AJ		 1185{
1186 decode_configs(c);
8ff374b9 1187 switch (c->processor_id & PRID_IMP_MASK) {
190fca3e
KC		 1188 case PRID_IMP_BMIPS32_REV4:
1189 case PRID_IMP_BMIPS32_REV8:
602977b0
KC		 1190 c->cputype = CPU_BMIPS32;
1191 __cpu_name[cpu] = "Broadcom BMIPS32";
06785df0 1192 set_elf_platform(cpu, "bmips32");
602977b0
KC		 1193 break;
1194 case PRID_IMP_BMIPS3300:
1195 case PRID_IMP_BMIPS3300_ALT:
1196 case PRID_IMP_BMIPS3300_BUG:
1197 c->cputype = CPU_BMIPS3300;
1198 __cpu_name[cpu] = "Broadcom BMIPS3300";
06785df0 1199 set_elf_platform(cpu, "bmips3300");
602977b0
KC		 1200 break;
1201 case PRID_IMP_BMIPS43XX: {
8ff374b9 1202 int rev = c->processor_id & PRID_REV_MASK;
602977b0
KC		 1203
1204 if (rev >= PRID_REV_BMIPS4380_LO &&
1205 rev <= PRID_REV_BMIPS4380_HI) {
1206 c->cputype = CPU_BMIPS4380;
1207 __cpu_name[cpu] = "Broadcom BMIPS4380";
06785df0 1208 set_elf_platform(cpu, "bmips4380");
602977b0
KC		 1209 } else {
1210 c->cputype = CPU_BMIPS4350;
1211 __cpu_name[cpu] = "Broadcom BMIPS4350";
06785df0 1212 set_elf_platform(cpu, "bmips4350");
602977b0 1213 }
0de663ef 1214 break;
602977b0
KC		 1215 }
1216 case PRID_IMP_BMIPS5000:
68e6a783 1217 case PRID_IMP_BMIPS5200:
602977b0
KC		 1218 c->cputype = CPU_BMIPS5000;
1219 __cpu_name[cpu] = "Broadcom BMIPS5000";
06785df0 1220 set_elf_platform(cpu, "bmips5000");
602977b0 1221 c->options |= MIPS_CPU_ULRI;
0de663ef 1222 break;
1c0c13eb
AJ		 1223 }
1224}
1225
0dd4781b
DD		 1226static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu)
1227{
1228 decode_configs(c);
8ff374b9 1229 switch (c->processor_id & PRID_IMP_MASK) {
0dd4781b
DD		 1230 case PRID_IMP_CAVIUM_CN38XX:
1231 case PRID_IMP_CAVIUM_CN31XX:
1232 case PRID_IMP_CAVIUM_CN30XX:
6f329468
DD		 1233 c->cputype = CPU_CAVIUM_OCTEON;
1234 __cpu_name[cpu] = "Cavium Octeon";
1235 goto platform;
0dd4781b
DD		 1236 case PRID_IMP_CAVIUM_CN58XX:
1237 case PRID_IMP_CAVIUM_CN56XX:
1238 case PRID_IMP_CAVIUM_CN50XX:
1239 case PRID_IMP_CAVIUM_CN52XX:
6f329468
DD		 1240 c->cputype = CPU_CAVIUM_OCTEON_PLUS;
1241 __cpu_name[cpu] = "Cavium Octeon+";
1242platform:
c094c99e 1243 set_elf_platform(cpu, "octeon");
0dd4781b 1244 break;
a1431b61 1245 case PRID_IMP_CAVIUM_CN61XX:
0e56b385 1246 case PRID_IMP_CAVIUM_CN63XX:
a1431b61
DD		 1247 case PRID_IMP_CAVIUM_CN66XX:
1248 case PRID_IMP_CAVIUM_CN68XX:
af04bb85 1249 case PRID_IMP_CAVIUM_CNF71XX:
0e56b385
DD		 1250 c->cputype = CPU_CAVIUM_OCTEON2;
1251 __cpu_name[cpu] = "Cavium Octeon II";
c094c99e 1252 set_elf_platform(cpu, "octeon2");
0e56b385 1253 break;
af04bb85
DD		 1254 case PRID_IMP_CAVIUM_CN70XX:
1255 case PRID_IMP_CAVIUM_CN78XX:
1256 c->cputype = CPU_CAVIUM_OCTEON3;
1257 __cpu_name[cpu] = "Cavium Octeon III";
1258 set_elf_platform(cpu, "octeon3");
1259 break;
0dd4781b
DD		 1260 default:
1261 printk(KERN_INFO "Unknown Octeon chip!\n");
1262 c->cputype = CPU_UNKNOWN;
1263 break;
1264 }
1265}
1266
83ccf69d
LPC		 1267static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
1268{
1269 decode_configs(c);
1270 /* JZRISC does not implement the CP0 counter. */
1271 c->options &= ~MIPS_CPU_COUNTER;
06947aaa 1272 BUG_ON(!__builtin_constant_p(cpu_has_counter) || cpu_has_counter);
8ff374b9 1273 switch (c->processor_id & PRID_IMP_MASK) {
83ccf69d
LPC		 1274 case PRID_IMP_JZRISC:
1275 c->cputype = CPU_JZRISC;
4f12b91d 1276 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
83ccf69d
LPC		 1277 __cpu_name[cpu] = "Ingenic JZRISC";
1278 break;
1279 default:
1280 panic("Unknown Ingenic Processor ID!");
1281 break;
1282 }
1283}
1284
a7117c6b
J		 1285static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu)
1286{
1287 decode_configs(c);
1288
8ff374b9 1289 if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_NETLOGIC_AU13XX) {
809f36c6
ML		 1290 c->cputype = CPU_ALCHEMY;
1291 __cpu_name[cpu] = "Au1300";
1292 /* following stuff is not for Alchemy */
1293 return;
1294 }
1295
70342287
RB		 1296 c->options = (MIPS_CPU_TLB |
1297 MIPS_CPU_4KEX |
a7117c6b 1298 MIPS_CPU_COUNTER |
70342287
RB		 1299 MIPS_CPU_DIVEC |
1300 MIPS_CPU_WATCH |
1301 MIPS_CPU_EJTAG |
a7117c6b
J		 1302 MIPS_CPU_LLSC);
1303
8ff374b9 1304 switch (c->processor_id & PRID_IMP_MASK) {
4ca86a2f 1305 case PRID_IMP_NETLOGIC_XLP2XX:
8907c55e 1306 case PRID_IMP_NETLOGIC_XLP9XX:
1c983986 1307 case PRID_IMP_NETLOGIC_XLP5XX:
4ca86a2f
J		 1308 c->cputype = CPU_XLP;
1309 __cpu_name[cpu] = "Broadcom XLPII";
1310 break;
1311
2aa54b20
J		 1312 case PRID_IMP_NETLOGIC_XLP8XX:
1313 case PRID_IMP_NETLOGIC_XLP3XX:
a3d4fb2d
J		 1314 c->cputype = CPU_XLP;
1315 __cpu_name[cpu] = "Netlogic XLP";
1316 break;
1317
a7117c6b
J		 1318 case PRID_IMP_NETLOGIC_XLR732:
1319 case PRID_IMP_NETLOGIC_XLR716:
1320 case PRID_IMP_NETLOGIC_XLR532:
1321 case PRID_IMP_NETLOGIC_XLR308:
1322 case PRID_IMP_NETLOGIC_XLR532C:
1323 case PRID_IMP_NETLOGIC_XLR516C:
1324 case PRID_IMP_NETLOGIC_XLR508C:
1325 case PRID_IMP_NETLOGIC_XLR308C:
1326 c->cputype = CPU_XLR;
1327 __cpu_name[cpu] = "Netlogic XLR";
1328 break;
1329
1330 case PRID_IMP_NETLOGIC_XLS608:
1331 case PRID_IMP_NETLOGIC_XLS408:
1332 case PRID_IMP_NETLOGIC_XLS404:
1333 case PRID_IMP_NETLOGIC_XLS208:
1334 case PRID_IMP_NETLOGIC_XLS204:
1335 case PRID_IMP_NETLOGIC_XLS108:
1336 case PRID_IMP_NETLOGIC_XLS104:
1337 case PRID_IMP_NETLOGIC_XLS616B:
1338 case PRID_IMP_NETLOGIC_XLS608B:
1339 case PRID_IMP_NETLOGIC_XLS416B:
1340 case PRID_IMP_NETLOGIC_XLS412B:
1341 case PRID_IMP_NETLOGIC_XLS408B:
1342 case PRID_IMP_NETLOGIC_XLS404B:
1343 c->cputype = CPU_XLR;
1344 __cpu_name[cpu] = "Netlogic XLS";
1345 break;
1346
1347 default:
a3d4fb2d 1348 pr_info("Unknown Netlogic chip id [%02x]!\n",
a7117c6b
J		 1349 c->processor_id);
1350 c->cputype = CPU_XLR;
1351 break;
1352 }
1353
a3d4fb2d 1354 if (c->cputype == CPU_XLP) {
a96102be 1355 set_isa(c, MIPS_CPU_ISA_M64R2);
a3d4fb2d
J		 1356 c->options |= (MIPS_CPU_FPU | MIPS_CPU_ULRI | MIPS_CPU_MCHECK);
1357 /* This will be updated again after all threads are woken up */
1358 c->tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1;
1359 } else {
a96102be 1360 set_isa(c, MIPS_CPU_ISA_M64R1);
a3d4fb2d
J		 1361 c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1;
1362 }
7777b939 1363 c->kscratch_mask = 0xf;
a7117c6b
J		 1364}
1365
949e51be
DD		 1366#ifdef CONFIG_64BIT
1367/* For use by uaccess.h */
1368u64 __ua_limit;
1369EXPORT_SYMBOL(__ua_limit);
1370#endif
1371
9966db25 1372const char *__cpu_name[NR_CPUS];
874fd3b5 1373const char *__elf_platform;
9966db25 1374
078a55fc 1375void cpu_probe(void)
1da177e4
LT		 1376{
1377 struct cpuinfo_mips *c = &current_cpu_data;
9966db25 1378 unsigned int cpu = smp_processor_id();
1da177e4 1379
70342287 1380 c->processor_id = PRID_IMP_UNKNOWN;
1da177e4
LT		 1381 c->fpu_id = FPIR_IMP_NONE;
1382 c->cputype = CPU_UNKNOWN;
4f12b91d 1383 c->writecombine = _CACHE_UNCACHED;
1da177e4 1384
9b26616c
MR		 1385 c->fpu_csr31 = FPU_CSR_RN;
1386 c->fpu_msk31 = FPU_CSR_RSVD | FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
1387
1da177e4 1388 c->processor_id = read_c0_prid();
8ff374b9 1389 switch (c->processor_id & PRID_COMP_MASK) {
1da177e4 1390 case PRID_COMP_LEGACY:
cea7e2df 1391 cpu_probe_legacy(c, cpu);
1da177e4
LT		 1392 break;
1393 case PRID_COMP_MIPS:
cea7e2df 1394 cpu_probe_mips(c, cpu);
1da177e4
LT		 1395 break;
1396 case PRID_COMP_ALCHEMY:
cea7e2df 1397 cpu_probe_alchemy(c, cpu);
1da177e4
LT		 1398 break;
1399 case PRID_COMP_SIBYTE:
cea7e2df 1400 cpu_probe_sibyte(c, cpu);
1da177e4 1401 break;
1c0c13eb 1402 case PRID_COMP_BROADCOM:
cea7e2df 1403 cpu_probe_broadcom(c, cpu);
1c0c13eb 1404 break;
1da177e4 1405 case PRID_COMP_SANDCRAFT:
cea7e2df 1406 cpu_probe_sandcraft(c, cpu);
1da177e4 1407 break;
a92b0588 1408 case PRID_COMP_NXP:
cea7e2df 1409 cpu_probe_nxp(c, cpu);
a3dddd56 1410 break;
0dd4781b
DD		 1411 case PRID_COMP_CAVIUM:
1412 cpu_probe_cavium(c, cpu);
1413 break;
83ccf69d
LPC		 1414 case PRID_COMP_INGENIC:
1415 cpu_probe_ingenic(c, cpu);
1416 break;
a7117c6b
J		 1417 case PRID_COMP_NETLOGIC:
1418 cpu_probe_netlogic(c, cpu);
1419 break;
1da177e4 1420 }
dec8b1ca 1421
cea7e2df
RB		 1422 BUG_ON(!__cpu_name[cpu]);
1423 BUG_ON(c->cputype == CPU_UNKNOWN);
1424
dec8b1ca
FBH		 1425 /*
1426 * Platform code can force the cpu type to optimize code
1427 * generation. In that case be sure the cpu type is correctly
1428 * manually setup otherwise it could trigger some nasty bugs.
1429 */
1430 BUG_ON(current_cpu_type() != c->cputype);
1431
0103d23f
KC		 1432 if (mips_fpu_disabled)
1433 c->options &= ~MIPS_CPU_FPU;
1434
1435 if (mips_dsp_disabled)
ee80f7c7 1436 c->ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
0103d23f 1437
3d528b32
MC		 1438 if (mips_htw_disabled) {
1439 c->options &= ~MIPS_CPU_HTW;
1440 write_c0_pwctl(read_c0_pwctl() &
1441 ~(1 << MIPS_PWCTL_PWEN_SHIFT));
1442 }
1443
4194318c 1444 if (c->options & MIPS_CPU_FPU) {
1da177e4 1445 c->fpu_id = cpu_get_fpu_id();
9b26616c 1446 mips_nofpu_msk31 = c->fpu_msk31;
4194318c 1447
9cb60e20
MR		 1448 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
1449 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
1450 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) {
4194318c
RB		 1451 if (c->fpu_id & MIPS_FPIR_3D)
1452 c->ases |= MIPS_ASE_MIPS3D;
adac5d53
PB		 1453 if (c->fpu_id & MIPS_FPIR_FREP)
1454 c->options |= MIPS_CPU_FRE;
4194318c 1455 }
9b26616c
MR		 1456
1457 cpu_set_fpu_fcsr_mask(c);
f6843626
MR		 1458 } else
1459 cpu_set_nofpu_id(c);
9966db25 1460
8b8aa636 1461 if (cpu_has_mips_r2_r6) {
f6771dbb 1462 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
da4b62cd
AC		 1463 /* R2 has Performance Counter Interrupt indicator */
1464 c->options |= MIPS_CPU_PCI;
1465 }
f6771dbb
RB		 1466 else
1467 c->srsets = 1;
91dfc423 1468
a8ad1367 1469 if (cpu_has_msa) {
a5e9a69e 1470 c->msa_id = cpu_get_msa_id();
a8ad1367
PB		 1471 WARN(c->msa_id & MSA_IR_WRPF,
1472 "Vector register partitioning unimplemented!");
1473 }
a5e9a69e 1474
91dfc423 1475 cpu_probe_vmbits(c);
949e51be
DD		 1476
1477#ifdef CONFIG_64BIT
1478 if (cpu == 0)
1479 __ua_limit = ~((1ull << cpu_vmbits) - 1);
1480#endif
1da177e4
LT		 1481}
1482
078a55fc 1483void cpu_report(void)
1da177e4
LT		 1484{
1485 struct cpuinfo_mips *c = &current_cpu_data;
1486
d9f897c9
LY		 1487 pr_info("CPU%d revision is: %08x (%s)\n",
1488 smp_processor_id(), c->processor_id, cpu_name_string());
1da177e4 1489 if (c->options & MIPS_CPU_FPU)
9966db25 1490 printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id);
a5e9a69e
PB		 1491 if (cpu_has_msa)
1492 pr_info("MSA revision is: %08x\n", c->msa_id);
1da177e4 1493}
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