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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Processor capabilities determination functions. | |
3 | * | |
4 | * Copyright (C) xxxx the Anonymous | |
010b853b | 5 | * Copyright (C) 1994 - 2006 Ralf Baechle |
4194318c | 6 | * Copyright (C) 2003, 2004 Maciej W. Rozycki |
70342287 | 7 | * Copyright (C) 2001, 2004, 2011, 2012 MIPS Technologies, Inc. |
1da177e4 LT |
8 | * |
9 | * This program is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License | |
11 | * as published by the Free Software Foundation; either version | |
12 | * 2 of the License, or (at your option) any later version. | |
13 | */ | |
1da177e4 LT |
14 | #include <linux/init.h> |
15 | #include <linux/kernel.h> | |
16 | #include <linux/ptrace.h> | |
631330f5 | 17 | #include <linux/smp.h> |
1da177e4 | 18 | #include <linux/stddef.h> |
73bc256d | 19 | #include <linux/export.h> |
1da177e4 | 20 | |
5759906c | 21 | #include <asm/bugs.h> |
1da177e4 | 22 | #include <asm/cpu.h> |
f6843626 | 23 | #include <asm/cpu-features.h> |
69f24d17 | 24 | #include <asm/cpu-type.h> |
1da177e4 LT |
25 | #include <asm/fpu.h> |
26 | #include <asm/mipsregs.h> | |
30ee615b | 27 | #include <asm/mipsmtregs.h> |
a5e9a69e | 28 | #include <asm/msa.h> |
654f57bf | 29 | #include <asm/watch.h> |
06372a63 | 30 | #include <asm/elf.h> |
4f12b91d | 31 | #include <asm/pgtable-bits.h> |
a074f0e8 | 32 | #include <asm/spram.h> |
949e51be DD |
33 | #include <asm/uaccess.h> |
34 | ||
7aecd5ca MR |
35 | /* |
36 | * Get the FPU Implementation/Revision. | |
37 | */ | |
38 | static inline unsigned long cpu_get_fpu_id(void) | |
39 | { | |
40 | unsigned long tmp, fpu_id; | |
41 | ||
42 | tmp = read_c0_status(); | |
43 | __enable_fpu(FPU_AS_IS); | |
44 | fpu_id = read_32bit_cp1_register(CP1_REVISION); | |
45 | write_c0_status(tmp); | |
46 | return fpu_id; | |
47 | } | |
48 | ||
49 | /* | |
50 | * Check if the CPU has an external FPU. | |
51 | */ | |
52 | static inline int __cpu_has_fpu(void) | |
53 | { | |
54 | return (cpu_get_fpu_id() & FPIR_IMP_MASK) != FPIR_IMP_NONE; | |
55 | } | |
56 | ||
57 | static inline unsigned long cpu_get_msa_id(void) | |
58 | { | |
59 | unsigned long status, msa_id; | |
60 | ||
61 | status = read_c0_status(); | |
62 | __enable_fpu(FPU_64BIT); | |
63 | enable_msa(); | |
64 | msa_id = read_msa_ir(); | |
65 | disable_msa(); | |
66 | write_c0_status(status); | |
67 | return msa_id; | |
68 | } | |
69 | ||
9b26616c MR |
70 | /* |
71 | * Determine the FCSR mask for FPU hardware. | |
72 | */ | |
73 | static inline void cpu_set_fpu_fcsr_mask(struct cpuinfo_mips *c) | |
74 | { | |
75 | unsigned long sr, mask, fcsr, fcsr0, fcsr1; | |
76 | ||
77 | mask = FPU_CSR_ALL_X | FPU_CSR_ALL_E | FPU_CSR_ALL_S | FPU_CSR_RM; | |
78 | ||
79 | sr = read_c0_status(); | |
80 | __enable_fpu(FPU_AS_IS); | |
81 | ||
82 | fcsr = read_32bit_cp1_register(CP1_STATUS); | |
83 | ||
84 | fcsr0 = fcsr & mask; | |
85 | write_32bit_cp1_register(CP1_STATUS, fcsr0); | |
86 | fcsr0 = read_32bit_cp1_register(CP1_STATUS); | |
87 | ||
88 | fcsr1 = fcsr | ~mask; | |
89 | write_32bit_cp1_register(CP1_STATUS, fcsr1); | |
90 | fcsr1 = read_32bit_cp1_register(CP1_STATUS); | |
91 | ||
92 | write_32bit_cp1_register(CP1_STATUS, fcsr); | |
93 | ||
94 | write_c0_status(sr); | |
95 | ||
96 | c->fpu_msk31 = ~(fcsr0 ^ fcsr1) & ~mask; | |
97 | } | |
98 | ||
f6843626 MR |
99 | /* |
100 | * Set the FIR feature flags for the FPU emulator. | |
101 | */ | |
102 | static void cpu_set_nofpu_id(struct cpuinfo_mips *c) | |
103 | { | |
104 | u32 value; | |
105 | ||
106 | value = 0; | |
107 | if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 | | |
108 | MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 | | |
109 | MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) | |
110 | value |= MIPS_FPIR_D | MIPS_FPIR_S; | |
111 | if (c->isa_level & (MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 | | |
112 | MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) | |
113 | value |= MIPS_FPIR_F64 | MIPS_FPIR_L | MIPS_FPIR_W; | |
114 | c->fpu_id = value; | |
115 | } | |
116 | ||
9b26616c MR |
117 | /* Determined FPU emulator mask to use for the boot CPU with "nofpu". */ |
118 | static unsigned int mips_nofpu_msk31; | |
119 | ||
7aecd5ca MR |
120 | /* |
121 | * Set options for FPU hardware. | |
122 | */ | |
123 | static void cpu_set_fpu_opts(struct cpuinfo_mips *c) | |
124 | { | |
125 | c->fpu_id = cpu_get_fpu_id(); | |
126 | mips_nofpu_msk31 = c->fpu_msk31; | |
127 | ||
128 | if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 | | |
129 | MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 | | |
130 | MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) { | |
131 | if (c->fpu_id & MIPS_FPIR_3D) | |
132 | c->ases |= MIPS_ASE_MIPS3D; | |
133 | if (c->fpu_id & MIPS_FPIR_FREP) | |
134 | c->options |= MIPS_CPU_FRE; | |
135 | } | |
136 | ||
137 | cpu_set_fpu_fcsr_mask(c); | |
138 | } | |
139 | ||
140 | /* | |
141 | * Set options for the FPU emulator. | |
142 | */ | |
143 | static void cpu_set_nofpu_opts(struct cpuinfo_mips *c) | |
144 | { | |
145 | c->options &= ~MIPS_CPU_FPU; | |
146 | c->fpu_msk31 = mips_nofpu_msk31; | |
147 | ||
148 | cpu_set_nofpu_id(c); | |
149 | } | |
150 | ||
078a55fc | 151 | static int mips_fpu_disabled; |
0103d23f KC |
152 | |
153 | static int __init fpu_disable(char *s) | |
154 | { | |
7aecd5ca | 155 | cpu_set_nofpu_opts(&boot_cpu_data); |
0103d23f KC |
156 | mips_fpu_disabled = 1; |
157 | ||
158 | return 1; | |
159 | } | |
160 | ||
161 | __setup("nofpu", fpu_disable); | |
162 | ||
078a55fc | 163 | int mips_dsp_disabled; |
0103d23f KC |
164 | |
165 | static int __init dsp_disable(char *s) | |
166 | { | |
ee80f7c7 | 167 | cpu_data[0].ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P); |
0103d23f KC |
168 | mips_dsp_disabled = 1; |
169 | ||
170 | return 1; | |
171 | } | |
172 | ||
173 | __setup("nodsp", dsp_disable); | |
174 | ||
3d528b32 MC |
175 | static int mips_htw_disabled; |
176 | ||
177 | static int __init htw_disable(char *s) | |
178 | { | |
179 | mips_htw_disabled = 1; | |
180 | cpu_data[0].options &= ~MIPS_CPU_HTW; | |
181 | write_c0_pwctl(read_c0_pwctl() & | |
182 | ~(1 << MIPS_PWCTL_PWEN_SHIFT)); | |
183 | ||
184 | return 1; | |
185 | } | |
186 | ||
187 | __setup("nohtw", htw_disable); | |
188 | ||
97f4ad29 MC |
189 | static int mips_ftlb_disabled; |
190 | static int mips_has_ftlb_configured; | |
191 | ||
192 | static void set_ftlb_enable(struct cpuinfo_mips *c, int enable); | |
193 | ||
194 | static int __init ftlb_disable(char *s) | |
195 | { | |
196 | unsigned int config4, mmuextdef; | |
197 | ||
198 | /* | |
199 | * If the core hasn't done any FTLB configuration, there is nothing | |
200 | * for us to do here. | |
201 | */ | |
202 | if (!mips_has_ftlb_configured) | |
203 | return 1; | |
204 | ||
205 | /* Disable it in the boot cpu */ | |
206 | set_ftlb_enable(&cpu_data[0], 0); | |
207 | ||
208 | back_to_back_c0_hazard(); | |
209 | ||
210 | config4 = read_c0_config4(); | |
211 | ||
212 | /* Check that FTLB has been disabled */ | |
213 | mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF; | |
214 | /* MMUSIZEEXT == VTLB ON, FTLB OFF */ | |
215 | if (mmuextdef == MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT) { | |
216 | /* This should never happen */ | |
217 | pr_warn("FTLB could not be disabled!\n"); | |
218 | return 1; | |
219 | } | |
220 | ||
221 | mips_ftlb_disabled = 1; | |
222 | mips_has_ftlb_configured = 0; | |
223 | ||
224 | /* | |
225 | * noftlb is mainly used for debug purposes so print | |
226 | * an informative message instead of using pr_debug() | |
227 | */ | |
228 | pr_info("FTLB has been disabled\n"); | |
229 | ||
230 | /* | |
231 | * Some of these bits are duplicated in the decode_config4. | |
232 | * MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT is the only possible case | |
233 | * once FTLB has been disabled so undo what decode_config4 did. | |
234 | */ | |
235 | cpu_data[0].tlbsize -= cpu_data[0].tlbsizeftlbways * | |
236 | cpu_data[0].tlbsizeftlbsets; | |
237 | cpu_data[0].tlbsizeftlbsets = 0; | |
238 | cpu_data[0].tlbsizeftlbways = 0; | |
239 | ||
240 | return 1; | |
241 | } | |
242 | ||
243 | __setup("noftlb", ftlb_disable); | |
244 | ||
245 | ||
9267a30d MSJ |
246 | static inline void check_errata(void) |
247 | { | |
248 | struct cpuinfo_mips *c = ¤t_cpu_data; | |
249 | ||
69f24d17 | 250 | switch (current_cpu_type()) { |
9267a30d MSJ |
251 | case CPU_34K: |
252 | /* | |
253 | * Erratum "RPS May Cause Incorrect Instruction Execution" | |
b633648c | 254 | * This code only handles VPE0, any SMP/RTOS code |
9267a30d MSJ |
255 | * making use of VPE1 will be responsable for that VPE. |
256 | */ | |
257 | if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2) | |
258 | write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS); | |
259 | break; | |
260 | default: | |
261 | break; | |
262 | } | |
263 | } | |
264 | ||
1da177e4 LT |
265 | void __init check_bugs32(void) |
266 | { | |
9267a30d | 267 | check_errata(); |
1da177e4 LT |
268 | } |
269 | ||
270 | /* | |
271 | * Probe whether cpu has config register by trying to play with | |
272 | * alternate cache bit and see whether it matters. | |
273 | * It's used by cpu_probe to distinguish between R3000A and R3081. | |
274 | */ | |
275 | static inline int cpu_has_confreg(void) | |
276 | { | |
277 | #ifdef CONFIG_CPU_R3000 | |
278 | extern unsigned long r3k_cache_size(unsigned long); | |
279 | unsigned long size1, size2; | |
280 | unsigned long cfg = read_c0_conf(); | |
281 | ||
282 | size1 = r3k_cache_size(ST0_ISC); | |
283 | write_c0_conf(cfg ^ R30XX_CONF_AC); | |
284 | size2 = r3k_cache_size(ST0_ISC); | |
285 | write_c0_conf(cfg); | |
286 | return size1 != size2; | |
287 | #else | |
288 | return 0; | |
289 | #endif | |
290 | } | |
291 | ||
c094c99e RM |
292 | static inline void set_elf_platform(int cpu, const char *plat) |
293 | { | |
294 | if (cpu == 0) | |
295 | __elf_platform = plat; | |
296 | } | |
297 | ||
91dfc423 GR |
298 | static inline void cpu_probe_vmbits(struct cpuinfo_mips *c) |
299 | { | |
300 | #ifdef __NEED_VMBITS_PROBE | |
5b7efa89 | 301 | write_c0_entryhi(0x3fffffffffffe000ULL); |
91dfc423 | 302 | back_to_back_c0_hazard(); |
5b7efa89 | 303 | c->vmbits = fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL); |
91dfc423 GR |
304 | #endif |
305 | } | |
306 | ||
078a55fc | 307 | static void set_isa(struct cpuinfo_mips *c, unsigned int isa) |
a96102be SH |
308 | { |
309 | switch (isa) { | |
310 | case MIPS_CPU_ISA_M64R2: | |
311 | c->isa_level |= MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2; | |
312 | case MIPS_CPU_ISA_M64R1: | |
313 | c->isa_level |= MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1; | |
314 | case MIPS_CPU_ISA_V: | |
315 | c->isa_level |= MIPS_CPU_ISA_V; | |
316 | case MIPS_CPU_ISA_IV: | |
317 | c->isa_level |= MIPS_CPU_ISA_IV; | |
318 | case MIPS_CPU_ISA_III: | |
1990e542 | 319 | c->isa_level |= MIPS_CPU_ISA_II | MIPS_CPU_ISA_III; |
a96102be SH |
320 | break; |
321 | ||
8b8aa636 LY |
322 | /* R6 incompatible with everything else */ |
323 | case MIPS_CPU_ISA_M64R6: | |
324 | c->isa_level |= MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6; | |
325 | case MIPS_CPU_ISA_M32R6: | |
326 | c->isa_level |= MIPS_CPU_ISA_M32R6; | |
327 | /* Break here so we don't add incompatible ISAs */ | |
328 | break; | |
a96102be SH |
329 | case MIPS_CPU_ISA_M32R2: |
330 | c->isa_level |= MIPS_CPU_ISA_M32R2; | |
331 | case MIPS_CPU_ISA_M32R1: | |
332 | c->isa_level |= MIPS_CPU_ISA_M32R1; | |
333 | case MIPS_CPU_ISA_II: | |
334 | c->isa_level |= MIPS_CPU_ISA_II; | |
a96102be SH |
335 | break; |
336 | } | |
337 | } | |
338 | ||
078a55fc | 339 | static char unknown_isa[] = KERN_ERR \ |
2fa36399 KC |
340 | "Unsupported ISA type, c0.config0: %d."; |
341 | ||
cf0a8aa0 MC |
342 | static unsigned int calculate_ftlb_probability(struct cpuinfo_mips *c) |
343 | { | |
344 | ||
345 | unsigned int probability = c->tlbsize / c->tlbsizevtlb; | |
346 | ||
347 | /* | |
348 | * 0 = All TLBWR instructions go to FTLB | |
349 | * 1 = 15:1: For every 16 TBLWR instructions, 15 go to the | |
350 | * FTLB and 1 goes to the VTLB. | |
351 | * 2 = 7:1: As above with 7:1 ratio. | |
352 | * 3 = 3:1: As above with 3:1 ratio. | |
353 | * | |
354 | * Use the linear midpoint as the probability threshold. | |
355 | */ | |
356 | if (probability >= 12) | |
357 | return 1; | |
358 | else if (probability >= 6) | |
359 | return 2; | |
360 | else | |
361 | /* | |
362 | * So FTLB is less than 4 times bigger than VTLB. | |
363 | * A 3:1 ratio can still be useful though. | |
364 | */ | |
365 | return 3; | |
366 | } | |
367 | ||
75b5b5e0 LY |
368 | static void set_ftlb_enable(struct cpuinfo_mips *c, int enable) |
369 | { | |
370 | unsigned int config6; | |
d83b0e82 JH |
371 | |
372 | /* It's implementation dependent how the FTLB can be enabled */ | |
373 | switch (c->cputype) { | |
374 | case CPU_PROAPTIV: | |
375 | case CPU_P5600: | |
376 | /* proAptiv & related cores use Config6 to enable the FTLB */ | |
75b5b5e0 | 377 | config6 = read_c0_config6(); |
cf0a8aa0 MC |
378 | /* Clear the old probability value */ |
379 | config6 &= ~(3 << MIPS_CONF6_FTLBP_SHIFT); | |
75b5b5e0 LY |
380 | if (enable) |
381 | /* Enable FTLB */ | |
cf0a8aa0 MC |
382 | write_c0_config6(config6 | |
383 | (calculate_ftlb_probability(c) | |
384 | << MIPS_CONF6_FTLBP_SHIFT) | |
385 | | MIPS_CONF6_FTLBEN); | |
75b5b5e0 LY |
386 | else |
387 | /* Disable FTLB */ | |
388 | write_c0_config6(config6 & ~MIPS_CONF6_FTLBEN); | |
389 | back_to_back_c0_hazard(); | |
d83b0e82 | 390 | break; |
75b5b5e0 LY |
391 | } |
392 | } | |
393 | ||
2fa36399 KC |
394 | static inline unsigned int decode_config0(struct cpuinfo_mips *c) |
395 | { | |
396 | unsigned int config0; | |
397 | int isa; | |
398 | ||
399 | config0 = read_c0_config(); | |
400 | ||
75b5b5e0 LY |
401 | /* |
402 | * Look for Standard TLB or Dual VTLB and FTLB | |
403 | */ | |
404 | if ((((config0 & MIPS_CONF_MT) >> 7) == 1) || | |
405 | (((config0 & MIPS_CONF_MT) >> 7) == 4)) | |
2fa36399 | 406 | c->options |= MIPS_CPU_TLB; |
75b5b5e0 | 407 | |
2fa36399 KC |
408 | isa = (config0 & MIPS_CONF_AT) >> 13; |
409 | switch (isa) { | |
410 | case 0: | |
411 | switch ((config0 & MIPS_CONF_AR) >> 10) { | |
412 | case 0: | |
a96102be | 413 | set_isa(c, MIPS_CPU_ISA_M32R1); |
2fa36399 KC |
414 | break; |
415 | case 1: | |
a96102be | 416 | set_isa(c, MIPS_CPU_ISA_M32R2); |
2fa36399 | 417 | break; |
8b8aa636 LY |
418 | case 2: |
419 | set_isa(c, MIPS_CPU_ISA_M32R6); | |
420 | break; | |
2fa36399 KC |
421 | default: |
422 | goto unknown; | |
423 | } | |
424 | break; | |
425 | case 2: | |
426 | switch ((config0 & MIPS_CONF_AR) >> 10) { | |
427 | case 0: | |
a96102be | 428 | set_isa(c, MIPS_CPU_ISA_M64R1); |
2fa36399 KC |
429 | break; |
430 | case 1: | |
a96102be | 431 | set_isa(c, MIPS_CPU_ISA_M64R2); |
2fa36399 | 432 | break; |
8b8aa636 LY |
433 | case 2: |
434 | set_isa(c, MIPS_CPU_ISA_M64R6); | |
435 | break; | |
2fa36399 KC |
436 | default: |
437 | goto unknown; | |
438 | } | |
439 | break; | |
440 | default: | |
441 | goto unknown; | |
442 | } | |
443 | ||
444 | return config0 & MIPS_CONF_M; | |
445 | ||
446 | unknown: | |
447 | panic(unknown_isa, config0); | |
448 | } | |
449 | ||
450 | static inline unsigned int decode_config1(struct cpuinfo_mips *c) | |
451 | { | |
452 | unsigned int config1; | |
453 | ||
454 | config1 = read_c0_config1(); | |
455 | ||
456 | if (config1 & MIPS_CONF1_MD) | |
457 | c->ases |= MIPS_ASE_MDMX; | |
458 | if (config1 & MIPS_CONF1_WR) | |
459 | c->options |= MIPS_CPU_WATCH; | |
460 | if (config1 & MIPS_CONF1_CA) | |
461 | c->ases |= MIPS_ASE_MIPS16; | |
462 | if (config1 & MIPS_CONF1_EP) | |
463 | c->options |= MIPS_CPU_EJTAG; | |
464 | if (config1 & MIPS_CONF1_FP) { | |
465 | c->options |= MIPS_CPU_FPU; | |
466 | c->options |= MIPS_CPU_32FPR; | |
467 | } | |
75b5b5e0 | 468 | if (cpu_has_tlb) { |
2fa36399 | 469 | c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1; |
75b5b5e0 LY |
470 | c->tlbsizevtlb = c->tlbsize; |
471 | c->tlbsizeftlbsets = 0; | |
472 | } | |
2fa36399 KC |
473 | |
474 | return config1 & MIPS_CONF_M; | |
475 | } | |
476 | ||
477 | static inline unsigned int decode_config2(struct cpuinfo_mips *c) | |
478 | { | |
479 | unsigned int config2; | |
480 | ||
481 | config2 = read_c0_config2(); | |
482 | ||
483 | if (config2 & MIPS_CONF2_SL) | |
484 | c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT; | |
485 | ||
486 | return config2 & MIPS_CONF_M; | |
487 | } | |
488 | ||
489 | static inline unsigned int decode_config3(struct cpuinfo_mips *c) | |
490 | { | |
491 | unsigned int config3; | |
492 | ||
493 | config3 = read_c0_config3(); | |
494 | ||
b2ab4f08 | 495 | if (config3 & MIPS_CONF3_SM) { |
2fa36399 | 496 | c->ases |= MIPS_ASE_SMARTMIPS; |
b2ab4f08 SH |
497 | c->options |= MIPS_CPU_RIXI; |
498 | } | |
499 | if (config3 & MIPS_CONF3_RXI) | |
500 | c->options |= MIPS_CPU_RIXI; | |
2fa36399 KC |
501 | if (config3 & MIPS_CONF3_DSP) |
502 | c->ases |= MIPS_ASE_DSP; | |
ee80f7c7 SH |
503 | if (config3 & MIPS_CONF3_DSP2P) |
504 | c->ases |= MIPS_ASE_DSP2P; | |
2fa36399 KC |
505 | if (config3 & MIPS_CONF3_VINT) |
506 | c->options |= MIPS_CPU_VINT; | |
507 | if (config3 & MIPS_CONF3_VEIC) | |
508 | c->options |= MIPS_CPU_VEIC; | |
509 | if (config3 & MIPS_CONF3_MT) | |
510 | c->ases |= MIPS_ASE_MIPSMT; | |
511 | if (config3 & MIPS_CONF3_ULRI) | |
512 | c->options |= MIPS_CPU_ULRI; | |
f8fa4811 SH |
513 | if (config3 & MIPS_CONF3_ISA) |
514 | c->options |= MIPS_CPU_MICROMIPS; | |
1e7decdb DD |
515 | if (config3 & MIPS_CONF3_VZ) |
516 | c->ases |= MIPS_ASE_VZ; | |
4a0156fb SH |
517 | if (config3 & MIPS_CONF3_SC) |
518 | c->options |= MIPS_CPU_SEGMENTS; | |
a5e9a69e PB |
519 | if (config3 & MIPS_CONF3_MSA) |
520 | c->ases |= MIPS_ASE_MSA; | |
3d528b32 | 521 | /* Only tested on 32-bit cores */ |
ed4cbc81 MC |
522 | if ((config3 & MIPS_CONF3_PW) && config_enabled(CONFIG_32BIT)) { |
523 | c->htw_seq = 0; | |
3d528b32 | 524 | c->options |= MIPS_CPU_HTW; |
ed4cbc81 | 525 | } |
9b3274bd JH |
526 | if (config3 & MIPS_CONF3_CDMM) |
527 | c->options |= MIPS_CPU_CDMM; | |
2fa36399 KC |
528 | |
529 | return config3 & MIPS_CONF_M; | |
530 | } | |
531 | ||
532 | static inline unsigned int decode_config4(struct cpuinfo_mips *c) | |
533 | { | |
534 | unsigned int config4; | |
75b5b5e0 LY |
535 | unsigned int newcf4; |
536 | unsigned int mmuextdef; | |
537 | unsigned int ftlb_page = MIPS_CONF4_FTLBPAGESIZE; | |
2fa36399 KC |
538 | |
539 | config4 = read_c0_config4(); | |
540 | ||
1745c1ef LY |
541 | if (cpu_has_tlb) { |
542 | if (((config4 & MIPS_CONF4_IE) >> 29) == 2) | |
543 | c->options |= MIPS_CPU_TLBINV; | |
75b5b5e0 LY |
544 | mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF; |
545 | switch (mmuextdef) { | |
546 | case MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT: | |
547 | c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40; | |
548 | c->tlbsizevtlb = c->tlbsize; | |
549 | break; | |
550 | case MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT: | |
551 | c->tlbsizevtlb += | |
552 | ((config4 & MIPS_CONF4_VTLBSIZEEXT) >> | |
553 | MIPS_CONF4_VTLBSIZEEXT_SHIFT) * 0x40; | |
554 | c->tlbsize = c->tlbsizevtlb; | |
555 | ftlb_page = MIPS_CONF4_VFTLBPAGESIZE; | |
556 | /* fall through */ | |
557 | case MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT: | |
97f4ad29 MC |
558 | if (mips_ftlb_disabled) |
559 | break; | |
75b5b5e0 LY |
560 | newcf4 = (config4 & ~ftlb_page) | |
561 | (page_size_ftlb(mmuextdef) << | |
562 | MIPS_CONF4_FTLBPAGESIZE_SHIFT); | |
563 | write_c0_config4(newcf4); | |
564 | back_to_back_c0_hazard(); | |
565 | config4 = read_c0_config4(); | |
566 | if (config4 != newcf4) { | |
567 | pr_err("PAGE_SIZE 0x%lx is not supported by FTLB (config4=0x%x)\n", | |
568 | PAGE_SIZE, config4); | |
569 | /* Switch FTLB off */ | |
570 | set_ftlb_enable(c, 0); | |
571 | break; | |
572 | } | |
573 | c->tlbsizeftlbsets = 1 << | |
574 | ((config4 & MIPS_CONF4_FTLBSETS) >> | |
575 | MIPS_CONF4_FTLBSETS_SHIFT); | |
576 | c->tlbsizeftlbways = ((config4 & MIPS_CONF4_FTLBWAYS) >> | |
577 | MIPS_CONF4_FTLBWAYS_SHIFT) + 2; | |
578 | c->tlbsize += c->tlbsizeftlbways * c->tlbsizeftlbsets; | |
97f4ad29 | 579 | mips_has_ftlb_configured = 1; |
75b5b5e0 LY |
580 | break; |
581 | } | |
1745c1ef LY |
582 | } |
583 | ||
2fa36399 KC |
584 | c->kscratch_mask = (config4 >> 16) & 0xff; |
585 | ||
586 | return config4 & MIPS_CONF_M; | |
587 | } | |
588 | ||
8b8a7634 RB |
589 | static inline unsigned int decode_config5(struct cpuinfo_mips *c) |
590 | { | |
591 | unsigned int config5; | |
592 | ||
593 | config5 = read_c0_config5(); | |
d175ed2b | 594 | config5 &= ~(MIPS_CONF5_UFR | MIPS_CONF5_UFE); |
8b8a7634 RB |
595 | write_c0_config5(config5); |
596 | ||
49016748 MC |
597 | if (config5 & MIPS_CONF5_EVA) |
598 | c->options |= MIPS_CPU_EVA; | |
1f6c52ff PB |
599 | if (config5 & MIPS_CONF5_MRP) |
600 | c->options |= MIPS_CPU_MAAR; | |
5aed9da1 MC |
601 | if (config5 & MIPS_CONF5_LLB) |
602 | c->options |= MIPS_CPU_RW_LLB; | |
c5b36783 SH |
603 | #ifdef CONFIG_XPA |
604 | if (config5 & MIPS_CONF5_MVH) | |
605 | c->options |= MIPS_CPU_XPA; | |
606 | #endif | |
49016748 | 607 | |
8b8a7634 RB |
608 | return config5 & MIPS_CONF_M; |
609 | } | |
610 | ||
078a55fc | 611 | static void decode_configs(struct cpuinfo_mips *c) |
2fa36399 KC |
612 | { |
613 | int ok; | |
614 | ||
615 | /* MIPS32 or MIPS64 compliant CPU. */ | |
616 | c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER | | |
617 | MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK; | |
618 | ||
619 | c->scache.flags = MIPS_CACHE_NOT_PRESENT; | |
620 | ||
97f4ad29 MC |
621 | /* Enable FTLB if present and not disabled */ |
622 | set_ftlb_enable(c, !mips_ftlb_disabled); | |
75b5b5e0 | 623 | |
2fa36399 | 624 | ok = decode_config0(c); /* Read Config registers. */ |
70342287 | 625 | BUG_ON(!ok); /* Arch spec violation! */ |
2fa36399 KC |
626 | if (ok) |
627 | ok = decode_config1(c); | |
628 | if (ok) | |
629 | ok = decode_config2(c); | |
630 | if (ok) | |
631 | ok = decode_config3(c); | |
632 | if (ok) | |
633 | ok = decode_config4(c); | |
8b8a7634 RB |
634 | if (ok) |
635 | ok = decode_config5(c); | |
2fa36399 KC |
636 | |
637 | mips_probe_watch_registers(c); | |
638 | ||
6575b1d4 LY |
639 | if (cpu_has_rixi) { |
640 | /* Enable the RIXI exceptions */ | |
a5770df0 | 641 | set_c0_pagegrain(PG_IEC); |
6575b1d4 LY |
642 | back_to_back_c0_hazard(); |
643 | /* Verify the IEC bit is set */ | |
644 | if (read_c0_pagegrain() & PG_IEC) | |
645 | c->options |= MIPS_CPU_RIXIEX; | |
646 | } | |
647 | ||
0ee958e1 | 648 | #ifndef CONFIG_MIPS_CPS |
8b8aa636 | 649 | if (cpu_has_mips_r2_r6) { |
45b585c8 | 650 | c->core = get_ebase_cpunum(); |
30ee615b PB |
651 | if (cpu_has_mipsmt) |
652 | c->core >>= fls(core_nvpes()) - 1; | |
653 | } | |
0ee958e1 | 654 | #endif |
2fa36399 KC |
655 | } |
656 | ||
02cf2119 | 657 | #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \ |
1da177e4 LT |
658 | | MIPS_CPU_COUNTER) |
659 | ||
cea7e2df | 660 | static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu) |
1da177e4 | 661 | { |
8ff374b9 | 662 | switch (c->processor_id & PRID_IMP_MASK) { |
1da177e4 LT |
663 | case PRID_IMP_R2000: |
664 | c->cputype = CPU_R2000; | |
cea7e2df | 665 | __cpu_name[cpu] = "R2000"; |
9b26616c | 666 | c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS; |
02cf2119 | 667 | c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE | |
03751e79 | 668 | MIPS_CPU_NOFPUEX; |
1da177e4 LT |
669 | if (__cpu_has_fpu()) |
670 | c->options |= MIPS_CPU_FPU; | |
671 | c->tlbsize = 64; | |
672 | break; | |
673 | case PRID_IMP_R3000: | |
8ff374b9 | 674 | if ((c->processor_id & PRID_REV_MASK) == PRID_REV_R3000A) { |
cea7e2df | 675 | if (cpu_has_confreg()) { |
1da177e4 | 676 | c->cputype = CPU_R3081E; |
cea7e2df RB |
677 | __cpu_name[cpu] = "R3081"; |
678 | } else { | |
1da177e4 | 679 | c->cputype = CPU_R3000A; |
cea7e2df RB |
680 | __cpu_name[cpu] = "R3000A"; |
681 | } | |
cea7e2df | 682 | } else { |
1da177e4 | 683 | c->cputype = CPU_R3000; |
cea7e2df RB |
684 | __cpu_name[cpu] = "R3000"; |
685 | } | |
9b26616c | 686 | c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS; |
02cf2119 | 687 | c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE | |
03751e79 | 688 | MIPS_CPU_NOFPUEX; |
1da177e4 LT |
689 | if (__cpu_has_fpu()) |
690 | c->options |= MIPS_CPU_FPU; | |
691 | c->tlbsize = 64; | |
692 | break; | |
693 | case PRID_IMP_R4000: | |
694 | if (read_c0_config() & CONF_SC) { | |
8ff374b9 MR |
695 | if ((c->processor_id & PRID_REV_MASK) >= |
696 | PRID_REV_R4400) { | |
1da177e4 | 697 | c->cputype = CPU_R4400PC; |
cea7e2df RB |
698 | __cpu_name[cpu] = "R4400PC"; |
699 | } else { | |
1da177e4 | 700 | c->cputype = CPU_R4000PC; |
cea7e2df RB |
701 | __cpu_name[cpu] = "R4000PC"; |
702 | } | |
1da177e4 | 703 | } else { |
7f177a52 MR |
704 | int cca = read_c0_config() & CONF_CM_CMASK; |
705 | int mc; | |
706 | ||
707 | /* | |
708 | * SC and MC versions can't be reliably told apart, | |
709 | * but only the latter support coherent caching | |
710 | * modes so assume the firmware has set the KSEG0 | |
711 | * coherency attribute reasonably (if uncached, we | |
712 | * assume SC). | |
713 | */ | |
714 | switch (cca) { | |
715 | case CONF_CM_CACHABLE_CE: | |
716 | case CONF_CM_CACHABLE_COW: | |
717 | case CONF_CM_CACHABLE_CUW: | |
718 | mc = 1; | |
719 | break; | |
720 | default: | |
721 | mc = 0; | |
722 | break; | |
723 | } | |
8ff374b9 MR |
724 | if ((c->processor_id & PRID_REV_MASK) >= |
725 | PRID_REV_R4400) { | |
7f177a52 MR |
726 | c->cputype = mc ? CPU_R4400MC : CPU_R4400SC; |
727 | __cpu_name[cpu] = mc ? "R4400MC" : "R4400SC"; | |
cea7e2df | 728 | } else { |
7f177a52 MR |
729 | c->cputype = mc ? CPU_R4000MC : CPU_R4000SC; |
730 | __cpu_name[cpu] = mc ? "R4000MC" : "R4000SC"; | |
cea7e2df | 731 | } |
1da177e4 LT |
732 | } |
733 | ||
a96102be | 734 | set_isa(c, MIPS_CPU_ISA_III); |
9b26616c | 735 | c->fpu_msk31 |= FPU_CSR_CONDX; |
1da177e4 | 736 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | |
03751e79 SH |
737 | MIPS_CPU_WATCH | MIPS_CPU_VCE | |
738 | MIPS_CPU_LLSC; | |
1da177e4 LT |
739 | c->tlbsize = 48; |
740 | break; | |
741 | case PRID_IMP_VR41XX: | |
9f91e506 | 742 | set_isa(c, MIPS_CPU_ISA_III); |
9b26616c | 743 | c->fpu_msk31 |= FPU_CSR_CONDX; |
9f91e506 YY |
744 | c->options = R4K_OPTS; |
745 | c->tlbsize = 32; | |
1da177e4 | 746 | switch (c->processor_id & 0xf0) { |
1da177e4 LT |
747 | case PRID_REV_VR4111: |
748 | c->cputype = CPU_VR4111; | |
cea7e2df | 749 | __cpu_name[cpu] = "NEC VR4111"; |
1da177e4 | 750 | break; |
1da177e4 LT |
751 | case PRID_REV_VR4121: |
752 | c->cputype = CPU_VR4121; | |
cea7e2df | 753 | __cpu_name[cpu] = "NEC VR4121"; |
1da177e4 LT |
754 | break; |
755 | case PRID_REV_VR4122: | |
cea7e2df | 756 | if ((c->processor_id & 0xf) < 0x3) { |
1da177e4 | 757 | c->cputype = CPU_VR4122; |
cea7e2df RB |
758 | __cpu_name[cpu] = "NEC VR4122"; |
759 | } else { | |
1da177e4 | 760 | c->cputype = CPU_VR4181A; |
cea7e2df RB |
761 | __cpu_name[cpu] = "NEC VR4181A"; |
762 | } | |
1da177e4 LT |
763 | break; |
764 | case PRID_REV_VR4130: | |
cea7e2df | 765 | if ((c->processor_id & 0xf) < 0x4) { |
1da177e4 | 766 | c->cputype = CPU_VR4131; |
cea7e2df RB |
767 | __cpu_name[cpu] = "NEC VR4131"; |
768 | } else { | |
1da177e4 | 769 | c->cputype = CPU_VR4133; |
9f91e506 | 770 | c->options |= MIPS_CPU_LLSC; |
cea7e2df RB |
771 | __cpu_name[cpu] = "NEC VR4133"; |
772 | } | |
1da177e4 LT |
773 | break; |
774 | default: | |
775 | printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n"); | |
776 | c->cputype = CPU_VR41XX; | |
cea7e2df | 777 | __cpu_name[cpu] = "NEC Vr41xx"; |
1da177e4 LT |
778 | break; |
779 | } | |
1da177e4 LT |
780 | break; |
781 | case PRID_IMP_R4300: | |
782 | c->cputype = CPU_R4300; | |
cea7e2df | 783 | __cpu_name[cpu] = "R4300"; |
a96102be | 784 | set_isa(c, MIPS_CPU_ISA_III); |
9b26616c | 785 | c->fpu_msk31 |= FPU_CSR_CONDX; |
1da177e4 | 786 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | |
03751e79 | 787 | MIPS_CPU_LLSC; |
1da177e4 LT |
788 | c->tlbsize = 32; |
789 | break; | |
790 | case PRID_IMP_R4600: | |
791 | c->cputype = CPU_R4600; | |
cea7e2df | 792 | __cpu_name[cpu] = "R4600"; |
a96102be | 793 | set_isa(c, MIPS_CPU_ISA_III); |
9b26616c | 794 | c->fpu_msk31 |= FPU_CSR_CONDX; |
075e7502 TS |
795 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | |
796 | MIPS_CPU_LLSC; | |
1da177e4 LT |
797 | c->tlbsize = 48; |
798 | break; | |
799 | #if 0 | |
03751e79 | 800 | case PRID_IMP_R4650: |
1da177e4 LT |
801 | /* |
802 | * This processor doesn't have an MMU, so it's not | |
803 | * "real easy" to run Linux on it. It is left purely | |
804 | * for documentation. Commented out because it shares | |
805 | * it's c0_prid id number with the TX3900. | |
806 | */ | |
a3dddd56 | 807 | c->cputype = CPU_R4650; |
cea7e2df | 808 | __cpu_name[cpu] = "R4650"; |
a96102be | 809 | set_isa(c, MIPS_CPU_ISA_III); |
9b26616c | 810 | c->fpu_msk31 |= FPU_CSR_CONDX; |
1da177e4 | 811 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC; |
03751e79 | 812 | c->tlbsize = 48; |
1da177e4 LT |
813 | break; |
814 | #endif | |
815 | case PRID_IMP_TX39: | |
9b26616c | 816 | c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS; |
02cf2119 | 817 | c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE; |
1da177e4 LT |
818 | |
819 | if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) { | |
820 | c->cputype = CPU_TX3927; | |
cea7e2df | 821 | __cpu_name[cpu] = "TX3927"; |
1da177e4 LT |
822 | c->tlbsize = 64; |
823 | } else { | |
8ff374b9 | 824 | switch (c->processor_id & PRID_REV_MASK) { |
1da177e4 LT |
825 | case PRID_REV_TX3912: |
826 | c->cputype = CPU_TX3912; | |
cea7e2df | 827 | __cpu_name[cpu] = "TX3912"; |
1da177e4 LT |
828 | c->tlbsize = 32; |
829 | break; | |
830 | case PRID_REV_TX3922: | |
831 | c->cputype = CPU_TX3922; | |
cea7e2df | 832 | __cpu_name[cpu] = "TX3922"; |
1da177e4 LT |
833 | c->tlbsize = 64; |
834 | break; | |
1da177e4 LT |
835 | } |
836 | } | |
837 | break; | |
838 | case PRID_IMP_R4700: | |
839 | c->cputype = CPU_R4700; | |
cea7e2df | 840 | __cpu_name[cpu] = "R4700"; |
a96102be | 841 | set_isa(c, MIPS_CPU_ISA_III); |
9b26616c | 842 | c->fpu_msk31 |= FPU_CSR_CONDX; |
1da177e4 | 843 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | |
03751e79 | 844 | MIPS_CPU_LLSC; |
1da177e4 LT |
845 | c->tlbsize = 48; |
846 | break; | |
847 | case PRID_IMP_TX49: | |
848 | c->cputype = CPU_TX49XX; | |
cea7e2df | 849 | __cpu_name[cpu] = "R49XX"; |
a96102be | 850 | set_isa(c, MIPS_CPU_ISA_III); |
9b26616c | 851 | c->fpu_msk31 |= FPU_CSR_CONDX; |
1da177e4 LT |
852 | c->options = R4K_OPTS | MIPS_CPU_LLSC; |
853 | if (!(c->processor_id & 0x08)) | |
854 | c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR; | |
855 | c->tlbsize = 48; | |
856 | break; | |
857 | case PRID_IMP_R5000: | |
858 | c->cputype = CPU_R5000; | |
cea7e2df | 859 | __cpu_name[cpu] = "R5000"; |
a96102be | 860 | set_isa(c, MIPS_CPU_ISA_IV); |
1da177e4 | 861 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | |
03751e79 | 862 | MIPS_CPU_LLSC; |
1da177e4 LT |
863 | c->tlbsize = 48; |
864 | break; | |
865 | case PRID_IMP_R5432: | |
866 | c->cputype = CPU_R5432; | |
cea7e2df | 867 | __cpu_name[cpu] = "R5432"; |
a96102be | 868 | set_isa(c, MIPS_CPU_ISA_IV); |
1da177e4 | 869 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | |
03751e79 | 870 | MIPS_CPU_WATCH | MIPS_CPU_LLSC; |
1da177e4 LT |
871 | c->tlbsize = 48; |
872 | break; | |
873 | case PRID_IMP_R5500: | |
874 | c->cputype = CPU_R5500; | |
cea7e2df | 875 | __cpu_name[cpu] = "R5500"; |
a96102be | 876 | set_isa(c, MIPS_CPU_ISA_IV); |
1da177e4 | 877 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | |
03751e79 | 878 | MIPS_CPU_WATCH | MIPS_CPU_LLSC; |
1da177e4 LT |
879 | c->tlbsize = 48; |
880 | break; | |
881 | case PRID_IMP_NEVADA: | |
882 | c->cputype = CPU_NEVADA; | |
cea7e2df | 883 | __cpu_name[cpu] = "Nevada"; |
a96102be | 884 | set_isa(c, MIPS_CPU_ISA_IV); |
1da177e4 | 885 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | |
03751e79 | 886 | MIPS_CPU_DIVEC | MIPS_CPU_LLSC; |
1da177e4 LT |
887 | c->tlbsize = 48; |
888 | break; | |
889 | case PRID_IMP_R6000: | |
890 | c->cputype = CPU_R6000; | |
cea7e2df | 891 | __cpu_name[cpu] = "R6000"; |
a96102be | 892 | set_isa(c, MIPS_CPU_ISA_II); |
9b26616c | 893 | c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS; |
1da177e4 | 894 | c->options = MIPS_CPU_TLB | MIPS_CPU_FPU | |
03751e79 | 895 | MIPS_CPU_LLSC; |
1da177e4 LT |
896 | c->tlbsize = 32; |
897 | break; | |
898 | case PRID_IMP_R6000A: | |
899 | c->cputype = CPU_R6000A; | |
cea7e2df | 900 | __cpu_name[cpu] = "R6000A"; |
a96102be | 901 | set_isa(c, MIPS_CPU_ISA_II); |
9b26616c | 902 | c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS; |
1da177e4 | 903 | c->options = MIPS_CPU_TLB | MIPS_CPU_FPU | |
03751e79 | 904 | MIPS_CPU_LLSC; |
1da177e4 LT |
905 | c->tlbsize = 32; |
906 | break; | |
907 | case PRID_IMP_RM7000: | |
908 | c->cputype = CPU_RM7000; | |
cea7e2df | 909 | __cpu_name[cpu] = "RM7000"; |
a96102be | 910 | set_isa(c, MIPS_CPU_ISA_IV); |
1da177e4 | 911 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | |
03751e79 | 912 | MIPS_CPU_LLSC; |
1da177e4 | 913 | /* |
70342287 | 914 | * Undocumented RM7000: Bit 29 in the info register of |
1da177e4 LT |
915 | * the RM7000 v2.0 indicates if the TLB has 48 or 64 |
916 | * entries. | |
917 | * | |
70342287 RB |
918 | * 29 1 => 64 entry JTLB |
919 | * 0 => 48 entry JTLB | |
1da177e4 LT |
920 | */ |
921 | c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48; | |
1da177e4 LT |
922 | break; |
923 | case PRID_IMP_R8000: | |
924 | c->cputype = CPU_R8000; | |
cea7e2df | 925 | __cpu_name[cpu] = "RM8000"; |
a96102be | 926 | set_isa(c, MIPS_CPU_ISA_IV); |
1da177e4 | 927 | c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX | |
03751e79 SH |
928 | MIPS_CPU_FPU | MIPS_CPU_32FPR | |
929 | MIPS_CPU_LLSC; | |
1da177e4 LT |
930 | c->tlbsize = 384; /* has weird TLB: 3-way x 128 */ |
931 | break; | |
932 | case PRID_IMP_R10000: | |
933 | c->cputype = CPU_R10000; | |
cea7e2df | 934 | __cpu_name[cpu] = "R10000"; |
a96102be | 935 | set_isa(c, MIPS_CPU_ISA_IV); |
8b36612a | 936 | c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | |
03751e79 | 937 | MIPS_CPU_FPU | MIPS_CPU_32FPR | |
1da177e4 | 938 | MIPS_CPU_COUNTER | MIPS_CPU_WATCH | |
03751e79 | 939 | MIPS_CPU_LLSC; |
1da177e4 LT |
940 | c->tlbsize = 64; |
941 | break; | |
942 | case PRID_IMP_R12000: | |
943 | c->cputype = CPU_R12000; | |
cea7e2df | 944 | __cpu_name[cpu] = "R12000"; |
a96102be | 945 | set_isa(c, MIPS_CPU_ISA_IV); |
8b36612a | 946 | c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | |
03751e79 | 947 | MIPS_CPU_FPU | MIPS_CPU_32FPR | |
1da177e4 | 948 | MIPS_CPU_COUNTER | MIPS_CPU_WATCH | |
03751e79 | 949 | MIPS_CPU_LLSC; |
1da177e4 LT |
950 | c->tlbsize = 64; |
951 | break; | |
44d921b2 | 952 | case PRID_IMP_R14000: |
30577391 JK |
953 | if (((c->processor_id >> 4) & 0x0f) > 2) { |
954 | c->cputype = CPU_R16000; | |
955 | __cpu_name[cpu] = "R16000"; | |
956 | } else { | |
957 | c->cputype = CPU_R14000; | |
958 | __cpu_name[cpu] = "R14000"; | |
959 | } | |
a96102be | 960 | set_isa(c, MIPS_CPU_ISA_IV); |
44d921b2 | 961 | c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | |
03751e79 | 962 | MIPS_CPU_FPU | MIPS_CPU_32FPR | |
44d921b2 | 963 | MIPS_CPU_COUNTER | MIPS_CPU_WATCH | |
03751e79 | 964 | MIPS_CPU_LLSC; |
44d921b2 K |
965 | c->tlbsize = 64; |
966 | break; | |
26859198 | 967 | case PRID_IMP_LOONGSON_64: /* Loongson-2/3 */ |
5aac1e8a RM |
968 | switch (c->processor_id & PRID_REV_MASK) { |
969 | case PRID_REV_LOONGSON2E: | |
c579d310 HC |
970 | c->cputype = CPU_LOONGSON2; |
971 | __cpu_name[cpu] = "ICT Loongson-2"; | |
5aac1e8a | 972 | set_elf_platform(cpu, "loongson2e"); |
7352c8b1 | 973 | set_isa(c, MIPS_CPU_ISA_III); |
9b26616c | 974 | c->fpu_msk31 |= FPU_CSR_CONDX; |
5aac1e8a RM |
975 | break; |
976 | case PRID_REV_LOONGSON2F: | |
c579d310 HC |
977 | c->cputype = CPU_LOONGSON2; |
978 | __cpu_name[cpu] = "ICT Loongson-2"; | |
5aac1e8a | 979 | set_elf_platform(cpu, "loongson2f"); |
7352c8b1 | 980 | set_isa(c, MIPS_CPU_ISA_III); |
9b26616c | 981 | c->fpu_msk31 |= FPU_CSR_CONDX; |
5aac1e8a | 982 | break; |
c579d310 HC |
983 | case PRID_REV_LOONGSON3A: |
984 | c->cputype = CPU_LOONGSON3; | |
985 | __cpu_name[cpu] = "ICT Loongson-3"; | |
986 | set_elf_platform(cpu, "loongson3a"); | |
7352c8b1 | 987 | set_isa(c, MIPS_CPU_ISA_M64R1); |
c579d310 | 988 | break; |
e7841be5 HC |
989 | case PRID_REV_LOONGSON3B_R1: |
990 | case PRID_REV_LOONGSON3B_R2: | |
991 | c->cputype = CPU_LOONGSON3; | |
992 | __cpu_name[cpu] = "ICT Loongson-3"; | |
993 | set_elf_platform(cpu, "loongson3b"); | |
7352c8b1 | 994 | set_isa(c, MIPS_CPU_ISA_M64R1); |
e7841be5 | 995 | break; |
5aac1e8a RM |
996 | } |
997 | ||
2a21c730 FZ |
998 | c->options = R4K_OPTS | |
999 | MIPS_CPU_FPU | MIPS_CPU_LLSC | | |
1000 | MIPS_CPU_32FPR; | |
1001 | c->tlbsize = 64; | |
cc94ea31 | 1002 | c->writecombine = _CACHE_UNCACHED_ACCELERATED; |
2a21c730 | 1003 | break; |
26859198 | 1004 | case PRID_IMP_LOONGSON_32: /* Loongson-1 */ |
2fa36399 | 1005 | decode_configs(c); |
b4672d37 | 1006 | |
2fa36399 | 1007 | c->cputype = CPU_LOONGSON1; |
1da177e4 | 1008 | |
2fa36399 KC |
1009 | switch (c->processor_id & PRID_REV_MASK) { |
1010 | case PRID_REV_LOONGSON1B: | |
1011 | __cpu_name[cpu] = "Loongson 1B"; | |
b4672d37 | 1012 | break; |
b4672d37 | 1013 | } |
4194318c | 1014 | |
2fa36399 | 1015 | break; |
1da177e4 | 1016 | } |
1da177e4 LT |
1017 | } |
1018 | ||
cea7e2df | 1019 | static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu) |
1da177e4 | 1020 | { |
4f12b91d | 1021 | c->writecombine = _CACHE_UNCACHED_ACCELERATED; |
8ff374b9 | 1022 | switch (c->processor_id & PRID_IMP_MASK) { |
b2498af5 LY |
1023 | case PRID_IMP_QEMU_GENERIC: |
1024 | c->writecombine = _CACHE_UNCACHED; | |
1025 | c->cputype = CPU_QEMU_GENERIC; | |
1026 | __cpu_name[cpu] = "MIPS GENERIC QEMU"; | |
1027 | break; | |
1da177e4 LT |
1028 | case PRID_IMP_4KC: |
1029 | c->cputype = CPU_4KC; | |
4f12b91d | 1030 | c->writecombine = _CACHE_UNCACHED; |
cea7e2df | 1031 | __cpu_name[cpu] = "MIPS 4Kc"; |
1da177e4 LT |
1032 | break; |
1033 | case PRID_IMP_4KEC: | |
2b07bd02 RB |
1034 | case PRID_IMP_4KECR2: |
1035 | c->cputype = CPU_4KEC; | |
4f12b91d | 1036 | c->writecombine = _CACHE_UNCACHED; |
cea7e2df | 1037 | __cpu_name[cpu] = "MIPS 4KEc"; |
2b07bd02 | 1038 | break; |
1da177e4 | 1039 | case PRID_IMP_4KSC: |
8afcb5d8 | 1040 | case PRID_IMP_4KSD: |
1da177e4 | 1041 | c->cputype = CPU_4KSC; |
4f12b91d | 1042 | c->writecombine = _CACHE_UNCACHED; |
cea7e2df | 1043 | __cpu_name[cpu] = "MIPS 4KSc"; |
1da177e4 LT |
1044 | break; |
1045 | case PRID_IMP_5KC: | |
1046 | c->cputype = CPU_5KC; | |
4f12b91d | 1047 | c->writecombine = _CACHE_UNCACHED; |
cea7e2df | 1048 | __cpu_name[cpu] = "MIPS 5Kc"; |
1da177e4 | 1049 | break; |
78d4803f LY |
1050 | case PRID_IMP_5KE: |
1051 | c->cputype = CPU_5KE; | |
4f12b91d | 1052 | c->writecombine = _CACHE_UNCACHED; |
78d4803f LY |
1053 | __cpu_name[cpu] = "MIPS 5KE"; |
1054 | break; | |
1da177e4 LT |
1055 | case PRID_IMP_20KC: |
1056 | c->cputype = CPU_20KC; | |
4f12b91d | 1057 | c->writecombine = _CACHE_UNCACHED; |
cea7e2df | 1058 | __cpu_name[cpu] = "MIPS 20Kc"; |
1da177e4 LT |
1059 | break; |
1060 | case PRID_IMP_24K: | |
1061 | c->cputype = CPU_24K; | |
4f12b91d | 1062 | c->writecombine = _CACHE_UNCACHED; |
cea7e2df | 1063 | __cpu_name[cpu] = "MIPS 24Kc"; |
1da177e4 | 1064 | break; |
42f3caef JC |
1065 | case PRID_IMP_24KE: |
1066 | c->cputype = CPU_24K; | |
4f12b91d | 1067 | c->writecombine = _CACHE_UNCACHED; |
42f3caef JC |
1068 | __cpu_name[cpu] = "MIPS 24KEc"; |
1069 | break; | |
1da177e4 LT |
1070 | case PRID_IMP_25KF: |
1071 | c->cputype = CPU_25KF; | |
4f12b91d | 1072 | c->writecombine = _CACHE_UNCACHED; |
cea7e2df | 1073 | __cpu_name[cpu] = "MIPS 25Kc"; |
1da177e4 | 1074 | break; |
bbc7f22f RB |
1075 | case PRID_IMP_34K: |
1076 | c->cputype = CPU_34K; | |
4f12b91d | 1077 | c->writecombine = _CACHE_UNCACHED; |
cea7e2df | 1078 | __cpu_name[cpu] = "MIPS 34Kc"; |
bbc7f22f | 1079 | break; |
c620953c CD |
1080 | case PRID_IMP_74K: |
1081 | c->cputype = CPU_74K; | |
4f12b91d | 1082 | c->writecombine = _CACHE_UNCACHED; |
cea7e2df | 1083 | __cpu_name[cpu] = "MIPS 74Kc"; |
c620953c | 1084 | break; |
113c62d9 SH |
1085 | case PRID_IMP_M14KC: |
1086 | c->cputype = CPU_M14KC; | |
4f12b91d | 1087 | c->writecombine = _CACHE_UNCACHED; |
113c62d9 SH |
1088 | __cpu_name[cpu] = "MIPS M14Kc"; |
1089 | break; | |
f8fa4811 SH |
1090 | case PRID_IMP_M14KEC: |
1091 | c->cputype = CPU_M14KEC; | |
4f12b91d | 1092 | c->writecombine = _CACHE_UNCACHED; |
f8fa4811 SH |
1093 | __cpu_name[cpu] = "MIPS M14KEc"; |
1094 | break; | |
39b8d525 RB |
1095 | case PRID_IMP_1004K: |
1096 | c->cputype = CPU_1004K; | |
4f12b91d | 1097 | c->writecombine = _CACHE_UNCACHED; |
cea7e2df | 1098 | __cpu_name[cpu] = "MIPS 1004Kc"; |
39b8d525 | 1099 | break; |
006a851b | 1100 | case PRID_IMP_1074K: |
442e14a2 | 1101 | c->cputype = CPU_1074K; |
4f12b91d | 1102 | c->writecombine = _CACHE_UNCACHED; |
006a851b SH |
1103 | __cpu_name[cpu] = "MIPS 1074Kc"; |
1104 | break; | |
b5f065e7 LY |
1105 | case PRID_IMP_INTERAPTIV_UP: |
1106 | c->cputype = CPU_INTERAPTIV; | |
1107 | __cpu_name[cpu] = "MIPS interAptiv"; | |
1108 | break; | |
1109 | case PRID_IMP_INTERAPTIV_MP: | |
1110 | c->cputype = CPU_INTERAPTIV; | |
1111 | __cpu_name[cpu] = "MIPS interAptiv (multi)"; | |
1112 | break; | |
b0d4d300 LY |
1113 | case PRID_IMP_PROAPTIV_UP: |
1114 | c->cputype = CPU_PROAPTIV; | |
1115 | __cpu_name[cpu] = "MIPS proAptiv"; | |
1116 | break; | |
1117 | case PRID_IMP_PROAPTIV_MP: | |
1118 | c->cputype = CPU_PROAPTIV; | |
1119 | __cpu_name[cpu] = "MIPS proAptiv (multi)"; | |
1120 | break; | |
829dcc0a JH |
1121 | case PRID_IMP_P5600: |
1122 | c->cputype = CPU_P5600; | |
1123 | __cpu_name[cpu] = "MIPS P5600"; | |
1124 | break; | |
9943ed92 LY |
1125 | case PRID_IMP_M5150: |
1126 | c->cputype = CPU_M5150; | |
1127 | __cpu_name[cpu] = "MIPS M5150"; | |
1128 | break; | |
1da177e4 | 1129 | } |
0b6d497f | 1130 | |
75b5b5e0 LY |
1131 | decode_configs(c); |
1132 | ||
0b6d497f | 1133 | spram_config(); |
1da177e4 LT |
1134 | } |
1135 | ||
cea7e2df | 1136 | static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu) |
1da177e4 | 1137 | { |
4194318c | 1138 | decode_configs(c); |
8ff374b9 | 1139 | switch (c->processor_id & PRID_IMP_MASK) { |
1da177e4 LT |
1140 | case PRID_IMP_AU1_REV1: |
1141 | case PRID_IMP_AU1_REV2: | |
270717a8 | 1142 | c->cputype = CPU_ALCHEMY; |
1da177e4 LT |
1143 | switch ((c->processor_id >> 24) & 0xff) { |
1144 | case 0: | |
cea7e2df | 1145 | __cpu_name[cpu] = "Au1000"; |
1da177e4 LT |
1146 | break; |
1147 | case 1: | |
cea7e2df | 1148 | __cpu_name[cpu] = "Au1500"; |
1da177e4 LT |
1149 | break; |
1150 | case 2: | |
cea7e2df | 1151 | __cpu_name[cpu] = "Au1100"; |
1da177e4 LT |
1152 | break; |
1153 | case 3: | |
cea7e2df | 1154 | __cpu_name[cpu] = "Au1550"; |
1da177e4 | 1155 | break; |
e3ad1c23 | 1156 | case 4: |
cea7e2df | 1157 | __cpu_name[cpu] = "Au1200"; |
8ff374b9 | 1158 | if ((c->processor_id & PRID_REV_MASK) == 2) |
cea7e2df | 1159 | __cpu_name[cpu] = "Au1250"; |
237cfee1 ML |
1160 | break; |
1161 | case 5: | |
cea7e2df | 1162 | __cpu_name[cpu] = "Au1210"; |
e3ad1c23 | 1163 | break; |
1da177e4 | 1164 | default: |
270717a8 | 1165 | __cpu_name[cpu] = "Au1xxx"; |
1da177e4 LT |
1166 | break; |
1167 | } | |
1da177e4 LT |
1168 | break; |
1169 | } | |
1170 | } | |
1171 | ||
cea7e2df | 1172 | static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu) |
1da177e4 | 1173 | { |
4194318c | 1174 | decode_configs(c); |
02cf2119 | 1175 | |
4f12b91d | 1176 | c->writecombine = _CACHE_UNCACHED_ACCELERATED; |
8ff374b9 | 1177 | switch (c->processor_id & PRID_IMP_MASK) { |
1da177e4 LT |
1178 | case PRID_IMP_SB1: |
1179 | c->cputype = CPU_SB1; | |
cea7e2df | 1180 | __cpu_name[cpu] = "SiByte SB1"; |
1da177e4 | 1181 | /* FPU in pass1 is known to have issues. */ |
8ff374b9 | 1182 | if ((c->processor_id & PRID_REV_MASK) < 0x02) |
010b853b | 1183 | c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR); |
1da177e4 | 1184 | break; |
93ce2f52 AI |
1185 | case PRID_IMP_SB1A: |
1186 | c->cputype = CPU_SB1A; | |
cea7e2df | 1187 | __cpu_name[cpu] = "SiByte SB1A"; |
93ce2f52 | 1188 | break; |
1da177e4 LT |
1189 | } |
1190 | } | |
1191 | ||
cea7e2df | 1192 | static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu) |
1da177e4 | 1193 | { |
4194318c | 1194 | decode_configs(c); |
8ff374b9 | 1195 | switch (c->processor_id & PRID_IMP_MASK) { |
1da177e4 LT |
1196 | case PRID_IMP_SR71000: |
1197 | c->cputype = CPU_SR71000; | |
cea7e2df | 1198 | __cpu_name[cpu] = "Sandcraft SR71000"; |
1da177e4 LT |
1199 | c->scache.ways = 8; |
1200 | c->tlbsize = 64; | |
1201 | break; | |
1202 | } | |
1203 | } | |
1204 | ||
cea7e2df | 1205 | static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu) |
bdf21b18 PP |
1206 | { |
1207 | decode_configs(c); | |
8ff374b9 | 1208 | switch (c->processor_id & PRID_IMP_MASK) { |
bdf21b18 PP |
1209 | case PRID_IMP_PR4450: |
1210 | c->cputype = CPU_PR4450; | |
cea7e2df | 1211 | __cpu_name[cpu] = "Philips PR4450"; |
a96102be | 1212 | set_isa(c, MIPS_CPU_ISA_M32R1); |
bdf21b18 | 1213 | break; |
bdf21b18 PP |
1214 | } |
1215 | } | |
1216 | ||
cea7e2df | 1217 | static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu) |
1c0c13eb AJ |
1218 | { |
1219 | decode_configs(c); | |
8ff374b9 | 1220 | switch (c->processor_id & PRID_IMP_MASK) { |
190fca3e KC |
1221 | case PRID_IMP_BMIPS32_REV4: |
1222 | case PRID_IMP_BMIPS32_REV8: | |
602977b0 KC |
1223 | c->cputype = CPU_BMIPS32; |
1224 | __cpu_name[cpu] = "Broadcom BMIPS32"; | |
06785df0 | 1225 | set_elf_platform(cpu, "bmips32"); |
602977b0 KC |
1226 | break; |
1227 | case PRID_IMP_BMIPS3300: | |
1228 | case PRID_IMP_BMIPS3300_ALT: | |
1229 | case PRID_IMP_BMIPS3300_BUG: | |
1230 | c->cputype = CPU_BMIPS3300; | |
1231 | __cpu_name[cpu] = "Broadcom BMIPS3300"; | |
06785df0 | 1232 | set_elf_platform(cpu, "bmips3300"); |
602977b0 KC |
1233 | break; |
1234 | case PRID_IMP_BMIPS43XX: { | |
8ff374b9 | 1235 | int rev = c->processor_id & PRID_REV_MASK; |
602977b0 KC |
1236 | |
1237 | if (rev >= PRID_REV_BMIPS4380_LO && | |
1238 | rev <= PRID_REV_BMIPS4380_HI) { | |
1239 | c->cputype = CPU_BMIPS4380; | |
1240 | __cpu_name[cpu] = "Broadcom BMIPS4380"; | |
06785df0 | 1241 | set_elf_platform(cpu, "bmips4380"); |
602977b0 KC |
1242 | } else { |
1243 | c->cputype = CPU_BMIPS4350; | |
1244 | __cpu_name[cpu] = "Broadcom BMIPS4350"; | |
06785df0 | 1245 | set_elf_platform(cpu, "bmips4350"); |
602977b0 | 1246 | } |
0de663ef | 1247 | break; |
602977b0 KC |
1248 | } |
1249 | case PRID_IMP_BMIPS5000: | |
68e6a783 | 1250 | case PRID_IMP_BMIPS5200: |
602977b0 KC |
1251 | c->cputype = CPU_BMIPS5000; |
1252 | __cpu_name[cpu] = "Broadcom BMIPS5000"; | |
06785df0 | 1253 | set_elf_platform(cpu, "bmips5000"); |
602977b0 | 1254 | c->options |= MIPS_CPU_ULRI; |
0de663ef | 1255 | break; |
1c0c13eb AJ |
1256 | } |
1257 | } | |
1258 | ||
0dd4781b DD |
1259 | static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu) |
1260 | { | |
1261 | decode_configs(c); | |
8ff374b9 | 1262 | switch (c->processor_id & PRID_IMP_MASK) { |
0dd4781b DD |
1263 | case PRID_IMP_CAVIUM_CN38XX: |
1264 | case PRID_IMP_CAVIUM_CN31XX: | |
1265 | case PRID_IMP_CAVIUM_CN30XX: | |
6f329468 DD |
1266 | c->cputype = CPU_CAVIUM_OCTEON; |
1267 | __cpu_name[cpu] = "Cavium Octeon"; | |
1268 | goto platform; | |
0dd4781b DD |
1269 | case PRID_IMP_CAVIUM_CN58XX: |
1270 | case PRID_IMP_CAVIUM_CN56XX: | |
1271 | case PRID_IMP_CAVIUM_CN50XX: | |
1272 | case PRID_IMP_CAVIUM_CN52XX: | |
6f329468 DD |
1273 | c->cputype = CPU_CAVIUM_OCTEON_PLUS; |
1274 | __cpu_name[cpu] = "Cavium Octeon+"; | |
1275 | platform: | |
c094c99e | 1276 | set_elf_platform(cpu, "octeon"); |
0dd4781b | 1277 | break; |
a1431b61 | 1278 | case PRID_IMP_CAVIUM_CN61XX: |
0e56b385 | 1279 | case PRID_IMP_CAVIUM_CN63XX: |
a1431b61 DD |
1280 | case PRID_IMP_CAVIUM_CN66XX: |
1281 | case PRID_IMP_CAVIUM_CN68XX: | |
af04bb85 | 1282 | case PRID_IMP_CAVIUM_CNF71XX: |
0e56b385 DD |
1283 | c->cputype = CPU_CAVIUM_OCTEON2; |
1284 | __cpu_name[cpu] = "Cavium Octeon II"; | |
c094c99e | 1285 | set_elf_platform(cpu, "octeon2"); |
0e56b385 | 1286 | break; |
af04bb85 DD |
1287 | case PRID_IMP_CAVIUM_CN70XX: |
1288 | case PRID_IMP_CAVIUM_CN78XX: | |
1289 | c->cputype = CPU_CAVIUM_OCTEON3; | |
1290 | __cpu_name[cpu] = "Cavium Octeon III"; | |
1291 | set_elf_platform(cpu, "octeon3"); | |
1292 | break; | |
0dd4781b DD |
1293 | default: |
1294 | printk(KERN_INFO "Unknown Octeon chip!\n"); | |
1295 | c->cputype = CPU_UNKNOWN; | |
1296 | break; | |
1297 | } | |
1298 | } | |
1299 | ||
83ccf69d LPC |
1300 | static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu) |
1301 | { | |
1302 | decode_configs(c); | |
1303 | /* JZRISC does not implement the CP0 counter. */ | |
1304 | c->options &= ~MIPS_CPU_COUNTER; | |
06947aaa | 1305 | BUG_ON(!__builtin_constant_p(cpu_has_counter) || cpu_has_counter); |
8ff374b9 | 1306 | switch (c->processor_id & PRID_IMP_MASK) { |
83ccf69d LPC |
1307 | case PRID_IMP_JZRISC: |
1308 | c->cputype = CPU_JZRISC; | |
4f12b91d | 1309 | c->writecombine = _CACHE_UNCACHED_ACCELERATED; |
83ccf69d LPC |
1310 | __cpu_name[cpu] = "Ingenic JZRISC"; |
1311 | break; | |
1312 | default: | |
1313 | panic("Unknown Ingenic Processor ID!"); | |
1314 | break; | |
1315 | } | |
1316 | } | |
1317 | ||
a7117c6b J |
1318 | static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu) |
1319 | { | |
1320 | decode_configs(c); | |
1321 | ||
8ff374b9 | 1322 | if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_NETLOGIC_AU13XX) { |
809f36c6 ML |
1323 | c->cputype = CPU_ALCHEMY; |
1324 | __cpu_name[cpu] = "Au1300"; | |
1325 | /* following stuff is not for Alchemy */ | |
1326 | return; | |
1327 | } | |
1328 | ||
70342287 RB |
1329 | c->options = (MIPS_CPU_TLB | |
1330 | MIPS_CPU_4KEX | | |
a7117c6b | 1331 | MIPS_CPU_COUNTER | |
70342287 RB |
1332 | MIPS_CPU_DIVEC | |
1333 | MIPS_CPU_WATCH | | |
1334 | MIPS_CPU_EJTAG | | |
a7117c6b J |
1335 | MIPS_CPU_LLSC); |
1336 | ||
8ff374b9 | 1337 | switch (c->processor_id & PRID_IMP_MASK) { |
4ca86a2f | 1338 | case PRID_IMP_NETLOGIC_XLP2XX: |
8907c55e | 1339 | case PRID_IMP_NETLOGIC_XLP9XX: |
1c983986 | 1340 | case PRID_IMP_NETLOGIC_XLP5XX: |
4ca86a2f J |
1341 | c->cputype = CPU_XLP; |
1342 | __cpu_name[cpu] = "Broadcom XLPII"; | |
1343 | break; | |
1344 | ||
2aa54b20 J |
1345 | case PRID_IMP_NETLOGIC_XLP8XX: |
1346 | case PRID_IMP_NETLOGIC_XLP3XX: | |
a3d4fb2d J |
1347 | c->cputype = CPU_XLP; |
1348 | __cpu_name[cpu] = "Netlogic XLP"; | |
1349 | break; | |
1350 | ||
a7117c6b J |
1351 | case PRID_IMP_NETLOGIC_XLR732: |
1352 | case PRID_IMP_NETLOGIC_XLR716: | |
1353 | case PRID_IMP_NETLOGIC_XLR532: | |
1354 | case PRID_IMP_NETLOGIC_XLR308: | |
1355 | case PRID_IMP_NETLOGIC_XLR532C: | |
1356 | case PRID_IMP_NETLOGIC_XLR516C: | |
1357 | case PRID_IMP_NETLOGIC_XLR508C: | |
1358 | case PRID_IMP_NETLOGIC_XLR308C: | |
1359 | c->cputype = CPU_XLR; | |
1360 | __cpu_name[cpu] = "Netlogic XLR"; | |
1361 | break; | |
1362 | ||
1363 | case PRID_IMP_NETLOGIC_XLS608: | |
1364 | case PRID_IMP_NETLOGIC_XLS408: | |
1365 | case PRID_IMP_NETLOGIC_XLS404: | |
1366 | case PRID_IMP_NETLOGIC_XLS208: | |
1367 | case PRID_IMP_NETLOGIC_XLS204: | |
1368 | case PRID_IMP_NETLOGIC_XLS108: | |
1369 | case PRID_IMP_NETLOGIC_XLS104: | |
1370 | case PRID_IMP_NETLOGIC_XLS616B: | |
1371 | case PRID_IMP_NETLOGIC_XLS608B: | |
1372 | case PRID_IMP_NETLOGIC_XLS416B: | |
1373 | case PRID_IMP_NETLOGIC_XLS412B: | |
1374 | case PRID_IMP_NETLOGIC_XLS408B: | |
1375 | case PRID_IMP_NETLOGIC_XLS404B: | |
1376 | c->cputype = CPU_XLR; | |
1377 | __cpu_name[cpu] = "Netlogic XLS"; | |
1378 | break; | |
1379 | ||
1380 | default: | |
a3d4fb2d | 1381 | pr_info("Unknown Netlogic chip id [%02x]!\n", |
a7117c6b J |
1382 | c->processor_id); |
1383 | c->cputype = CPU_XLR; | |
1384 | break; | |
1385 | } | |
1386 | ||
a3d4fb2d | 1387 | if (c->cputype == CPU_XLP) { |
a96102be | 1388 | set_isa(c, MIPS_CPU_ISA_M64R2); |
a3d4fb2d J |
1389 | c->options |= (MIPS_CPU_FPU | MIPS_CPU_ULRI | MIPS_CPU_MCHECK); |
1390 | /* This will be updated again after all threads are woken up */ | |
1391 | c->tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1; | |
1392 | } else { | |
a96102be | 1393 | set_isa(c, MIPS_CPU_ISA_M64R1); |
a3d4fb2d J |
1394 | c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1; |
1395 | } | |
7777b939 | 1396 | c->kscratch_mask = 0xf; |
a7117c6b J |
1397 | } |
1398 | ||
949e51be DD |
1399 | #ifdef CONFIG_64BIT |
1400 | /* For use by uaccess.h */ | |
1401 | u64 __ua_limit; | |
1402 | EXPORT_SYMBOL(__ua_limit); | |
1403 | #endif | |
1404 | ||
9966db25 | 1405 | const char *__cpu_name[NR_CPUS]; |
874fd3b5 | 1406 | const char *__elf_platform; |
9966db25 | 1407 | |
078a55fc | 1408 | void cpu_probe(void) |
1da177e4 LT |
1409 | { |
1410 | struct cpuinfo_mips *c = ¤t_cpu_data; | |
9966db25 | 1411 | unsigned int cpu = smp_processor_id(); |
1da177e4 | 1412 | |
70342287 | 1413 | c->processor_id = PRID_IMP_UNKNOWN; |
1da177e4 LT |
1414 | c->fpu_id = FPIR_IMP_NONE; |
1415 | c->cputype = CPU_UNKNOWN; | |
4f12b91d | 1416 | c->writecombine = _CACHE_UNCACHED; |
1da177e4 | 1417 | |
9b26616c MR |
1418 | c->fpu_csr31 = FPU_CSR_RN; |
1419 | c->fpu_msk31 = FPU_CSR_RSVD | FPU_CSR_ABS2008 | FPU_CSR_NAN2008; | |
1420 | ||
1da177e4 | 1421 | c->processor_id = read_c0_prid(); |
8ff374b9 | 1422 | switch (c->processor_id & PRID_COMP_MASK) { |
1da177e4 | 1423 | case PRID_COMP_LEGACY: |
cea7e2df | 1424 | cpu_probe_legacy(c, cpu); |
1da177e4 LT |
1425 | break; |
1426 | case PRID_COMP_MIPS: | |
cea7e2df | 1427 | cpu_probe_mips(c, cpu); |
1da177e4 LT |
1428 | break; |
1429 | case PRID_COMP_ALCHEMY: | |
cea7e2df | 1430 | cpu_probe_alchemy(c, cpu); |
1da177e4 LT |
1431 | break; |
1432 | case PRID_COMP_SIBYTE: | |
cea7e2df | 1433 | cpu_probe_sibyte(c, cpu); |
1da177e4 | 1434 | break; |
1c0c13eb | 1435 | case PRID_COMP_BROADCOM: |
cea7e2df | 1436 | cpu_probe_broadcom(c, cpu); |
1c0c13eb | 1437 | break; |
1da177e4 | 1438 | case PRID_COMP_SANDCRAFT: |
cea7e2df | 1439 | cpu_probe_sandcraft(c, cpu); |
1da177e4 | 1440 | break; |
a92b0588 | 1441 | case PRID_COMP_NXP: |
cea7e2df | 1442 | cpu_probe_nxp(c, cpu); |
a3dddd56 | 1443 | break; |
0dd4781b DD |
1444 | case PRID_COMP_CAVIUM: |
1445 | cpu_probe_cavium(c, cpu); | |
1446 | break; | |
83ccf69d LPC |
1447 | case PRID_COMP_INGENIC: |
1448 | cpu_probe_ingenic(c, cpu); | |
1449 | break; | |
a7117c6b J |
1450 | case PRID_COMP_NETLOGIC: |
1451 | cpu_probe_netlogic(c, cpu); | |
1452 | break; | |
1da177e4 | 1453 | } |
dec8b1ca | 1454 | |
cea7e2df RB |
1455 | BUG_ON(!__cpu_name[cpu]); |
1456 | BUG_ON(c->cputype == CPU_UNKNOWN); | |
1457 | ||
dec8b1ca FBH |
1458 | /* |
1459 | * Platform code can force the cpu type to optimize code | |
1460 | * generation. In that case be sure the cpu type is correctly | |
1461 | * manually setup otherwise it could trigger some nasty bugs. | |
1462 | */ | |
1463 | BUG_ON(current_cpu_type() != c->cputype); | |
1464 | ||
0103d23f KC |
1465 | if (mips_fpu_disabled) |
1466 | c->options &= ~MIPS_CPU_FPU; | |
1467 | ||
1468 | if (mips_dsp_disabled) | |
ee80f7c7 | 1469 | c->ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P); |
0103d23f | 1470 | |
3d528b32 MC |
1471 | if (mips_htw_disabled) { |
1472 | c->options &= ~MIPS_CPU_HTW; | |
1473 | write_c0_pwctl(read_c0_pwctl() & | |
1474 | ~(1 << MIPS_PWCTL_PWEN_SHIFT)); | |
1475 | } | |
1476 | ||
7aecd5ca MR |
1477 | if (c->options & MIPS_CPU_FPU) |
1478 | cpu_set_fpu_opts(c); | |
1479 | else | |
1480 | cpu_set_nofpu_opts(c); | |
9966db25 | 1481 | |
8b8aa636 | 1482 | if (cpu_has_mips_r2_r6) { |
f6771dbb | 1483 | c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1; |
da4b62cd AC |
1484 | /* R2 has Performance Counter Interrupt indicator */ |
1485 | c->options |= MIPS_CPU_PCI; | |
1486 | } | |
f6771dbb RB |
1487 | else |
1488 | c->srsets = 1; | |
91dfc423 | 1489 | |
a8ad1367 | 1490 | if (cpu_has_msa) { |
a5e9a69e | 1491 | c->msa_id = cpu_get_msa_id(); |
a8ad1367 PB |
1492 | WARN(c->msa_id & MSA_IR_WRPF, |
1493 | "Vector register partitioning unimplemented!"); | |
1494 | } | |
a5e9a69e | 1495 | |
91dfc423 | 1496 | cpu_probe_vmbits(c); |
949e51be DD |
1497 | |
1498 | #ifdef CONFIG_64BIT | |
1499 | if (cpu == 0) | |
1500 | __ua_limit = ~((1ull << cpu_vmbits) - 1); | |
1501 | #endif | |
1da177e4 LT |
1502 | } |
1503 | ||
078a55fc | 1504 | void cpu_report(void) |
1da177e4 LT |
1505 | { |
1506 | struct cpuinfo_mips *c = ¤t_cpu_data; | |
1507 | ||
d9f897c9 LY |
1508 | pr_info("CPU%d revision is: %08x (%s)\n", |
1509 | smp_processor_id(), c->processor_id, cpu_name_string()); | |
1da177e4 | 1510 | if (c->options & MIPS_CPU_FPU) |
9966db25 | 1511 | printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id); |
a5e9a69e PB |
1512 | if (cpu_has_msa) |
1513 | pr_info("MSA revision is: %08x\n", c->msa_id); | |
1da177e4 | 1514 | } |