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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Processor capabilities determination functions. | |
3 | * | |
4 | * Copyright (C) xxxx the Anonymous | |
010b853b | 5 | * Copyright (C) 1994 - 2006 Ralf Baechle |
4194318c | 6 | * Copyright (C) 2003, 2004 Maciej W. Rozycki |
70342287 | 7 | * Copyright (C) 2001, 2004, 2011, 2012 MIPS Technologies, Inc. |
1da177e4 LT |
8 | * |
9 | * This program is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License | |
11 | * as published by the Free Software Foundation; either version | |
12 | * 2 of the License, or (at your option) any later version. | |
13 | */ | |
1da177e4 LT |
14 | #include <linux/init.h> |
15 | #include <linux/kernel.h> | |
16 | #include <linux/ptrace.h> | |
631330f5 | 17 | #include <linux/smp.h> |
1da177e4 | 18 | #include <linux/stddef.h> |
73bc256d | 19 | #include <linux/export.h> |
1da177e4 | 20 | |
5759906c | 21 | #include <asm/bugs.h> |
1da177e4 | 22 | #include <asm/cpu.h> |
f6843626 | 23 | #include <asm/cpu-features.h> |
69f24d17 | 24 | #include <asm/cpu-type.h> |
1da177e4 LT |
25 | #include <asm/fpu.h> |
26 | #include <asm/mipsregs.h> | |
30ee615b | 27 | #include <asm/mipsmtregs.h> |
a5e9a69e | 28 | #include <asm/msa.h> |
654f57bf | 29 | #include <asm/watch.h> |
06372a63 | 30 | #include <asm/elf.h> |
4f12b91d | 31 | #include <asm/pgtable-bits.h> |
a074f0e8 | 32 | #include <asm/spram.h> |
949e51be DD |
33 | #include <asm/uaccess.h> |
34 | ||
7aecd5ca MR |
35 | /* |
36 | * Get the FPU Implementation/Revision. | |
37 | */ | |
38 | static inline unsigned long cpu_get_fpu_id(void) | |
39 | { | |
40 | unsigned long tmp, fpu_id; | |
41 | ||
42 | tmp = read_c0_status(); | |
43 | __enable_fpu(FPU_AS_IS); | |
44 | fpu_id = read_32bit_cp1_register(CP1_REVISION); | |
45 | write_c0_status(tmp); | |
46 | return fpu_id; | |
47 | } | |
48 | ||
49 | /* | |
50 | * Check if the CPU has an external FPU. | |
51 | */ | |
52 | static inline int __cpu_has_fpu(void) | |
53 | { | |
54 | return (cpu_get_fpu_id() & FPIR_IMP_MASK) != FPIR_IMP_NONE; | |
55 | } | |
56 | ||
57 | static inline unsigned long cpu_get_msa_id(void) | |
58 | { | |
59 | unsigned long status, msa_id; | |
60 | ||
61 | status = read_c0_status(); | |
62 | __enable_fpu(FPU_64BIT); | |
63 | enable_msa(); | |
64 | msa_id = read_msa_ir(); | |
65 | disable_msa(); | |
66 | write_c0_status(status); | |
67 | return msa_id; | |
68 | } | |
69 | ||
9b26616c MR |
70 | /* |
71 | * Determine the FCSR mask for FPU hardware. | |
72 | */ | |
73 | static inline void cpu_set_fpu_fcsr_mask(struct cpuinfo_mips *c) | |
74 | { | |
75 | unsigned long sr, mask, fcsr, fcsr0, fcsr1; | |
76 | ||
90b712dd | 77 | fcsr = c->fpu_csr31; |
9b26616c MR |
78 | mask = FPU_CSR_ALL_X | FPU_CSR_ALL_E | FPU_CSR_ALL_S | FPU_CSR_RM; |
79 | ||
80 | sr = read_c0_status(); | |
81 | __enable_fpu(FPU_AS_IS); | |
82 | ||
9b26616c MR |
83 | fcsr0 = fcsr & mask; |
84 | write_32bit_cp1_register(CP1_STATUS, fcsr0); | |
85 | fcsr0 = read_32bit_cp1_register(CP1_STATUS); | |
86 | ||
87 | fcsr1 = fcsr | ~mask; | |
88 | write_32bit_cp1_register(CP1_STATUS, fcsr1); | |
89 | fcsr1 = read_32bit_cp1_register(CP1_STATUS); | |
90 | ||
91 | write_32bit_cp1_register(CP1_STATUS, fcsr); | |
92 | ||
93 | write_c0_status(sr); | |
94 | ||
95 | c->fpu_msk31 = ~(fcsr0 ^ fcsr1) & ~mask; | |
96 | } | |
97 | ||
f6843626 MR |
98 | /* |
99 | * Set the FIR feature flags for the FPU emulator. | |
100 | */ | |
101 | static void cpu_set_nofpu_id(struct cpuinfo_mips *c) | |
102 | { | |
103 | u32 value; | |
104 | ||
105 | value = 0; | |
106 | if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 | | |
107 | MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 | | |
108 | MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) | |
109 | value |= MIPS_FPIR_D | MIPS_FPIR_S; | |
110 | if (c->isa_level & (MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 | | |
111 | MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) | |
112 | value |= MIPS_FPIR_F64 | MIPS_FPIR_L | MIPS_FPIR_W; | |
113 | c->fpu_id = value; | |
114 | } | |
115 | ||
9b26616c MR |
116 | /* Determined FPU emulator mask to use for the boot CPU with "nofpu". */ |
117 | static unsigned int mips_nofpu_msk31; | |
118 | ||
7aecd5ca MR |
119 | /* |
120 | * Set options for FPU hardware. | |
121 | */ | |
122 | static void cpu_set_fpu_opts(struct cpuinfo_mips *c) | |
123 | { | |
124 | c->fpu_id = cpu_get_fpu_id(); | |
125 | mips_nofpu_msk31 = c->fpu_msk31; | |
126 | ||
127 | if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 | | |
128 | MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 | | |
129 | MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) { | |
130 | if (c->fpu_id & MIPS_FPIR_3D) | |
131 | c->ases |= MIPS_ASE_MIPS3D; | |
132 | if (c->fpu_id & MIPS_FPIR_FREP) | |
133 | c->options |= MIPS_CPU_FRE; | |
134 | } | |
135 | ||
136 | cpu_set_fpu_fcsr_mask(c); | |
137 | } | |
138 | ||
139 | /* | |
140 | * Set options for the FPU emulator. | |
141 | */ | |
142 | static void cpu_set_nofpu_opts(struct cpuinfo_mips *c) | |
143 | { | |
144 | c->options &= ~MIPS_CPU_FPU; | |
145 | c->fpu_msk31 = mips_nofpu_msk31; | |
146 | ||
147 | cpu_set_nofpu_id(c); | |
148 | } | |
149 | ||
078a55fc | 150 | static int mips_fpu_disabled; |
0103d23f KC |
151 | |
152 | static int __init fpu_disable(char *s) | |
153 | { | |
7aecd5ca | 154 | cpu_set_nofpu_opts(&boot_cpu_data); |
0103d23f KC |
155 | mips_fpu_disabled = 1; |
156 | ||
157 | return 1; | |
158 | } | |
159 | ||
160 | __setup("nofpu", fpu_disable); | |
161 | ||
078a55fc | 162 | int mips_dsp_disabled; |
0103d23f KC |
163 | |
164 | static int __init dsp_disable(char *s) | |
165 | { | |
ee80f7c7 | 166 | cpu_data[0].ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P); |
0103d23f KC |
167 | mips_dsp_disabled = 1; |
168 | ||
169 | return 1; | |
170 | } | |
171 | ||
172 | __setup("nodsp", dsp_disable); | |
173 | ||
3d528b32 MC |
174 | static int mips_htw_disabled; |
175 | ||
176 | static int __init htw_disable(char *s) | |
177 | { | |
178 | mips_htw_disabled = 1; | |
179 | cpu_data[0].options &= ~MIPS_CPU_HTW; | |
180 | write_c0_pwctl(read_c0_pwctl() & | |
181 | ~(1 << MIPS_PWCTL_PWEN_SHIFT)); | |
182 | ||
183 | return 1; | |
184 | } | |
185 | ||
186 | __setup("nohtw", htw_disable); | |
187 | ||
97f4ad29 MC |
188 | static int mips_ftlb_disabled; |
189 | static int mips_has_ftlb_configured; | |
190 | ||
191 | static void set_ftlb_enable(struct cpuinfo_mips *c, int enable); | |
192 | ||
193 | static int __init ftlb_disable(char *s) | |
194 | { | |
195 | unsigned int config4, mmuextdef; | |
196 | ||
197 | /* | |
198 | * If the core hasn't done any FTLB configuration, there is nothing | |
199 | * for us to do here. | |
200 | */ | |
201 | if (!mips_has_ftlb_configured) | |
202 | return 1; | |
203 | ||
204 | /* Disable it in the boot cpu */ | |
205 | set_ftlb_enable(&cpu_data[0], 0); | |
206 | ||
207 | back_to_back_c0_hazard(); | |
208 | ||
209 | config4 = read_c0_config4(); | |
210 | ||
211 | /* Check that FTLB has been disabled */ | |
212 | mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF; | |
213 | /* MMUSIZEEXT == VTLB ON, FTLB OFF */ | |
214 | if (mmuextdef == MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT) { | |
215 | /* This should never happen */ | |
216 | pr_warn("FTLB could not be disabled!\n"); | |
217 | return 1; | |
218 | } | |
219 | ||
220 | mips_ftlb_disabled = 1; | |
221 | mips_has_ftlb_configured = 0; | |
222 | ||
223 | /* | |
224 | * noftlb is mainly used for debug purposes so print | |
225 | * an informative message instead of using pr_debug() | |
226 | */ | |
227 | pr_info("FTLB has been disabled\n"); | |
228 | ||
229 | /* | |
230 | * Some of these bits are duplicated in the decode_config4. | |
231 | * MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT is the only possible case | |
232 | * once FTLB has been disabled so undo what decode_config4 did. | |
233 | */ | |
234 | cpu_data[0].tlbsize -= cpu_data[0].tlbsizeftlbways * | |
235 | cpu_data[0].tlbsizeftlbsets; | |
236 | cpu_data[0].tlbsizeftlbsets = 0; | |
237 | cpu_data[0].tlbsizeftlbways = 0; | |
238 | ||
239 | return 1; | |
240 | } | |
241 | ||
242 | __setup("noftlb", ftlb_disable); | |
243 | ||
244 | ||
9267a30d MSJ |
245 | static inline void check_errata(void) |
246 | { | |
247 | struct cpuinfo_mips *c = ¤t_cpu_data; | |
248 | ||
69f24d17 | 249 | switch (current_cpu_type()) { |
9267a30d MSJ |
250 | case CPU_34K: |
251 | /* | |
252 | * Erratum "RPS May Cause Incorrect Instruction Execution" | |
b633648c | 253 | * This code only handles VPE0, any SMP/RTOS code |
9267a30d MSJ |
254 | * making use of VPE1 will be responsable for that VPE. |
255 | */ | |
256 | if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2) | |
257 | write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS); | |
258 | break; | |
259 | default: | |
260 | break; | |
261 | } | |
262 | } | |
263 | ||
1da177e4 LT |
264 | void __init check_bugs32(void) |
265 | { | |
9267a30d | 266 | check_errata(); |
1da177e4 LT |
267 | } |
268 | ||
269 | /* | |
270 | * Probe whether cpu has config register by trying to play with | |
271 | * alternate cache bit and see whether it matters. | |
272 | * It's used by cpu_probe to distinguish between R3000A and R3081. | |
273 | */ | |
274 | static inline int cpu_has_confreg(void) | |
275 | { | |
276 | #ifdef CONFIG_CPU_R3000 | |
277 | extern unsigned long r3k_cache_size(unsigned long); | |
278 | unsigned long size1, size2; | |
279 | unsigned long cfg = read_c0_conf(); | |
280 | ||
281 | size1 = r3k_cache_size(ST0_ISC); | |
282 | write_c0_conf(cfg ^ R30XX_CONF_AC); | |
283 | size2 = r3k_cache_size(ST0_ISC); | |
284 | write_c0_conf(cfg); | |
285 | return size1 != size2; | |
286 | #else | |
287 | return 0; | |
288 | #endif | |
289 | } | |
290 | ||
c094c99e RM |
291 | static inline void set_elf_platform(int cpu, const char *plat) |
292 | { | |
293 | if (cpu == 0) | |
294 | __elf_platform = plat; | |
295 | } | |
296 | ||
91dfc423 GR |
297 | static inline void cpu_probe_vmbits(struct cpuinfo_mips *c) |
298 | { | |
299 | #ifdef __NEED_VMBITS_PROBE | |
5b7efa89 | 300 | write_c0_entryhi(0x3fffffffffffe000ULL); |
91dfc423 | 301 | back_to_back_c0_hazard(); |
5b7efa89 | 302 | c->vmbits = fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL); |
91dfc423 GR |
303 | #endif |
304 | } | |
305 | ||
078a55fc | 306 | static void set_isa(struct cpuinfo_mips *c, unsigned int isa) |
a96102be SH |
307 | { |
308 | switch (isa) { | |
309 | case MIPS_CPU_ISA_M64R2: | |
310 | c->isa_level |= MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2; | |
311 | case MIPS_CPU_ISA_M64R1: | |
312 | c->isa_level |= MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1; | |
313 | case MIPS_CPU_ISA_V: | |
314 | c->isa_level |= MIPS_CPU_ISA_V; | |
315 | case MIPS_CPU_ISA_IV: | |
316 | c->isa_level |= MIPS_CPU_ISA_IV; | |
317 | case MIPS_CPU_ISA_III: | |
1990e542 | 318 | c->isa_level |= MIPS_CPU_ISA_II | MIPS_CPU_ISA_III; |
a96102be SH |
319 | break; |
320 | ||
8b8aa636 LY |
321 | /* R6 incompatible with everything else */ |
322 | case MIPS_CPU_ISA_M64R6: | |
323 | c->isa_level |= MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6; | |
324 | case MIPS_CPU_ISA_M32R6: | |
325 | c->isa_level |= MIPS_CPU_ISA_M32R6; | |
326 | /* Break here so we don't add incompatible ISAs */ | |
327 | break; | |
a96102be SH |
328 | case MIPS_CPU_ISA_M32R2: |
329 | c->isa_level |= MIPS_CPU_ISA_M32R2; | |
330 | case MIPS_CPU_ISA_M32R1: | |
331 | c->isa_level |= MIPS_CPU_ISA_M32R1; | |
332 | case MIPS_CPU_ISA_II: | |
333 | c->isa_level |= MIPS_CPU_ISA_II; | |
a96102be SH |
334 | break; |
335 | } | |
336 | } | |
337 | ||
078a55fc | 338 | static char unknown_isa[] = KERN_ERR \ |
2fa36399 KC |
339 | "Unsupported ISA type, c0.config0: %d."; |
340 | ||
cf0a8aa0 MC |
341 | static unsigned int calculate_ftlb_probability(struct cpuinfo_mips *c) |
342 | { | |
343 | ||
344 | unsigned int probability = c->tlbsize / c->tlbsizevtlb; | |
345 | ||
346 | /* | |
347 | * 0 = All TLBWR instructions go to FTLB | |
348 | * 1 = 15:1: For every 16 TBLWR instructions, 15 go to the | |
349 | * FTLB and 1 goes to the VTLB. | |
350 | * 2 = 7:1: As above with 7:1 ratio. | |
351 | * 3 = 3:1: As above with 3:1 ratio. | |
352 | * | |
353 | * Use the linear midpoint as the probability threshold. | |
354 | */ | |
355 | if (probability >= 12) | |
356 | return 1; | |
357 | else if (probability >= 6) | |
358 | return 2; | |
359 | else | |
360 | /* | |
361 | * So FTLB is less than 4 times bigger than VTLB. | |
362 | * A 3:1 ratio can still be useful though. | |
363 | */ | |
364 | return 3; | |
365 | } | |
366 | ||
75b5b5e0 LY |
367 | static void set_ftlb_enable(struct cpuinfo_mips *c, int enable) |
368 | { | |
369 | unsigned int config6; | |
d83b0e82 JH |
370 | |
371 | /* It's implementation dependent how the FTLB can be enabled */ | |
372 | switch (c->cputype) { | |
373 | case CPU_PROAPTIV: | |
374 | case CPU_P5600: | |
375 | /* proAptiv & related cores use Config6 to enable the FTLB */ | |
75b5b5e0 | 376 | config6 = read_c0_config6(); |
cf0a8aa0 MC |
377 | /* Clear the old probability value */ |
378 | config6 &= ~(3 << MIPS_CONF6_FTLBP_SHIFT); | |
75b5b5e0 LY |
379 | if (enable) |
380 | /* Enable FTLB */ | |
cf0a8aa0 MC |
381 | write_c0_config6(config6 | |
382 | (calculate_ftlb_probability(c) | |
383 | << MIPS_CONF6_FTLBP_SHIFT) | |
384 | | MIPS_CONF6_FTLBEN); | |
75b5b5e0 LY |
385 | else |
386 | /* Disable FTLB */ | |
387 | write_c0_config6(config6 & ~MIPS_CONF6_FTLBEN); | |
d83b0e82 | 388 | break; |
75b5b5e0 LY |
389 | } |
390 | } | |
391 | ||
2fa36399 KC |
392 | static inline unsigned int decode_config0(struct cpuinfo_mips *c) |
393 | { | |
394 | unsigned int config0; | |
395 | int isa; | |
396 | ||
397 | config0 = read_c0_config(); | |
398 | ||
75b5b5e0 LY |
399 | /* |
400 | * Look for Standard TLB or Dual VTLB and FTLB | |
401 | */ | |
402 | if ((((config0 & MIPS_CONF_MT) >> 7) == 1) || | |
403 | (((config0 & MIPS_CONF_MT) >> 7) == 4)) | |
2fa36399 | 404 | c->options |= MIPS_CPU_TLB; |
75b5b5e0 | 405 | |
2fa36399 KC |
406 | isa = (config0 & MIPS_CONF_AT) >> 13; |
407 | switch (isa) { | |
408 | case 0: | |
409 | switch ((config0 & MIPS_CONF_AR) >> 10) { | |
410 | case 0: | |
a96102be | 411 | set_isa(c, MIPS_CPU_ISA_M32R1); |
2fa36399 KC |
412 | break; |
413 | case 1: | |
a96102be | 414 | set_isa(c, MIPS_CPU_ISA_M32R2); |
2fa36399 | 415 | break; |
8b8aa636 LY |
416 | case 2: |
417 | set_isa(c, MIPS_CPU_ISA_M32R6); | |
418 | break; | |
2fa36399 KC |
419 | default: |
420 | goto unknown; | |
421 | } | |
422 | break; | |
423 | case 2: | |
424 | switch ((config0 & MIPS_CONF_AR) >> 10) { | |
425 | case 0: | |
a96102be | 426 | set_isa(c, MIPS_CPU_ISA_M64R1); |
2fa36399 KC |
427 | break; |
428 | case 1: | |
a96102be | 429 | set_isa(c, MIPS_CPU_ISA_M64R2); |
2fa36399 | 430 | break; |
8b8aa636 LY |
431 | case 2: |
432 | set_isa(c, MIPS_CPU_ISA_M64R6); | |
433 | break; | |
2fa36399 KC |
434 | default: |
435 | goto unknown; | |
436 | } | |
437 | break; | |
438 | default: | |
439 | goto unknown; | |
440 | } | |
441 | ||
442 | return config0 & MIPS_CONF_M; | |
443 | ||
444 | unknown: | |
445 | panic(unknown_isa, config0); | |
446 | } | |
447 | ||
448 | static inline unsigned int decode_config1(struct cpuinfo_mips *c) | |
449 | { | |
450 | unsigned int config1; | |
451 | ||
452 | config1 = read_c0_config1(); | |
453 | ||
454 | if (config1 & MIPS_CONF1_MD) | |
455 | c->ases |= MIPS_ASE_MDMX; | |
456 | if (config1 & MIPS_CONF1_WR) | |
457 | c->options |= MIPS_CPU_WATCH; | |
458 | if (config1 & MIPS_CONF1_CA) | |
459 | c->ases |= MIPS_ASE_MIPS16; | |
460 | if (config1 & MIPS_CONF1_EP) | |
461 | c->options |= MIPS_CPU_EJTAG; | |
462 | if (config1 & MIPS_CONF1_FP) { | |
463 | c->options |= MIPS_CPU_FPU; | |
464 | c->options |= MIPS_CPU_32FPR; | |
465 | } | |
75b5b5e0 | 466 | if (cpu_has_tlb) { |
2fa36399 | 467 | c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1; |
75b5b5e0 LY |
468 | c->tlbsizevtlb = c->tlbsize; |
469 | c->tlbsizeftlbsets = 0; | |
470 | } | |
2fa36399 KC |
471 | |
472 | return config1 & MIPS_CONF_M; | |
473 | } | |
474 | ||
475 | static inline unsigned int decode_config2(struct cpuinfo_mips *c) | |
476 | { | |
477 | unsigned int config2; | |
478 | ||
479 | config2 = read_c0_config2(); | |
480 | ||
481 | if (config2 & MIPS_CONF2_SL) | |
482 | c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT; | |
483 | ||
484 | return config2 & MIPS_CONF_M; | |
485 | } | |
486 | ||
487 | static inline unsigned int decode_config3(struct cpuinfo_mips *c) | |
488 | { | |
489 | unsigned int config3; | |
490 | ||
491 | config3 = read_c0_config3(); | |
492 | ||
b2ab4f08 | 493 | if (config3 & MIPS_CONF3_SM) { |
2fa36399 | 494 | c->ases |= MIPS_ASE_SMARTMIPS; |
b2ab4f08 SH |
495 | c->options |= MIPS_CPU_RIXI; |
496 | } | |
497 | if (config3 & MIPS_CONF3_RXI) | |
498 | c->options |= MIPS_CPU_RIXI; | |
2fa36399 KC |
499 | if (config3 & MIPS_CONF3_DSP) |
500 | c->ases |= MIPS_ASE_DSP; | |
ee80f7c7 SH |
501 | if (config3 & MIPS_CONF3_DSP2P) |
502 | c->ases |= MIPS_ASE_DSP2P; | |
2fa36399 KC |
503 | if (config3 & MIPS_CONF3_VINT) |
504 | c->options |= MIPS_CPU_VINT; | |
505 | if (config3 & MIPS_CONF3_VEIC) | |
506 | c->options |= MIPS_CPU_VEIC; | |
507 | if (config3 & MIPS_CONF3_MT) | |
508 | c->ases |= MIPS_ASE_MIPSMT; | |
509 | if (config3 & MIPS_CONF3_ULRI) | |
510 | c->options |= MIPS_CPU_ULRI; | |
f8fa4811 SH |
511 | if (config3 & MIPS_CONF3_ISA) |
512 | c->options |= MIPS_CPU_MICROMIPS; | |
1e7decdb DD |
513 | if (config3 & MIPS_CONF3_VZ) |
514 | c->ases |= MIPS_ASE_VZ; | |
4a0156fb SH |
515 | if (config3 & MIPS_CONF3_SC) |
516 | c->options |= MIPS_CPU_SEGMENTS; | |
a5e9a69e PB |
517 | if (config3 & MIPS_CONF3_MSA) |
518 | c->ases |= MIPS_ASE_MSA; | |
3d528b32 | 519 | /* Only tested on 32-bit cores */ |
ed4cbc81 MC |
520 | if ((config3 & MIPS_CONF3_PW) && config_enabled(CONFIG_32BIT)) { |
521 | c->htw_seq = 0; | |
3d528b32 | 522 | c->options |= MIPS_CPU_HTW; |
ed4cbc81 | 523 | } |
9b3274bd JH |
524 | if (config3 & MIPS_CONF3_CDMM) |
525 | c->options |= MIPS_CPU_CDMM; | |
2fa36399 KC |
526 | |
527 | return config3 & MIPS_CONF_M; | |
528 | } | |
529 | ||
530 | static inline unsigned int decode_config4(struct cpuinfo_mips *c) | |
531 | { | |
532 | unsigned int config4; | |
75b5b5e0 LY |
533 | unsigned int newcf4; |
534 | unsigned int mmuextdef; | |
535 | unsigned int ftlb_page = MIPS_CONF4_FTLBPAGESIZE; | |
2fa36399 KC |
536 | |
537 | config4 = read_c0_config4(); | |
538 | ||
1745c1ef LY |
539 | if (cpu_has_tlb) { |
540 | if (((config4 & MIPS_CONF4_IE) >> 29) == 2) | |
541 | c->options |= MIPS_CPU_TLBINV; | |
75b5b5e0 LY |
542 | mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF; |
543 | switch (mmuextdef) { | |
544 | case MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT: | |
545 | c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40; | |
546 | c->tlbsizevtlb = c->tlbsize; | |
547 | break; | |
548 | case MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT: | |
549 | c->tlbsizevtlb += | |
550 | ((config4 & MIPS_CONF4_VTLBSIZEEXT) >> | |
551 | MIPS_CONF4_VTLBSIZEEXT_SHIFT) * 0x40; | |
552 | c->tlbsize = c->tlbsizevtlb; | |
553 | ftlb_page = MIPS_CONF4_VFTLBPAGESIZE; | |
554 | /* fall through */ | |
555 | case MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT: | |
97f4ad29 MC |
556 | if (mips_ftlb_disabled) |
557 | break; | |
75b5b5e0 LY |
558 | newcf4 = (config4 & ~ftlb_page) | |
559 | (page_size_ftlb(mmuextdef) << | |
560 | MIPS_CONF4_FTLBPAGESIZE_SHIFT); | |
561 | write_c0_config4(newcf4); | |
562 | back_to_back_c0_hazard(); | |
563 | config4 = read_c0_config4(); | |
564 | if (config4 != newcf4) { | |
565 | pr_err("PAGE_SIZE 0x%lx is not supported by FTLB (config4=0x%x)\n", | |
566 | PAGE_SIZE, config4); | |
567 | /* Switch FTLB off */ | |
568 | set_ftlb_enable(c, 0); | |
569 | break; | |
570 | } | |
571 | c->tlbsizeftlbsets = 1 << | |
572 | ((config4 & MIPS_CONF4_FTLBSETS) >> | |
573 | MIPS_CONF4_FTLBSETS_SHIFT); | |
574 | c->tlbsizeftlbways = ((config4 & MIPS_CONF4_FTLBWAYS) >> | |
575 | MIPS_CONF4_FTLBWAYS_SHIFT) + 2; | |
576 | c->tlbsize += c->tlbsizeftlbways * c->tlbsizeftlbsets; | |
97f4ad29 | 577 | mips_has_ftlb_configured = 1; |
75b5b5e0 LY |
578 | break; |
579 | } | |
1745c1ef LY |
580 | } |
581 | ||
2fa36399 KC |
582 | c->kscratch_mask = (config4 >> 16) & 0xff; |
583 | ||
584 | return config4 & MIPS_CONF_M; | |
585 | } | |
586 | ||
8b8a7634 RB |
587 | static inline unsigned int decode_config5(struct cpuinfo_mips *c) |
588 | { | |
589 | unsigned int config5; | |
590 | ||
591 | config5 = read_c0_config5(); | |
d175ed2b | 592 | config5 &= ~(MIPS_CONF5_UFR | MIPS_CONF5_UFE); |
8b8a7634 RB |
593 | write_c0_config5(config5); |
594 | ||
49016748 MC |
595 | if (config5 & MIPS_CONF5_EVA) |
596 | c->options |= MIPS_CPU_EVA; | |
1f6c52ff PB |
597 | if (config5 & MIPS_CONF5_MRP) |
598 | c->options |= MIPS_CPU_MAAR; | |
5aed9da1 MC |
599 | if (config5 & MIPS_CONF5_LLB) |
600 | c->options |= MIPS_CPU_RW_LLB; | |
c5b36783 SH |
601 | #ifdef CONFIG_XPA |
602 | if (config5 & MIPS_CONF5_MVH) | |
603 | c->options |= MIPS_CPU_XPA; | |
604 | #endif | |
49016748 | 605 | |
8b8a7634 RB |
606 | return config5 & MIPS_CONF_M; |
607 | } | |
608 | ||
078a55fc | 609 | static void decode_configs(struct cpuinfo_mips *c) |
2fa36399 KC |
610 | { |
611 | int ok; | |
612 | ||
613 | /* MIPS32 or MIPS64 compliant CPU. */ | |
614 | c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER | | |
615 | MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK; | |
616 | ||
617 | c->scache.flags = MIPS_CACHE_NOT_PRESENT; | |
618 | ||
97f4ad29 MC |
619 | /* Enable FTLB if present and not disabled */ |
620 | set_ftlb_enable(c, !mips_ftlb_disabled); | |
75b5b5e0 | 621 | |
2fa36399 | 622 | ok = decode_config0(c); /* Read Config registers. */ |
70342287 | 623 | BUG_ON(!ok); /* Arch spec violation! */ |
2fa36399 KC |
624 | if (ok) |
625 | ok = decode_config1(c); | |
626 | if (ok) | |
627 | ok = decode_config2(c); | |
628 | if (ok) | |
629 | ok = decode_config3(c); | |
630 | if (ok) | |
631 | ok = decode_config4(c); | |
8b8a7634 RB |
632 | if (ok) |
633 | ok = decode_config5(c); | |
2fa36399 KC |
634 | |
635 | mips_probe_watch_registers(c); | |
636 | ||
6575b1d4 LY |
637 | if (cpu_has_rixi) { |
638 | /* Enable the RIXI exceptions */ | |
a5770df0 | 639 | set_c0_pagegrain(PG_IEC); |
6575b1d4 LY |
640 | back_to_back_c0_hazard(); |
641 | /* Verify the IEC bit is set */ | |
642 | if (read_c0_pagegrain() & PG_IEC) | |
643 | c->options |= MIPS_CPU_RIXIEX; | |
644 | } | |
645 | ||
0ee958e1 | 646 | #ifndef CONFIG_MIPS_CPS |
8b8aa636 | 647 | if (cpu_has_mips_r2_r6) { |
45b585c8 | 648 | c->core = get_ebase_cpunum(); |
30ee615b PB |
649 | if (cpu_has_mipsmt) |
650 | c->core >>= fls(core_nvpes()) - 1; | |
651 | } | |
0ee958e1 | 652 | #endif |
2fa36399 KC |
653 | } |
654 | ||
02cf2119 | 655 | #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \ |
1da177e4 LT |
656 | | MIPS_CPU_COUNTER) |
657 | ||
cea7e2df | 658 | static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu) |
1da177e4 | 659 | { |
8ff374b9 | 660 | switch (c->processor_id & PRID_IMP_MASK) { |
1da177e4 LT |
661 | case PRID_IMP_R2000: |
662 | c->cputype = CPU_R2000; | |
cea7e2df | 663 | __cpu_name[cpu] = "R2000"; |
9b26616c | 664 | c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS; |
02cf2119 | 665 | c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE | |
03751e79 | 666 | MIPS_CPU_NOFPUEX; |
1da177e4 LT |
667 | if (__cpu_has_fpu()) |
668 | c->options |= MIPS_CPU_FPU; | |
669 | c->tlbsize = 64; | |
670 | break; | |
671 | case PRID_IMP_R3000: | |
8ff374b9 | 672 | if ((c->processor_id & PRID_REV_MASK) == PRID_REV_R3000A) { |
cea7e2df | 673 | if (cpu_has_confreg()) { |
1da177e4 | 674 | c->cputype = CPU_R3081E; |
cea7e2df RB |
675 | __cpu_name[cpu] = "R3081"; |
676 | } else { | |
1da177e4 | 677 | c->cputype = CPU_R3000A; |
cea7e2df RB |
678 | __cpu_name[cpu] = "R3000A"; |
679 | } | |
cea7e2df | 680 | } else { |
1da177e4 | 681 | c->cputype = CPU_R3000; |
cea7e2df RB |
682 | __cpu_name[cpu] = "R3000"; |
683 | } | |
9b26616c | 684 | c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS; |
02cf2119 | 685 | c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE | |
03751e79 | 686 | MIPS_CPU_NOFPUEX; |
1da177e4 LT |
687 | if (__cpu_has_fpu()) |
688 | c->options |= MIPS_CPU_FPU; | |
689 | c->tlbsize = 64; | |
690 | break; | |
691 | case PRID_IMP_R4000: | |
692 | if (read_c0_config() & CONF_SC) { | |
8ff374b9 MR |
693 | if ((c->processor_id & PRID_REV_MASK) >= |
694 | PRID_REV_R4400) { | |
1da177e4 | 695 | c->cputype = CPU_R4400PC; |
cea7e2df RB |
696 | __cpu_name[cpu] = "R4400PC"; |
697 | } else { | |
1da177e4 | 698 | c->cputype = CPU_R4000PC; |
cea7e2df RB |
699 | __cpu_name[cpu] = "R4000PC"; |
700 | } | |
1da177e4 | 701 | } else { |
7f177a52 MR |
702 | int cca = read_c0_config() & CONF_CM_CMASK; |
703 | int mc; | |
704 | ||
705 | /* | |
706 | * SC and MC versions can't be reliably told apart, | |
707 | * but only the latter support coherent caching | |
708 | * modes so assume the firmware has set the KSEG0 | |
709 | * coherency attribute reasonably (if uncached, we | |
710 | * assume SC). | |
711 | */ | |
712 | switch (cca) { | |
713 | case CONF_CM_CACHABLE_CE: | |
714 | case CONF_CM_CACHABLE_COW: | |
715 | case CONF_CM_CACHABLE_CUW: | |
716 | mc = 1; | |
717 | break; | |
718 | default: | |
719 | mc = 0; | |
720 | break; | |
721 | } | |
8ff374b9 MR |
722 | if ((c->processor_id & PRID_REV_MASK) >= |
723 | PRID_REV_R4400) { | |
7f177a52 MR |
724 | c->cputype = mc ? CPU_R4400MC : CPU_R4400SC; |
725 | __cpu_name[cpu] = mc ? "R4400MC" : "R4400SC"; | |
cea7e2df | 726 | } else { |
7f177a52 MR |
727 | c->cputype = mc ? CPU_R4000MC : CPU_R4000SC; |
728 | __cpu_name[cpu] = mc ? "R4000MC" : "R4000SC"; | |
cea7e2df | 729 | } |
1da177e4 LT |
730 | } |
731 | ||
a96102be | 732 | set_isa(c, MIPS_CPU_ISA_III); |
9b26616c | 733 | c->fpu_msk31 |= FPU_CSR_CONDX; |
1da177e4 | 734 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | |
03751e79 SH |
735 | MIPS_CPU_WATCH | MIPS_CPU_VCE | |
736 | MIPS_CPU_LLSC; | |
1da177e4 LT |
737 | c->tlbsize = 48; |
738 | break; | |
739 | case PRID_IMP_VR41XX: | |
9f91e506 | 740 | set_isa(c, MIPS_CPU_ISA_III); |
9b26616c | 741 | c->fpu_msk31 |= FPU_CSR_CONDX; |
9f91e506 YY |
742 | c->options = R4K_OPTS; |
743 | c->tlbsize = 32; | |
1da177e4 | 744 | switch (c->processor_id & 0xf0) { |
1da177e4 LT |
745 | case PRID_REV_VR4111: |
746 | c->cputype = CPU_VR4111; | |
cea7e2df | 747 | __cpu_name[cpu] = "NEC VR4111"; |
1da177e4 | 748 | break; |
1da177e4 LT |
749 | case PRID_REV_VR4121: |
750 | c->cputype = CPU_VR4121; | |
cea7e2df | 751 | __cpu_name[cpu] = "NEC VR4121"; |
1da177e4 LT |
752 | break; |
753 | case PRID_REV_VR4122: | |
cea7e2df | 754 | if ((c->processor_id & 0xf) < 0x3) { |
1da177e4 | 755 | c->cputype = CPU_VR4122; |
cea7e2df RB |
756 | __cpu_name[cpu] = "NEC VR4122"; |
757 | } else { | |
1da177e4 | 758 | c->cputype = CPU_VR4181A; |
cea7e2df RB |
759 | __cpu_name[cpu] = "NEC VR4181A"; |
760 | } | |
1da177e4 LT |
761 | break; |
762 | case PRID_REV_VR4130: | |
cea7e2df | 763 | if ((c->processor_id & 0xf) < 0x4) { |
1da177e4 | 764 | c->cputype = CPU_VR4131; |
cea7e2df RB |
765 | __cpu_name[cpu] = "NEC VR4131"; |
766 | } else { | |
1da177e4 | 767 | c->cputype = CPU_VR4133; |
9f91e506 | 768 | c->options |= MIPS_CPU_LLSC; |
cea7e2df RB |
769 | __cpu_name[cpu] = "NEC VR4133"; |
770 | } | |
1da177e4 LT |
771 | break; |
772 | default: | |
773 | printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n"); | |
774 | c->cputype = CPU_VR41XX; | |
cea7e2df | 775 | __cpu_name[cpu] = "NEC Vr41xx"; |
1da177e4 LT |
776 | break; |
777 | } | |
1da177e4 LT |
778 | break; |
779 | case PRID_IMP_R4300: | |
780 | c->cputype = CPU_R4300; | |
cea7e2df | 781 | __cpu_name[cpu] = "R4300"; |
a96102be | 782 | set_isa(c, MIPS_CPU_ISA_III); |
9b26616c | 783 | c->fpu_msk31 |= FPU_CSR_CONDX; |
1da177e4 | 784 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | |
03751e79 | 785 | MIPS_CPU_LLSC; |
1da177e4 LT |
786 | c->tlbsize = 32; |
787 | break; | |
788 | case PRID_IMP_R4600: | |
789 | c->cputype = CPU_R4600; | |
cea7e2df | 790 | __cpu_name[cpu] = "R4600"; |
a96102be | 791 | set_isa(c, MIPS_CPU_ISA_III); |
9b26616c | 792 | c->fpu_msk31 |= FPU_CSR_CONDX; |
075e7502 TS |
793 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | |
794 | MIPS_CPU_LLSC; | |
1da177e4 LT |
795 | c->tlbsize = 48; |
796 | break; | |
797 | #if 0 | |
03751e79 | 798 | case PRID_IMP_R4650: |
1da177e4 LT |
799 | /* |
800 | * This processor doesn't have an MMU, so it's not | |
801 | * "real easy" to run Linux on it. It is left purely | |
802 | * for documentation. Commented out because it shares | |
803 | * it's c0_prid id number with the TX3900. | |
804 | */ | |
a3dddd56 | 805 | c->cputype = CPU_R4650; |
cea7e2df | 806 | __cpu_name[cpu] = "R4650"; |
a96102be | 807 | set_isa(c, MIPS_CPU_ISA_III); |
9b26616c | 808 | c->fpu_msk31 |= FPU_CSR_CONDX; |
1da177e4 | 809 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC; |
03751e79 | 810 | c->tlbsize = 48; |
1da177e4 LT |
811 | break; |
812 | #endif | |
813 | case PRID_IMP_TX39: | |
9b26616c | 814 | c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS; |
02cf2119 | 815 | c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE; |
1da177e4 LT |
816 | |
817 | if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) { | |
818 | c->cputype = CPU_TX3927; | |
cea7e2df | 819 | __cpu_name[cpu] = "TX3927"; |
1da177e4 LT |
820 | c->tlbsize = 64; |
821 | } else { | |
8ff374b9 | 822 | switch (c->processor_id & PRID_REV_MASK) { |
1da177e4 LT |
823 | case PRID_REV_TX3912: |
824 | c->cputype = CPU_TX3912; | |
cea7e2df | 825 | __cpu_name[cpu] = "TX3912"; |
1da177e4 LT |
826 | c->tlbsize = 32; |
827 | break; | |
828 | case PRID_REV_TX3922: | |
829 | c->cputype = CPU_TX3922; | |
cea7e2df | 830 | __cpu_name[cpu] = "TX3922"; |
1da177e4 LT |
831 | c->tlbsize = 64; |
832 | break; | |
1da177e4 LT |
833 | } |
834 | } | |
835 | break; | |
836 | case PRID_IMP_R4700: | |
837 | c->cputype = CPU_R4700; | |
cea7e2df | 838 | __cpu_name[cpu] = "R4700"; |
a96102be | 839 | set_isa(c, MIPS_CPU_ISA_III); |
9b26616c | 840 | c->fpu_msk31 |= FPU_CSR_CONDX; |
1da177e4 | 841 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | |
03751e79 | 842 | MIPS_CPU_LLSC; |
1da177e4 LT |
843 | c->tlbsize = 48; |
844 | break; | |
845 | case PRID_IMP_TX49: | |
846 | c->cputype = CPU_TX49XX; | |
cea7e2df | 847 | __cpu_name[cpu] = "R49XX"; |
a96102be | 848 | set_isa(c, MIPS_CPU_ISA_III); |
9b26616c | 849 | c->fpu_msk31 |= FPU_CSR_CONDX; |
1da177e4 LT |
850 | c->options = R4K_OPTS | MIPS_CPU_LLSC; |
851 | if (!(c->processor_id & 0x08)) | |
852 | c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR; | |
853 | c->tlbsize = 48; | |
854 | break; | |
855 | case PRID_IMP_R5000: | |
856 | c->cputype = CPU_R5000; | |
cea7e2df | 857 | __cpu_name[cpu] = "R5000"; |
a96102be | 858 | set_isa(c, MIPS_CPU_ISA_IV); |
1da177e4 | 859 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | |
03751e79 | 860 | MIPS_CPU_LLSC; |
1da177e4 LT |
861 | c->tlbsize = 48; |
862 | break; | |
863 | case PRID_IMP_R5432: | |
864 | c->cputype = CPU_R5432; | |
cea7e2df | 865 | __cpu_name[cpu] = "R5432"; |
a96102be | 866 | set_isa(c, MIPS_CPU_ISA_IV); |
1da177e4 | 867 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | |
03751e79 | 868 | MIPS_CPU_WATCH | MIPS_CPU_LLSC; |
1da177e4 LT |
869 | c->tlbsize = 48; |
870 | break; | |
871 | case PRID_IMP_R5500: | |
872 | c->cputype = CPU_R5500; | |
cea7e2df | 873 | __cpu_name[cpu] = "R5500"; |
a96102be | 874 | set_isa(c, MIPS_CPU_ISA_IV); |
1da177e4 | 875 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | |
03751e79 | 876 | MIPS_CPU_WATCH | MIPS_CPU_LLSC; |
1da177e4 LT |
877 | c->tlbsize = 48; |
878 | break; | |
879 | case PRID_IMP_NEVADA: | |
880 | c->cputype = CPU_NEVADA; | |
cea7e2df | 881 | __cpu_name[cpu] = "Nevada"; |
a96102be | 882 | set_isa(c, MIPS_CPU_ISA_IV); |
1da177e4 | 883 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | |
03751e79 | 884 | MIPS_CPU_DIVEC | MIPS_CPU_LLSC; |
1da177e4 LT |
885 | c->tlbsize = 48; |
886 | break; | |
887 | case PRID_IMP_R6000: | |
888 | c->cputype = CPU_R6000; | |
cea7e2df | 889 | __cpu_name[cpu] = "R6000"; |
a96102be | 890 | set_isa(c, MIPS_CPU_ISA_II); |
9b26616c | 891 | c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS; |
1da177e4 | 892 | c->options = MIPS_CPU_TLB | MIPS_CPU_FPU | |
03751e79 | 893 | MIPS_CPU_LLSC; |
1da177e4 LT |
894 | c->tlbsize = 32; |
895 | break; | |
896 | case PRID_IMP_R6000A: | |
897 | c->cputype = CPU_R6000A; | |
cea7e2df | 898 | __cpu_name[cpu] = "R6000A"; |
a96102be | 899 | set_isa(c, MIPS_CPU_ISA_II); |
9b26616c | 900 | c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS; |
1da177e4 | 901 | c->options = MIPS_CPU_TLB | MIPS_CPU_FPU | |
03751e79 | 902 | MIPS_CPU_LLSC; |
1da177e4 LT |
903 | c->tlbsize = 32; |
904 | break; | |
905 | case PRID_IMP_RM7000: | |
906 | c->cputype = CPU_RM7000; | |
cea7e2df | 907 | __cpu_name[cpu] = "RM7000"; |
a96102be | 908 | set_isa(c, MIPS_CPU_ISA_IV); |
1da177e4 | 909 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | |
03751e79 | 910 | MIPS_CPU_LLSC; |
1da177e4 | 911 | /* |
70342287 | 912 | * Undocumented RM7000: Bit 29 in the info register of |
1da177e4 LT |
913 | * the RM7000 v2.0 indicates if the TLB has 48 or 64 |
914 | * entries. | |
915 | * | |
70342287 RB |
916 | * 29 1 => 64 entry JTLB |
917 | * 0 => 48 entry JTLB | |
1da177e4 LT |
918 | */ |
919 | c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48; | |
1da177e4 LT |
920 | break; |
921 | case PRID_IMP_R8000: | |
922 | c->cputype = CPU_R8000; | |
cea7e2df | 923 | __cpu_name[cpu] = "RM8000"; |
a96102be | 924 | set_isa(c, MIPS_CPU_ISA_IV); |
1da177e4 | 925 | c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX | |
03751e79 SH |
926 | MIPS_CPU_FPU | MIPS_CPU_32FPR | |
927 | MIPS_CPU_LLSC; | |
1da177e4 LT |
928 | c->tlbsize = 384; /* has weird TLB: 3-way x 128 */ |
929 | break; | |
930 | case PRID_IMP_R10000: | |
931 | c->cputype = CPU_R10000; | |
cea7e2df | 932 | __cpu_name[cpu] = "R10000"; |
a96102be | 933 | set_isa(c, MIPS_CPU_ISA_IV); |
8b36612a | 934 | c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | |
03751e79 | 935 | MIPS_CPU_FPU | MIPS_CPU_32FPR | |
1da177e4 | 936 | MIPS_CPU_COUNTER | MIPS_CPU_WATCH | |
03751e79 | 937 | MIPS_CPU_LLSC; |
1da177e4 LT |
938 | c->tlbsize = 64; |
939 | break; | |
940 | case PRID_IMP_R12000: | |
941 | c->cputype = CPU_R12000; | |
cea7e2df | 942 | __cpu_name[cpu] = "R12000"; |
a96102be | 943 | set_isa(c, MIPS_CPU_ISA_IV); |
8b36612a | 944 | c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | |
03751e79 | 945 | MIPS_CPU_FPU | MIPS_CPU_32FPR | |
1da177e4 | 946 | MIPS_CPU_COUNTER | MIPS_CPU_WATCH | |
8d5ded16 | 947 | MIPS_CPU_LLSC | MIPS_CPU_BP_GHIST; |
1da177e4 LT |
948 | c->tlbsize = 64; |
949 | break; | |
44d921b2 | 950 | case PRID_IMP_R14000: |
30577391 JK |
951 | if (((c->processor_id >> 4) & 0x0f) > 2) { |
952 | c->cputype = CPU_R16000; | |
953 | __cpu_name[cpu] = "R16000"; | |
954 | } else { | |
955 | c->cputype = CPU_R14000; | |
956 | __cpu_name[cpu] = "R14000"; | |
957 | } | |
a96102be | 958 | set_isa(c, MIPS_CPU_ISA_IV); |
44d921b2 | 959 | c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | |
03751e79 | 960 | MIPS_CPU_FPU | MIPS_CPU_32FPR | |
44d921b2 | 961 | MIPS_CPU_COUNTER | MIPS_CPU_WATCH | |
8d5ded16 | 962 | MIPS_CPU_LLSC | MIPS_CPU_BP_GHIST; |
44d921b2 K |
963 | c->tlbsize = 64; |
964 | break; | |
26859198 | 965 | case PRID_IMP_LOONGSON_64: /* Loongson-2/3 */ |
5aac1e8a RM |
966 | switch (c->processor_id & PRID_REV_MASK) { |
967 | case PRID_REV_LOONGSON2E: | |
c579d310 HC |
968 | c->cputype = CPU_LOONGSON2; |
969 | __cpu_name[cpu] = "ICT Loongson-2"; | |
5aac1e8a | 970 | set_elf_platform(cpu, "loongson2e"); |
7352c8b1 | 971 | set_isa(c, MIPS_CPU_ISA_III); |
9b26616c | 972 | c->fpu_msk31 |= FPU_CSR_CONDX; |
5aac1e8a RM |
973 | break; |
974 | case PRID_REV_LOONGSON2F: | |
c579d310 HC |
975 | c->cputype = CPU_LOONGSON2; |
976 | __cpu_name[cpu] = "ICT Loongson-2"; | |
5aac1e8a | 977 | set_elf_platform(cpu, "loongson2f"); |
7352c8b1 | 978 | set_isa(c, MIPS_CPU_ISA_III); |
9b26616c | 979 | c->fpu_msk31 |= FPU_CSR_CONDX; |
5aac1e8a | 980 | break; |
c579d310 HC |
981 | case PRID_REV_LOONGSON3A: |
982 | c->cputype = CPU_LOONGSON3; | |
983 | __cpu_name[cpu] = "ICT Loongson-3"; | |
984 | set_elf_platform(cpu, "loongson3a"); | |
7352c8b1 | 985 | set_isa(c, MIPS_CPU_ISA_M64R1); |
c579d310 | 986 | break; |
e7841be5 HC |
987 | case PRID_REV_LOONGSON3B_R1: |
988 | case PRID_REV_LOONGSON3B_R2: | |
989 | c->cputype = CPU_LOONGSON3; | |
990 | __cpu_name[cpu] = "ICT Loongson-3"; | |
991 | set_elf_platform(cpu, "loongson3b"); | |
7352c8b1 | 992 | set_isa(c, MIPS_CPU_ISA_M64R1); |
e7841be5 | 993 | break; |
5aac1e8a RM |
994 | } |
995 | ||
2a21c730 FZ |
996 | c->options = R4K_OPTS | |
997 | MIPS_CPU_FPU | MIPS_CPU_LLSC | | |
998 | MIPS_CPU_32FPR; | |
999 | c->tlbsize = 64; | |
cc94ea31 | 1000 | c->writecombine = _CACHE_UNCACHED_ACCELERATED; |
2a21c730 | 1001 | break; |
26859198 | 1002 | case PRID_IMP_LOONGSON_32: /* Loongson-1 */ |
2fa36399 | 1003 | decode_configs(c); |
b4672d37 | 1004 | |
2fa36399 | 1005 | c->cputype = CPU_LOONGSON1; |
1da177e4 | 1006 | |
2fa36399 KC |
1007 | switch (c->processor_id & PRID_REV_MASK) { |
1008 | case PRID_REV_LOONGSON1B: | |
1009 | __cpu_name[cpu] = "Loongson 1B"; | |
b4672d37 | 1010 | break; |
b4672d37 | 1011 | } |
4194318c | 1012 | |
2fa36399 | 1013 | break; |
1da177e4 | 1014 | } |
1da177e4 LT |
1015 | } |
1016 | ||
cea7e2df | 1017 | static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu) |
1da177e4 | 1018 | { |
4f12b91d | 1019 | c->writecombine = _CACHE_UNCACHED_ACCELERATED; |
8ff374b9 | 1020 | switch (c->processor_id & PRID_IMP_MASK) { |
b2498af5 LY |
1021 | case PRID_IMP_QEMU_GENERIC: |
1022 | c->writecombine = _CACHE_UNCACHED; | |
1023 | c->cputype = CPU_QEMU_GENERIC; | |
1024 | __cpu_name[cpu] = "MIPS GENERIC QEMU"; | |
1025 | break; | |
1da177e4 LT |
1026 | case PRID_IMP_4KC: |
1027 | c->cputype = CPU_4KC; | |
4f12b91d | 1028 | c->writecombine = _CACHE_UNCACHED; |
cea7e2df | 1029 | __cpu_name[cpu] = "MIPS 4Kc"; |
1da177e4 LT |
1030 | break; |
1031 | case PRID_IMP_4KEC: | |
2b07bd02 RB |
1032 | case PRID_IMP_4KECR2: |
1033 | c->cputype = CPU_4KEC; | |
4f12b91d | 1034 | c->writecombine = _CACHE_UNCACHED; |
cea7e2df | 1035 | __cpu_name[cpu] = "MIPS 4KEc"; |
2b07bd02 | 1036 | break; |
1da177e4 | 1037 | case PRID_IMP_4KSC: |
8afcb5d8 | 1038 | case PRID_IMP_4KSD: |
1da177e4 | 1039 | c->cputype = CPU_4KSC; |
4f12b91d | 1040 | c->writecombine = _CACHE_UNCACHED; |
cea7e2df | 1041 | __cpu_name[cpu] = "MIPS 4KSc"; |
1da177e4 LT |
1042 | break; |
1043 | case PRID_IMP_5KC: | |
1044 | c->cputype = CPU_5KC; | |
4f12b91d | 1045 | c->writecombine = _CACHE_UNCACHED; |
cea7e2df | 1046 | __cpu_name[cpu] = "MIPS 5Kc"; |
1da177e4 | 1047 | break; |
78d4803f LY |
1048 | case PRID_IMP_5KE: |
1049 | c->cputype = CPU_5KE; | |
4f12b91d | 1050 | c->writecombine = _CACHE_UNCACHED; |
78d4803f LY |
1051 | __cpu_name[cpu] = "MIPS 5KE"; |
1052 | break; | |
1da177e4 LT |
1053 | case PRID_IMP_20KC: |
1054 | c->cputype = CPU_20KC; | |
4f12b91d | 1055 | c->writecombine = _CACHE_UNCACHED; |
cea7e2df | 1056 | __cpu_name[cpu] = "MIPS 20Kc"; |
1da177e4 LT |
1057 | break; |
1058 | case PRID_IMP_24K: | |
1059 | c->cputype = CPU_24K; | |
4f12b91d | 1060 | c->writecombine = _CACHE_UNCACHED; |
cea7e2df | 1061 | __cpu_name[cpu] = "MIPS 24Kc"; |
1da177e4 | 1062 | break; |
42f3caef JC |
1063 | case PRID_IMP_24KE: |
1064 | c->cputype = CPU_24K; | |
4f12b91d | 1065 | c->writecombine = _CACHE_UNCACHED; |
42f3caef JC |
1066 | __cpu_name[cpu] = "MIPS 24KEc"; |
1067 | break; | |
1da177e4 LT |
1068 | case PRID_IMP_25KF: |
1069 | c->cputype = CPU_25KF; | |
4f12b91d | 1070 | c->writecombine = _CACHE_UNCACHED; |
cea7e2df | 1071 | __cpu_name[cpu] = "MIPS 25Kc"; |
1da177e4 | 1072 | break; |
bbc7f22f RB |
1073 | case PRID_IMP_34K: |
1074 | c->cputype = CPU_34K; | |
4f12b91d | 1075 | c->writecombine = _CACHE_UNCACHED; |
cea7e2df | 1076 | __cpu_name[cpu] = "MIPS 34Kc"; |
bbc7f22f | 1077 | break; |
c620953c CD |
1078 | case PRID_IMP_74K: |
1079 | c->cputype = CPU_74K; | |
4f12b91d | 1080 | c->writecombine = _CACHE_UNCACHED; |
cea7e2df | 1081 | __cpu_name[cpu] = "MIPS 74Kc"; |
c620953c | 1082 | break; |
113c62d9 SH |
1083 | case PRID_IMP_M14KC: |
1084 | c->cputype = CPU_M14KC; | |
4f12b91d | 1085 | c->writecombine = _CACHE_UNCACHED; |
113c62d9 SH |
1086 | __cpu_name[cpu] = "MIPS M14Kc"; |
1087 | break; | |
f8fa4811 SH |
1088 | case PRID_IMP_M14KEC: |
1089 | c->cputype = CPU_M14KEC; | |
4f12b91d | 1090 | c->writecombine = _CACHE_UNCACHED; |
f8fa4811 SH |
1091 | __cpu_name[cpu] = "MIPS M14KEc"; |
1092 | break; | |
39b8d525 RB |
1093 | case PRID_IMP_1004K: |
1094 | c->cputype = CPU_1004K; | |
4f12b91d | 1095 | c->writecombine = _CACHE_UNCACHED; |
cea7e2df | 1096 | __cpu_name[cpu] = "MIPS 1004Kc"; |
39b8d525 | 1097 | break; |
006a851b | 1098 | case PRID_IMP_1074K: |
442e14a2 | 1099 | c->cputype = CPU_1074K; |
4f12b91d | 1100 | c->writecombine = _CACHE_UNCACHED; |
006a851b SH |
1101 | __cpu_name[cpu] = "MIPS 1074Kc"; |
1102 | break; | |
b5f065e7 LY |
1103 | case PRID_IMP_INTERAPTIV_UP: |
1104 | c->cputype = CPU_INTERAPTIV; | |
1105 | __cpu_name[cpu] = "MIPS interAptiv"; | |
1106 | break; | |
1107 | case PRID_IMP_INTERAPTIV_MP: | |
1108 | c->cputype = CPU_INTERAPTIV; | |
1109 | __cpu_name[cpu] = "MIPS interAptiv (multi)"; | |
1110 | break; | |
b0d4d300 LY |
1111 | case PRID_IMP_PROAPTIV_UP: |
1112 | c->cputype = CPU_PROAPTIV; | |
1113 | __cpu_name[cpu] = "MIPS proAptiv"; | |
1114 | break; | |
1115 | case PRID_IMP_PROAPTIV_MP: | |
1116 | c->cputype = CPU_PROAPTIV; | |
1117 | __cpu_name[cpu] = "MIPS proAptiv (multi)"; | |
1118 | break; | |
829dcc0a JH |
1119 | case PRID_IMP_P5600: |
1120 | c->cputype = CPU_P5600; | |
1121 | __cpu_name[cpu] = "MIPS P5600"; | |
1122 | break; | |
e57f9a2d MC |
1123 | case PRID_IMP_I6400: |
1124 | c->cputype = CPU_I6400; | |
1125 | __cpu_name[cpu] = "MIPS I6400"; | |
1126 | break; | |
9943ed92 LY |
1127 | case PRID_IMP_M5150: |
1128 | c->cputype = CPU_M5150; | |
1129 | __cpu_name[cpu] = "MIPS M5150"; | |
1130 | break; | |
1da177e4 | 1131 | } |
0b6d497f | 1132 | |
75b5b5e0 LY |
1133 | decode_configs(c); |
1134 | ||
0b6d497f | 1135 | spram_config(); |
1da177e4 LT |
1136 | } |
1137 | ||
cea7e2df | 1138 | static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu) |
1da177e4 | 1139 | { |
4194318c | 1140 | decode_configs(c); |
8ff374b9 | 1141 | switch (c->processor_id & PRID_IMP_MASK) { |
1da177e4 LT |
1142 | case PRID_IMP_AU1_REV1: |
1143 | case PRID_IMP_AU1_REV2: | |
270717a8 | 1144 | c->cputype = CPU_ALCHEMY; |
1da177e4 LT |
1145 | switch ((c->processor_id >> 24) & 0xff) { |
1146 | case 0: | |
cea7e2df | 1147 | __cpu_name[cpu] = "Au1000"; |
1da177e4 LT |
1148 | break; |
1149 | case 1: | |
cea7e2df | 1150 | __cpu_name[cpu] = "Au1500"; |
1da177e4 LT |
1151 | break; |
1152 | case 2: | |
cea7e2df | 1153 | __cpu_name[cpu] = "Au1100"; |
1da177e4 LT |
1154 | break; |
1155 | case 3: | |
cea7e2df | 1156 | __cpu_name[cpu] = "Au1550"; |
1da177e4 | 1157 | break; |
e3ad1c23 | 1158 | case 4: |
cea7e2df | 1159 | __cpu_name[cpu] = "Au1200"; |
8ff374b9 | 1160 | if ((c->processor_id & PRID_REV_MASK) == 2) |
cea7e2df | 1161 | __cpu_name[cpu] = "Au1250"; |
237cfee1 ML |
1162 | break; |
1163 | case 5: | |
cea7e2df | 1164 | __cpu_name[cpu] = "Au1210"; |
e3ad1c23 | 1165 | break; |
1da177e4 | 1166 | default: |
270717a8 | 1167 | __cpu_name[cpu] = "Au1xxx"; |
1da177e4 LT |
1168 | break; |
1169 | } | |
1da177e4 LT |
1170 | break; |
1171 | } | |
1172 | } | |
1173 | ||
cea7e2df | 1174 | static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu) |
1da177e4 | 1175 | { |
4194318c | 1176 | decode_configs(c); |
02cf2119 | 1177 | |
4f12b91d | 1178 | c->writecombine = _CACHE_UNCACHED_ACCELERATED; |
8ff374b9 | 1179 | switch (c->processor_id & PRID_IMP_MASK) { |
1da177e4 LT |
1180 | case PRID_IMP_SB1: |
1181 | c->cputype = CPU_SB1; | |
cea7e2df | 1182 | __cpu_name[cpu] = "SiByte SB1"; |
1da177e4 | 1183 | /* FPU in pass1 is known to have issues. */ |
8ff374b9 | 1184 | if ((c->processor_id & PRID_REV_MASK) < 0x02) |
010b853b | 1185 | c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR); |
1da177e4 | 1186 | break; |
93ce2f52 AI |
1187 | case PRID_IMP_SB1A: |
1188 | c->cputype = CPU_SB1A; | |
cea7e2df | 1189 | __cpu_name[cpu] = "SiByte SB1A"; |
93ce2f52 | 1190 | break; |
1da177e4 LT |
1191 | } |
1192 | } | |
1193 | ||
cea7e2df | 1194 | static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu) |
1da177e4 | 1195 | { |
4194318c | 1196 | decode_configs(c); |
8ff374b9 | 1197 | switch (c->processor_id & PRID_IMP_MASK) { |
1da177e4 LT |
1198 | case PRID_IMP_SR71000: |
1199 | c->cputype = CPU_SR71000; | |
cea7e2df | 1200 | __cpu_name[cpu] = "Sandcraft SR71000"; |
1da177e4 LT |
1201 | c->scache.ways = 8; |
1202 | c->tlbsize = 64; | |
1203 | break; | |
1204 | } | |
1205 | } | |
1206 | ||
cea7e2df | 1207 | static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu) |
bdf21b18 PP |
1208 | { |
1209 | decode_configs(c); | |
8ff374b9 | 1210 | switch (c->processor_id & PRID_IMP_MASK) { |
bdf21b18 PP |
1211 | case PRID_IMP_PR4450: |
1212 | c->cputype = CPU_PR4450; | |
cea7e2df | 1213 | __cpu_name[cpu] = "Philips PR4450"; |
a96102be | 1214 | set_isa(c, MIPS_CPU_ISA_M32R1); |
bdf21b18 | 1215 | break; |
bdf21b18 PP |
1216 | } |
1217 | } | |
1218 | ||
cea7e2df | 1219 | static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu) |
1c0c13eb AJ |
1220 | { |
1221 | decode_configs(c); | |
8ff374b9 | 1222 | switch (c->processor_id & PRID_IMP_MASK) { |
190fca3e KC |
1223 | case PRID_IMP_BMIPS32_REV4: |
1224 | case PRID_IMP_BMIPS32_REV8: | |
602977b0 KC |
1225 | c->cputype = CPU_BMIPS32; |
1226 | __cpu_name[cpu] = "Broadcom BMIPS32"; | |
06785df0 | 1227 | set_elf_platform(cpu, "bmips32"); |
602977b0 KC |
1228 | break; |
1229 | case PRID_IMP_BMIPS3300: | |
1230 | case PRID_IMP_BMIPS3300_ALT: | |
1231 | case PRID_IMP_BMIPS3300_BUG: | |
1232 | c->cputype = CPU_BMIPS3300; | |
1233 | __cpu_name[cpu] = "Broadcom BMIPS3300"; | |
06785df0 | 1234 | set_elf_platform(cpu, "bmips3300"); |
602977b0 KC |
1235 | break; |
1236 | case PRID_IMP_BMIPS43XX: { | |
8ff374b9 | 1237 | int rev = c->processor_id & PRID_REV_MASK; |
602977b0 KC |
1238 | |
1239 | if (rev >= PRID_REV_BMIPS4380_LO && | |
1240 | rev <= PRID_REV_BMIPS4380_HI) { | |
1241 | c->cputype = CPU_BMIPS4380; | |
1242 | __cpu_name[cpu] = "Broadcom BMIPS4380"; | |
06785df0 | 1243 | set_elf_platform(cpu, "bmips4380"); |
602977b0 KC |
1244 | } else { |
1245 | c->cputype = CPU_BMIPS4350; | |
1246 | __cpu_name[cpu] = "Broadcom BMIPS4350"; | |
06785df0 | 1247 | set_elf_platform(cpu, "bmips4350"); |
602977b0 | 1248 | } |
0de663ef | 1249 | break; |
602977b0 KC |
1250 | } |
1251 | case PRID_IMP_BMIPS5000: | |
68e6a783 | 1252 | case PRID_IMP_BMIPS5200: |
602977b0 KC |
1253 | c->cputype = CPU_BMIPS5000; |
1254 | __cpu_name[cpu] = "Broadcom BMIPS5000"; | |
06785df0 | 1255 | set_elf_platform(cpu, "bmips5000"); |
602977b0 | 1256 | c->options |= MIPS_CPU_ULRI; |
0de663ef | 1257 | break; |
1c0c13eb AJ |
1258 | } |
1259 | } | |
1260 | ||
0dd4781b DD |
1261 | static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu) |
1262 | { | |
1263 | decode_configs(c); | |
8ff374b9 | 1264 | switch (c->processor_id & PRID_IMP_MASK) { |
0dd4781b DD |
1265 | case PRID_IMP_CAVIUM_CN38XX: |
1266 | case PRID_IMP_CAVIUM_CN31XX: | |
1267 | case PRID_IMP_CAVIUM_CN30XX: | |
6f329468 DD |
1268 | c->cputype = CPU_CAVIUM_OCTEON; |
1269 | __cpu_name[cpu] = "Cavium Octeon"; | |
1270 | goto platform; | |
0dd4781b DD |
1271 | case PRID_IMP_CAVIUM_CN58XX: |
1272 | case PRID_IMP_CAVIUM_CN56XX: | |
1273 | case PRID_IMP_CAVIUM_CN50XX: | |
1274 | case PRID_IMP_CAVIUM_CN52XX: | |
6f329468 DD |
1275 | c->cputype = CPU_CAVIUM_OCTEON_PLUS; |
1276 | __cpu_name[cpu] = "Cavium Octeon+"; | |
1277 | platform: | |
c094c99e | 1278 | set_elf_platform(cpu, "octeon"); |
0dd4781b | 1279 | break; |
a1431b61 | 1280 | case PRID_IMP_CAVIUM_CN61XX: |
0e56b385 | 1281 | case PRID_IMP_CAVIUM_CN63XX: |
a1431b61 DD |
1282 | case PRID_IMP_CAVIUM_CN66XX: |
1283 | case PRID_IMP_CAVIUM_CN68XX: | |
af04bb85 | 1284 | case PRID_IMP_CAVIUM_CNF71XX: |
0e56b385 DD |
1285 | c->cputype = CPU_CAVIUM_OCTEON2; |
1286 | __cpu_name[cpu] = "Cavium Octeon II"; | |
c094c99e | 1287 | set_elf_platform(cpu, "octeon2"); |
0e56b385 | 1288 | break; |
af04bb85 DD |
1289 | case PRID_IMP_CAVIUM_CN70XX: |
1290 | case PRID_IMP_CAVIUM_CN78XX: | |
1291 | c->cputype = CPU_CAVIUM_OCTEON3; | |
1292 | __cpu_name[cpu] = "Cavium Octeon III"; | |
1293 | set_elf_platform(cpu, "octeon3"); | |
1294 | break; | |
0dd4781b DD |
1295 | default: |
1296 | printk(KERN_INFO "Unknown Octeon chip!\n"); | |
1297 | c->cputype = CPU_UNKNOWN; | |
1298 | break; | |
1299 | } | |
1300 | } | |
1301 | ||
83ccf69d LPC |
1302 | static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu) |
1303 | { | |
1304 | decode_configs(c); | |
1305 | /* JZRISC does not implement the CP0 counter. */ | |
1306 | c->options &= ~MIPS_CPU_COUNTER; | |
06947aaa | 1307 | BUG_ON(!__builtin_constant_p(cpu_has_counter) || cpu_has_counter); |
8ff374b9 | 1308 | switch (c->processor_id & PRID_IMP_MASK) { |
83ccf69d LPC |
1309 | case PRID_IMP_JZRISC: |
1310 | c->cputype = CPU_JZRISC; | |
4f12b91d | 1311 | c->writecombine = _CACHE_UNCACHED_ACCELERATED; |
83ccf69d LPC |
1312 | __cpu_name[cpu] = "Ingenic JZRISC"; |
1313 | break; | |
1314 | default: | |
1315 | panic("Unknown Ingenic Processor ID!"); | |
1316 | break; | |
1317 | } | |
1318 | } | |
1319 | ||
a7117c6b J |
1320 | static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu) |
1321 | { | |
1322 | decode_configs(c); | |
1323 | ||
8ff374b9 | 1324 | if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_NETLOGIC_AU13XX) { |
809f36c6 ML |
1325 | c->cputype = CPU_ALCHEMY; |
1326 | __cpu_name[cpu] = "Au1300"; | |
1327 | /* following stuff is not for Alchemy */ | |
1328 | return; | |
1329 | } | |
1330 | ||
70342287 RB |
1331 | c->options = (MIPS_CPU_TLB | |
1332 | MIPS_CPU_4KEX | | |
a7117c6b | 1333 | MIPS_CPU_COUNTER | |
70342287 RB |
1334 | MIPS_CPU_DIVEC | |
1335 | MIPS_CPU_WATCH | | |
1336 | MIPS_CPU_EJTAG | | |
a7117c6b J |
1337 | MIPS_CPU_LLSC); |
1338 | ||
8ff374b9 | 1339 | switch (c->processor_id & PRID_IMP_MASK) { |
4ca86a2f | 1340 | case PRID_IMP_NETLOGIC_XLP2XX: |
8907c55e | 1341 | case PRID_IMP_NETLOGIC_XLP9XX: |
1c983986 | 1342 | case PRID_IMP_NETLOGIC_XLP5XX: |
4ca86a2f J |
1343 | c->cputype = CPU_XLP; |
1344 | __cpu_name[cpu] = "Broadcom XLPII"; | |
1345 | break; | |
1346 | ||
2aa54b20 J |
1347 | case PRID_IMP_NETLOGIC_XLP8XX: |
1348 | case PRID_IMP_NETLOGIC_XLP3XX: | |
a3d4fb2d J |
1349 | c->cputype = CPU_XLP; |
1350 | __cpu_name[cpu] = "Netlogic XLP"; | |
1351 | break; | |
1352 | ||
a7117c6b J |
1353 | case PRID_IMP_NETLOGIC_XLR732: |
1354 | case PRID_IMP_NETLOGIC_XLR716: | |
1355 | case PRID_IMP_NETLOGIC_XLR532: | |
1356 | case PRID_IMP_NETLOGIC_XLR308: | |
1357 | case PRID_IMP_NETLOGIC_XLR532C: | |
1358 | case PRID_IMP_NETLOGIC_XLR516C: | |
1359 | case PRID_IMP_NETLOGIC_XLR508C: | |
1360 | case PRID_IMP_NETLOGIC_XLR308C: | |
1361 | c->cputype = CPU_XLR; | |
1362 | __cpu_name[cpu] = "Netlogic XLR"; | |
1363 | break; | |
1364 | ||
1365 | case PRID_IMP_NETLOGIC_XLS608: | |
1366 | case PRID_IMP_NETLOGIC_XLS408: | |
1367 | case PRID_IMP_NETLOGIC_XLS404: | |
1368 | case PRID_IMP_NETLOGIC_XLS208: | |
1369 | case PRID_IMP_NETLOGIC_XLS204: | |
1370 | case PRID_IMP_NETLOGIC_XLS108: | |
1371 | case PRID_IMP_NETLOGIC_XLS104: | |
1372 | case PRID_IMP_NETLOGIC_XLS616B: | |
1373 | case PRID_IMP_NETLOGIC_XLS608B: | |
1374 | case PRID_IMP_NETLOGIC_XLS416B: | |
1375 | case PRID_IMP_NETLOGIC_XLS412B: | |
1376 | case PRID_IMP_NETLOGIC_XLS408B: | |
1377 | case PRID_IMP_NETLOGIC_XLS404B: | |
1378 | c->cputype = CPU_XLR; | |
1379 | __cpu_name[cpu] = "Netlogic XLS"; | |
1380 | break; | |
1381 | ||
1382 | default: | |
a3d4fb2d | 1383 | pr_info("Unknown Netlogic chip id [%02x]!\n", |
a7117c6b J |
1384 | c->processor_id); |
1385 | c->cputype = CPU_XLR; | |
1386 | break; | |
1387 | } | |
1388 | ||
a3d4fb2d | 1389 | if (c->cputype == CPU_XLP) { |
a96102be | 1390 | set_isa(c, MIPS_CPU_ISA_M64R2); |
a3d4fb2d J |
1391 | c->options |= (MIPS_CPU_FPU | MIPS_CPU_ULRI | MIPS_CPU_MCHECK); |
1392 | /* This will be updated again after all threads are woken up */ | |
1393 | c->tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1; | |
1394 | } else { | |
a96102be | 1395 | set_isa(c, MIPS_CPU_ISA_M64R1); |
a3d4fb2d J |
1396 | c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1; |
1397 | } | |
7777b939 | 1398 | c->kscratch_mask = 0xf; |
a7117c6b J |
1399 | } |
1400 | ||
949e51be DD |
1401 | #ifdef CONFIG_64BIT |
1402 | /* For use by uaccess.h */ | |
1403 | u64 __ua_limit; | |
1404 | EXPORT_SYMBOL(__ua_limit); | |
1405 | #endif | |
1406 | ||
9966db25 | 1407 | const char *__cpu_name[NR_CPUS]; |
874fd3b5 | 1408 | const char *__elf_platform; |
9966db25 | 1409 | |
078a55fc | 1410 | void cpu_probe(void) |
1da177e4 LT |
1411 | { |
1412 | struct cpuinfo_mips *c = ¤t_cpu_data; | |
9966db25 | 1413 | unsigned int cpu = smp_processor_id(); |
1da177e4 | 1414 | |
70342287 | 1415 | c->processor_id = PRID_IMP_UNKNOWN; |
1da177e4 LT |
1416 | c->fpu_id = FPIR_IMP_NONE; |
1417 | c->cputype = CPU_UNKNOWN; | |
4f12b91d | 1418 | c->writecombine = _CACHE_UNCACHED; |
1da177e4 | 1419 | |
9b26616c MR |
1420 | c->fpu_csr31 = FPU_CSR_RN; |
1421 | c->fpu_msk31 = FPU_CSR_RSVD | FPU_CSR_ABS2008 | FPU_CSR_NAN2008; | |
1422 | ||
1da177e4 | 1423 | c->processor_id = read_c0_prid(); |
8ff374b9 | 1424 | switch (c->processor_id & PRID_COMP_MASK) { |
1da177e4 | 1425 | case PRID_COMP_LEGACY: |
cea7e2df | 1426 | cpu_probe_legacy(c, cpu); |
1da177e4 LT |
1427 | break; |
1428 | case PRID_COMP_MIPS: | |
cea7e2df | 1429 | cpu_probe_mips(c, cpu); |
1da177e4 LT |
1430 | break; |
1431 | case PRID_COMP_ALCHEMY: | |
cea7e2df | 1432 | cpu_probe_alchemy(c, cpu); |
1da177e4 LT |
1433 | break; |
1434 | case PRID_COMP_SIBYTE: | |
cea7e2df | 1435 | cpu_probe_sibyte(c, cpu); |
1da177e4 | 1436 | break; |
1c0c13eb | 1437 | case PRID_COMP_BROADCOM: |
cea7e2df | 1438 | cpu_probe_broadcom(c, cpu); |
1c0c13eb | 1439 | break; |
1da177e4 | 1440 | case PRID_COMP_SANDCRAFT: |
cea7e2df | 1441 | cpu_probe_sandcraft(c, cpu); |
1da177e4 | 1442 | break; |
a92b0588 | 1443 | case PRID_COMP_NXP: |
cea7e2df | 1444 | cpu_probe_nxp(c, cpu); |
a3dddd56 | 1445 | break; |
0dd4781b DD |
1446 | case PRID_COMP_CAVIUM: |
1447 | cpu_probe_cavium(c, cpu); | |
1448 | break; | |
252617a4 PB |
1449 | case PRID_COMP_INGENIC_D0: |
1450 | case PRID_COMP_INGENIC_D1: | |
1451 | case PRID_COMP_INGENIC_E1: | |
83ccf69d LPC |
1452 | cpu_probe_ingenic(c, cpu); |
1453 | break; | |
a7117c6b J |
1454 | case PRID_COMP_NETLOGIC: |
1455 | cpu_probe_netlogic(c, cpu); | |
1456 | break; | |
1da177e4 | 1457 | } |
dec8b1ca | 1458 | |
cea7e2df RB |
1459 | BUG_ON(!__cpu_name[cpu]); |
1460 | BUG_ON(c->cputype == CPU_UNKNOWN); | |
1461 | ||
dec8b1ca FBH |
1462 | /* |
1463 | * Platform code can force the cpu type to optimize code | |
1464 | * generation. In that case be sure the cpu type is correctly | |
1465 | * manually setup otherwise it could trigger some nasty bugs. | |
1466 | */ | |
1467 | BUG_ON(current_cpu_type() != c->cputype); | |
1468 | ||
0103d23f KC |
1469 | if (mips_fpu_disabled) |
1470 | c->options &= ~MIPS_CPU_FPU; | |
1471 | ||
1472 | if (mips_dsp_disabled) | |
ee80f7c7 | 1473 | c->ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P); |
0103d23f | 1474 | |
3d528b32 MC |
1475 | if (mips_htw_disabled) { |
1476 | c->options &= ~MIPS_CPU_HTW; | |
1477 | write_c0_pwctl(read_c0_pwctl() & | |
1478 | ~(1 << MIPS_PWCTL_PWEN_SHIFT)); | |
1479 | } | |
1480 | ||
7aecd5ca MR |
1481 | if (c->options & MIPS_CPU_FPU) |
1482 | cpu_set_fpu_opts(c); | |
1483 | else | |
1484 | cpu_set_nofpu_opts(c); | |
9966db25 | 1485 | |
8d5ded16 JK |
1486 | if (cpu_has_bp_ghist) |
1487 | write_c0_r10k_diag(read_c0_r10k_diag() | | |
1488 | R10K_DIAG_E_GHIST); | |
1489 | ||
8b8aa636 | 1490 | if (cpu_has_mips_r2_r6) { |
f6771dbb | 1491 | c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1; |
da4b62cd AC |
1492 | /* R2 has Performance Counter Interrupt indicator */ |
1493 | c->options |= MIPS_CPU_PCI; | |
1494 | } | |
f6771dbb RB |
1495 | else |
1496 | c->srsets = 1; | |
91dfc423 | 1497 | |
a8ad1367 | 1498 | if (cpu_has_msa) { |
a5e9a69e | 1499 | c->msa_id = cpu_get_msa_id(); |
a8ad1367 PB |
1500 | WARN(c->msa_id & MSA_IR_WRPF, |
1501 | "Vector register partitioning unimplemented!"); | |
1502 | } | |
a5e9a69e | 1503 | |
91dfc423 | 1504 | cpu_probe_vmbits(c); |
949e51be DD |
1505 | |
1506 | #ifdef CONFIG_64BIT | |
1507 | if (cpu == 0) | |
1508 | __ua_limit = ~((1ull << cpu_vmbits) - 1); | |
1509 | #endif | |
1da177e4 LT |
1510 | } |
1511 | ||
078a55fc | 1512 | void cpu_report(void) |
1da177e4 LT |
1513 | { |
1514 | struct cpuinfo_mips *c = ¤t_cpu_data; | |
1515 | ||
d9f897c9 LY |
1516 | pr_info("CPU%d revision is: %08x (%s)\n", |
1517 | smp_processor_id(), c->processor_id, cpu_name_string()); | |
1da177e4 | 1518 | if (c->options & MIPS_CPU_FPU) |
9966db25 | 1519 | printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id); |
a5e9a69e PB |
1520 | if (cpu_has_msa) |
1521 | pr_info("MSA revision is: %08x\n", c->msa_id); | |
1da177e4 | 1522 | } |