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MIPS: Configure FTLB after probing TLB sizes from config4
[mirror_ubuntu-eoan-kernel.git] / arch / mips / kernel / cpu-probe.c
CommitLineData
1da177e4
LT		 1/*
2 * Processor capabilities determination functions.
3 *
4 * Copyright (C) xxxx the Anonymous
010b853b 5 * Copyright (C) 1994 - 2006 Ralf Baechle
4194318c 6 * Copyright (C) 2003, 2004 Maciej W. Rozycki
70342287 7 * Copyright (C) 2001, 2004, 2011, 2012 MIPS Technologies, Inc.
1da177e4
LT		 8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
13 */
1da177e4
LT		 14#include <linux/init.h>
15#include <linux/kernel.h>
16#include <linux/ptrace.h>
631330f5 17#include <linux/smp.h>
1da177e4 18#include <linux/stddef.h>
73bc256d 19#include <linux/export.h>
1da177e4 20
5759906c 21#include <asm/bugs.h>
1da177e4 22#include <asm/cpu.h>
f6843626 23#include <asm/cpu-features.h>
69f24d17 24#include <asm/cpu-type.h>
1da177e4
LT		 25#include <asm/fpu.h>
26#include <asm/mipsregs.h>
30ee615b 27#include <asm/mipsmtregs.h>
a5e9a69e 28#include <asm/msa.h>
654f57bf 29#include <asm/watch.h>
06372a63 30#include <asm/elf.h>
4f12b91d 31#include <asm/pgtable-bits.h>
a074f0e8 32#include <asm/spram.h>
949e51be
DD		 33#include <asm/uaccess.h>
34
e14f1db7
PB		 35/* Hardware capabilities */
36unsigned int elf_hwcap __read_mostly;
37
7aecd5ca
MR		 38/*
39 * Get the FPU Implementation/Revision.
40 */
41static inline unsigned long cpu_get_fpu_id(void)
42{
43 unsigned long tmp, fpu_id;
44
45 tmp = read_c0_status();
46 __enable_fpu(FPU_AS_IS);
47 fpu_id = read_32bit_cp1_register(CP1_REVISION);
48 write_c0_status(tmp);
49 return fpu_id;
50}
51
52/*
53 * Check if the CPU has an external FPU.
54 */
55static inline int __cpu_has_fpu(void)
56{
57 return (cpu_get_fpu_id() & FPIR_IMP_MASK) != FPIR_IMP_NONE;
58}
59
60static inline unsigned long cpu_get_msa_id(void)
61{
62 unsigned long status, msa_id;
63
64 status = read_c0_status();
65 __enable_fpu(FPU_64BIT);
66 enable_msa();
67 msa_id = read_msa_ir();
68 disable_msa();
69 write_c0_status(status);
70 return msa_id;
71}
72
9b26616c
MR		 73/*
74 * Determine the FCSR mask for FPU hardware.
75 */
76static inline void cpu_set_fpu_fcsr_mask(struct cpuinfo_mips *c)
77{
78 unsigned long sr, mask, fcsr, fcsr0, fcsr1;
79
90b712dd 80 fcsr = c->fpu_csr31;
9b26616c
MR		 81 mask = FPU_CSR_ALL_X | FPU_CSR_ALL_E | FPU_CSR_ALL_S | FPU_CSR_RM;
82
83 sr = read_c0_status();
84 __enable_fpu(FPU_AS_IS);
85
9b26616c
MR		 86 fcsr0 = fcsr & mask;
87 write_32bit_cp1_register(CP1_STATUS, fcsr0);
88 fcsr0 = read_32bit_cp1_register(CP1_STATUS);
89
90 fcsr1 = fcsr | ~mask;
91 write_32bit_cp1_register(CP1_STATUS, fcsr1);
92 fcsr1 = read_32bit_cp1_register(CP1_STATUS);
93
94 write_32bit_cp1_register(CP1_STATUS, fcsr);
95
96 write_c0_status(sr);
97
98 c->fpu_msk31 = ~(fcsr0 ^ fcsr1) & ~mask;
99}
100
93adeaf6
MR		 101/*
102 * Determine the IEEE 754 NaN encodings and ABS.fmt/NEG.fmt execution modes
103 * supported by FPU hardware.
104 */
105static void cpu_set_fpu_2008(struct cpuinfo_mips *c)
106{
107 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
108 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
109 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) {
110 unsigned long sr, fir, fcsr, fcsr0, fcsr1;
111
112 sr = read_c0_status();
113 __enable_fpu(FPU_AS_IS);
114
115 fir = read_32bit_cp1_register(CP1_REVISION);
116 if (fir & MIPS_FPIR_HAS2008) {
117 fcsr = read_32bit_cp1_register(CP1_STATUS);
118
119 fcsr0 = fcsr & ~(FPU_CSR_ABS2008 | FPU_CSR_NAN2008);
120 write_32bit_cp1_register(CP1_STATUS, fcsr0);
121 fcsr0 = read_32bit_cp1_register(CP1_STATUS);
122
123 fcsr1 = fcsr | FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
124 write_32bit_cp1_register(CP1_STATUS, fcsr1);
125 fcsr1 = read_32bit_cp1_register(CP1_STATUS);
126
127 write_32bit_cp1_register(CP1_STATUS, fcsr);
128
129 if (!(fcsr0 & FPU_CSR_NAN2008))
130 c->options |= MIPS_CPU_NAN_LEGACY;
131 if (fcsr1 & FPU_CSR_NAN2008)
132 c->options |= MIPS_CPU_NAN_2008;
133
134 if ((fcsr0 ^ fcsr1) & FPU_CSR_ABS2008)
135 c->fpu_msk31 &= ~FPU_CSR_ABS2008;
136 else
137 c->fpu_csr31 |= fcsr & FPU_CSR_ABS2008;
138
139 if ((fcsr0 ^ fcsr1) & FPU_CSR_NAN2008)
140 c->fpu_msk31 &= ~FPU_CSR_NAN2008;
141 else
142 c->fpu_csr31 |= fcsr & FPU_CSR_NAN2008;
143 } else {
144 c->options |= MIPS_CPU_NAN_LEGACY;
145 }
146
147 write_c0_status(sr);
148 } else {
149 c->options |= MIPS_CPU_NAN_LEGACY;
150 }
151}
152
153/*
503943e0
MR		 154 * IEEE 754 conformance mode to use. Affects the NaN encoding and the
155 * ABS.fmt/NEG.fmt execution mode.
156 */
157static enum { STRICT, LEGACY, STD2008, RELAXED } ieee754 = STRICT;
158
159/*
160 * Set the IEEE 754 NaN encodings and the ABS.fmt/NEG.fmt execution modes
161 * to support by the FPU emulator according to the IEEE 754 conformance
162 * mode selected. Note that "relaxed" straps the emulator so that it
163 * allows 2008-NaN binaries even for legacy processors.
93adeaf6
MR		 164 */
165static void cpu_set_nofpu_2008(struct cpuinfo_mips *c)
166{
503943e0 167 c->options &= ~(MIPS_CPU_NAN_2008 | MIPS_CPU_NAN_LEGACY);
93adeaf6 168 c->fpu_csr31 &= ~(FPU_CSR_ABS2008 | FPU_CSR_NAN2008);
503943e0
MR		 169 c->fpu_msk31 &= ~(FPU_CSR_ABS2008 | FPU_CSR_NAN2008);
170
171 switch (ieee754) {
172 case STRICT:
173 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
174 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
175 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) {
176 c->options |= MIPS_CPU_NAN_2008 | MIPS_CPU_NAN_LEGACY;
177 } else {
178 c->options |= MIPS_CPU_NAN_LEGACY;
179 c->fpu_msk31 |= FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
180 }
181 break;
182 case LEGACY:
93adeaf6
MR		 183 c->options |= MIPS_CPU_NAN_LEGACY;
184 c->fpu_msk31 |= FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
503943e0
MR		 185 break;
186 case STD2008:
187 c->options |= MIPS_CPU_NAN_2008;
188 c->fpu_csr31 |= FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
189 c->fpu_msk31 |= FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
190 break;
191 case RELAXED:
192 c->options |= MIPS_CPU_NAN_2008 | MIPS_CPU_NAN_LEGACY;
193 break;
93adeaf6
MR		 194 }
195}
196
503943e0
MR		 197/*
198 * Override the IEEE 754 NaN encoding and ABS.fmt/NEG.fmt execution mode
199 * according to the "ieee754=" parameter.
200 */
201static void cpu_set_nan_2008(struct cpuinfo_mips *c)
202{
203 switch (ieee754) {
204 case STRICT:
205 mips_use_nan_legacy = !!cpu_has_nan_legacy;
206 mips_use_nan_2008 = !!cpu_has_nan_2008;
207 break;
208 case LEGACY:
209 mips_use_nan_legacy = !!cpu_has_nan_legacy;
210 mips_use_nan_2008 = !cpu_has_nan_legacy;
211 break;
212 case STD2008:
213 mips_use_nan_legacy = !cpu_has_nan_2008;
214 mips_use_nan_2008 = !!cpu_has_nan_2008;
215 break;
216 case RELAXED:
217 mips_use_nan_legacy = true;
218 mips_use_nan_2008 = true;
219 break;
220 }
221}
222
223/*
224 * IEEE 754 NaN encoding and ABS.fmt/NEG.fmt execution mode override
225 * settings:
226 *
227 * strict: accept binaries that request a NaN encoding supported by the FPU
228 * legacy: only accept legacy-NaN binaries
229 * 2008: only accept 2008-NaN binaries
230 * relaxed: accept any binaries regardless of whether supported by the FPU
231 */
232static int __init ieee754_setup(char *s)
233{
234 if (!s)
235 return -1;
236 else if (!strcmp(s, "strict"))
237 ieee754 = STRICT;
238 else if (!strcmp(s, "legacy"))
239 ieee754 = LEGACY;
240 else if (!strcmp(s, "2008"))
241 ieee754 = STD2008;
242 else if (!strcmp(s, "relaxed"))
243 ieee754 = RELAXED;
244 else
245 return -1;
246
247 if (!(boot_cpu_data.options & MIPS_CPU_FPU))
248 cpu_set_nofpu_2008(&boot_cpu_data);
249 cpu_set_nan_2008(&boot_cpu_data);
250
251 return 0;
252}
253
254early_param("ieee754", ieee754_setup);
255
f6843626
MR		 256/*
257 * Set the FIR feature flags for the FPU emulator.
258 */
259static void cpu_set_nofpu_id(struct cpuinfo_mips *c)
260{
261 u32 value;
262
263 value = 0;
264 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
265 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
266 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6))
267 value |= MIPS_FPIR_D | MIPS_FPIR_S;
268 if (c->isa_level & (MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
269 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6))
270 value |= MIPS_FPIR_F64 | MIPS_FPIR_L | MIPS_FPIR_W;
90d53a91
MR		 271 if (c->options & MIPS_CPU_NAN_2008)
272 value |= MIPS_FPIR_HAS2008;
f6843626
MR		 273 c->fpu_id = value;
274}
275
9b26616c
MR		 276/* Determined FPU emulator mask to use for the boot CPU with "nofpu". */
277static unsigned int mips_nofpu_msk31;
278
7aecd5ca
MR		 279/*
280 * Set options for FPU hardware.
281 */
282static void cpu_set_fpu_opts(struct cpuinfo_mips *c)
283{
284 c->fpu_id = cpu_get_fpu_id();
285 mips_nofpu_msk31 = c->fpu_msk31;
286
287 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
288 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
289 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) {
290 if (c->fpu_id & MIPS_FPIR_3D)
291 c->ases |= MIPS_ASE_MIPS3D;
292 if (c->fpu_id & MIPS_FPIR_FREP)
293 c->options |= MIPS_CPU_FRE;
294 }
295
296 cpu_set_fpu_fcsr_mask(c);
93adeaf6 297 cpu_set_fpu_2008(c);
503943e0 298 cpu_set_nan_2008(c);
7aecd5ca
MR		 299}
300
301/*
302 * Set options for the FPU emulator.
303 */
304static void cpu_set_nofpu_opts(struct cpuinfo_mips *c)
305{
306 c->options &= ~MIPS_CPU_FPU;
307 c->fpu_msk31 = mips_nofpu_msk31;
308
93adeaf6 309 cpu_set_nofpu_2008(c);
503943e0 310 cpu_set_nan_2008(c);
7aecd5ca
MR		 311 cpu_set_nofpu_id(c);
312}
313
078a55fc 314static int mips_fpu_disabled;
0103d23f
KC		 315
316static int __init fpu_disable(char *s)
317{
7aecd5ca 318 cpu_set_nofpu_opts(&boot_cpu_data);
0103d23f
KC		 319 mips_fpu_disabled = 1;
320
321 return 1;
322}
323
324__setup("nofpu", fpu_disable);
325
078a55fc 326int mips_dsp_disabled;
0103d23f
KC		 327
328static int __init dsp_disable(char *s)
329{
ee80f7c7 330 cpu_data[0].ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
0103d23f
KC		 331 mips_dsp_disabled = 1;
332
333 return 1;
334}
335
336__setup("nodsp", dsp_disable);
337
3d528b32
MC		 338static int mips_htw_disabled;
339
340static int __init htw_disable(char *s)
341{
342 mips_htw_disabled = 1;
343 cpu_data[0].options &= ~MIPS_CPU_HTW;
344 write_c0_pwctl(read_c0_pwctl() &
345 ~(1 << MIPS_PWCTL_PWEN_SHIFT));
346
347 return 1;
348}
349
350__setup("nohtw", htw_disable);
351
97f4ad29
MC		 352static int mips_ftlb_disabled;
353static int mips_has_ftlb_configured;
354
ebd0e0f5
PB		 355enum ftlb_flags {
356 FTLB_EN = 1 << 0,
357 FTLB_SET_PROB = 1 << 1,
358};
359
360static int set_ftlb_enable(struct cpuinfo_mips *c, enum ftlb_flags flags);
97f4ad29
MC		 361
362static int __init ftlb_disable(char *s)
363{
364 unsigned int config4, mmuextdef;
365
366 /*
367 * If the core hasn't done any FTLB configuration, there is nothing
368 * for us to do here.
369 */
370 if (!mips_has_ftlb_configured)
371 return 1;
372
373 /* Disable it in the boot cpu */
912708c2
MC		 374 if (set_ftlb_enable(&cpu_data[0], 0)) {
375 pr_warn("Can't turn FTLB off\n");
376 return 1;
377 }
97f4ad29
MC		 378
379 back_to_back_c0_hazard();
380
381 config4 = read_c0_config4();
382
383 /* Check that FTLB has been disabled */
384 mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF;
385 /* MMUSIZEEXT == VTLB ON, FTLB OFF */
386 if (mmuextdef == MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT) {
387 /* This should never happen */
388 pr_warn("FTLB could not be disabled!\n");
389 return 1;
390 }
391
392 mips_ftlb_disabled = 1;
393 mips_has_ftlb_configured = 0;
394
395 /*
396 * noftlb is mainly used for debug purposes so print
397 * an informative message instead of using pr_debug()
398 */
399 pr_info("FTLB has been disabled\n");
400
401 /*
402 * Some of these bits are duplicated in the decode_config4.
403 * MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT is the only possible case
404 * once FTLB has been disabled so undo what decode_config4 did.
405 */
406 cpu_data[0].tlbsize -= cpu_data[0].tlbsizeftlbways *
407 cpu_data[0].tlbsizeftlbsets;
408 cpu_data[0].tlbsizeftlbsets = 0;
409 cpu_data[0].tlbsizeftlbways = 0;
410
411 return 1;
412}
413
414__setup("noftlb", ftlb_disable);
415
416
9267a30d
MSJ		 417static inline void check_errata(void)
418{
419 struct cpuinfo_mips *c = &current_cpu_data;
420
69f24d17 421 switch (current_cpu_type()) {
9267a30d
MSJ		 422 case CPU_34K:
423 /*
424 * Erratum "RPS May Cause Incorrect Instruction Execution"
b633648c 425 * This code only handles VPE0, any SMP/RTOS code
9267a30d
MSJ		 426 * making use of VPE1 will be responsable for that VPE.
427 */
428 if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2)
429 write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS);
430 break;
431 default:
432 break;
433 }
434}
435
1da177e4
LT		 436void __init check_bugs32(void)
437{
9267a30d 438 check_errata();
1da177e4
LT		 439}
440
441/*
442 * Probe whether cpu has config register by trying to play with
443 * alternate cache bit and see whether it matters.
444 * It's used by cpu_probe to distinguish between R3000A and R3081.
445 */
446static inline int cpu_has_confreg(void)
447{
448#ifdef CONFIG_CPU_R3000
449 extern unsigned long r3k_cache_size(unsigned long);
450 unsigned long size1, size2;
451 unsigned long cfg = read_c0_conf();
452
453 size1 = r3k_cache_size(ST0_ISC);
454 write_c0_conf(cfg ^ R30XX_CONF_AC);
455 size2 = r3k_cache_size(ST0_ISC);
456 write_c0_conf(cfg);
457 return size1 != size2;
458#else
459 return 0;
460#endif
461}
462
c094c99e
RM		 463static inline void set_elf_platform(int cpu, const char *plat)
464{
465 if (cpu == 0)
466 __elf_platform = plat;
467}
468
91dfc423
GR		 469static inline void cpu_probe_vmbits(struct cpuinfo_mips *c)
470{
471#ifdef __NEED_VMBITS_PROBE
5b7efa89 472 write_c0_entryhi(0x3fffffffffffe000ULL);
91dfc423 473 back_to_back_c0_hazard();
5b7efa89 474 c->vmbits = fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL);
91dfc423
GR		 475#endif
476}
477
078a55fc 478static void set_isa(struct cpuinfo_mips *c, unsigned int isa)
a96102be
SH		 479{
480 switch (isa) {
481 case MIPS_CPU_ISA_M64R2:
482 c->isa_level |= MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2;
483 case MIPS_CPU_ISA_M64R1:
484 c->isa_level |= MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1;
485 case MIPS_CPU_ISA_V:
486 c->isa_level |= MIPS_CPU_ISA_V;
487 case MIPS_CPU_ISA_IV:
488 c->isa_level |= MIPS_CPU_ISA_IV;
489 case MIPS_CPU_ISA_III:
1990e542 490 c->isa_level |= MIPS_CPU_ISA_II | MIPS_CPU_ISA_III;
a96102be
SH		 491 break;
492
8b8aa636
LY		 493 /* R6 incompatible with everything else */
494 case MIPS_CPU_ISA_M64R6:
495 c->isa_level |= MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6;
496 case MIPS_CPU_ISA_M32R6:
497 c->isa_level |= MIPS_CPU_ISA_M32R6;
498 /* Break here so we don't add incompatible ISAs */
499 break;
a96102be
SH		 500 case MIPS_CPU_ISA_M32R2:
501 c->isa_level |= MIPS_CPU_ISA_M32R2;
502 case MIPS_CPU_ISA_M32R1:
503 c->isa_level |= MIPS_CPU_ISA_M32R1;
504 case MIPS_CPU_ISA_II:
505 c->isa_level |= MIPS_CPU_ISA_II;
a96102be
SH		 506 break;
507 }
508}
509
078a55fc 510static char unknown_isa[] = KERN_ERR \
2fa36399
KC		 511 "Unsupported ISA type, c0.config0: %d.";
512
cf0a8aa0
MC		 513static unsigned int calculate_ftlb_probability(struct cpuinfo_mips *c)
514{
515
516 unsigned int probability = c->tlbsize / c->tlbsizevtlb;
517
518 /*
519 * 0 = All TLBWR instructions go to FTLB
520 * 1 = 15:1: For every 16 TBLWR instructions, 15 go to the
521 * FTLB and 1 goes to the VTLB.
522 * 2 = 7:1: As above with 7:1 ratio.
523 * 3 = 3:1: As above with 3:1 ratio.
524 *
525 * Use the linear midpoint as the probability threshold.
526 */
527 if (probability >= 12)
528 return 1;
529 else if (probability >= 6)
530 return 2;
531 else
532 /*
533 * So FTLB is less than 4 times bigger than VTLB.
534 * A 3:1 ratio can still be useful though.
535 */
536 return 3;
537}
538
ebd0e0f5 539static int set_ftlb_enable(struct cpuinfo_mips *c, enum ftlb_flags flags)
75b5b5e0 540{
20a7f7e5 541 unsigned int config;
d83b0e82
JH		 542
543 /* It's implementation dependent how the FTLB can be enabled */
544 switch (c->cputype) {
545 case CPU_PROAPTIV:
546 case CPU_P5600:
1091bfa2 547 case CPU_P6600:
d83b0e82 548 /* proAptiv & related cores use Config6 to enable the FTLB */
20a7f7e5 549 config = read_c0_config6();
ebd0e0f5
PB		 550
551 if (flags & FTLB_EN)
552 config |= MIPS_CONF6_FTLBEN;
75b5b5e0 553 else
ebd0e0f5
PB		 554 config &= ~MIPS_CONF6_FTLBEN;
555
556 if (flags & FTLB_SET_PROB) {
557 config &= ~(3 << MIPS_CONF6_FTLBP_SHIFT);
558 config |= calculate_ftlb_probability(c)
559 << MIPS_CONF6_FTLBP_SHIFT;
560 }
561
562 write_c0_config6(config);
20a7f7e5
MC		 563 break;
564 case CPU_I6400:
72c70f01 565 /* There's no way to disable the FTLB */
ebd0e0f5
PB		 566 if (!(flags & FTLB_EN))
567 return 1;
568 return 0;
b2edcfc8 569 case CPU_LOONGSON3:
06e4814e
HC		 570 /* Flush ITLB, DTLB, VTLB and FTLB */
571 write_c0_diag(LOONGSON_DIAG_ITLB | LOONGSON_DIAG_DTLB |
572 LOONGSON_DIAG_VTLB | LOONGSON_DIAG_FTLB);
b2edcfc8
HC		 573 /* Loongson-3 cores use Config6 to enable the FTLB */
574 config = read_c0_config6();
ebd0e0f5 575 if (flags & FTLB_EN)
b2edcfc8
HC		 576 /* Enable FTLB */
577 write_c0_config6(config & ~MIPS_CONF6_FTLBDIS);
578 else
579 /* Disable FTLB */
580 write_c0_config6(config | MIPS_CONF6_FTLBDIS);
581 break;
912708c2
MC		 582 default:
583 return 1;
75b5b5e0 584 }
912708c2
MC		 585
586 return 0;
75b5b5e0
LY		 587}
588
2fa36399
KC		 589static inline unsigned int decode_config0(struct cpuinfo_mips *c)
590{
591 unsigned int config0;
2f6f3136 592 int isa, mt;
2fa36399
KC		 593
594 config0 = read_c0_config();
595
75b5b5e0
LY		 596 /*
597 * Look for Standard TLB or Dual VTLB and FTLB
598 */
2f6f3136
JH		 599 mt = config0 & MIPS_CONF_MT;
600 if (mt == MIPS_CONF_MT_TLB)
2fa36399 601 c->options |= MIPS_CPU_TLB;
2f6f3136
JH		 602 else if (mt == MIPS_CONF_MT_FTLB)
603 c->options |= MIPS_CPU_TLB | MIPS_CPU_FTLB;
75b5b5e0 604
2fa36399
KC		 605 isa = (config0 & MIPS_CONF_AT) >> 13;
606 switch (isa) {
607 case 0:
608 switch ((config0 & MIPS_CONF_AR) >> 10) {
609 case 0:
a96102be 610 set_isa(c, MIPS_CPU_ISA_M32R1);
2fa36399
KC		 611 break;
612 case 1:
a96102be 613 set_isa(c, MIPS_CPU_ISA_M32R2);
2fa36399 614 break;
8b8aa636
LY		 615 case 2:
616 set_isa(c, MIPS_CPU_ISA_M32R6);
617 break;
2fa36399
KC		 618 default:
619 goto unknown;
620 }
621 break;
622 case 2:
623 switch ((config0 & MIPS_CONF_AR) >> 10) {
624 case 0:
a96102be 625 set_isa(c, MIPS_CPU_ISA_M64R1);
2fa36399
KC		 626 break;
627 case 1:
a96102be 628 set_isa(c, MIPS_CPU_ISA_M64R2);
2fa36399 629 break;
8b8aa636
LY		 630 case 2:
631 set_isa(c, MIPS_CPU_ISA_M64R6);
632 break;
2fa36399
KC		 633 default:
634 goto unknown;
635 }
636 break;
637 default:
638 goto unknown;
639 }
640
641 return config0 & MIPS_CONF_M;
642
643unknown:
644 panic(unknown_isa, config0);
645}
646
647static inline unsigned int decode_config1(struct cpuinfo_mips *c)
648{
649 unsigned int config1;
650
651 config1 = read_c0_config1();
652
653 if (config1 & MIPS_CONF1_MD)
654 c->ases |= MIPS_ASE_MDMX;
30228c40
JH		 655 if (config1 & MIPS_CONF1_PC)
656 c->options |= MIPS_CPU_PERF;
2fa36399
KC		 657 if (config1 & MIPS_CONF1_WR)
658 c->options |= MIPS_CPU_WATCH;
659 if (config1 & MIPS_CONF1_CA)
660 c->ases |= MIPS_ASE_MIPS16;
661 if (config1 & MIPS_CONF1_EP)
662 c->options |= MIPS_CPU_EJTAG;
663 if (config1 & MIPS_CONF1_FP) {
664 c->options |= MIPS_CPU_FPU;
665 c->options |= MIPS_CPU_32FPR;
666 }
75b5b5e0 667 if (cpu_has_tlb) {
2fa36399 668 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;
75b5b5e0
LY		 669 c->tlbsizevtlb = c->tlbsize;
670 c->tlbsizeftlbsets = 0;
671 }
2fa36399
KC		 672
673 return config1 & MIPS_CONF_M;
674}
675
676static inline unsigned int decode_config2(struct cpuinfo_mips *c)
677{
678 unsigned int config2;
679
680 config2 = read_c0_config2();
681
682 if (config2 & MIPS_CONF2_SL)
683 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
684
685 return config2 & MIPS_CONF_M;
686}
687
688static inline unsigned int decode_config3(struct cpuinfo_mips *c)
689{
690 unsigned int config3;
691
692 config3 = read_c0_config3();
693
b2ab4f08 694 if (config3 & MIPS_CONF3_SM) {
2fa36399 695 c->ases |= MIPS_ASE_SMARTMIPS;
f18bdfa1 696 c->options |= MIPS_CPU_RIXI | MIPS_CPU_CTXTC;
b2ab4f08
SH		 697 }
698 if (config3 & MIPS_CONF3_RXI)
699 c->options |= MIPS_CPU_RIXI;
f18bdfa1
JH		 700 if (config3 & MIPS_CONF3_CTXTC)
701 c->options |= MIPS_CPU_CTXTC;
2fa36399
KC		 702 if (config3 & MIPS_CONF3_DSP)
703 c->ases |= MIPS_ASE_DSP;
b5a6455c 704 if (config3 & MIPS_CONF3_DSP2P) {
ee80f7c7 705 c->ases |= MIPS_ASE_DSP2P;
b5a6455c
ZLK		 706 if (cpu_has_mips_r6)
707 c->ases |= MIPS_ASE_DSP3;
708 }
2fa36399
KC		 709 if (config3 & MIPS_CONF3_VINT)
710 c->options |= MIPS_CPU_VINT;
711 if (config3 & MIPS_CONF3_VEIC)
712 c->options |= MIPS_CPU_VEIC;
12822570
JH		 713 if (config3 & MIPS_CONF3_LPA)
714 c->options |= MIPS_CPU_LPA;
2fa36399
KC		 715 if (config3 & MIPS_CONF3_MT)
716 c->ases |= MIPS_ASE_MIPSMT;
717 if (config3 & MIPS_CONF3_ULRI)
718 c->options |= MIPS_CPU_ULRI;
f8fa4811
SH		 719 if (config3 & MIPS_CONF3_ISA)
720 c->options |= MIPS_CPU_MICROMIPS;
1e7decdb
DD		 721 if (config3 & MIPS_CONF3_VZ)
722 c->ases |= MIPS_ASE_VZ;
4a0156fb
SH		 723 if (config3 & MIPS_CONF3_SC)
724 c->options |= MIPS_CPU_SEGMENTS;
e06a1548
JH		 725 if (config3 & MIPS_CONF3_BI)
726 c->options |= MIPS_CPU_BADINSTR;
727 if (config3 & MIPS_CONF3_BP)
728 c->options |= MIPS_CPU_BADINSTRP;
a5e9a69e
PB		 729 if (config3 & MIPS_CONF3_MSA)
730 c->ases |= MIPS_ASE_MSA;
cab25bc7 731 if (config3 & MIPS_CONF3_PW) {
ed4cbc81 732 c->htw_seq = 0;
3d528b32 733 c->options |= MIPS_CPU_HTW;
ed4cbc81 734 }
9b3274bd
JH		 735 if (config3 & MIPS_CONF3_CDMM)
736 c->options |= MIPS_CPU_CDMM;
aaa7be48
JH		 737 if (config3 & MIPS_CONF3_SP)
738 c->options |= MIPS_CPU_SP;
2fa36399
KC		 739
740 return config3 & MIPS_CONF_M;
741}
742
743static inline unsigned int decode_config4(struct cpuinfo_mips *c)
744{
745 unsigned int config4;
75b5b5e0
LY		 746 unsigned int newcf4;
747 unsigned int mmuextdef;
748 unsigned int ftlb_page = MIPS_CONF4_FTLBPAGESIZE;
2db003a5 749 unsigned long asid_mask;
2fa36399
KC		 750
751 config4 = read_c0_config4();
752
1745c1ef
LY		 753 if (cpu_has_tlb) {
754 if (((config4 & MIPS_CONF4_IE) >> 29) == 2)
755 c->options |= MIPS_CPU_TLBINV;
43d104db 756
e87569cd 757 /*
43d104db
JH		 758 * R6 has dropped the MMUExtDef field from config4.
759 * On R6 the fields always describe the FTLB, and only if it is
760 * present according to Config.MT.
e87569cd 761 */
43d104db
JH		 762 if (!cpu_has_mips_r6)
763 mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF;
764 else if (cpu_has_ftlb)
e87569cd
MC		 765 mmuextdef = MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT;
766 else
43d104db 767 mmuextdef = 0;
e87569cd 768
75b5b5e0
LY		 769 switch (mmuextdef) {
770 case MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT:
771 c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40;
772 c->tlbsizevtlb = c->tlbsize;
773 break;
774 case MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT:
775 c->tlbsizevtlb +=
776 ((config4 & MIPS_CONF4_VTLBSIZEEXT) >>
777 MIPS_CONF4_VTLBSIZEEXT_SHIFT) * 0x40;
778 c->tlbsize = c->tlbsizevtlb;
779 ftlb_page = MIPS_CONF4_VFTLBPAGESIZE;
780 /* fall through */
781 case MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT:
97f4ad29
MC		 782 if (mips_ftlb_disabled)
783 break;
75b5b5e0
LY		 784 newcf4 = (config4 & ~ftlb_page) |
785 (page_size_ftlb(mmuextdef) <<
786 MIPS_CONF4_FTLBPAGESIZE_SHIFT);
787 write_c0_config4(newcf4);
788 back_to_back_c0_hazard();
789 config4 = read_c0_config4();
790 if (config4 != newcf4) {
791 pr_err("PAGE_SIZE 0x%lx is not supported by FTLB (config4=0x%x)\n",
792 PAGE_SIZE, config4);
793 /* Switch FTLB off */
794 set_ftlb_enable(c, 0);
ebd0e0f5 795 mips_ftlb_disabled = 1;
75b5b5e0
LY		 796 break;
797 }
798 c->tlbsizeftlbsets = 1 <<
799 ((config4 & MIPS_CONF4_FTLBSETS) >>
800 MIPS_CONF4_FTLBSETS_SHIFT);
801 c->tlbsizeftlbways = ((config4 & MIPS_CONF4_FTLBWAYS) >>
802 MIPS_CONF4_FTLBWAYS_SHIFT) + 2;
803 c->tlbsize += c->tlbsizeftlbways * c->tlbsizeftlbsets;
97f4ad29 804 mips_has_ftlb_configured = 1;
75b5b5e0
LY		 805 break;
806 }
1745c1ef
LY		 807 }
808
9e575f75
JH		 809 c->kscratch_mask = (config4 & MIPS_CONF4_KSCREXIST)
810 >> MIPS_CONF4_KSCREXIST_SHIFT;
2fa36399 811
2db003a5
PB		 812 asid_mask = MIPS_ENTRYHI_ASID;
813 if (config4 & MIPS_CONF4_AE)
814 asid_mask |= MIPS_ENTRYHI_ASIDX;
815 set_cpu_asid_mask(c, asid_mask);
816
817 /*
818 * Warn if the computed ASID mask doesn't match the mask the kernel
819 * is built for. This may indicate either a serious problem or an
820 * easy optimisation opportunity, but either way should be addressed.
821 */
822 WARN_ON(asid_mask != cpu_asid_mask(c));
823
2fa36399
KC		 824 return config4 & MIPS_CONF_M;
825}
826
8b8a7634
RB		 827static inline unsigned int decode_config5(struct cpuinfo_mips *c)
828{
829 unsigned int config5;
830
831 config5 = read_c0_config5();
d175ed2b 832 config5 &= ~(MIPS_CONF5_UFR | MIPS_CONF5_UFE);
8b8a7634
RB		 833 write_c0_config5(config5);
834
49016748
MC		 835 if (config5 & MIPS_CONF5_EVA)
836 c->options |= MIPS_CPU_EVA;
1f6c52ff
PB		 837 if (config5 & MIPS_CONF5_MRP)
838 c->options |= MIPS_CPU_MAAR;
5aed9da1
MC		 839 if (config5 & MIPS_CONF5_LLB)
840 c->options |= MIPS_CPU_RW_LLB;
c5b36783 841 if (config5 & MIPS_CONF5_MVH)
0f2d988d 842 c->options |= MIPS_CPU_MVH;
f270d881
PB		 843 if (cpu_has_mips_r6 && (config5 & MIPS_CONF5_VP))
844 c->options |= MIPS_CPU_VP;
49016748 845
8b8a7634
RB		 846 return config5 & MIPS_CONF_M;
847}
848
078a55fc 849static void decode_configs(struct cpuinfo_mips *c)
2fa36399
KC		 850{
851 int ok;
852
853 /* MIPS32 or MIPS64 compliant CPU. */
854 c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
855 MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
856
857 c->scache.flags = MIPS_CACHE_NOT_PRESENT;
858
97f4ad29 859 /* Enable FTLB if present and not disabled */
ebd0e0f5 860 set_ftlb_enable(c, mips_ftlb_disabled ? 0 : FTLB_EN);
75b5b5e0 861
2fa36399 862 ok = decode_config0(c); /* Read Config registers. */
70342287 863 BUG_ON(!ok); /* Arch spec violation! */
2fa36399
KC		 864 if (ok)
865 ok = decode_config1(c);
866 if (ok)
867 ok = decode_config2(c);
868 if (ok)
869 ok = decode_config3(c);
870 if (ok)
871 ok = decode_config4(c);
8b8a7634
RB		 872 if (ok)
873 ok = decode_config5(c);
2fa36399 874
37fb60f8
JH		 875 /* Probe the EBase.WG bit */
876 if (cpu_has_mips_r2_r6) {
877 u64 ebase;
878 unsigned int status;
879
880 /* {read,write}_c0_ebase_64() may be UNDEFINED prior to r6 */
881 ebase = cpu_has_mips64r6 ? read_c0_ebase_64()
882 : (s32)read_c0_ebase();
883 if (ebase & MIPS_EBASE_WG) {
884 /* WG bit already set, we can avoid the clumsy probe */
885 c->options |= MIPS_CPU_EBASE_WG;
886 } else {
887 /* Its UNDEFINED to change EBase while BEV=0 */
888 status = read_c0_status();
889 write_c0_status(status | ST0_BEV);
890 irq_enable_hazard();
891 /*
892 * On pre-r6 cores, this may well clobber the upper bits
893 * of EBase. This is hard to avoid without potentially
894 * hitting UNDEFINED dm*c0 behaviour if EBase is 32-bit.
895 */
896 if (cpu_has_mips64r6)
897 write_c0_ebase_64(ebase | MIPS_EBASE_WG);
898 else
899 write_c0_ebase(ebase | MIPS_EBASE_WG);
900 back_to_back_c0_hazard();
901 /* Restore BEV */
902 write_c0_status(status);
903 if (read_c0_ebase() & MIPS_EBASE_WG) {
904 c->options |= MIPS_CPU_EBASE_WG;
905 write_c0_ebase(ebase);
906 }
907 }
908 }
909
ebd0e0f5
PB		 910 /* configure the FTLB write probability */
911 set_ftlb_enable(c, (mips_ftlb_disabled ? 0 : FTLB_EN) | FTLB_SET_PROB);
912
2fa36399
KC		 913 mips_probe_watch_registers(c);
914
0ee958e1 915#ifndef CONFIG_MIPS_CPS
8b8aa636 916 if (cpu_has_mips_r2_r6) {
45b585c8 917 c->core = get_ebase_cpunum();
30ee615b
PB		 918 if (cpu_has_mipsmt)
919 c->core >>= fls(core_nvpes()) - 1;
920 }
0ee958e1 921#endif
2fa36399
KC		 922}
923
6ad816e7
JH		 924/*
925 * Probe for certain guest capabilities by writing config bits and reading back.
926 * Finally write back the original value.
927 */
928#define probe_gc0_config(name, maxconf, bits) \
929do { \
930 unsigned int tmp; \
931 tmp = read_gc0_##name(); \
932 write_gc0_##name(tmp | (bits)); \
933 back_to_back_c0_hazard(); \
934 maxconf = read_gc0_##name(); \
935 write_gc0_##name(tmp); \
936} while (0)
937
938/*
939 * Probe for dynamic guest capabilities by changing certain config bits and
940 * reading back to see if they change. Finally write back the original value.
941 */
942#define probe_gc0_config_dyn(name, maxconf, dynconf, bits) \
943do { \
944 maxconf = read_gc0_##name(); \
945 write_gc0_##name(maxconf ^ (bits)); \
946 back_to_back_c0_hazard(); \
947 dynconf = maxconf ^ read_gc0_##name(); \
948 write_gc0_##name(maxconf); \
949 maxconf |= dynconf; \
950} while (0)
951
952static inline unsigned int decode_guest_config0(struct cpuinfo_mips *c)
953{
954 unsigned int config0;
955
956 probe_gc0_config(config, config0, MIPS_CONF_M);
957
958 if (config0 & MIPS_CONF_M)
959 c->guest.conf |= BIT(1);
960 return config0 & MIPS_CONF_M;
961}
962
963static inline unsigned int decode_guest_config1(struct cpuinfo_mips *c)
964{
965 unsigned int config1, config1_dyn;
966
967 probe_gc0_config_dyn(config1, config1, config1_dyn,
968 MIPS_CONF_M | MIPS_CONF1_PC | MIPS_CONF1_WR |
969 MIPS_CONF1_FP);
970
971 if (config1 & MIPS_CONF1_FP)
972 c->guest.options |= MIPS_CPU_FPU;
973 if (config1_dyn & MIPS_CONF1_FP)
974 c->guest.options_dyn |= MIPS_CPU_FPU;
975
976 if (config1 & MIPS_CONF1_WR)
977 c->guest.options |= MIPS_CPU_WATCH;
978 if (config1_dyn & MIPS_CONF1_WR)
979 c->guest.options_dyn |= MIPS_CPU_WATCH;
980
981 if (config1 & MIPS_CONF1_PC)
982 c->guest.options |= MIPS_CPU_PERF;
983 if (config1_dyn & MIPS_CONF1_PC)
984 c->guest.options_dyn |= MIPS_CPU_PERF;
985
986 if (config1 & MIPS_CONF_M)
987 c->guest.conf |= BIT(2);
988 return config1 & MIPS_CONF_M;
989}
990
991static inline unsigned int decode_guest_config2(struct cpuinfo_mips *c)
992{
993 unsigned int config2;
994
995 probe_gc0_config(config2, config2, MIPS_CONF_M);
996
997 if (config2 & MIPS_CONF_M)
998 c->guest.conf |= BIT(3);
999 return config2 & MIPS_CONF_M;
1000}
1001
1002static inline unsigned int decode_guest_config3(struct cpuinfo_mips *c)
1003{
1004 unsigned int config3, config3_dyn;
1005
1006 probe_gc0_config_dyn(config3, config3, config3_dyn,
1007 MIPS_CONF_M | MIPS_CONF3_MSA | MIPS_CONF3_CTXTC);
1008
1009 if (config3 & MIPS_CONF3_CTXTC)
1010 c->guest.options |= MIPS_CPU_CTXTC;
1011 if (config3_dyn & MIPS_CONF3_CTXTC)
1012 c->guest.options_dyn |= MIPS_CPU_CTXTC;
1013
1014 if (config3 & MIPS_CONF3_PW)
1015 c->guest.options |= MIPS_CPU_HTW;
1016
1017 if (config3 & MIPS_CONF3_SC)
1018 c->guest.options |= MIPS_CPU_SEGMENTS;
1019
1020 if (config3 & MIPS_CONF3_BI)
1021 c->guest.options |= MIPS_CPU_BADINSTR;
1022 if (config3 & MIPS_CONF3_BP)
1023 c->guest.options |= MIPS_CPU_BADINSTRP;
1024
1025 if (config3 & MIPS_CONF3_MSA)
1026 c->guest.ases |= MIPS_ASE_MSA;
1027 if (config3_dyn & MIPS_CONF3_MSA)
1028 c->guest.ases_dyn |= MIPS_ASE_MSA;
1029
1030 if (config3 & MIPS_CONF_M)
1031 c->guest.conf |= BIT(4);
1032 return config3 & MIPS_CONF_M;
1033}
1034
1035static inline unsigned int decode_guest_config4(struct cpuinfo_mips *c)
1036{
1037 unsigned int config4;
1038
1039 probe_gc0_config(config4, config4,
1040 MIPS_CONF_M | MIPS_CONF4_KSCREXIST);
1041
1042 c->guest.kscratch_mask = (config4 & MIPS_CONF4_KSCREXIST)
1043 >> MIPS_CONF4_KSCREXIST_SHIFT;
1044
1045 if (config4 & MIPS_CONF_M)
1046 c->guest.conf |= BIT(5);
1047 return config4 & MIPS_CONF_M;
1048}
1049
1050static inline unsigned int decode_guest_config5(struct cpuinfo_mips *c)
1051{
1052 unsigned int config5, config5_dyn;
1053
1054 probe_gc0_config_dyn(config5, config5, config5_dyn,
1055 MIPS_CONF_M | MIPS_CONF5_MRP);
1056
1057 if (config5 & MIPS_CONF5_MRP)
1058 c->guest.options |= MIPS_CPU_MAAR;
1059 if (config5_dyn & MIPS_CONF5_MRP)
1060 c->guest.options_dyn |= MIPS_CPU_MAAR;
1061
1062 if (config5 & MIPS_CONF5_LLB)
1063 c->guest.options |= MIPS_CPU_RW_LLB;
1064
1065 if (config5 & MIPS_CONF_M)
1066 c->guest.conf |= BIT(6);
1067 return config5 & MIPS_CONF_M;
1068}
1069
1070static inline void decode_guest_configs(struct cpuinfo_mips *c)
1071{
1072 unsigned int ok;
1073
1074 ok = decode_guest_config0(c);
1075 if (ok)
1076 ok = decode_guest_config1(c);
1077 if (ok)
1078 ok = decode_guest_config2(c);
1079 if (ok)
1080 ok = decode_guest_config3(c);
1081 if (ok)
1082 ok = decode_guest_config4(c);
1083 if (ok)
1084 decode_guest_config5(c);
1085}
1086
1087static inline void cpu_probe_guestctl0(struct cpuinfo_mips *c)
1088{
1089 unsigned int guestctl0, temp;
1090
1091 guestctl0 = read_c0_guestctl0();
1092
1093 if (guestctl0 & MIPS_GCTL0_G0E)
1094 c->options |= MIPS_CPU_GUESTCTL0EXT;
1095 if (guestctl0 & MIPS_GCTL0_G1)
1096 c->options |= MIPS_CPU_GUESTCTL1;
1097 if (guestctl0 & MIPS_GCTL0_G2)
1098 c->options |= MIPS_CPU_GUESTCTL2;
1099 if (!(guestctl0 & MIPS_GCTL0_RAD)) {
1100 c->options |= MIPS_CPU_GUESTID;
1101
1102 /*
1103 * Probe for Direct Root to Guest (DRG). Set GuestCtl1.RID = 0
1104 * first, otherwise all data accesses will be fully virtualised
1105 * as if they were performed by guest mode.
1106 */
1107 write_c0_guestctl1(0);
1108 tlbw_use_hazard();
1109
1110 write_c0_guestctl0(guestctl0 | MIPS_GCTL0_DRG);
1111 back_to_back_c0_hazard();
1112 temp = read_c0_guestctl0();
1113
1114 if (temp & MIPS_GCTL0_DRG) {
1115 write_c0_guestctl0(guestctl0);
1116 c->options |= MIPS_CPU_DRG;
1117 }
1118 }
1119}
1120
1121static inline void cpu_probe_guestctl1(struct cpuinfo_mips *c)
1122{
1123 if (cpu_has_guestid) {
1124 /* determine the number of bits of GuestID available */
1125 write_c0_guestctl1(MIPS_GCTL1_ID);
1126 back_to_back_c0_hazard();
1127 c->guestid_mask = (read_c0_guestctl1() & MIPS_GCTL1_ID)
1128 >> MIPS_GCTL1_ID_SHIFT;
1129 write_c0_guestctl1(0);
1130 }
1131}
1132
1133static inline void cpu_probe_gtoffset(struct cpuinfo_mips *c)
1134{
1135 /* determine the number of bits of GTOffset available */
1136 write_c0_gtoffset(0xffffffff);
1137 back_to_back_c0_hazard();
1138 c->gtoffset_mask = read_c0_gtoffset();
1139 write_c0_gtoffset(0);
1140}
1141
1142static inline void cpu_probe_vz(struct cpuinfo_mips *c)
1143{
1144 cpu_probe_guestctl0(c);
1145 if (cpu_has_guestctl1)
1146 cpu_probe_guestctl1(c);
1147
1148 cpu_probe_gtoffset(c);
1149
1150 decode_guest_configs(c);
1151}
1152
02cf2119 1153#define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
1da177e4
LT		 1154 | MIPS_CPU_COUNTER)
1155
cea7e2df 1156static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4 1157{
8ff374b9 1158 switch (c->processor_id & PRID_IMP_MASK) {
1da177e4
LT		 1159 case PRID_IMP_R2000:
1160 c->cputype = CPU_R2000;
cea7e2df 1161 __cpu_name[cpu] = "R2000";
9b26616c 1162 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
02cf2119 1163 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
03751e79 1164 MIPS_CPU_NOFPUEX;
1da177e4
LT		 1165 if (__cpu_has_fpu())
1166 c->options |= MIPS_CPU_FPU;
1167 c->tlbsize = 64;
1168 break;
1169 case PRID_IMP_R3000:
8ff374b9 1170 if ((c->processor_id & PRID_REV_MASK) == PRID_REV_R3000A) {
cea7e2df 1171 if (cpu_has_confreg()) {
1da177e4 1172 c->cputype = CPU_R3081E;
cea7e2df
RB		 1173 __cpu_name[cpu] = "R3081";
1174 } else {
1da177e4 1175 c->cputype = CPU_R3000A;
cea7e2df
RB		 1176 __cpu_name[cpu] = "R3000A";
1177 }
cea7e2df 1178 } else {
1da177e4 1179 c->cputype = CPU_R3000;
cea7e2df
RB		 1180 __cpu_name[cpu] = "R3000";
1181 }
9b26616c 1182 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
02cf2119 1183 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
03751e79 1184 MIPS_CPU_NOFPUEX;
1da177e4
LT		 1185 if (__cpu_has_fpu())
1186 c->options |= MIPS_CPU_FPU;
1187 c->tlbsize = 64;
1188 break;
1189 case PRID_IMP_R4000:
1190 if (read_c0_config() & CONF_SC) {
8ff374b9
MR		 1191 if ((c->processor_id & PRID_REV_MASK) >=
1192 PRID_REV_R4400) {
1da177e4 1193 c->cputype = CPU_R4400PC;
cea7e2df
RB		 1194 __cpu_name[cpu] = "R4400PC";
1195 } else {
1da177e4 1196 c->cputype = CPU_R4000PC;
cea7e2df
RB		 1197 __cpu_name[cpu] = "R4000PC";
1198 }
1da177e4 1199 } else {
7f177a52
MR		 1200 int cca = read_c0_config() & CONF_CM_CMASK;
1201 int mc;
1202
1203 /*
1204 * SC and MC versions can't be reliably told apart,
1205 * but only the latter support coherent caching
1206 * modes so assume the firmware has set the KSEG0
1207 * coherency attribute reasonably (if uncached, we
1208 * assume SC).
1209 */
1210 switch (cca) {
1211 case CONF_CM_CACHABLE_CE:
1212 case CONF_CM_CACHABLE_COW:
1213 case CONF_CM_CACHABLE_CUW:
1214 mc = 1;
1215 break;
1216 default:
1217 mc = 0;
1218 break;
1219 }
8ff374b9
MR		 1220 if ((c->processor_id & PRID_REV_MASK) >=
1221 PRID_REV_R4400) {
7f177a52
MR		 1222 c->cputype = mc ? CPU_R4400MC : CPU_R4400SC;
1223 __cpu_name[cpu] = mc ? "R4400MC" : "R4400SC";
cea7e2df 1224 } else {
7f177a52
MR		 1225 c->cputype = mc ? CPU_R4000MC : CPU_R4000SC;
1226 __cpu_name[cpu] = mc ? "R4000MC" : "R4000SC";
cea7e2df 1227 }
1da177e4
LT		 1228 }
1229
a96102be 1230 set_isa(c, MIPS_CPU_ISA_III);
9b26616c 1231 c->fpu_msk31 |= FPU_CSR_CONDX;
1da177e4 1232 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79
SH		 1233 MIPS_CPU_WATCH | MIPS_CPU_VCE |
1234 MIPS_CPU_LLSC;
1da177e4
LT		 1235 c->tlbsize = 48;
1236 break;
1237 case PRID_IMP_VR41XX:
9f91e506 1238 set_isa(c, MIPS_CPU_ISA_III);
9b26616c 1239 c->fpu_msk31 |= FPU_CSR_CONDX;
9f91e506
YY		 1240 c->options = R4K_OPTS;
1241 c->tlbsize = 32;
1da177e4 1242 switch (c->processor_id & 0xf0) {
1da177e4
LT		 1243 case PRID_REV_VR4111:
1244 c->cputype = CPU_VR4111;
cea7e2df 1245 __cpu_name[cpu] = "NEC VR4111";
1da177e4 1246 break;
1da177e4
LT		 1247 case PRID_REV_VR4121:
1248 c->cputype = CPU_VR4121;
cea7e2df 1249 __cpu_name[cpu] = "NEC VR4121";
1da177e4
LT		 1250 break;
1251 case PRID_REV_VR4122:
cea7e2df 1252 if ((c->processor_id & 0xf) < 0x3) {
1da177e4 1253 c->cputype = CPU_VR4122;
cea7e2df
RB		 1254 __cpu_name[cpu] = "NEC VR4122";
1255 } else {
1da177e4 1256 c->cputype = CPU_VR4181A;
cea7e2df
RB		 1257 __cpu_name[cpu] = "NEC VR4181A";
1258 }
1da177e4
LT		 1259 break;
1260 case PRID_REV_VR4130:
cea7e2df 1261 if ((c->processor_id & 0xf) < 0x4) {
1da177e4 1262 c->cputype = CPU_VR4131;
cea7e2df
RB		 1263 __cpu_name[cpu] = "NEC VR4131";
1264 } else {
1da177e4 1265 c->cputype = CPU_VR4133;
9f91e506 1266 c->options |= MIPS_CPU_LLSC;
cea7e2df
RB		 1267 __cpu_name[cpu] = "NEC VR4133";
1268 }
1da177e4
LT		 1269 break;
1270 default:
1271 printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
1272 c->cputype = CPU_VR41XX;
cea7e2df 1273 __cpu_name[cpu] = "NEC Vr41xx";
1da177e4
LT		 1274 break;
1275 }
1da177e4
LT		 1276 break;
1277 case PRID_IMP_R4300:
1278 c->cputype = CPU_R4300;
cea7e2df 1279 __cpu_name[cpu] = "R4300";
a96102be 1280 set_isa(c, MIPS_CPU_ISA_III);
9b26616c 1281 c->fpu_msk31 |= FPU_CSR_CONDX;
1da177e4 1282 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 1283 MIPS_CPU_LLSC;
1da177e4
LT		 1284 c->tlbsize = 32;
1285 break;
1286 case PRID_IMP_R4600:
1287 c->cputype = CPU_R4600;
cea7e2df 1288 __cpu_name[cpu] = "R4600";
a96102be 1289 set_isa(c, MIPS_CPU_ISA_III);
9b26616c 1290 c->fpu_msk31 |= FPU_CSR_CONDX;
075e7502
TS		 1291 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1292 MIPS_CPU_LLSC;
1da177e4
LT		 1293 c->tlbsize = 48;
1294 break;
1295 #if 0
03751e79 1296 case PRID_IMP_R4650:
1da177e4
LT		 1297 /*
1298 * This processor doesn't have an MMU, so it's not
1299 * "real easy" to run Linux on it. It is left purely
1300 * for documentation. Commented out because it shares
1301 * it's c0_prid id number with the TX3900.
1302 */
a3dddd56 1303 c->cputype = CPU_R4650;
cea7e2df 1304 __cpu_name[cpu] = "R4650";
a96102be 1305 set_isa(c, MIPS_CPU_ISA_III);
9b26616c 1306 c->fpu_msk31 |= FPU_CSR_CONDX;
1da177e4 1307 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
03751e79 1308 c->tlbsize = 48;
1da177e4
LT		 1309 break;
1310 #endif
1311 case PRID_IMP_TX39:
9b26616c 1312 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
02cf2119 1313 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE;
1da177e4
LT		 1314
1315 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
1316 c->cputype = CPU_TX3927;
cea7e2df 1317 __cpu_name[cpu] = "TX3927";
1da177e4
LT		 1318 c->tlbsize = 64;
1319 } else {
8ff374b9 1320 switch (c->processor_id & PRID_REV_MASK) {
1da177e4
LT		 1321 case PRID_REV_TX3912:
1322 c->cputype = CPU_TX3912;
cea7e2df 1323 __cpu_name[cpu] = "TX3912";
1da177e4
LT		 1324 c->tlbsize = 32;
1325 break;
1326 case PRID_REV_TX3922:
1327 c->cputype = CPU_TX3922;
cea7e2df 1328 __cpu_name[cpu] = "TX3922";
1da177e4
LT		 1329 c->tlbsize = 64;
1330 break;
1da177e4
LT		 1331 }
1332 }
1333 break;
1334 case PRID_IMP_R4700:
1335 c->cputype = CPU_R4700;
cea7e2df 1336 __cpu_name[cpu] = "R4700";
a96102be 1337 set_isa(c, MIPS_CPU_ISA_III);
9b26616c 1338 c->fpu_msk31 |= FPU_CSR_CONDX;
1da177e4 1339 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 1340 MIPS_CPU_LLSC;
1da177e4
LT		 1341 c->tlbsize = 48;
1342 break;
1343 case PRID_IMP_TX49:
1344 c->cputype = CPU_TX49XX;
cea7e2df 1345 __cpu_name[cpu] = "R49XX";
a96102be 1346 set_isa(c, MIPS_CPU_ISA_III);
9b26616c 1347 c->fpu_msk31 |= FPU_CSR_CONDX;
1da177e4
LT		 1348 c->options = R4K_OPTS | MIPS_CPU_LLSC;
1349 if (!(c->processor_id & 0x08))
1350 c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
1351 c->tlbsize = 48;
1352 break;
1353 case PRID_IMP_R5000:
1354 c->cputype = CPU_R5000;
cea7e2df 1355 __cpu_name[cpu] = "R5000";
a96102be 1356 set_isa(c, MIPS_CPU_ISA_IV);
1da177e4 1357 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 1358 MIPS_CPU_LLSC;
1da177e4
LT		 1359 c->tlbsize = 48;
1360 break;
1361 case PRID_IMP_R5432:
1362 c->cputype = CPU_R5432;
cea7e2df 1363 __cpu_name[cpu] = "R5432";
a96102be 1364 set_isa(c, MIPS_CPU_ISA_IV);
1da177e4 1365 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 1366 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
1da177e4
LT		 1367 c->tlbsize = 48;
1368 break;
1369 case PRID_IMP_R5500:
1370 c->cputype = CPU_R5500;
cea7e2df 1371 __cpu_name[cpu] = "R5500";
a96102be 1372 set_isa(c, MIPS_CPU_ISA_IV);
1da177e4 1373 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 1374 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
1da177e4
LT		 1375 c->tlbsize = 48;
1376 break;
1377 case PRID_IMP_NEVADA:
1378 c->cputype = CPU_NEVADA;
cea7e2df 1379 __cpu_name[cpu] = "Nevada";
a96102be 1380 set_isa(c, MIPS_CPU_ISA_IV);
1da177e4 1381 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 1382 MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
1da177e4
LT		 1383 c->tlbsize = 48;
1384 break;
1385 case PRID_IMP_R6000:
1386 c->cputype = CPU_R6000;
cea7e2df 1387 __cpu_name[cpu] = "R6000";
a96102be 1388 set_isa(c, MIPS_CPU_ISA_II);
9b26616c 1389 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
1da177e4 1390 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
03751e79 1391 MIPS_CPU_LLSC;
1da177e4
LT		 1392 c->tlbsize = 32;
1393 break;
1394 case PRID_IMP_R6000A:
1395 c->cputype = CPU_R6000A;
cea7e2df 1396 __cpu_name[cpu] = "R6000A";
a96102be 1397 set_isa(c, MIPS_CPU_ISA_II);
9b26616c 1398 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
1da177e4 1399 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
03751e79 1400 MIPS_CPU_LLSC;
1da177e4
LT		 1401 c->tlbsize = 32;
1402 break;
1403 case PRID_IMP_RM7000:
1404 c->cputype = CPU_RM7000;
cea7e2df 1405 __cpu_name[cpu] = "RM7000";
a96102be 1406 set_isa(c, MIPS_CPU_ISA_IV);
1da177e4 1407 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 1408 MIPS_CPU_LLSC;
1da177e4 1409 /*
70342287 1410 * Undocumented RM7000: Bit 29 in the info register of
1da177e4
LT		 1411 * the RM7000 v2.0 indicates if the TLB has 48 or 64
1412 * entries.
1413 *
70342287
RB		 1414 * 29 1 => 64 entry JTLB
1415 * 0 => 48 entry JTLB
1da177e4
LT		 1416 */
1417 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
1da177e4
LT		 1418 break;
1419 case PRID_IMP_R8000:
1420 c->cputype = CPU_R8000;
cea7e2df 1421 __cpu_name[cpu] = "RM8000";
a96102be 1422 set_isa(c, MIPS_CPU_ISA_IV);
1da177e4 1423 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
03751e79
SH		 1424 MIPS_CPU_FPU | MIPS_CPU_32FPR |
1425 MIPS_CPU_LLSC;
1da177e4
LT		 1426 c->tlbsize = 384; /* has weird TLB: 3-way x 128 */
1427 break;
1428 case PRID_IMP_R10000:
1429 c->cputype = CPU_R10000;
cea7e2df 1430 __cpu_name[cpu] = "R10000";
a96102be 1431 set_isa(c, MIPS_CPU_ISA_IV);
8b36612a 1432 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
03751e79 1433 MIPS_CPU_FPU | MIPS_CPU_32FPR |
1da177e4 1434 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
03751e79 1435 MIPS_CPU_LLSC;
1da177e4
LT		 1436 c->tlbsize = 64;
1437 break;
1438 case PRID_IMP_R12000:
1439 c->cputype = CPU_R12000;
cea7e2df 1440 __cpu_name[cpu] = "R12000";
a96102be 1441 set_isa(c, MIPS_CPU_ISA_IV);
8b36612a 1442 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
03751e79 1443 MIPS_CPU_FPU | MIPS_CPU_32FPR |
1da177e4 1444 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
8d5ded16 1445 MIPS_CPU_LLSC | MIPS_CPU_BP_GHIST;
1da177e4
LT		 1446 c->tlbsize = 64;
1447 break;
44d921b2 1448 case PRID_IMP_R14000:
30577391
JK		 1449 if (((c->processor_id >> 4) & 0x0f) > 2) {
1450 c->cputype = CPU_R16000;
1451 __cpu_name[cpu] = "R16000";
1452 } else {
1453 c->cputype = CPU_R14000;
1454 __cpu_name[cpu] = "R14000";
1455 }
a96102be 1456 set_isa(c, MIPS_CPU_ISA_IV);
44d921b2 1457 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
03751e79 1458 MIPS_CPU_FPU | MIPS_CPU_32FPR |
44d921b2 1459 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
8d5ded16 1460 MIPS_CPU_LLSC | MIPS_CPU_BP_GHIST;
44d921b2
K		 1461 c->tlbsize = 64;
1462 break;
26859198 1463 case PRID_IMP_LOONGSON_64: /* Loongson-2/3 */
5aac1e8a
RM		 1464 switch (c->processor_id & PRID_REV_MASK) {
1465 case PRID_REV_LOONGSON2E:
c579d310
HC		 1466 c->cputype = CPU_LOONGSON2;
1467 __cpu_name[cpu] = "ICT Loongson-2";
5aac1e8a 1468 set_elf_platform(cpu, "loongson2e");
7352c8b1 1469 set_isa(c, MIPS_CPU_ISA_III);
9b26616c 1470 c->fpu_msk31 |= FPU_CSR_CONDX;
5aac1e8a
RM		 1471 break;
1472 case PRID_REV_LOONGSON2F:
c579d310
HC		 1473 c->cputype = CPU_LOONGSON2;
1474 __cpu_name[cpu] = "ICT Loongson-2";
5aac1e8a 1475 set_elf_platform(cpu, "loongson2f");
7352c8b1 1476 set_isa(c, MIPS_CPU_ISA_III);
9b26616c 1477 c->fpu_msk31 |= FPU_CSR_CONDX;
5aac1e8a 1478 break;
b2edcfc8 1479 case PRID_REV_LOONGSON3A_R1:
c579d310
HC		 1480 c->cputype = CPU_LOONGSON3;
1481 __cpu_name[cpu] = "ICT Loongson-3";
1482 set_elf_platform(cpu, "loongson3a");
7352c8b1 1483 set_isa(c, MIPS_CPU_ISA_M64R1);
c579d310 1484 break;
e7841be5
HC		 1485 case PRID_REV_LOONGSON3B_R1:
1486 case PRID_REV_LOONGSON3B_R2:
1487 c->cputype = CPU_LOONGSON3;
1488 __cpu_name[cpu] = "ICT Loongson-3";
1489 set_elf_platform(cpu, "loongson3b");
7352c8b1 1490 set_isa(c, MIPS_CPU_ISA_M64R1);
e7841be5 1491 break;
5aac1e8a
RM		 1492 }
1493
2a21c730
FZ		 1494 c->options = R4K_OPTS |
1495 MIPS_CPU_FPU | MIPS_CPU_LLSC |
1496 MIPS_CPU_32FPR;
1497 c->tlbsize = 64;
cc94ea31 1498 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
2a21c730 1499 break;
26859198 1500 case PRID_IMP_LOONGSON_32: /* Loongson-1 */
2fa36399 1501 decode_configs(c);
b4672d37 1502
2fa36399 1503 c->cputype = CPU_LOONGSON1;
1da177e4 1504
2fa36399
KC		 1505 switch (c->processor_id & PRID_REV_MASK) {
1506 case PRID_REV_LOONGSON1B:
1507 __cpu_name[cpu] = "Loongson 1B";
b4672d37 1508 break;
b4672d37 1509 }
4194318c 1510
2fa36399 1511 break;
1da177e4 1512 }
1da177e4
LT		 1513}
1514
cea7e2df 1515static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4 1516{
4f12b91d 1517 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
8ff374b9 1518 switch (c->processor_id & PRID_IMP_MASK) {
b2498af5
LY		 1519 case PRID_IMP_QEMU_GENERIC:
1520 c->writecombine = _CACHE_UNCACHED;
1521 c->cputype = CPU_QEMU_GENERIC;
1522 __cpu_name[cpu] = "MIPS GENERIC QEMU";
1523 break;
1da177e4
LT		 1524 case PRID_IMP_4KC:
1525 c->cputype = CPU_4KC;
4f12b91d 1526 c->writecombine = _CACHE_UNCACHED;
cea7e2df 1527 __cpu_name[cpu] = "MIPS 4Kc";
1da177e4
LT		 1528 break;
1529 case PRID_IMP_4KEC:
2b07bd02
RB		 1530 case PRID_IMP_4KECR2:
1531 c->cputype = CPU_4KEC;
4f12b91d 1532 c->writecombine = _CACHE_UNCACHED;
cea7e2df 1533 __cpu_name[cpu] = "MIPS 4KEc";
2b07bd02 1534 break;
1da177e4 1535 case PRID_IMP_4KSC:
8afcb5d8 1536 case PRID_IMP_4KSD:
1da177e4 1537 c->cputype = CPU_4KSC;
4f12b91d 1538 c->writecombine = _CACHE_UNCACHED;
cea7e2df 1539 __cpu_name[cpu] = "MIPS 4KSc";
1da177e4
LT		 1540 break;
1541 case PRID_IMP_5KC:
1542 c->cputype = CPU_5KC;
4f12b91d 1543 c->writecombine = _CACHE_UNCACHED;
cea7e2df 1544 __cpu_name[cpu] = "MIPS 5Kc";
1da177e4 1545 break;
78d4803f
LY		 1546 case PRID_IMP_5KE:
1547 c->cputype = CPU_5KE;
4f12b91d 1548 c->writecombine = _CACHE_UNCACHED;
78d4803f
LY		 1549 __cpu_name[cpu] = "MIPS 5KE";
1550 break;
1da177e4
LT		 1551 case PRID_IMP_20KC:
1552 c->cputype = CPU_20KC;
4f12b91d 1553 c->writecombine = _CACHE_UNCACHED;
cea7e2df 1554 __cpu_name[cpu] = "MIPS 20Kc";
1da177e4
LT		 1555 break;
1556 case PRID_IMP_24K:
1557 c->cputype = CPU_24K;
4f12b91d 1558 c->writecombine = _CACHE_UNCACHED;
cea7e2df 1559 __cpu_name[cpu] = "MIPS 24Kc";
1da177e4 1560 break;
42f3caef
JC		 1561 case PRID_IMP_24KE:
1562 c->cputype = CPU_24K;
4f12b91d 1563 c->writecombine = _CACHE_UNCACHED;
42f3caef
JC		 1564 __cpu_name[cpu] = "MIPS 24KEc";
1565 break;
1da177e4
LT		 1566 case PRID_IMP_25KF:
1567 c->cputype = CPU_25KF;
4f12b91d 1568 c->writecombine = _CACHE_UNCACHED;
cea7e2df 1569 __cpu_name[cpu] = "MIPS 25Kc";
1da177e4 1570 break;
bbc7f22f
RB		 1571 case PRID_IMP_34K:
1572 c->cputype = CPU_34K;
4f12b91d 1573 c->writecombine = _CACHE_UNCACHED;
cea7e2df 1574 __cpu_name[cpu] = "MIPS 34Kc";
bbc7f22f 1575 break;
c620953c
CD		 1576 case PRID_IMP_74K:
1577 c->cputype = CPU_74K;
4f12b91d 1578 c->writecombine = _CACHE_UNCACHED;
cea7e2df 1579 __cpu_name[cpu] = "MIPS 74Kc";
c620953c 1580 break;
113c62d9
SH		 1581 case PRID_IMP_M14KC:
1582 c->cputype = CPU_M14KC;
4f12b91d 1583 c->writecombine = _CACHE_UNCACHED;
113c62d9
SH		 1584 __cpu_name[cpu] = "MIPS M14Kc";
1585 break;
f8fa4811
SH		 1586 case PRID_IMP_M14KEC:
1587 c->cputype = CPU_M14KEC;
4f12b91d 1588 c->writecombine = _CACHE_UNCACHED;
f8fa4811
SH		 1589 __cpu_name[cpu] = "MIPS M14KEc";
1590 break;
39b8d525
RB		 1591 case PRID_IMP_1004K:
1592 c->cputype = CPU_1004K;
4f12b91d 1593 c->writecombine = _CACHE_UNCACHED;
cea7e2df 1594 __cpu_name[cpu] = "MIPS 1004Kc";
39b8d525 1595 break;
006a851b 1596 case PRID_IMP_1074K:
442e14a2 1597 c->cputype = CPU_1074K;
4f12b91d 1598 c->writecombine = _CACHE_UNCACHED;
006a851b
SH		 1599 __cpu_name[cpu] = "MIPS 1074Kc";
1600 break;
b5f065e7
LY		 1601 case PRID_IMP_INTERAPTIV_UP:
1602 c->cputype = CPU_INTERAPTIV;
1603 __cpu_name[cpu] = "MIPS interAptiv";
1604 break;
1605 case PRID_IMP_INTERAPTIV_MP:
1606 c->cputype = CPU_INTERAPTIV;
1607 __cpu_name[cpu] = "MIPS interAptiv (multi)";
1608 break;
b0d4d300
LY		 1609 case PRID_IMP_PROAPTIV_UP:
1610 c->cputype = CPU_PROAPTIV;
1611 __cpu_name[cpu] = "MIPS proAptiv";
1612 break;
1613 case PRID_IMP_PROAPTIV_MP:
1614 c->cputype = CPU_PROAPTIV;
1615 __cpu_name[cpu] = "MIPS proAptiv (multi)";
1616 break;
829dcc0a
JH		 1617 case PRID_IMP_P5600:
1618 c->cputype = CPU_P5600;
1619 __cpu_name[cpu] = "MIPS P5600";
1620 break;
eba20a3a
PB		 1621 case PRID_IMP_P6600:
1622 c->cputype = CPU_P6600;
1623 __cpu_name[cpu] = "MIPS P6600";
1624 break;
e57f9a2d
MC		 1625 case PRID_IMP_I6400:
1626 c->cputype = CPU_I6400;
1627 __cpu_name[cpu] = "MIPS I6400";
1628 break;
9943ed92
LY		 1629 case PRID_IMP_M5150:
1630 c->cputype = CPU_M5150;
1631 __cpu_name[cpu] = "MIPS M5150";
1632 break;
43aff742
PB		 1633 case PRID_IMP_M6250:
1634 c->cputype = CPU_M6250;
1635 __cpu_name[cpu] = "MIPS M6250";
1636 break;
1da177e4 1637 }
0b6d497f 1638
75b5b5e0
LY		 1639 decode_configs(c);
1640
0b6d497f 1641 spram_config();
1da177e4
LT		 1642}
1643
cea7e2df 1644static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4 1645{
4194318c 1646 decode_configs(c);
8ff374b9 1647 switch (c->processor_id & PRID_IMP_MASK) {
1da177e4
LT		 1648 case PRID_IMP_AU1_REV1:
1649 case PRID_IMP_AU1_REV2:
270717a8 1650 c->cputype = CPU_ALCHEMY;
1da177e4
LT		 1651 switch ((c->processor_id >> 24) & 0xff) {
1652 case 0:
cea7e2df 1653 __cpu_name[cpu] = "Au1000";
1da177e4
LT		 1654 break;
1655 case 1:
cea7e2df 1656 __cpu_name[cpu] = "Au1500";
1da177e4
LT		 1657 break;
1658 case 2:
cea7e2df 1659 __cpu_name[cpu] = "Au1100";
1da177e4
LT		 1660 break;
1661 case 3:
cea7e2df 1662 __cpu_name[cpu] = "Au1550";
1da177e4 1663 break;
e3ad1c23 1664 case 4:
cea7e2df 1665 __cpu_name[cpu] = "Au1200";
8ff374b9 1666 if ((c->processor_id & PRID_REV_MASK) == 2)
cea7e2df 1667 __cpu_name[cpu] = "Au1250";
237cfee1
ML		 1668 break;
1669 case 5:
cea7e2df 1670 __cpu_name[cpu] = "Au1210";
e3ad1c23 1671 break;
1da177e4 1672 default:
270717a8 1673 __cpu_name[cpu] = "Au1xxx";
1da177e4
LT		 1674 break;
1675 }
1da177e4
LT		 1676 break;
1677 }
1678}
1679
cea7e2df 1680static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4 1681{
4194318c 1682 decode_configs(c);
02cf2119 1683
4f12b91d 1684 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
8ff374b9 1685 switch (c->processor_id & PRID_IMP_MASK) {
1da177e4
LT		 1686 case PRID_IMP_SB1:
1687 c->cputype = CPU_SB1;
cea7e2df 1688 __cpu_name[cpu] = "SiByte SB1";
1da177e4 1689 /* FPU in pass1 is known to have issues. */
8ff374b9 1690 if ((c->processor_id & PRID_REV_MASK) < 0x02)
010b853b 1691 c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
1da177e4 1692 break;
93ce2f52
AI		 1693 case PRID_IMP_SB1A:
1694 c->cputype = CPU_SB1A;
cea7e2df 1695 __cpu_name[cpu] = "SiByte SB1A";
93ce2f52 1696 break;
1da177e4
LT		 1697 }
1698}
1699
cea7e2df 1700static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4 1701{
4194318c 1702 decode_configs(c);
8ff374b9 1703 switch (c->processor_id & PRID_IMP_MASK) {
1da177e4
LT		 1704 case PRID_IMP_SR71000:
1705 c->cputype = CPU_SR71000;
cea7e2df 1706 __cpu_name[cpu] = "Sandcraft SR71000";
1da177e4
LT		 1707 c->scache.ways = 8;
1708 c->tlbsize = 64;
1709 break;
1710 }
1711}
1712
cea7e2df 1713static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu)
bdf21b18
PP		 1714{
1715 decode_configs(c);
8ff374b9 1716 switch (c->processor_id & PRID_IMP_MASK) {
bdf21b18
PP		 1717 case PRID_IMP_PR4450:
1718 c->cputype = CPU_PR4450;
cea7e2df 1719 __cpu_name[cpu] = "Philips PR4450";
a96102be 1720 set_isa(c, MIPS_CPU_ISA_M32R1);
bdf21b18 1721 break;
bdf21b18
PP		 1722 }
1723}
1724
cea7e2df 1725static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
1c0c13eb
AJ		 1726{
1727 decode_configs(c);
8ff374b9 1728 switch (c->processor_id & PRID_IMP_MASK) {
190fca3e
KC		 1729 case PRID_IMP_BMIPS32_REV4:
1730 case PRID_IMP_BMIPS32_REV8:
602977b0
KC		 1731 c->cputype = CPU_BMIPS32;
1732 __cpu_name[cpu] = "Broadcom BMIPS32";
06785df0 1733 set_elf_platform(cpu, "bmips32");
602977b0
KC		 1734 break;
1735 case PRID_IMP_BMIPS3300:
1736 case PRID_IMP_BMIPS3300_ALT:
1737 case PRID_IMP_BMIPS3300_BUG:
1738 c->cputype = CPU_BMIPS3300;
1739 __cpu_name[cpu] = "Broadcom BMIPS3300";
06785df0 1740 set_elf_platform(cpu, "bmips3300");
602977b0
KC		 1741 break;
1742 case PRID_IMP_BMIPS43XX: {
8ff374b9 1743 int rev = c->processor_id & PRID_REV_MASK;
602977b0
KC		 1744
1745 if (rev >= PRID_REV_BMIPS4380_LO &&
1746 rev <= PRID_REV_BMIPS4380_HI) {
1747 c->cputype = CPU_BMIPS4380;
1748 __cpu_name[cpu] = "Broadcom BMIPS4380";
06785df0 1749 set_elf_platform(cpu, "bmips4380");
b4720809 1750 c->options |= MIPS_CPU_RIXI;
602977b0
KC		 1751 } else {
1752 c->cputype = CPU_BMIPS4350;
1753 __cpu_name[cpu] = "Broadcom BMIPS4350";
06785df0 1754 set_elf_platform(cpu, "bmips4350");
602977b0 1755 }
0de663ef 1756 break;
602977b0
KC		 1757 }
1758 case PRID_IMP_BMIPS5000:
68e6a783 1759 case PRID_IMP_BMIPS5200:
602977b0 1760 c->cputype = CPU_BMIPS5000;
37808d62
FF		 1761 if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_BMIPS5200)
1762 __cpu_name[cpu] = "Broadcom BMIPS5200";
1763 else
1764 __cpu_name[cpu] = "Broadcom BMIPS5000";
06785df0 1765 set_elf_platform(cpu, "bmips5000");
b4720809 1766 c->options |= MIPS_CPU_ULRI | MIPS_CPU_RIXI;
0de663ef 1767 break;
1c0c13eb
AJ		 1768 }
1769}
1770
0dd4781b
DD		 1771static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu)
1772{
1773 decode_configs(c);
8ff374b9 1774 switch (c->processor_id & PRID_IMP_MASK) {
0dd4781b
DD		 1775 case PRID_IMP_CAVIUM_CN38XX:
1776 case PRID_IMP_CAVIUM_CN31XX:
1777 case PRID_IMP_CAVIUM_CN30XX:
6f329468
DD		 1778 c->cputype = CPU_CAVIUM_OCTEON;
1779 __cpu_name[cpu] = "Cavium Octeon";
1780 goto platform;
0dd4781b
DD		 1781 case PRID_IMP_CAVIUM_CN58XX:
1782 case PRID_IMP_CAVIUM_CN56XX:
1783 case PRID_IMP_CAVIUM_CN50XX:
1784 case PRID_IMP_CAVIUM_CN52XX:
6f329468
DD		 1785 c->cputype = CPU_CAVIUM_OCTEON_PLUS;
1786 __cpu_name[cpu] = "Cavium Octeon+";
1787platform:
c094c99e 1788 set_elf_platform(cpu, "octeon");
0dd4781b 1789 break;
a1431b61 1790 case PRID_IMP_CAVIUM_CN61XX:
0e56b385 1791 case PRID_IMP_CAVIUM_CN63XX:
a1431b61
DD		 1792 case PRID_IMP_CAVIUM_CN66XX:
1793 case PRID_IMP_CAVIUM_CN68XX:
af04bb85 1794 case PRID_IMP_CAVIUM_CNF71XX:
0e56b385
DD		 1795 c->cputype = CPU_CAVIUM_OCTEON2;
1796 __cpu_name[cpu] = "Cavium Octeon II";
c094c99e 1797 set_elf_platform(cpu, "octeon2");
0e56b385 1798 break;
af04bb85 1799 case PRID_IMP_CAVIUM_CN70XX:
b8c8f665
DD		 1800 case PRID_IMP_CAVIUM_CN73XX:
1801 case PRID_IMP_CAVIUM_CNF75XX:
af04bb85
DD		 1802 case PRID_IMP_CAVIUM_CN78XX:
1803 c->cputype = CPU_CAVIUM_OCTEON3;
1804 __cpu_name[cpu] = "Cavium Octeon III";
1805 set_elf_platform(cpu, "octeon3");
1806 break;
0dd4781b
DD		 1807 default:
1808 printk(KERN_INFO "Unknown Octeon chip!\n");
1809 c->cputype = CPU_UNKNOWN;
1810 break;
1811 }
1812}
1813
b2edcfc8
HC		 1814static inline void cpu_probe_loongson(struct cpuinfo_mips *c, unsigned int cpu)
1815{
1816 switch (c->processor_id & PRID_IMP_MASK) {
1817 case PRID_IMP_LOONGSON_64: /* Loongson-2/3 */
1818 switch (c->processor_id & PRID_REV_MASK) {
1819 case PRID_REV_LOONGSON3A_R2:
1820 c->cputype = CPU_LOONGSON3;
1821 __cpu_name[cpu] = "ICT Loongson-3";
1822 set_elf_platform(cpu, "loongson3a");
1823 set_isa(c, MIPS_CPU_ISA_M64R2);
1824 break;
1825 }
1826
1827 decode_configs(c);
380cd582 1828 c->options |= MIPS_CPU_TLBINV | MIPS_CPU_LDPTE;
b2edcfc8
HC		 1829 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1830 break;
1831 default:
1832 panic("Unknown Loongson Processor ID!");
1833 break;
1834 }
1835}
1836
83ccf69d
LPC		 1837static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
1838{
1839 decode_configs(c);
1840 /* JZRISC does not implement the CP0 counter. */
1841 c->options &= ~MIPS_CPU_COUNTER;
06947aaa 1842 BUG_ON(!__builtin_constant_p(cpu_has_counter) || cpu_has_counter);
8ff374b9 1843 switch (c->processor_id & PRID_IMP_MASK) {
83ccf69d
LPC		 1844 case PRID_IMP_JZRISC:
1845 c->cputype = CPU_JZRISC;
4f12b91d 1846 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
83ccf69d
LPC		 1847 __cpu_name[cpu] = "Ingenic JZRISC";
1848 break;
1849 default:
1850 panic("Unknown Ingenic Processor ID!");
1851 break;
1852 }
1853}
1854
a7117c6b
J		 1855static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu)
1856{
1857 decode_configs(c);
1858
8ff374b9 1859 if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_NETLOGIC_AU13XX) {
809f36c6
ML		 1860 c->cputype = CPU_ALCHEMY;
1861 __cpu_name[cpu] = "Au1300";
1862 /* following stuff is not for Alchemy */
1863 return;
1864 }
1865
70342287
RB		 1866 c->options = (MIPS_CPU_TLB |
1867 MIPS_CPU_4KEX |
a7117c6b 1868 MIPS_CPU_COUNTER |
70342287
RB		 1869 MIPS_CPU_DIVEC |
1870 MIPS_CPU_WATCH |
1871 MIPS_CPU_EJTAG |
a7117c6b
J		 1872 MIPS_CPU_LLSC);
1873
8ff374b9 1874 switch (c->processor_id & PRID_IMP_MASK) {
4ca86a2f 1875 case PRID_IMP_NETLOGIC_XLP2XX:
8907c55e 1876 case PRID_IMP_NETLOGIC_XLP9XX:
1c983986 1877 case PRID_IMP_NETLOGIC_XLP5XX:
4ca86a2f
J		 1878 c->cputype = CPU_XLP;
1879 __cpu_name[cpu] = "Broadcom XLPII";
1880 break;
1881
2aa54b20
J		 1882 case PRID_IMP_NETLOGIC_XLP8XX:
1883 case PRID_IMP_NETLOGIC_XLP3XX:
a3d4fb2d
J		 1884 c->cputype = CPU_XLP;
1885 __cpu_name[cpu] = "Netlogic XLP";
1886 break;
1887
a7117c6b
J		 1888 case PRID_IMP_NETLOGIC_XLR732:
1889 case PRID_IMP_NETLOGIC_XLR716:
1890 case PRID_IMP_NETLOGIC_XLR532:
1891 case PRID_IMP_NETLOGIC_XLR308:
1892 case PRID_IMP_NETLOGIC_XLR532C:
1893 case PRID_IMP_NETLOGIC_XLR516C:
1894 case PRID_IMP_NETLOGIC_XLR508C:
1895 case PRID_IMP_NETLOGIC_XLR308C:
1896 c->cputype = CPU_XLR;
1897 __cpu_name[cpu] = "Netlogic XLR";
1898 break;
1899
1900 case PRID_IMP_NETLOGIC_XLS608:
1901 case PRID_IMP_NETLOGIC_XLS408:
1902 case PRID_IMP_NETLOGIC_XLS404:
1903 case PRID_IMP_NETLOGIC_XLS208:
1904 case PRID_IMP_NETLOGIC_XLS204:
1905 case PRID_IMP_NETLOGIC_XLS108:
1906 case PRID_IMP_NETLOGIC_XLS104:
1907 case PRID_IMP_NETLOGIC_XLS616B:
1908 case PRID_IMP_NETLOGIC_XLS608B:
1909 case PRID_IMP_NETLOGIC_XLS416B:
1910 case PRID_IMP_NETLOGIC_XLS412B:
1911 case PRID_IMP_NETLOGIC_XLS408B:
1912 case PRID_IMP_NETLOGIC_XLS404B:
1913 c->cputype = CPU_XLR;
1914 __cpu_name[cpu] = "Netlogic XLS";
1915 break;
1916
1917 default:
a3d4fb2d 1918 pr_info("Unknown Netlogic chip id [%02x]!\n",
a7117c6b
J		 1919 c->processor_id);
1920 c->cputype = CPU_XLR;
1921 break;
1922 }
1923
a3d4fb2d 1924 if (c->cputype == CPU_XLP) {
a96102be 1925 set_isa(c, MIPS_CPU_ISA_M64R2);
a3d4fb2d
J		 1926 c->options |= (MIPS_CPU_FPU | MIPS_CPU_ULRI | MIPS_CPU_MCHECK);
1927 /* This will be updated again after all threads are woken up */
1928 c->tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1;
1929 } else {
a96102be 1930 set_isa(c, MIPS_CPU_ISA_M64R1);
a3d4fb2d
J		 1931 c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1;
1932 }
7777b939 1933 c->kscratch_mask = 0xf;
a7117c6b
J		 1934}
1935
949e51be
DD		 1936#ifdef CONFIG_64BIT
1937/* For use by uaccess.h */
1938u64 __ua_limit;
1939EXPORT_SYMBOL(__ua_limit);
1940#endif
1941
9966db25 1942const char *__cpu_name[NR_CPUS];
874fd3b5 1943const char *__elf_platform;
9966db25 1944
078a55fc 1945void cpu_probe(void)
1da177e4
LT		 1946{
1947 struct cpuinfo_mips *c = &current_cpu_data;
9966db25 1948 unsigned int cpu = smp_processor_id();
1da177e4 1949
70342287 1950 c->processor_id = PRID_IMP_UNKNOWN;
1da177e4
LT		 1951 c->fpu_id = FPIR_IMP_NONE;
1952 c->cputype = CPU_UNKNOWN;
4f12b91d 1953 c->writecombine = _CACHE_UNCACHED;
1da177e4 1954
9b26616c
MR		 1955 c->fpu_csr31 = FPU_CSR_RN;
1956 c->fpu_msk31 = FPU_CSR_RSVD | FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
1957
1da177e4 1958 c->processor_id = read_c0_prid();
8ff374b9 1959 switch (c->processor_id & PRID_COMP_MASK) {
1da177e4 1960 case PRID_COMP_LEGACY:
cea7e2df 1961 cpu_probe_legacy(c, cpu);
1da177e4
LT		 1962 break;
1963 case PRID_COMP_MIPS:
cea7e2df 1964 cpu_probe_mips(c, cpu);
1da177e4
LT		 1965 break;
1966 case PRID_COMP_ALCHEMY:
cea7e2df 1967 cpu_probe_alchemy(c, cpu);
1da177e4
LT		 1968 break;
1969 case PRID_COMP_SIBYTE:
cea7e2df 1970 cpu_probe_sibyte(c, cpu);
1da177e4 1971 break;
1c0c13eb 1972 case PRID_COMP_BROADCOM:
cea7e2df 1973 cpu_probe_broadcom(c, cpu);
1c0c13eb 1974 break;
1da177e4 1975 case PRID_COMP_SANDCRAFT:
cea7e2df 1976 cpu_probe_sandcraft(c, cpu);
1da177e4 1977 break;
a92b0588 1978 case PRID_COMP_NXP:
cea7e2df 1979 cpu_probe_nxp(c, cpu);
a3dddd56 1980 break;
0dd4781b
DD		 1981 case PRID_COMP_CAVIUM:
1982 cpu_probe_cavium(c, cpu);
1983 break;
b2edcfc8
HC		 1984 case PRID_COMP_LOONGSON:
1985 cpu_probe_loongson(c, cpu);
1986 break;
252617a4
PB		 1987 case PRID_COMP_INGENIC_D0:
1988 case PRID_COMP_INGENIC_D1:
1989 case PRID_COMP_INGENIC_E1:
83ccf69d
LPC		 1990 cpu_probe_ingenic(c, cpu);
1991 break;
a7117c6b
J		 1992 case PRID_COMP_NETLOGIC:
1993 cpu_probe_netlogic(c, cpu);
1994 break;
1da177e4 1995 }
dec8b1ca 1996
cea7e2df
RB		 1997 BUG_ON(!__cpu_name[cpu]);
1998 BUG_ON(c->cputype == CPU_UNKNOWN);
1999
dec8b1ca
FBH		 2000 /*
2001 * Platform code can force the cpu type to optimize code
2002 * generation. In that case be sure the cpu type is correctly
2003 * manually setup otherwise it could trigger some nasty bugs.
2004 */
2005 BUG_ON(current_cpu_type() != c->cputype);
2006
2e274768
FF		 2007 if (cpu_has_rixi) {
2008 /* Enable the RIXI exceptions */
2009 set_c0_pagegrain(PG_IEC);
2010 back_to_back_c0_hazard();
2011 /* Verify the IEC bit is set */
2012 if (read_c0_pagegrain() & PG_IEC)
2013 c->options |= MIPS_CPU_RIXIEX;
2014 }
2015
0103d23f
KC		 2016 if (mips_fpu_disabled)
2017 c->options &= ~MIPS_CPU_FPU;
2018
2019 if (mips_dsp_disabled)
ee80f7c7 2020 c->ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
0103d23f 2021
3d528b32
MC		 2022 if (mips_htw_disabled) {
2023 c->options &= ~MIPS_CPU_HTW;
2024 write_c0_pwctl(read_c0_pwctl() &
2025 ~(1 << MIPS_PWCTL_PWEN_SHIFT));
2026 }
2027
7aecd5ca
MR		 2028 if (c->options & MIPS_CPU_FPU)
2029 cpu_set_fpu_opts(c);
2030 else
2031 cpu_set_nofpu_opts(c);
9966db25 2032
8d5ded16
JK		 2033 if (cpu_has_bp_ghist)
2034 write_c0_r10k_diag(read_c0_r10k_diag() |
2035 R10K_DIAG_E_GHIST);
2036
8b8aa636 2037 if (cpu_has_mips_r2_r6) {
f6771dbb 2038 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
da4b62cd
AC		 2039 /* R2 has Performance Counter Interrupt indicator */
2040 c->options |= MIPS_CPU_PCI;
2041 }
f6771dbb
RB		 2042 else
2043 c->srsets = 1;
91dfc423 2044
4c063034
PB		 2045 if (cpu_has_mips_r6)
2046 elf_hwcap |= HWCAP_MIPS_R6;
2047
a8ad1367 2048 if (cpu_has_msa) {
a5e9a69e 2049 c->msa_id = cpu_get_msa_id();
a8ad1367
PB		 2050 WARN(c->msa_id & MSA_IR_WRPF,
2051 "Vector register partitioning unimplemented!");
3cc9fa7f 2052 elf_hwcap |= HWCAP_MIPS_MSA;
a8ad1367 2053 }
a5e9a69e 2054
6ad816e7
JH		 2055 if (cpu_has_vz)
2056 cpu_probe_vz(c);
2057
91dfc423 2058 cpu_probe_vmbits(c);
949e51be
DD		 2059
2060#ifdef CONFIG_64BIT
2061 if (cpu == 0)
2062 __ua_limit = ~((1ull << cpu_vmbits) - 1);
2063#endif
1da177e4
LT		 2064}
2065
078a55fc 2066void cpu_report(void)
1da177e4
LT		 2067{
2068 struct cpuinfo_mips *c = &current_cpu_data;
2069
d9f897c9
LY		 2070 pr_info("CPU%d revision is: %08x (%s)\n",
2071 smp_processor_id(), c->processor_id, cpu_name_string());
1da177e4 2072 if (c->options & MIPS_CPU_FPU)
9966db25 2073 printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id);
a5e9a69e
PB		 2074 if (cpu_has_msa)
2075 pr_info("MSA revision is: %08x\n", c->msa_id);
1da177e4 2076}
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