[mirror_ubuntu-artful-kernel.git] / arch / mips / kernel / head.S

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 1994, 1995 Waldorf Electronics
 * Written by Ralf Baechle and Andreas Busse
 * Copyright (C) 1994 - 99, 2003, 06 Ralf Baechle
 * Copyright (C) 1996 Paul M. Antoine
 * Modified for DECStation and hence R3000 support by Paul M. Antoine
 * Further modifications by David S. Miller and Harald Koerfgen
 * Copyright (C) 1999 Silicon Graphics, Inc.
 * Kevin Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
 * Copyright (C) 2000 MIPS Technologies, Inc.  All rights reserved.
 */
#include <linux/init.h>
#include <linux/threads.h>

#include <asm/addrspace.h>
#include <asm/asm.h>
#include <asm/asmmacro.h>
#include <asm/irqflags.h>
#include <asm/regdef.h>
#include <asm/mipsregs.h>
#include <asm/stackframe.h>

#include <kernel-entry-init.h>

	/*
	 * For the moment disable interrupts, mark the kernel mode and
	 * set ST0_KX so that the CPU does not spit fire when using
	 * 64-bit addresses.  A full initialization of the CPU's status
	 * register is done later in per_cpu_trap_init().
	 */
	.macro	setup_c0_status set clr
	.set	push
	mfc0	t0, CP0_STATUS
	or	t0, ST0_CU0|\set|0x1f|\clr
	xor	t0, 0x1f|\clr
	mtc0	t0, CP0_STATUS
	.set	noreorder
	sll	zero,3				# ehb
	.set	pop
	.endm

	.macro	setup_c0_status_pri
#ifdef CONFIG_64BIT
	setup_c0_status ST0_KX 0
#else
	setup_c0_status 0 0
#endif
	.endm

	.macro	setup_c0_status_sec
#ifdef CONFIG_64BIT
	setup_c0_status ST0_KX ST0_BEV
#else
	setup_c0_status 0 ST0_BEV
#endif
	.endm

#ifndef CONFIG_NO_EXCEPT_FILL
	/*
	 * Reserved space for exception handlers.
	 * Necessary for machines which link their kernels at KSEG0.
	 */
	.fill	0x400
#endif

EXPORT(_stext)

#ifdef CONFIG_BOOT_RAW
	/*
	 * Give us a fighting chance of running if execution beings at the
	 * kernel load address.	 This is needed because this platform does
	 * not have a ELF loader yet.
	 */
FEXPORT(__kernel_entry)
	j	kernel_entry
#endif

	__REF

NESTED(kernel_entry, 16, sp)			# kernel entry point

	kernel_entry_setup			# cpu specific setup

	setup_c0_status_pri

	/* We might not get launched at the address the kernel is linked to,
	   so we jump there.  */
	PTR_LA	t0, 0f
	jr	t0
0:

#ifdef CONFIG_USE_OF
#ifdef CONFIG_MIPS_RAW_APPENDED_DTB
	PTR_LA		t2, __appended_dtb

#ifdef CONFIG_CPU_BIG_ENDIAN
	li		t1, 0xd00dfeed
#else
	li		t1, 0xedfe0dd0
#endif
	lw		t0, (t2)
	beq		t0, t1, dtb_found
#endif
	li		t1, -2
	move		t2, a1
	beq		a0, t1, dtb_found

	li		t2, 0
dtb_found:
#endif
	PTR_LA		t0, __bss_start		# clear .bss
	LONG_S		zero, (t0)
	PTR_LA		t1, __bss_stop - LONGSIZE
1:
	PTR_ADDIU	t0, LONGSIZE
	LONG_S		zero, (t0)
	bne		t0, t1, 1b

	LONG_S		a0, fw_arg0		# firmware arguments
	LONG_S		a1, fw_arg1
	LONG_S		a2, fw_arg2
	LONG_S		a3, fw_arg3

#ifdef CONFIG_USE_OF
	LONG_S		t2, fw_passed_dtb
#endif

	MTC0		zero, CP0_CONTEXT	# clear context register
	PTR_LA		$28, init_thread_union
	/* Set the SP after an empty pt_regs.  */
	PTR_LI		sp, _THREAD_SIZE - 32 - PT_SIZE
	PTR_ADDU	sp, $28
	back_to_back_c0_hazard
	set_saved_sp	sp, t0, t1
	PTR_SUBU	sp, 4 * SZREG		# init stack pointer

#ifdef CONFIG_RELOCATABLE
	/* Copy kernel and apply the relocations */
	jal		relocate_kernel

	/* Repoint the sp into the new kernel image */
	PTR_LI		sp, _THREAD_SIZE - 32 - PT_SIZE
	PTR_ADDU	sp, $28
	set_saved_sp	sp, t0, t1
	PTR_SUBU	sp, 4 * SZREG		# init stack pointer

	/*
	 * relocate_kernel returns the entry point either
	 * in the relocated kernel or the original if for
	 * some reason relocation failed - jump there now
	 * with instruction hazard barrier because of the
	 * newly sync'd icache.
	 */
	jr.hb		v0
#else
	j		start_kernel
#endif
	END(kernel_entry)

#ifdef CONFIG_SMP
/*
 * SMP slave cpus entry point.	Board specific code for bootstrap calls this
 * function after setting up the stack and gp registers.
 */
NESTED(smp_bootstrap, 16, sp)
	smp_slave_setup
	setup_c0_status_sec
	j	start_secondary
	END(smp_bootstrap)
#endif /* CONFIG_SMP */
Commit	Line	Data
1da177e4 LT	1	/*
	2	* This file is subject to the terms and conditions of the GNU General Public
	3	* License. See the file "COPYING" in the main directory of this archive
	4	* for more details.
	5	*
	6	* Copyright (C) 1994, 1995 Waldorf Electronics
	7	* Written by Ralf Baechle and Andreas Busse
192ef366	8	* Copyright (C) 1994 - 99, 2003, 06 Ralf Baechle
1da177e4 LT	9	* Copyright (C) 1996 Paul M. Antoine
	10	* Modified for DECStation and hence R3000 support by Paul M. Antoine
	11	* Further modifications by David S. Miller and Harald Koerfgen
	12	* Copyright (C) 1999 Silicon Graphics, Inc.
	13	* Kevin Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
	14	* Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
	15	*/
1da177e4 LT	16	#include <linux/init.h>
	17	#include <linux/threads.h>
	18
9267a30d	19	#include <asm/addrspace.h>
1da177e4	20	#include <asm/asm.h>
41c594ab	21	#include <asm/asmmacro.h>
192ef366	22	#include <asm/irqflags.h>
1da177e4	23	#include <asm/regdef.h>
1da177e4 LT	24	#include <asm/mipsregs.h>
1da177e4 LT	25	#include <asm/stackframe.h>
7e35952b RB	26
7e35952b RB	27	#include <kernel-entry-init.h>
1da177e4	28
1da177e4 LT	29	/*
	30	* For the moment disable interrupts, mark the kernel mode and
	31	* set ST0_KX so that the CPU does not spit fire when using
	32	* 64-bit addresses. A full initialization of the CPU's status
	33	* register is done later in per_cpu_trap_init().
	34	*/
	35	.macro setup_c0_status set clr
	36	.set push
	37	mfc0 t0, CP0_STATUS
	38	or t0, ST0_CU0\|\set\|0x1f\|\clr
	39	xor t0, 0x1f\|\clr
	40	mtc0 t0, CP0_STATUS
	41	.set noreorder
	42	sll zero,3 # ehb
	43	.set pop
	44	.endm
	45
	46	.macro setup_c0_status_pri
875d43e7	47	#ifdef CONFIG_64BIT
1da177e4 LT	48	setup_c0_status ST0_KX 0
	49	#else
	50	setup_c0_status 0 0
	51	#endif
	52	.endm
	53
	54	.macro setup_c0_status_sec
875d43e7	55	#ifdef CONFIG_64BIT
1da177e4 LT	56	setup_c0_status ST0_KX ST0_BEV
	57	#else
	58	setup_c0_status 0 ST0_BEV
	59	#endif
	60	.endm
	61
9267a30d	62	#ifndef CONFIG_NO_EXCEPT_FILL
1da177e4 LT	63	/*
	64	* Reserved space for exception handlers.
	65	* Necessary for machines which link their kernels at KSEG0.
	66	*/
	67	.fill 0x400
9267a30d	68	#endif
1da177e4	69
1da177e4 LT	70	EXPORT(_stext)
1da177e4 LT	71
396a2ae0	72	#ifdef CONFIG_BOOT_RAW
b490ff42 RB	73	/*
b490ff42 RB	74	* Give us a fighting chance of running if execution beings at the
70342287	75	* kernel load address. This is needed because this platform does
b490ff42 RB	76	* not have a ELF loader yet.
b490ff42 RB	77	*/
ba820c5c RB	78	FEXPORT(__kernel_entry)
ba820c5c RB	79	j kernel_entry
f6e2373a	80	#endif
1da177e4	81
a055917e	82	__REF
396a2ae0	83
1da177e4	84	NESTED(kernel_entry, 16, sp) # kernel entry point
1da177e4	85
7e35952b RB	86	kernel_entry_setup # cpu specific setup
	87
	88	setup_c0_status_pri
1da177e4	89
15ad838d TB	90	/* We might not get launched at the address the kernel is linked to,
	91	so we jump there. */
	92	PTR_LA t0, 0f
	93	jr t0
	94	0:
1da177e4	95
15f37e15	96	#ifdef CONFIG_USE_OF
1da8f179	97	#ifdef CONFIG_MIPS_RAW_APPENDED_DTB
15f37e15	98	PTR_LA t2, __appended_dtb
1da8f179 JG	99
	100	#ifdef CONFIG_CPU_BIG_ENDIAN
	101	li t1, 0xd00dfeed
	102	#else
	103	li t1, 0xedfe0dd0
	104	#endif
15f37e15 JG	105	lw t0, (t2)
	106	beq t0, t1, dtb_found
	107	#endif
	108	li t1, -2
15f37e15	109	move t2, a1
25d8b92e	110	beq a0, t1, dtb_found
1da8f179	111
15f37e15 JG	112	li t2, 0
15f37e15 JG	113	dtb_found:
1da8f179	114	#endif
1da177e4 LT	115	PTR_LA t0, __bss_start # clear .bss
	116	LONG_S zero, (t0)
	117	PTR_LA t1, __bss_stop - LONGSIZE
	118	1:
	119	PTR_ADDIU t0, LONGSIZE
	120	LONG_S zero, (t0)
	121	bne t0, t1, 1b
	122
	123	LONG_S a0, fw_arg0 # firmware arguments
	124	LONG_S a1, fw_arg1
	125	LONG_S a2, fw_arg2
	126	LONG_S a3, fw_arg3
	127
15f37e15 JG	128	#ifdef CONFIG_USE_OF
	129	LONG_S t2, fw_passed_dtb
	130	#endif
	131
1b3a6e97	132	MTC0 zero, CP0_CONTEXT # clear context register
1da177e4	133	PTR_LA $28, init_thread_union
484889fc DD	134	/* Set the SP after an empty pt_regs. */
484889fc DD	135	PTR_LI sp, _THREAD_SIZE - 32 - PT_SIZE
242954b5	136	PTR_ADDU sp, $28
c2ea1d56	137	back_to_back_c0_hazard
1da177e4 LT	138	set_saved_sp sp, t0, t1
	139	PTR_SUBU sp, 4 * SZREG # init stack pointer
	140
af09ab5e MR	141	#ifdef CONFIG_RELOCATABLE
	142	/* Copy kernel and apply the relocations */
	143	jal relocate_kernel
	144
	145	/* Repoint the sp into the new kernel image */
	146	PTR_LI sp, _THREAD_SIZE - 32 - PT_SIZE
	147	PTR_ADDU sp, $28
	148	set_saved_sp sp, t0, t1
	149	PTR_SUBU sp, 4 * SZREG # init stack pointer
	150
	151	/*
	152	* relocate_kernel returns the entry point either
	153	* in the relocated kernel or the original if for
	154	* some reason relocation failed - jump there now
	155	* with instruction hazard barrier because of the
	156	* newly sync'd icache.
	157	*/
	158	jr.hb v0
	159	#else
1da177e4	160	j start_kernel
af09ab5e	161	#endif
1da177e4 LT	162	END(kernel_entry)
	163
	164	#ifdef CONFIG_SMP
	165	/*
70342287	166	* SMP slave cpus entry point. Board specific code for bootstrap calls this
1da177e4 LT	167	* function after setting up the stack and gp registers.
	168	*/
	169	NESTED(smp_bootstrap, 16, sp)
7e35952b	170	smp_slave_setup
d0ba3544	171	setup_c0_status_sec
1da177e4 LT	172	j start_secondary
	173	END(smp_bootstrap)
	174	#endif /* CONFIG_SMP */