[mirror_ubuntu-zesty-kernel.git] / arch / mips / kernel / i8259.c

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Code to handle x86 style IRQs plus some generic interrupt stuff.
 *
 * Copyright (C) 1992 Linus Torvalds
 * Copyright (C) 1994 - 2000 Ralf Baechle
 */
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/ioport.h>
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/spinlock.h>
#include <linux/sysdev.h>

#include <asm/i8259.h>
#include <asm/io.h>

/*
 * This is the 'legacy' 8259A Programmable Interrupt Controller,
 * present in the majority of PC/AT boxes.
 * plus some generic x86 specific things if generic specifics makes
 * any sense at all.
 * this file should become arch/i386/kernel/irq.c when the old irq.c
 * moves to arch independent land
 */

static int i8259A_auto_eoi = -1;
DEFINE_SPINLOCK(i8259A_lock);
static void disable_8259A_irq(unsigned int irq);
static void enable_8259A_irq(unsigned int irq);
static void mask_and_ack_8259A(unsigned int irq);
static void init_8259A(int auto_eoi);

static struct irq_chip i8259A_chip = {
	.name		= "XT-PIC",
	.mask		= disable_8259A_irq,
	.disable	= disable_8259A_irq,
	.unmask		= enable_8259A_irq,
	.mask_ack	= mask_and_ack_8259A,
#ifdef CONFIG_MIPS_MT_SMTC_IRQAFF
	.set_affinity	= plat_set_irq_affinity,
#endif /* CONFIG_MIPS_MT_SMTC_IRQAFF */
};

/*
 * 8259A PIC functions to handle ISA devices:
 */

/*
 * This contains the irq mask for both 8259A irq controllers,
 */
static unsigned int cached_irq_mask = 0xffff;

#define cached_master_mask	(cached_irq_mask)
#define cached_slave_mask	(cached_irq_mask >> 8)

static void disable_8259A_irq(unsigned int irq)
{
	unsigned int mask;
	unsigned long flags;

	irq -= I8259A_IRQ_BASE;
	mask = 1 << irq;
	spin_lock_irqsave(&i8259A_lock, flags);
	cached_irq_mask |= mask;
	if (irq & 8)
		outb(cached_slave_mask, PIC_SLAVE_IMR);
	else
		outb(cached_master_mask, PIC_MASTER_IMR);
	spin_unlock_irqrestore(&i8259A_lock, flags);
}

static void enable_8259A_irq(unsigned int irq)
{
	unsigned int mask;
	unsigned long flags;

	irq -= I8259A_IRQ_BASE;
	mask = ~(1 << irq);
	spin_lock_irqsave(&i8259A_lock, flags);
	cached_irq_mask &= mask;
	if (irq & 8)
		outb(cached_slave_mask, PIC_SLAVE_IMR);
	else
		outb(cached_master_mask, PIC_MASTER_IMR);
	spin_unlock_irqrestore(&i8259A_lock, flags);
}

int i8259A_irq_pending(unsigned int irq)
{
	unsigned int mask;
	unsigned long flags;
	int ret;

	irq -= I8259A_IRQ_BASE;
	mask = 1 << irq;
	spin_lock_irqsave(&i8259A_lock, flags);
	if (irq < 8)
		ret = inb(PIC_MASTER_CMD) & mask;
	else
		ret = inb(PIC_SLAVE_CMD) & (mask >> 8);
	spin_unlock_irqrestore(&i8259A_lock, flags);

	return ret;
}

void make_8259A_irq(unsigned int irq)
{
	disable_irq_nosync(irq);
	set_irq_chip_and_handler(irq, &i8259A_chip, handle_level_irq);
	enable_irq(irq);
}

/*
 * This function assumes to be called rarely. Switching between
 * 8259A registers is slow.
 * This has to be protected by the irq controller spinlock
 * before being called.
 */
static inline int i8259A_irq_real(unsigned int irq)
{
	int value;
	int irqmask = 1 << irq;

	if (irq < 8) {
		outb(0x0B, PIC_MASTER_CMD);	/* ISR register */
		value = inb(PIC_MASTER_CMD) & irqmask;
		outb(0x0A, PIC_MASTER_CMD);	/* back to the IRR register */
		return value;
	}
	outb(0x0B, PIC_SLAVE_CMD);	/* ISR register */
	value = inb(PIC_SLAVE_CMD) & (irqmask >> 8);
	outb(0x0A, PIC_SLAVE_CMD);	/* back to the IRR register */
	return value;
}

/*
 * Careful! The 8259A is a fragile beast, it pretty
 * much _has_ to be done exactly like this (mask it
 * first, _then_ send the EOI, and the order of EOI
 * to the two 8259s is important!
 */
static void mask_and_ack_8259A(unsigned int irq)
{
	unsigned int irqmask;
	unsigned long flags;

	irq -= I8259A_IRQ_BASE;
	irqmask = 1 << irq;
	spin_lock_irqsave(&i8259A_lock, flags);
	/*
	 * Lightweight spurious IRQ detection. We do not want
	 * to overdo spurious IRQ handling - it's usually a sign
	 * of hardware problems, so we only do the checks we can
	 * do without slowing down good hardware unnecessarily.
	 *
	 * Note that IRQ7 and IRQ15 (the two spurious IRQs
	 * usually resulting from the 8259A-1|2 PICs) occur
	 * even if the IRQ is masked in the 8259A. Thus we
	 * can check spurious 8259A IRQs without doing the
	 * quite slow i8259A_irq_real() call for every IRQ.
	 * This does not cover 100% of spurious interrupts,
	 * but should be enough to warn the user that there
	 * is something bad going on ...
	 */
	if (cached_irq_mask & irqmask)
		goto spurious_8259A_irq;
	cached_irq_mask |= irqmask;

handle_real_irq:
	if (irq & 8) {
		inb(PIC_SLAVE_IMR);	/* DUMMY - (do we need this?) */
		outb(cached_slave_mask, PIC_SLAVE_IMR);
		outb(0x60+(irq&7), PIC_SLAVE_CMD);/* 'Specific EOI' to slave */
		outb(0x60+PIC_CASCADE_IR, PIC_MASTER_CMD); /* 'Specific EOI' to master-IRQ2 */
	} else {
		inb(PIC_MASTER_IMR);	/* DUMMY - (do we need this?) */
		outb(cached_master_mask, PIC_MASTER_IMR);
		outb(0x60+irq, PIC_MASTER_CMD);	/* 'Specific EOI to master */
	}
	smtc_im_ack_irq(irq);
	spin_unlock_irqrestore(&i8259A_lock, flags);
	return;

spurious_8259A_irq:
	/*
	 * this is the slow path - should happen rarely.
	 */
	if (i8259A_irq_real(irq))
		/*
		 * oops, the IRQ _is_ in service according to the
		 * 8259A - not spurious, go handle it.
		 */
		goto handle_real_irq;

	{
		static int spurious_irq_mask;
		/*
		 * At this point we can be sure the IRQ is spurious,
		 * lets ACK and report it. [once per IRQ]
		 */
		if (!(spurious_irq_mask & irqmask)) {
			printk(KERN_DEBUG "spurious 8259A interrupt: IRQ%d.\n", irq);
			spurious_irq_mask |= irqmask;
		}
		atomic_inc(&irq_err_count);
		/*
		 * Theoretically we do not have to handle this IRQ,
		 * but in Linux this does not cause problems and is
		 * simpler for us.
		 */
		goto handle_real_irq;
	}
}

static int i8259A_resume(struct sys_device *dev)
{
	if (i8259A_auto_eoi >= 0)
		init_8259A(i8259A_auto_eoi);
	return 0;
}

static int i8259A_shutdown(struct sys_device *dev)
{
	/* Put the i8259A into a quiescent state that
	 * the kernel initialization code can get it
	 * out of.
	 */
	if (i8259A_auto_eoi >= 0) {
		outb(0xff, PIC_MASTER_IMR);	/* mask all of 8259A-1 */
		outb(0xff, PIC_SLAVE_IMR);	/* mask all of 8259A-1 */
	}
	return 0;
}

static struct sysdev_class i8259_sysdev_class = {
	.name = "i8259",
	.resume = i8259A_resume,
	.shutdown = i8259A_shutdown,
};

static struct sys_device device_i8259A = {
	.id	= 0,
	.cls	= &i8259_sysdev_class,
};

static int __init i8259A_init_sysfs(void)
{
	int error = sysdev_class_register(&i8259_sysdev_class);
	if (!error)
		error = sysdev_register(&device_i8259A);
	return error;
}

device_initcall(i8259A_init_sysfs);

static void init_8259A(int auto_eoi)
{
	unsigned long flags;

	i8259A_auto_eoi = auto_eoi;

	spin_lock_irqsave(&i8259A_lock, flags);

	outb(0xff, PIC_MASTER_IMR);	/* mask all of 8259A-1 */
	outb(0xff, PIC_SLAVE_IMR);	/* mask all of 8259A-2 */

	/*
	 * outb_p - this has to work on a wide range of PC hardware.
	 */
	outb_p(0x11, PIC_MASTER_CMD);	/* ICW1: select 8259A-1 init */
	outb_p(I8259A_IRQ_BASE + 0, PIC_MASTER_IMR);	/* ICW2: 8259A-1 IR0 mapped to I8259A_IRQ_BASE + 0x00 */
	outb_p(1U << PIC_CASCADE_IR, PIC_MASTER_IMR);	/* 8259A-1 (the master) has a slave on IR2 */
	if (auto_eoi)	/* master does Auto EOI */
		outb_p(MASTER_ICW4_DEFAULT | PIC_ICW4_AEOI, PIC_MASTER_IMR);
	else		/* master expects normal EOI */
		outb_p(MASTER_ICW4_DEFAULT, PIC_MASTER_IMR);

	outb_p(0x11, PIC_SLAVE_CMD);	/* ICW1: select 8259A-2 init */
	outb_p(I8259A_IRQ_BASE + 8, PIC_SLAVE_IMR);	/* ICW2: 8259A-2 IR0 mapped to I8259A_IRQ_BASE + 0x08 */
	outb_p(PIC_CASCADE_IR, PIC_SLAVE_IMR);	/* 8259A-2 is a slave on master's IR2 */
	outb_p(SLAVE_ICW4_DEFAULT, PIC_SLAVE_IMR); /* (slave's support for AEOI in flat mode is to be investigated) */
	if (auto_eoi)
		/*
		 * In AEOI mode we just have to mask the interrupt
		 * when acking.
		 */
		i8259A_chip.mask_ack = disable_8259A_irq;
	else
		i8259A_chip.mask_ack = mask_and_ack_8259A;

	udelay(100);		/* wait for 8259A to initialize */

	outb(cached_master_mask, PIC_MASTER_IMR); /* restore master IRQ mask */
	outb(cached_slave_mask, PIC_SLAVE_IMR);	  /* restore slave IRQ mask */

	spin_unlock_irqrestore(&i8259A_lock, flags);
}

/*
 * IRQ2 is cascade interrupt to second interrupt controller
 */
static struct irqaction irq2 = {
	.handler = no_action,
	.name = "cascade",
};

static struct resource pic1_io_resource = {
	.name = "pic1",
	.start = PIC_MASTER_CMD,
	.end = PIC_MASTER_IMR,
	.flags = IORESOURCE_BUSY
};

static struct resource pic2_io_resource = {
	.name = "pic2",
	.start = PIC_SLAVE_CMD,
	.end = PIC_SLAVE_IMR,
	.flags = IORESOURCE_BUSY
};

/*
 * On systems with i8259-style interrupt controllers we assume for
 * driver compatibility reasons interrupts 0 - 15 to be the i8259
 * interrupts even if the hardware uses a different interrupt numbering.
 */
void __init init_i8259_irqs(void)
{
	int i;

	insert_resource(&ioport_resource, &pic1_io_resource);
	insert_resource(&ioport_resource, &pic2_io_resource);

	init_8259A(0);

	for (i = I8259A_IRQ_BASE; i < I8259A_IRQ_BASE + 16; i++) {
		set_irq_chip_and_handler(i, &i8259A_chip, handle_level_irq);
		set_irq_probe(i);
	}

	setup_irq(I8259A_IRQ_BASE + PIC_CASCADE_IR, &irq2);
}
Commit	Line	Data
1da177e4 LT	1	/*
	2	* This file is subject to the terms and conditions of the GNU General Public
	3	* License. See the file "COPYING" in the main directory of this archive
	4	* for more details.
	5	*
	6	* Code to handle x86 style IRQs plus some generic interrupt stuff.
	7	*
	8	* Copyright (C) 1992 Linus Torvalds
	9	* Copyright (C) 1994 - 2000 Ralf Baechle
	10	*/
	11	#include <linux/delay.h>
	12	#include <linux/init.h>
	13	#include <linux/ioport.h>
	14	#include <linux/interrupt.h>
	15	#include <linux/kernel.h>
	16	#include <linux/spinlock.h>
	17	#include <linux/sysdev.h>
	18
	19	#include <asm/i8259.h>
	20	#include <asm/io.h>
	21
1da177e4 LT	22	/*
	23	* This is the 'legacy' 8259A Programmable Interrupt Controller,
	24	* present in the majority of PC/AT boxes.
	25	* plus some generic x86 specific things if generic specifics makes
	26	* any sense at all.
	27	* this file should become arch/i386/kernel/irq.c when the old irq.c
	28	* moves to arch independent land
	29	*/
	30
a0be2f79	31	static int i8259A_auto_eoi = -1;
9383292f	32	DEFINE_SPINLOCK(i8259A_lock);
d80c1c0b YY	33	static void disable_8259A_irq(unsigned int irq);
	34	static void enable_8259A_irq(unsigned int irq);
	35	static void mask_and_ack_8259A(unsigned int irq);
	36	static void init_8259A(int auto_eoi);
1da177e4	37
2cafe978 AN	38	static struct irq_chip i8259A_chip = {
	39	.name = "XT-PIC",
	40	.mask = disable_8259A_irq,
d77a283d	41	.disable = disable_8259A_irq,
2cafe978 AN	42	.unmask = enable_8259A_irq,
2cafe978 AN	43	.mask_ack = mask_and_ack_8259A,
f571eff0 KK	44	#ifdef CONFIG_MIPS_MT_SMTC_IRQAFF
	45	.set_affinity = plat_set_irq_affinity,
	46	#endif /* CONFIG_MIPS_MT_SMTC_IRQAFF */
1da177e4 LT	47	};
	48
	49	/*
	50	* 8259A PIC functions to handle ISA devices:
	51	*/
	52
	53	/*
	54	* This contains the irq mask for both 8259A irq controllers,
	55	*/
	56	static unsigned int cached_irq_mask = 0xffff;
	57
2cafe978 AN	58	#define cached_master_mask (cached_irq_mask)
2cafe978 AN	59	#define cached_slave_mask (cached_irq_mask >> 8)
1da177e4	60
d80c1c0b	61	static void disable_8259A_irq(unsigned int irq)
1da177e4	62	{
2fa7937b	63	unsigned int mask;
1da177e4 LT	64	unsigned long flags;
1da177e4 LT	65
2fa7937b AN	66	irq -= I8259A_IRQ_BASE;
2fa7937b AN	67	mask = 1 << irq;
1da177e4 LT	68	spin_lock_irqsave(&i8259A_lock, flags);
	69	cached_irq_mask \|= mask;
	70	if (irq & 8)
2cafe978	71	outb(cached_slave_mask, PIC_SLAVE_IMR);
1da177e4	72	else
2cafe978	73	outb(cached_master_mask, PIC_MASTER_IMR);
1da177e4 LT	74	spin_unlock_irqrestore(&i8259A_lock, flags);
	75	}
	76
d80c1c0b	77	static void enable_8259A_irq(unsigned int irq)
1da177e4	78	{
2fa7937b	79	unsigned int mask;
1da177e4 LT	80	unsigned long flags;
1da177e4 LT	81
2fa7937b AN	82	irq -= I8259A_IRQ_BASE;
2fa7937b AN	83	mask = ~(1 << irq);
1da177e4 LT	84	spin_lock_irqsave(&i8259A_lock, flags);
	85	cached_irq_mask &= mask;
	86	if (irq & 8)
2cafe978	87	outb(cached_slave_mask, PIC_SLAVE_IMR);
1da177e4	88	else
2cafe978	89	outb(cached_master_mask, PIC_MASTER_IMR);
1da177e4 LT	90	spin_unlock_irqrestore(&i8259A_lock, flags);
	91	}
	92
	93	int i8259A_irq_pending(unsigned int irq)
	94	{
2fa7937b	95	unsigned int mask;
1da177e4 LT	96	unsigned long flags;
	97	int ret;
	98
2fa7937b AN	99	irq -= I8259A_IRQ_BASE;
2fa7937b AN	100	mask = 1 << irq;
1da177e4 LT	101	spin_lock_irqsave(&i8259A_lock, flags);
1da177e4 LT	102	if (irq < 8)
2cafe978	103	ret = inb(PIC_MASTER_CMD) & mask;
1da177e4	104	else
2cafe978	105	ret = inb(PIC_SLAVE_CMD) & (mask >> 8);
1da177e4 LT	106	spin_unlock_irqrestore(&i8259A_lock, flags);
	107
	108	return ret;
	109	}
	110
	111	void make_8259A_irq(unsigned int irq)
	112	{
	113	disable_irq_nosync(irq);
2cafe978	114	set_irq_chip_and_handler(irq, &i8259A_chip, handle_level_irq);
1da177e4 LT	115	enable_irq(irq);
	116	}
	117
	118	/*
	119	* This function assumes to be called rarely. Switching between
	120	* 8259A registers is slow.
	121	* This has to be protected by the irq controller spinlock
	122	* before being called.
	123	*/
	124	static inline int i8259A_irq_real(unsigned int irq)
	125	{
	126	int value;
	127	int irqmask = 1 << irq;
	128
	129	if (irq < 8) {
21a151d8	130	outb(0x0B, PIC_MASTER_CMD); /* ISR register */
2cafe978	131	value = inb(PIC_MASTER_CMD) & irqmask;
21a151d8	132	outb(0x0A, PIC_MASTER_CMD); /* back to the IRR register */
1da177e4 LT	133	return value;
1da177e4 LT	134	}
21a151d8	135	outb(0x0B, PIC_SLAVE_CMD); /* ISR register */
2cafe978	136	value = inb(PIC_SLAVE_CMD) & (irqmask >> 8);
21a151d8	137	outb(0x0A, PIC_SLAVE_CMD); /* back to the IRR register */
1da177e4 LT	138	return value;
	139	}
	140
	141	/*
	142	* Careful! The 8259A is a fragile beast, it pretty
	143	* much _has_ to be done exactly like this (mask it
	144	* first, _then_ send the EOI, and the order of EOI
	145	* to the two 8259s is important!
	146	*/
d80c1c0b	147	static void mask_and_ack_8259A(unsigned int irq)
1da177e4	148	{
2fa7937b	149	unsigned int irqmask;
1da177e4 LT	150	unsigned long flags;
1da177e4 LT	151
2fa7937b AN	152	irq -= I8259A_IRQ_BASE;
2fa7937b AN	153	irqmask = 1 << irq;
1da177e4 LT	154	spin_lock_irqsave(&i8259A_lock, flags);
1da177e4 LT	155	/*
2cafe978 AN	156	* Lightweight spurious IRQ detection. We do not want
	157	* to overdo spurious IRQ handling - it's usually a sign
	158	* of hardware problems, so we only do the checks we can
	159	* do without slowing down good hardware unnecessarily.
1da177e4	160	*
2cafe978 AN	161	* Note that IRQ7 and IRQ15 (the two spurious IRQs
	162	* usually resulting from the 8259A-1\|2 PICs) occur
	163	* even if the IRQ is masked in the 8259A. Thus we
	164	* can check spurious 8259A IRQs without doing the
	165	* quite slow i8259A_irq_real() call for every IRQ.
	166	* This does not cover 100% of spurious interrupts,
	167	* but should be enough to warn the user that there
	168	* is something bad going on ...
1da177e4 LT	169	*/
	170	if (cached_irq_mask & irqmask)
	171	goto spurious_8259A_irq;
	172	cached_irq_mask \|= irqmask;
	173
	174	handle_real_irq:
	175	if (irq & 8) {
2cafe978 AN	176	inb(PIC_SLAVE_IMR); /* DUMMY - (do we need this?) */
2cafe978 AN	177	outb(cached_slave_mask, PIC_SLAVE_IMR);
21a151d8 RB	178	outb(0x60+(irq&7), PIC_SLAVE_CMD);/* 'Specific EOI' to slave */
21a151d8 RB	179	outb(0x60+PIC_CASCADE_IR, PIC_MASTER_CMD); /* 'Specific EOI' to master-IRQ2 */
1da177e4	180	} else {
2cafe978 AN	181	inb(PIC_MASTER_IMR); /* DUMMY - (do we need this?) */
2cafe978 AN	182	outb(cached_master_mask, PIC_MASTER_IMR);
21a151d8	183	outb(0x60+irq, PIC_MASTER_CMD); /* 'Specific EOI to master */
1da177e4	184	}
1146fe30	185	smtc_im_ack_irq(irq);
1da177e4 LT	186	spin_unlock_irqrestore(&i8259A_lock, flags);
	187	return;
	188
	189	spurious_8259A_irq:
	190	/*
	191	* this is the slow path - should happen rarely.
	192	*/
	193	if (i8259A_irq_real(irq))
	194	/*
	195	* oops, the IRQ _is_ in service according to the
	196	* 8259A - not spurious, go handle it.
	197	*/
	198	goto handle_real_irq;
	199
	200	{
2cafe978	201	static int spurious_irq_mask;
1da177e4 LT	202	/*
	203	* At this point we can be sure the IRQ is spurious,
	204	* lets ACK and report it. [once per IRQ]
	205	*/
	206	if (!(spurious_irq_mask & irqmask)) {
	207	printk(KERN_DEBUG "spurious 8259A interrupt: IRQ%d.\n", irq);
	208	spurious_irq_mask \|= irqmask;
	209	}
	210	atomic_inc(&irq_err_count);
	211	/*
	212	* Theoretically we do not have to handle this IRQ,
	213	* but in Linux this does not cause problems and is
	214	* simpler for us.
	215	*/
	216	goto handle_real_irq;
	217	}
	218	}
	219
	220	static int i8259A_resume(struct sys_device *dev)
	221	{
a0be2f79 AN	222	if (i8259A_auto_eoi >= 0)
a0be2f79 AN	223	init_8259A(i8259A_auto_eoi);
2cafe978 AN	224	return 0;
	225	}
	226
	227	static int i8259A_shutdown(struct sys_device *dev)
	228	{
	229	/* Put the i8259A into a quiescent state that
	230	* the kernel initialization code can get it
	231	* out of.
	232	*/
a0be2f79 AN	233	if (i8259A_auto_eoi >= 0) {
	234	outb(0xff, PIC_MASTER_IMR); /* mask all of 8259A-1 */
	235	outb(0xff, PIC_SLAVE_IMR); /* mask all of 8259A-1 */
	236	}
1da177e4 LT	237	return 0;
	238	}
	239
	240	static struct sysdev_class i8259_sysdev_class = {
af5ca3f4	241	.name = "i8259",
1da177e4	242	.resume = i8259A_resume,
2cafe978	243	.shutdown = i8259A_shutdown,
1da177e4 LT	244	};
	245
	246	static struct sys_device device_i8259A = {
	247	.id = 0,
	248	.cls = &i8259_sysdev_class,
	249	};
	250
	251	static int __init i8259A_init_sysfs(void)
	252	{
	253	int error = sysdev_class_register(&i8259_sysdev_class);
	254	if (!error)
	255	error = sysdev_register(&device_i8259A);
	256	return error;
	257	}
	258
	259	device_initcall(i8259A_init_sysfs);
	260
d80c1c0b	261	static void init_8259A(int auto_eoi)
1da177e4 LT	262	{
	263	unsigned long flags;
	264
2cafe978 AN	265	i8259A_auto_eoi = auto_eoi;
2cafe978 AN	266
1da177e4 LT	267	spin_lock_irqsave(&i8259A_lock, flags);
1da177e4 LT	268
2cafe978 AN	269	outb(0xff, PIC_MASTER_IMR); /* mask all of 8259A-1 */
2cafe978 AN	270	outb(0xff, PIC_SLAVE_IMR); /* mask all of 8259A-2 */
1da177e4 LT	271
	272	/*
	273	* outb_p - this has to work on a wide range of PC hardware.
	274	*/
2cafe978 AN	275	outb_p(0x11, PIC_MASTER_CMD); /* ICW1: select 8259A-1 init */
	276	outb_p(I8259A_IRQ_BASE + 0, PIC_MASTER_IMR); /* ICW2: 8259A-1 IR0 mapped to I8259A_IRQ_BASE + 0x00 */
	277	outb_p(1U << PIC_CASCADE_IR, PIC_MASTER_IMR); /* 8259A-1 (the master) has a slave on IR2 */
	278	if (auto_eoi) /* master does Auto EOI */
	279	outb_p(MASTER_ICW4_DEFAULT \| PIC_ICW4_AEOI, PIC_MASTER_IMR);
	280	else /* master expects normal EOI */
	281	outb_p(MASTER_ICW4_DEFAULT, PIC_MASTER_IMR);
	282
	283	outb_p(0x11, PIC_SLAVE_CMD); /* ICW1: select 8259A-2 init */
	284	outb_p(I8259A_IRQ_BASE + 8, PIC_SLAVE_IMR); /* ICW2: 8259A-2 IR0 mapped to I8259A_IRQ_BASE + 0x08 */
	285	outb_p(PIC_CASCADE_IR, PIC_SLAVE_IMR); /* 8259A-2 is a slave on master's IR2 */
	286	outb_p(SLAVE_ICW4_DEFAULT, PIC_SLAVE_IMR); /* (slave's support for AEOI in flat mode is to be investigated) */
1da177e4 LT	287	if (auto_eoi)
1da177e4 LT	288	/*
2cafe978	289	* In AEOI mode we just have to mask the interrupt
1da177e4 LT	290	* when acking.
1da177e4 LT	291	*/
2cafe978	292	i8259A_chip.mask_ack = disable_8259A_irq;
1da177e4	293	else
2cafe978	294	i8259A_chip.mask_ack = mask_and_ack_8259A;
1da177e4 LT	295
	296	udelay(100); /* wait for 8259A to initialize */
	297
2cafe978 AN	298	outb(cached_master_mask, PIC_MASTER_IMR); /* restore master IRQ mask */
2cafe978 AN	299	outb(cached_slave_mask, PIC_SLAVE_IMR); /* restore slave IRQ mask */
1da177e4 LT	300
	301	spin_unlock_irqrestore(&i8259A_lock, flags);
	302	}
	303
	304	/*
	305	* IRQ2 is cascade interrupt to second interrupt controller
	306	*/
	307	static struct irqaction irq2 = {
4e45171c	308	.handler = no_action,
4e45171c	309	.name = "cascade",
1da177e4 LT	310	};
	311
	312	static struct resource pic1_io_resource = {
2cafe978 AN	313	.name = "pic1",
	314	.start = PIC_MASTER_CMD,
	315	.end = PIC_MASTER_IMR,
	316	.flags = IORESOURCE_BUSY
1da177e4 LT	317	};
	318
	319	static struct resource pic2_io_resource = {
2cafe978 AN	320	.name = "pic2",
	321	.start = PIC_SLAVE_CMD,
	322	.end = PIC_SLAVE_IMR,
	323	.flags = IORESOURCE_BUSY
1da177e4 LT	324	};
	325
	326	/*
	327	* On systems with i8259-style interrupt controllers we assume for
28a7879d	328	* driver compatibility reasons interrupts 0 - 15 to be the i8259
1da177e4 LT	329	* interrupts even if the hardware uses a different interrupt numbering.
1da177e4 LT	330	*/
49a89efb	331	void __init init_i8259_irqs(void)
1da177e4 LT	332	{
	333	int i;
	334
639702bd TB	335	insert_resource(&ioport_resource, &pic1_io_resource);
639702bd TB	336	insert_resource(&ioport_resource, &pic2_io_resource);
1da177e4 LT	337
	338	init_8259A(0);
	339
24649c00	340	for (i = I8259A_IRQ_BASE; i < I8259A_IRQ_BASE + 16; i++) {
2cafe978	341	set_irq_chip_and_handler(i, &i8259A_chip, handle_level_irq);
24649c00 RB	342	set_irq_probe(i);
24649c00 RB	343	}
1da177e4	344
2fa7937b	345	setup_irq(I8259A_IRQ_BASE + PIC_CASCADE_IR, &irq2);
1da177e4	346	}