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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public | |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
6 | * Code to handle x86 style IRQs plus some generic interrupt stuff. | |
7 | * | |
8 | * Copyright (C) 1992 Linus Torvalds | |
9 | * Copyright (C) 1994 - 2000 Ralf Baechle | |
10 | */ | |
11 | #include <linux/delay.h> | |
12 | #include <linux/init.h> | |
13 | #include <linux/ioport.h> | |
14 | #include <linux/interrupt.h> | |
079a4601 | 15 | #include <linux/irqdomain.h> |
1da177e4 | 16 | #include <linux/kernel.h> |
5f93ef5c | 17 | #include <linux/of_irq.h> |
1da177e4 | 18 | #include <linux/spinlock.h> |
84652e83 | 19 | #include <linux/syscore_ops.h> |
ca4d3e67 | 20 | #include <linux/irq.h> |
1da177e4 LT |
21 | |
22 | #include <asm/i8259.h> | |
23 | #include <asm/io.h> | |
24 | ||
5f93ef5c PB |
25 | #include "../../drivers/irqchip/irqchip.h" |
26 | ||
1da177e4 LT |
27 | /* |
28 | * This is the 'legacy' 8259A Programmable Interrupt Controller, | |
29 | * present in the majority of PC/AT boxes. | |
30 | * plus some generic x86 specific things if generic specifics makes | |
31 | * any sense at all. | |
32 | * this file should become arch/i386/kernel/irq.c when the old irq.c | |
33 | * moves to arch independent land | |
34 | */ | |
35 | ||
a0be2f79 | 36 | static int i8259A_auto_eoi = -1; |
89650870 | 37 | DEFINE_RAW_SPINLOCK(i8259A_lock); |
7c8d948f TG |
38 | static void disable_8259A_irq(struct irq_data *d); |
39 | static void enable_8259A_irq(struct irq_data *d); | |
40 | static void mask_and_ack_8259A(struct irq_data *d); | |
d80c1c0b | 41 | static void init_8259A(int auto_eoi); |
1da177e4 | 42 | |
2cafe978 | 43 | static struct irq_chip i8259A_chip = { |
7c8d948f TG |
44 | .name = "XT-PIC", |
45 | .irq_mask = disable_8259A_irq, | |
46 | .irq_disable = disable_8259A_irq, | |
47 | .irq_unmask = enable_8259A_irq, | |
48 | .irq_mask_ack = mask_and_ack_8259A, | |
1da177e4 LT |
49 | }; |
50 | ||
51 | /* | |
52 | * 8259A PIC functions to handle ISA devices: | |
53 | */ | |
54 | ||
55 | /* | |
56 | * This contains the irq mask for both 8259A irq controllers, | |
57 | */ | |
58 | static unsigned int cached_irq_mask = 0xffff; | |
59 | ||
2cafe978 AN |
60 | #define cached_master_mask (cached_irq_mask) |
61 | #define cached_slave_mask (cached_irq_mask >> 8) | |
1da177e4 | 62 | |
7c8d948f | 63 | static void disable_8259A_irq(struct irq_data *d) |
1da177e4 | 64 | { |
7c8d948f | 65 | unsigned int mask, irq = d->irq - I8259A_IRQ_BASE; |
1da177e4 LT |
66 | unsigned long flags; |
67 | ||
2fa7937b | 68 | mask = 1 << irq; |
89650870 | 69 | raw_spin_lock_irqsave(&i8259A_lock, flags); |
1da177e4 LT |
70 | cached_irq_mask |= mask; |
71 | if (irq & 8) | |
2cafe978 | 72 | outb(cached_slave_mask, PIC_SLAVE_IMR); |
1da177e4 | 73 | else |
2cafe978 | 74 | outb(cached_master_mask, PIC_MASTER_IMR); |
89650870 | 75 | raw_spin_unlock_irqrestore(&i8259A_lock, flags); |
1da177e4 LT |
76 | } |
77 | ||
7c8d948f | 78 | static void enable_8259A_irq(struct irq_data *d) |
1da177e4 | 79 | { |
7c8d948f | 80 | unsigned int mask, irq = d->irq - I8259A_IRQ_BASE; |
1da177e4 LT |
81 | unsigned long flags; |
82 | ||
2fa7937b | 83 | mask = ~(1 << irq); |
89650870 | 84 | raw_spin_lock_irqsave(&i8259A_lock, flags); |
1da177e4 LT |
85 | cached_irq_mask &= mask; |
86 | if (irq & 8) | |
2cafe978 | 87 | outb(cached_slave_mask, PIC_SLAVE_IMR); |
1da177e4 | 88 | else |
2cafe978 | 89 | outb(cached_master_mask, PIC_MASTER_IMR); |
89650870 | 90 | raw_spin_unlock_irqrestore(&i8259A_lock, flags); |
1da177e4 LT |
91 | } |
92 | ||
93 | int i8259A_irq_pending(unsigned int irq) | |
94 | { | |
2fa7937b | 95 | unsigned int mask; |
1da177e4 LT |
96 | unsigned long flags; |
97 | int ret; | |
98 | ||
2fa7937b AN |
99 | irq -= I8259A_IRQ_BASE; |
100 | mask = 1 << irq; | |
89650870 | 101 | raw_spin_lock_irqsave(&i8259A_lock, flags); |
1da177e4 | 102 | if (irq < 8) |
2cafe978 | 103 | ret = inb(PIC_MASTER_CMD) & mask; |
1da177e4 | 104 | else |
2cafe978 | 105 | ret = inb(PIC_SLAVE_CMD) & (mask >> 8); |
89650870 | 106 | raw_spin_unlock_irqrestore(&i8259A_lock, flags); |
1da177e4 LT |
107 | |
108 | return ret; | |
109 | } | |
110 | ||
111 | void make_8259A_irq(unsigned int irq) | |
112 | { | |
113 | disable_irq_nosync(irq); | |
e4ec7989 | 114 | irq_set_chip_and_handler(irq, &i8259A_chip, handle_level_irq); |
1da177e4 LT |
115 | enable_irq(irq); |
116 | } | |
117 | ||
118 | /* | |
119 | * This function assumes to be called rarely. Switching between | |
120 | * 8259A registers is slow. | |
121 | * This has to be protected by the irq controller spinlock | |
122 | * before being called. | |
123 | */ | |
124 | static inline int i8259A_irq_real(unsigned int irq) | |
125 | { | |
126 | int value; | |
127 | int irqmask = 1 << irq; | |
128 | ||
129 | if (irq < 8) { | |
21a151d8 | 130 | outb(0x0B, PIC_MASTER_CMD); /* ISR register */ |
2cafe978 | 131 | value = inb(PIC_MASTER_CMD) & irqmask; |
21a151d8 | 132 | outb(0x0A, PIC_MASTER_CMD); /* back to the IRR register */ |
1da177e4 LT |
133 | return value; |
134 | } | |
21a151d8 | 135 | outb(0x0B, PIC_SLAVE_CMD); /* ISR register */ |
2cafe978 | 136 | value = inb(PIC_SLAVE_CMD) & (irqmask >> 8); |
21a151d8 | 137 | outb(0x0A, PIC_SLAVE_CMD); /* back to the IRR register */ |
1da177e4 LT |
138 | return value; |
139 | } | |
140 | ||
141 | /* | |
142 | * Careful! The 8259A is a fragile beast, it pretty | |
143 | * much _has_ to be done exactly like this (mask it | |
144 | * first, _then_ send the EOI, and the order of EOI | |
145 | * to the two 8259s is important! | |
146 | */ | |
7c8d948f | 147 | static void mask_and_ack_8259A(struct irq_data *d) |
1da177e4 | 148 | { |
7c8d948f | 149 | unsigned int irqmask, irq = d->irq - I8259A_IRQ_BASE; |
1da177e4 LT |
150 | unsigned long flags; |
151 | ||
2fa7937b | 152 | irqmask = 1 << irq; |
89650870 | 153 | raw_spin_lock_irqsave(&i8259A_lock, flags); |
1da177e4 | 154 | /* |
2cafe978 AN |
155 | * Lightweight spurious IRQ detection. We do not want |
156 | * to overdo spurious IRQ handling - it's usually a sign | |
157 | * of hardware problems, so we only do the checks we can | |
158 | * do without slowing down good hardware unnecessarily. | |
1da177e4 | 159 | * |
2cafe978 AN |
160 | * Note that IRQ7 and IRQ15 (the two spurious IRQs |
161 | * usually resulting from the 8259A-1|2 PICs) occur | |
162 | * even if the IRQ is masked in the 8259A. Thus we | |
163 | * can check spurious 8259A IRQs without doing the | |
164 | * quite slow i8259A_irq_real() call for every IRQ. | |
165 | * This does not cover 100% of spurious interrupts, | |
166 | * but should be enough to warn the user that there | |
167 | * is something bad going on ... | |
1da177e4 LT |
168 | */ |
169 | if (cached_irq_mask & irqmask) | |
170 | goto spurious_8259A_irq; | |
171 | cached_irq_mask |= irqmask; | |
172 | ||
173 | handle_real_irq: | |
174 | if (irq & 8) { | |
2cafe978 AN |
175 | inb(PIC_SLAVE_IMR); /* DUMMY - (do we need this?) */ |
176 | outb(cached_slave_mask, PIC_SLAVE_IMR); | |
21a151d8 RB |
177 | outb(0x60+(irq&7), PIC_SLAVE_CMD);/* 'Specific EOI' to slave */ |
178 | outb(0x60+PIC_CASCADE_IR, PIC_MASTER_CMD); /* 'Specific EOI' to master-IRQ2 */ | |
1da177e4 | 179 | } else { |
2cafe978 AN |
180 | inb(PIC_MASTER_IMR); /* DUMMY - (do we need this?) */ |
181 | outb(cached_master_mask, PIC_MASTER_IMR); | |
70342287 | 182 | outb(0x60+irq, PIC_MASTER_CMD); /* 'Specific EOI to master */ |
1da177e4 | 183 | } |
89650870 | 184 | raw_spin_unlock_irqrestore(&i8259A_lock, flags); |
1da177e4 LT |
185 | return; |
186 | ||
187 | spurious_8259A_irq: | |
188 | /* | |
189 | * this is the slow path - should happen rarely. | |
190 | */ | |
191 | if (i8259A_irq_real(irq)) | |
192 | /* | |
193 | * oops, the IRQ _is_ in service according to the | |
194 | * 8259A - not spurious, go handle it. | |
195 | */ | |
196 | goto handle_real_irq; | |
197 | ||
198 | { | |
2cafe978 | 199 | static int spurious_irq_mask; |
1da177e4 LT |
200 | /* |
201 | * At this point we can be sure the IRQ is spurious, | |
202 | * lets ACK and report it. [once per IRQ] | |
203 | */ | |
204 | if (!(spurious_irq_mask & irqmask)) { | |
205 | printk(KERN_DEBUG "spurious 8259A interrupt: IRQ%d.\n", irq); | |
206 | spurious_irq_mask |= irqmask; | |
207 | } | |
208 | atomic_inc(&irq_err_count); | |
209 | /* | |
210 | * Theoretically we do not have to handle this IRQ, | |
211 | * but in Linux this does not cause problems and is | |
212 | * simpler for us. | |
213 | */ | |
214 | goto handle_real_irq; | |
215 | } | |
216 | } | |
217 | ||
84652e83 | 218 | static void i8259A_resume(void) |
1da177e4 | 219 | { |
a0be2f79 AN |
220 | if (i8259A_auto_eoi >= 0) |
221 | init_8259A(i8259A_auto_eoi); | |
2cafe978 AN |
222 | } |
223 | ||
84652e83 | 224 | static void i8259A_shutdown(void) |
2cafe978 AN |
225 | { |
226 | /* Put the i8259A into a quiescent state that | |
227 | * the kernel initialization code can get it | |
228 | * out of. | |
229 | */ | |
a0be2f79 AN |
230 | if (i8259A_auto_eoi >= 0) { |
231 | outb(0xff, PIC_MASTER_IMR); /* mask all of 8259A-1 */ | |
fe0b030c | 232 | outb(0xff, PIC_SLAVE_IMR); /* mask all of 8259A-2 */ |
a0be2f79 | 233 | } |
1da177e4 LT |
234 | } |
235 | ||
84652e83 | 236 | static struct syscore_ops i8259_syscore_ops = { |
1da177e4 | 237 | .resume = i8259A_resume, |
2cafe978 | 238 | .shutdown = i8259A_shutdown, |
1da177e4 LT |
239 | }; |
240 | ||
1da177e4 LT |
241 | static int __init i8259A_init_sysfs(void) |
242 | { | |
84652e83 RW |
243 | register_syscore_ops(&i8259_syscore_ops); |
244 | return 0; | |
1da177e4 LT |
245 | } |
246 | ||
247 | device_initcall(i8259A_init_sysfs); | |
248 | ||
d80c1c0b | 249 | static void init_8259A(int auto_eoi) |
1da177e4 LT |
250 | { |
251 | unsigned long flags; | |
252 | ||
2cafe978 AN |
253 | i8259A_auto_eoi = auto_eoi; |
254 | ||
89650870 | 255 | raw_spin_lock_irqsave(&i8259A_lock, flags); |
1da177e4 | 256 | |
2cafe978 AN |
257 | outb(0xff, PIC_MASTER_IMR); /* mask all of 8259A-1 */ |
258 | outb(0xff, PIC_SLAVE_IMR); /* mask all of 8259A-2 */ | |
1da177e4 LT |
259 | |
260 | /* | |
261 | * outb_p - this has to work on a wide range of PC hardware. | |
262 | */ | |
2cafe978 AN |
263 | outb_p(0x11, PIC_MASTER_CMD); /* ICW1: select 8259A-1 init */ |
264 | outb_p(I8259A_IRQ_BASE + 0, PIC_MASTER_IMR); /* ICW2: 8259A-1 IR0 mapped to I8259A_IRQ_BASE + 0x00 */ | |
265 | outb_p(1U << PIC_CASCADE_IR, PIC_MASTER_IMR); /* 8259A-1 (the master) has a slave on IR2 */ | |
266 | if (auto_eoi) /* master does Auto EOI */ | |
267 | outb_p(MASTER_ICW4_DEFAULT | PIC_ICW4_AEOI, PIC_MASTER_IMR); | |
268 | else /* master expects normal EOI */ | |
269 | outb_p(MASTER_ICW4_DEFAULT, PIC_MASTER_IMR); | |
270 | ||
271 | outb_p(0x11, PIC_SLAVE_CMD); /* ICW1: select 8259A-2 init */ | |
272 | outb_p(I8259A_IRQ_BASE + 8, PIC_SLAVE_IMR); /* ICW2: 8259A-2 IR0 mapped to I8259A_IRQ_BASE + 0x08 */ | |
273 | outb_p(PIC_CASCADE_IR, PIC_SLAVE_IMR); /* 8259A-2 is a slave on master's IR2 */ | |
274 | outb_p(SLAVE_ICW4_DEFAULT, PIC_SLAVE_IMR); /* (slave's support for AEOI in flat mode is to be investigated) */ | |
1da177e4 LT |
275 | if (auto_eoi) |
276 | /* | |
2cafe978 | 277 | * In AEOI mode we just have to mask the interrupt |
1da177e4 LT |
278 | * when acking. |
279 | */ | |
7c8d948f | 280 | i8259A_chip.irq_mask_ack = disable_8259A_irq; |
1da177e4 | 281 | else |
7c8d948f | 282 | i8259A_chip.irq_mask_ack = mask_and_ack_8259A; |
1da177e4 LT |
283 | |
284 | udelay(100); /* wait for 8259A to initialize */ | |
285 | ||
2cafe978 AN |
286 | outb(cached_master_mask, PIC_MASTER_IMR); /* restore master IRQ mask */ |
287 | outb(cached_slave_mask, PIC_SLAVE_IMR); /* restore slave IRQ mask */ | |
1da177e4 | 288 | |
89650870 | 289 | raw_spin_unlock_irqrestore(&i8259A_lock, flags); |
1da177e4 LT |
290 | } |
291 | ||
292 | /* | |
293 | * IRQ2 is cascade interrupt to second interrupt controller | |
294 | */ | |
295 | static struct irqaction irq2 = { | |
4e45171c | 296 | .handler = no_action, |
4e45171c | 297 | .name = "cascade", |
5c22cd40 | 298 | .flags = IRQF_NO_THREAD, |
1da177e4 LT |
299 | }; |
300 | ||
301 | static struct resource pic1_io_resource = { | |
2cafe978 AN |
302 | .name = "pic1", |
303 | .start = PIC_MASTER_CMD, | |
304 | .end = PIC_MASTER_IMR, | |
305 | .flags = IORESOURCE_BUSY | |
1da177e4 LT |
306 | }; |
307 | ||
308 | static struct resource pic2_io_resource = { | |
2cafe978 AN |
309 | .name = "pic2", |
310 | .start = PIC_SLAVE_CMD, | |
311 | .end = PIC_SLAVE_IMR, | |
312 | .flags = IORESOURCE_BUSY | |
1da177e4 LT |
313 | }; |
314 | ||
079a4601 AB |
315 | static int i8259A_irq_domain_map(struct irq_domain *d, unsigned int virq, |
316 | irq_hw_number_t hw) | |
317 | { | |
318 | irq_set_chip_and_handler(virq, &i8259A_chip, handle_level_irq); | |
319 | irq_set_probe(virq); | |
320 | return 0; | |
321 | } | |
322 | ||
323 | static struct irq_domain_ops i8259A_ops = { | |
324 | .map = i8259A_irq_domain_map, | |
325 | .xlate = irq_domain_xlate_onecell, | |
326 | }; | |
327 | ||
1da177e4 LT |
328 | /* |
329 | * On systems with i8259-style interrupt controllers we assume for | |
28a7879d | 330 | * driver compatibility reasons interrupts 0 - 15 to be the i8259 |
1da177e4 LT |
331 | * interrupts even if the hardware uses a different interrupt numbering. |
332 | */ | |
5f93ef5c | 333 | struct irq_domain * __init __init_i8259_irqs(struct device_node *node) |
1da177e4 | 334 | { |
079a4601 | 335 | struct irq_domain *domain; |
1da177e4 | 336 | |
639702bd TB |
337 | insert_resource(&ioport_resource, &pic1_io_resource); |
338 | insert_resource(&ioport_resource, &pic2_io_resource); | |
1da177e4 LT |
339 | |
340 | init_8259A(0); | |
341 | ||
5f93ef5c | 342 | domain = irq_domain_add_legacy(node, 16, I8259A_IRQ_BASE, 0, |
079a4601 AB |
343 | &i8259A_ops, NULL); |
344 | if (!domain) | |
345 | panic("Failed to add i8259 IRQ domain"); | |
1da177e4 | 346 | |
2fa7937b | 347 | setup_irq(I8259A_IRQ_BASE + PIC_CASCADE_IR, &irq2); |
5f93ef5c PB |
348 | return domain; |
349 | } | |
350 | ||
351 | void __init init_i8259_irqs(void) | |
352 | { | |
353 | __init_i8259_irqs(NULL); | |
354 | } | |
355 | ||
356 | static void i8259_irq_dispatch(unsigned int irq, struct irq_desc *desc) | |
357 | { | |
358 | struct irq_domain *domain = irq_get_handler_data(irq); | |
359 | int hwirq = i8259_irq(); | |
360 | ||
361 | if (hwirq < 0) | |
362 | return; | |
363 | ||
364 | irq = irq_linear_revmap(domain, hwirq); | |
365 | generic_handle_irq(irq); | |
366 | } | |
367 | ||
368 | int __init i8259_of_init(struct device_node *node, struct device_node *parent) | |
369 | { | |
370 | struct irq_domain *domain; | |
371 | unsigned int parent_irq; | |
372 | ||
373 | parent_irq = irq_of_parse_and_map(node, 0); | |
374 | if (!parent_irq) { | |
375 | pr_err("Failed to map i8259 parent IRQ\n"); | |
376 | return -ENODEV; | |
377 | } | |
378 | ||
379 | domain = __init_i8259_irqs(node); | |
380 | irq_set_handler_data(parent_irq, domain); | |
381 | irq_set_chained_handler(parent_irq, i8259_irq_dispatch); | |
382 | return 0; | |
1da177e4 | 383 | } |
5f93ef5c | 384 | IRQCHIP_DECLARE(i8259, "intel,i8259", i8259_of_init); |