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2874c5fd | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
49f2ec91 RB |
2 | /* |
3 | * MIPS idle loop and WAIT instruction support. | |
4 | * | |
5 | * Copyright (C) xxxx the Anonymous | |
6 | * Copyright (C) 1994 - 2006 Ralf Baechle | |
7 | * Copyright (C) 2003, 2004 Maciej W. Rozycki | |
8 | * Copyright (C) 2001, 2004, 2011, 2012 MIPS Technologies, Inc. | |
49f2ec91 | 9 | */ |
91955e3e | 10 | #include <linux/cpu.h> |
49f2ec91 RB |
11 | #include <linux/export.h> |
12 | #include <linux/init.h> | |
13 | #include <linux/irqflags.h> | |
14 | #include <linux/printk.h> | |
15 | #include <linux/sched.h> | |
16 | #include <asm/cpu.h> | |
17 | #include <asm/cpu-info.h> | |
69f24d17 | 18 | #include <asm/cpu-type.h> |
bdc92d74 | 19 | #include <asm/idle.h> |
49f2ec91 RB |
20 | #include <asm/mipsregs.h> |
21 | ||
22 | /* | |
23 | * Not all of the MIPS CPUs have the "wait" instruction available. Moreover, | |
24 | * the implementation of the "wait" feature differs between CPU families. This | |
25 | * points to the function that implements CPU specific wait. | |
26 | * The wait instruction stops the pipeline and reduces the power consumption of | |
27 | * the CPU very much. | |
28 | */ | |
29 | void (*cpu_wait)(void); | |
30 | EXPORT_SYMBOL(cpu_wait); | |
31 | ||
97c8580e | 32 | static void __cpuidle r3081_wait(void) |
49f2ec91 RB |
33 | { |
34 | unsigned long cfg = read_c0_conf(); | |
35 | write_c0_conf(cfg | R30XX_CONF_HALT); | |
fb40bc3e | 36 | local_irq_enable(); |
49f2ec91 RB |
37 | } |
38 | ||
97c8580e | 39 | static void __cpuidle r39xx_wait(void) |
49f2ec91 | 40 | { |
49f2ec91 RB |
41 | if (!need_resched()) |
42 | write_c0_conf(read_c0_conf() | TX39_CONF_HALT); | |
43 | local_irq_enable(); | |
44 | } | |
45 | ||
97c8580e | 46 | void __cpuidle r4k_wait(void) |
087d990b RB |
47 | { |
48 | local_irq_enable(); | |
49 | __r4k_wait(); | |
50 | } | |
51 | ||
49f2ec91 RB |
52 | /* |
53 | * This variant is preferable as it allows testing need_resched and going to | |
54 | * sleep depending on the outcome atomically. Unfortunately the "It is | |
55 | * implementation-dependent whether the pipeline restarts when a non-enabled | |
56 | * interrupt is requested" restriction in the MIPS32/MIPS64 architecture makes | |
57 | * using this version a gamble. | |
58 | */ | |
97c8580e | 59 | void __cpuidle r4k_wait_irqoff(void) |
49f2ec91 | 60 | { |
49f2ec91 | 61 | if (!need_resched()) |
f91a148a RB |
62 | __asm__( |
63 | " .set push \n" | |
a809d460 | 64 | " .set arch=r4000 \n" |
f91a148a RB |
65 | " wait \n" |
66 | " .set pop \n"); | |
49f2ec91 | 67 | local_irq_enable(); |
49f2ec91 RB |
68 | } |
69 | ||
70 | /* | |
71 | * The RM7000 variant has to handle erratum 38. The workaround is to not | |
72 | * have any pending stores when the WAIT instruction is executed. | |
73 | */ | |
97c8580e | 74 | static void __cpuidle rm7k_wait_irqoff(void) |
49f2ec91 | 75 | { |
49f2ec91 RB |
76 | if (!need_resched()) |
77 | __asm__( | |
78 | " .set push \n" | |
a809d460 | 79 | " .set arch=r4000 \n" |
49f2ec91 RB |
80 | " .set noat \n" |
81 | " mfc0 $1, $12 \n" | |
82 | " sync \n" | |
83 | " mtc0 $1, $12 # stalls until W stage \n" | |
84 | " wait \n" | |
85 | " mtc0 $1, $12 # stalls until W stage \n" | |
86 | " .set pop \n"); | |
87 | local_irq_enable(); | |
88 | } | |
89 | ||
90 | /* | |
e63a24dd ML |
91 | * Au1 'wait' is only useful when the 32kHz counter is used as timer, |
92 | * since coreclock (and the cp0 counter) stops upon executing it. Only an | |
93 | * interrupt can wake it, so they must be enabled before entering idle modes. | |
49f2ec91 | 94 | */ |
97c8580e | 95 | static void __cpuidle au1k_wait(void) |
49f2ec91 | 96 | { |
e63a24dd ML |
97 | unsigned long c0status = read_c0_status() | 1; /* irqs on */ |
98 | ||
f91a148a | 99 | __asm__( |
378ed6f0 PB |
100 | " .set push \n" |
101 | " .set arch=r4000 \n" | |
f91a148a RB |
102 | " cache 0x14, 0(%0) \n" |
103 | " cache 0x14, 32(%0) \n" | |
104 | " sync \n" | |
e63a24dd | 105 | " mtc0 %1, $12 \n" /* wr c0status */ |
f91a148a RB |
106 | " wait \n" |
107 | " nop \n" | |
108 | " nop \n" | |
109 | " nop \n" | |
110 | " nop \n" | |
378ed6f0 | 111 | " .set pop \n" |
e63a24dd | 112 | : : "r" (au1k_wait), "r" (c0status)); |
49f2ec91 RB |
113 | } |
114 | ||
115 | static int __initdata nowait; | |
116 | ||
117 | static int __init wait_disable(char *s) | |
118 | { | |
119 | nowait = 1; | |
120 | ||
121 | return 1; | |
122 | } | |
123 | ||
124 | __setup("nowait", wait_disable); | |
125 | ||
126 | void __init check_wait(void) | |
127 | { | |
128 | struct cpuinfo_mips *c = ¤t_cpu_data; | |
129 | ||
130 | if (nowait) { | |
131 | printk("Wait instruction disabled.\n"); | |
132 | return; | |
133 | } | |
134 | ||
5b10a0e8 PB |
135 | /* |
136 | * MIPSr6 specifies that masked interrupts should unblock an executing | |
137 | * wait instruction, and thus that it is safe for us to use | |
138 | * r4k_wait_irqoff. Yippee! | |
139 | */ | |
140 | if (cpu_has_mips_r6) { | |
141 | cpu_wait = r4k_wait_irqoff; | |
142 | return; | |
143 | } | |
144 | ||
69f24d17 | 145 | switch (current_cpu_type()) { |
49f2ec91 RB |
146 | case CPU_R3081: |
147 | case CPU_R3081E: | |
148 | cpu_wait = r3081_wait; | |
149 | break; | |
150 | case CPU_TX3927: | |
151 | cpu_wait = r39xx_wait; | |
152 | break; | |
153 | case CPU_R4200: | |
154 | /* case CPU_R4300: */ | |
155 | case CPU_R4600: | |
156 | case CPU_R4640: | |
157 | case CPU_R4650: | |
158 | case CPU_R4700: | |
159 | case CPU_R5000: | |
160 | case CPU_R5500: | |
161 | case CPU_NEVADA: | |
162 | case CPU_4KC: | |
163 | case CPU_4KEC: | |
164 | case CPU_4KSC: | |
165 | case CPU_5KC: | |
bf463f2f | 166 | case CPU_5KE: |
49f2ec91 RB |
167 | case CPU_25KF: |
168 | case CPU_PR4450: | |
169 | case CPU_BMIPS3300: | |
170 | case CPU_BMIPS4350: | |
171 | case CPU_BMIPS4380: | |
49f2ec91 RB |
172 | case CPU_CAVIUM_OCTEON: |
173 | case CPU_CAVIUM_OCTEON_PLUS: | |
174 | case CPU_CAVIUM_OCTEON2: | |
4122af0a | 175 | case CPU_CAVIUM_OCTEON3: |
49f2ec91 RB |
176 | case CPU_JZRISC: |
177 | case CPU_LOONGSON1: | |
178 | case CPU_XLR: | |
179 | case CPU_XLP: | |
180 | cpu_wait = r4k_wait; | |
181 | break; | |
b2edcfc8 | 182 | case CPU_LOONGSON3: |
f3ade253 | 183 | if ((c->processor_id & PRID_REV_MASK) >= PRID_REV_LOONGSON3A_R2_0) |
b2edcfc8 HC |
184 | cpu_wait = r4k_wait; |
185 | break; | |
186 | ||
adaa0b6c PG |
187 | case CPU_BMIPS5000: |
188 | cpu_wait = r4k_wait_irqoff; | |
189 | break; | |
49f2ec91 RB |
190 | case CPU_RM7000: |
191 | cpu_wait = rm7k_wait_irqoff; | |
192 | break; | |
193 | ||
e38df288 JH |
194 | case CPU_PROAPTIV: |
195 | case CPU_P5600: | |
196 | /* | |
197 | * Incoming Fast Debug Channel (FDC) data during a wait | |
198 | * instruction causes the wait never to resume, even if an | |
199 | * interrupt is received. Avoid using wait at all if FDC data is | |
200 | * likely to be received. | |
201 | */ | |
202 | if (IS_ENABLED(CONFIG_MIPS_EJTAG_FDC_TTY)) | |
203 | break; | |
204 | /* fall through */ | |
49f2ec91 RB |
205 | case CPU_M14KC: |
206 | case CPU_M14KEC: | |
207 | case CPU_24K: | |
208 | case CPU_34K: | |
209 | case CPU_1004K: | |
442e14a2 | 210 | case CPU_1074K: |
26ab96df | 211 | case CPU_INTERAPTIV: |
f36c4720 | 212 | case CPU_M5150: |
4695089f | 213 | case CPU_QEMU_GENERIC: |
49f2ec91 RB |
214 | cpu_wait = r4k_wait; |
215 | if (read_c0_config7() & MIPS_CONF7_WII) | |
216 | cpu_wait = r4k_wait_irqoff; | |
217 | break; | |
218 | ||
219 | case CPU_74K: | |
220 | cpu_wait = r4k_wait; | |
221 | if ((c->processor_id & 0xff) >= PRID_REV_ENCODE_332(2, 1, 0)) | |
222 | cpu_wait = r4k_wait_irqoff; | |
223 | break; | |
224 | ||
225 | case CPU_TX49XX: | |
226 | cpu_wait = r4k_wait_irqoff; | |
227 | break; | |
228 | case CPU_ALCHEMY: | |
229 | cpu_wait = au1k_wait; | |
230 | break; | |
231 | case CPU_20KC: | |
232 | /* | |
233 | * WAIT on Rev1.0 has E1, E2, E3 and E16. | |
234 | * WAIT on Rev2.0 and Rev3.0 has E16. | |
235 | * Rev3.1 WAIT is nop, why bother | |
236 | */ | |
237 | if ((c->processor_id & 0xff) <= 0x64) | |
238 | break; | |
239 | ||
240 | /* | |
241 | * Another rev is incremeting c0_count at a reduced clock | |
242 | * rate while in WAIT mode. So we basically have the choice | |
243 | * between using the cp0 timer as clocksource or avoiding | |
244 | * the WAIT instruction. Until more details are known, | |
245 | * disable the use of WAIT for 20Kc entirely. | |
246 | cpu_wait = r4k_wait; | |
247 | */ | |
248 | break; | |
49f2ec91 RB |
249 | default: |
250 | break; | |
251 | } | |
252 | } | |
253 | ||
00baf857 RB |
254 | void arch_cpu_idle(void) |
255 | { | |
49f2ec91 | 256 | if (cpu_wait) |
c9b6869d | 257 | cpu_wait(); |
49f2ec91 RB |
258 | else |
259 | local_irq_enable(); | |
260 | } | |
da9f970f PB |
261 | |
262 | #ifdef CONFIG_CPU_IDLE | |
263 | ||
264 | int mips_cpuidle_wait_enter(struct cpuidle_device *dev, | |
265 | struct cpuidle_driver *drv, int index) | |
266 | { | |
267 | arch_cpu_idle(); | |
268 | return index; | |
269 | } | |
270 | ||
271 | #endif |