[mirror_ubuntu-hirsute-kernel.git] / arch / mips / kernel / irq-gic.c

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 2008 Ralf Baechle (ralf@linux-mips.org)
 * Copyright (C) 2012 MIPS Technologies, Inc.  All rights reserved.
 */
#include <linux/bitmap.h>
#include <linux/init.h>
#include <linux/smp.h>
#include <linux/irq.h>

#include <asm/io.h>
#include <asm/gic.h>
#include <asm/gcmpregs.h>
#include <linux/hardirq.h>
#include <asm-generic/bitops/find.h>

unsigned long _gic_base;
unsigned int gic_irq_base;
unsigned int gic_irq_flags[GIC_NUM_INTRS];

static struct gic_pcpu_mask pcpu_masks[NR_CPUS];
static struct gic_pending_regs pending_regs[NR_CPUS];
static struct gic_intrmask_regs intrmask_regs[NR_CPUS];

void gic_send_ipi(unsigned int intr)
{
	GICWRITE(GIC_REG(SHARED, GIC_SH_WEDGE), 0x80000000 | intr);
}

static void __init vpe_local_setup(unsigned int numvpes)
{
	unsigned long timer_interrupt = GIC_INT_TMR;
	unsigned long perf_interrupt = GIC_INT_PERFCTR;
	unsigned int vpe_ctl;
	int i;

	/*
	 * Setup the default performance counter timer interrupts
	 * for all VPEs
	 */
	for (i = 0; i < numvpes; i++) {
		GICWRITE(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), i);

		/* Are Interrupts locally routable? */
		GICREAD(GIC_REG(VPE_OTHER, GIC_VPE_CTL), vpe_ctl);
		if (vpe_ctl & GIC_VPE_CTL_TIMER_RTBL_MSK)
			GICWRITE(GIC_REG(VPE_OTHER, GIC_VPE_TIMER_MAP),
				 GIC_MAP_TO_PIN_MSK | timer_interrupt);

		if (vpe_ctl & GIC_VPE_CTL_PERFCNT_RTBL_MSK)
			GICWRITE(GIC_REG(VPE_OTHER, GIC_VPE_PERFCTR_MAP),
				 GIC_MAP_TO_PIN_MSK | perf_interrupt);
	}
}

unsigned int gic_get_int(void)
{
	unsigned int i;
	unsigned long *pending, *intrmask, *pcpu_mask;
	unsigned long *pending_abs, *intrmask_abs;

	/* Get per-cpu bitmaps */
	pending = pending_regs[smp_processor_id()].pending;
	intrmask = intrmask_regs[smp_processor_id()].intrmask;
	pcpu_mask = pcpu_masks[smp_processor_id()].pcpu_mask;

	pending_abs = (unsigned long *) GIC_REG_ABS_ADDR(SHARED,
							 GIC_SH_PEND_31_0_OFS);
	intrmask_abs = (unsigned long *) GIC_REG_ABS_ADDR(SHARED,
							  GIC_SH_MASK_31_0_OFS);

	for (i = 0; i < BITS_TO_LONGS(GIC_NUM_INTRS); i++) {
		GICREAD(*pending_abs, pending[i]);
		GICREAD(*intrmask_abs, intrmask[i]);
		pending_abs++;
		intrmask_abs++;
	}

	bitmap_and(pending, pending, intrmask, GIC_NUM_INTRS);
	bitmap_and(pending, pending, pcpu_mask, GIC_NUM_INTRS);

	return find_first_bit(pending, GIC_NUM_INTRS);
}

static void gic_mask_irq(struct irq_data *d)
{
	GIC_CLR_INTR_MASK(d->irq - gic_irq_base);
}

static void gic_unmask_irq(struct irq_data *d)
{
	GIC_SET_INTR_MASK(d->irq - gic_irq_base);
}

#ifdef CONFIG_SMP
static DEFINE_SPINLOCK(gic_lock);

static int gic_set_affinity(struct irq_data *d, const struct cpumask *cpumask,
			    bool force)
{
	unsigned int irq = (d->irq - gic_irq_base);
	cpumask_t	tmp = CPU_MASK_NONE;
	unsigned long	flags;
	int		i;

	cpumask_and(&tmp, cpumask, cpu_online_mask);
	if (cpus_empty(tmp))
		return -1;

	/* Assumption : cpumask refers to a single CPU */
	spin_lock_irqsave(&gic_lock, flags);
	for (;;) {
		/* Re-route this IRQ */
		GIC_SH_MAP_TO_VPE_SMASK(irq, first_cpu(tmp));

		/* Update the pcpu_masks */
		for (i = 0; i < NR_CPUS; i++)
			clear_bit(irq, pcpu_masks[i].pcpu_mask);
		set_bit(irq, pcpu_masks[first_cpu(tmp)].pcpu_mask);

	}
	cpumask_copy(d->affinity, cpumask);
	spin_unlock_irqrestore(&gic_lock, flags);

	return IRQ_SET_MASK_OK_NOCOPY;
}
#endif

static struct irq_chip gic_irq_controller = {
	.name			=	"MIPS GIC",
	.irq_ack		=	gic_irq_ack,
	.irq_mask		=	gic_mask_irq,
	.irq_mask_ack		=	gic_mask_irq,
	.irq_unmask		=	gic_unmask_irq,
	.irq_eoi		=	gic_unmask_irq,
#ifdef CONFIG_SMP
	.irq_set_affinity	=	gic_set_affinity,
#endif
};

static void __init gic_setup_intr(unsigned int intr, unsigned int cpu,
	unsigned int pin, unsigned int polarity, unsigned int trigtype,
	unsigned int flags)
{
	/* Setup Intr to Pin mapping */
	if (pin & GIC_MAP_TO_NMI_MSK) {
		GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_MAP_TO_PIN(intr)), pin);
		/* FIXME: hack to route NMI to all cpu's */
		for (cpu = 0; cpu < NR_CPUS; cpu += 32) {
			GICWRITE(GIC_REG_ADDR(SHARED,
					  GIC_SH_MAP_TO_VPE_REG_OFF(intr, cpu)),
				 0xffffffff);
		}
	} else {
		GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_MAP_TO_PIN(intr)),
			 GIC_MAP_TO_PIN_MSK | pin);
		/* Setup Intr to CPU mapping */
		GIC_SH_MAP_TO_VPE_SMASK(intr, cpu);
	}

	/* Setup Intr Polarity */
	GIC_SET_POLARITY(intr, polarity);

	/* Setup Intr Trigger Type */
	GIC_SET_TRIGGER(intr, trigtype);

	/* Init Intr Masks */
	GIC_CLR_INTR_MASK(intr);

	/* Initialise per-cpu Interrupt software masks */
	if (flags & GIC_FLAG_IPI)
		set_bit(intr, pcpu_masks[cpu].pcpu_mask);
	if (flags & GIC_FLAG_TRANSPARENT)
		GIC_SET_INTR_MASK(intr);
	if (trigtype == GIC_TRIG_EDGE)
		gic_irq_flags[intr] |= GIC_TRIG_EDGE;
}

static void __init gic_basic_init(int numintrs, int numvpes,
			struct gic_intr_map *intrmap, int mapsize)
{
	unsigned int i, cpu;

	/* Setup defaults */
	for (i = 0; i < numintrs; i++) {
		GIC_SET_POLARITY(i, GIC_POL_POS);
		GIC_SET_TRIGGER(i, GIC_TRIG_LEVEL);
		GIC_CLR_INTR_MASK(i);
		if (i < GIC_NUM_INTRS)
			gic_irq_flags[i] = 0;
	}

	/* Setup specifics */
	for (i = 0; i < mapsize; i++) {
		cpu = intrmap[i].cpunum;
		if (cpu == GIC_UNUSED)
			continue;
		if (cpu == 0 && i != 0 && intrmap[i].flags == 0)
			continue;
		gic_setup_intr(i,
			intrmap[i].cpunum,
			intrmap[i].pin,
			intrmap[i].polarity,
			intrmap[i].trigtype,
			intrmap[i].flags);
	}

	vpe_local_setup(numvpes);
}

void __init gic_init(unsigned long gic_base_addr,
		     unsigned long gic_addrspace_size,
		     struct gic_intr_map *intr_map, unsigned int intr_map_size,
		     unsigned int irqbase)
{
	unsigned int gicconfig;
	int numvpes, numintrs;

	_gic_base = (unsigned long) ioremap_nocache(gic_base_addr,
						    gic_addrspace_size);
	gic_irq_base = irqbase;

	GICREAD(GIC_REG(SHARED, GIC_SH_CONFIG), gicconfig);
	numintrs = (gicconfig & GIC_SH_CONFIG_NUMINTRS_MSK) >>
		   GIC_SH_CONFIG_NUMINTRS_SHF;
	numintrs = ((numintrs + 1) * 8);

	numvpes = (gicconfig & GIC_SH_CONFIG_NUMVPES_MSK) >>
		  GIC_SH_CONFIG_NUMVPES_SHF;

	gic_basic_init(numintrs, numvpes, intr_map, intr_map_size);

	gic_platform_init(numintrs, &gic_irq_controller);
}
Commit	Line	Data
2299c49d SH	1	/*
	2	* This file is subject to the terms and conditions of the GNU General Public
	3	* License. See the file "COPYING" in the main directory of this archive
	4	* for more details.
	5	*
	6	* Copyright (C) 2008 Ralf Baechle (ralf@linux-mips.org)
	7	* Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
	8	*/
39b8d525 RB	9	#include <linux/bitmap.h>
39b8d525 RB	10	#include <linux/init.h>
631330f5	11	#include <linux/smp.h>
ca4d3e67	12	#include <linux/irq.h>
39b8d525 RB	13
	14	#include <asm/io.h>
	15	#include <asm/gic.h>
	16	#include <asm/gcmpregs.h>
39b8d525 RB	17	#include <linux/hardirq.h>
	18	#include <asm-generic/bitops/find.h>
	19
0b271f56 SH	20	unsigned long _gic_base;
	21	unsigned int gic_irq_base;
	22	unsigned int gic_irq_flags[GIC_NUM_INTRS];
39b8d525	23
0b271f56	24	static struct gic_pcpu_mask pcpu_masks[NR_CPUS];
39b8d525 RB	25	static struct gic_pending_regs pending_regs[NR_CPUS];
	26	static struct gic_intrmask_regs intrmask_regs[NR_CPUS];
	27
39b8d525 RB	28	void gic_send_ipi(unsigned int intr)
39b8d525 RB	29	{
39b8d525	30	GICWRITE(GIC_REG(SHARED, GIC_SH_WEDGE), 0x80000000 \| intr);
39b8d525 RB	31	}
39b8d525 RB	32
7098f748	33	static void __init vpe_local_setup(unsigned int numvpes)
39b8d525	34	{
2299c49d SH	35	unsigned long timer_interrupt = GIC_INT_TMR;
2299c49d SH	36	unsigned long perf_interrupt = GIC_INT_PERFCTR;
39b8d525	37	unsigned int vpe_ctl;
2299c49d	38	int i;
39b8d525 RB	39
	40	/*
	41	* Setup the default performance counter timer interrupts
	42	* for all VPEs
	43	*/
	44	for (i = 0; i < numvpes; i++) {
	45	GICWRITE(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), i);
	46
	47	/* Are Interrupts locally routable? */
	48	GICREAD(GIC_REG(VPE_OTHER, GIC_VPE_CTL), vpe_ctl);
	49	if (vpe_ctl & GIC_VPE_CTL_TIMER_RTBL_MSK)
	50	GICWRITE(GIC_REG(VPE_OTHER, GIC_VPE_TIMER_MAP),
	51	GIC_MAP_TO_PIN_MSK \| timer_interrupt);
	52
	53	if (vpe_ctl & GIC_VPE_CTL_PERFCNT_RTBL_MSK)
	54	GICWRITE(GIC_REG(VPE_OTHER, GIC_VPE_PERFCTR_MAP),
	55	GIC_MAP_TO_PIN_MSK \| perf_interrupt);
	56	}
	57	}
	58
	59	unsigned int gic_get_int(void)
	60	{
	61	unsigned int i;
	62	unsigned long pending, intrmask, *pcpu_mask;
	63	unsigned long pending_abs, intrmask_abs;
	64
	65	/* Get per-cpu bitmaps */
	66	pending = pending_regs[smp_processor_id()].pending;
	67	intrmask = intrmask_regs[smp_processor_id()].intrmask;
	68	pcpu_mask = pcpu_masks[smp_processor_id()].pcpu_mask;
	69
	70	pending_abs = (unsigned long *) GIC_REG_ABS_ADDR(SHARED,
	71	GIC_SH_PEND_31_0_OFS);
	72	intrmask_abs = (unsigned long *) GIC_REG_ABS_ADDR(SHARED,
	73	GIC_SH_MASK_31_0_OFS);
	74
	75	for (i = 0; i < BITS_TO_LONGS(GIC_NUM_INTRS); i++) {
	76	GICREAD(*pending_abs, pending[i]);
	77	GICREAD(*intrmask_abs, intrmask[i]);
	78	pending_abs++;
	79	intrmask_abs++;
	80	}
	81
	82	bitmap_and(pending, pending, intrmask, GIC_NUM_INTRS);
	83	bitmap_and(pending, pending, pcpu_mask, GIC_NUM_INTRS);
	84
2299c49d	85	return find_first_bit(pending, GIC_NUM_INTRS);
39b8d525 RB	86	}
39b8d525 RB	87
161d049e	88	static void gic_mask_irq(struct irq_data *d)
39b8d525	89	{
2299c49d	90	GIC_CLR_INTR_MASK(d->irq - gic_irq_base);
39b8d525 RB	91	}
39b8d525 RB	92
161d049e	93	static void gic_unmask_irq(struct irq_data *d)
39b8d525	94	{
2299c49d	95	GIC_SET_INTR_MASK(d->irq - gic_irq_base);
39b8d525 RB	96	}
	97
	98	#ifdef CONFIG_SMP
39b8d525 RB	99	static DEFINE_SPINLOCK(gic_lock);
39b8d525 RB	100
161d049e TG	101	static int gic_set_affinity(struct irq_data d, const struct cpumask cpumask,
161d049e TG	102	bool force)
39b8d525	103	{
2299c49d	104	unsigned int irq = (d->irq - gic_irq_base);
39b8d525 RB	105	cpumask_t tmp = CPU_MASK_NONE;
	106	unsigned long flags;
	107	int i;
	108
0de26520	109	cpumask_and(&tmp, cpumask, cpu_online_mask);
39b8d525	110	if (cpus_empty(tmp))
d5dedd45	111	return -1;
39b8d525 RB	112
	113	/* Assumption : cpumask refers to a single CPU */
	114	spin_lock_irqsave(&gic_lock, flags);
	115	for (;;) {
	116	/* Re-route this IRQ */
	117	GIC_SH_MAP_TO_VPE_SMASK(irq, first_cpu(tmp));
	118
39b8d525 RB	119	/* Update the pcpu_masks */
	120	for (i = 0; i < NR_CPUS; i++)
	121	clear_bit(irq, pcpu_masks[i].pcpu_mask);
	122	set_bit(irq, pcpu_masks[first_cpu(tmp)].pcpu_mask);
	123
	124	}
161d049e	125	cpumask_copy(d->affinity, cpumask);
39b8d525 RB	126	spin_unlock_irqrestore(&gic_lock, flags);
39b8d525 RB	127
161d049e	128	return IRQ_SET_MASK_OK_NOCOPY;
39b8d525 RB	129	}
	130	#endif
	131
	132	static struct irq_chip gic_irq_controller = {
161d049e TG	133	.name = "MIPS GIC",
	134	.irq_ack = gic_irq_ack,
	135	.irq_mask = gic_mask_irq,
	136	.irq_mask_ack = gic_mask_irq,
	137	.irq_unmask = gic_unmask_irq,
	138	.irq_eoi = gic_unmask_irq,
39b8d525	139	#ifdef CONFIG_SMP
161d049e	140	.irq_set_affinity = gic_set_affinity,
39b8d525 RB	141	#endif
	142	};
	143
7098f748 CD	144	static void __init gic_setup_intr(unsigned int intr, unsigned int cpu,
	145	unsigned int pin, unsigned int polarity, unsigned int trigtype,
	146	unsigned int flags)
39b8d525 RB	147	{
	148	/* Setup Intr to Pin mapping */
	149	if (pin & GIC_MAP_TO_NMI_MSK) {
	150	GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_MAP_TO_PIN(intr)), pin);
	151	/* FIXME: hack to route NMI to all cpu's */
	152	for (cpu = 0; cpu < NR_CPUS; cpu += 32) {
	153	GICWRITE(GIC_REG_ADDR(SHARED,
	154	GIC_SH_MAP_TO_VPE_REG_OFF(intr, cpu)),
	155	0xffffffff);
	156	}
	157	} else {
	158	GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_MAP_TO_PIN(intr)),
	159	GIC_MAP_TO_PIN_MSK \| pin);
	160	/* Setup Intr to CPU mapping */
	161	GIC_SH_MAP_TO_VPE_SMASK(intr, cpu);
	162	}
	163
	164	/* Setup Intr Polarity */
	165	GIC_SET_POLARITY(intr, polarity);
	166
	167	/* Setup Intr Trigger Type */
	168	GIC_SET_TRIGGER(intr, trigtype);
	169
	170	/* Init Intr Masks */
7098f748	171	GIC_CLR_INTR_MASK(intr);
2299c49d	172
7098f748 CD	173	/* Initialise per-cpu Interrupt software masks */
	174	if (flags & GIC_FLAG_IPI)
	175	set_bit(intr, pcpu_masks[cpu].pcpu_mask);
	176	if (flags & GIC_FLAG_TRANSPARENT)
	177	GIC_SET_INTR_MASK(intr);
	178	if (trigtype == GIC_TRIG_EDGE)
0b271f56	179	gic_irq_flags[intr] \|= GIC_TRIG_EDGE;
39b8d525 RB	180	}
39b8d525 RB	181
7098f748 CD	182	static void __init gic_basic_init(int numintrs, int numvpes,
7098f748 CD	183	struct gic_intr_map *intrmap, int mapsize)
39b8d525 RB	184	{
	185	unsigned int i, cpu;
	186
	187	/* Setup defaults */
7098f748	188	for (i = 0; i < numintrs; i++) {
39b8d525 RB	189	GIC_SET_POLARITY(i, GIC_POL_POS);
39b8d525 RB	190	GIC_SET_TRIGGER(i, GIC_TRIG_LEVEL);
7098f748 CD	191	GIC_CLR_INTR_MASK(i);
	192	if (i < GIC_NUM_INTRS)
	193	gic_irq_flags[i] = 0;
39b8d525 RB	194	}
	195
	196	/* Setup specifics */
7098f748 CD	197	for (i = 0; i < mapsize; i++) {
7098f748 CD	198	cpu = intrmap[i].cpunum;
863cb9ba	199	if (cpu == GIC_UNUSED)
39b8d525	200	continue;
7098f748	201	if (cpu == 0 && i != 0 && intrmap[i].flags == 0)
a214cef9	202	continue;
7098f748 CD	203	gic_setup_intr(i,
	204	intrmap[i].cpunum,
	205	intrmap[i].pin,
	206	intrmap[i].polarity,
	207	intrmap[i].trigtype,
	208	intrmap[i].flags);
39b8d525 RB	209	}
	210
	211	vpe_local_setup(numvpes);
39b8d525 RB	212	}
	213
	214	void __init gic_init(unsigned long gic_base_addr,
	215	unsigned long gic_addrspace_size,
	216	struct gic_intr_map *intr_map, unsigned int intr_map_size,
	217	unsigned int irqbase)
	218	{
	219	unsigned int gicconfig;
7098f748	220	int numvpes, numintrs;
39b8d525 RB	221
	222	_gic_base = (unsigned long) ioremap_nocache(gic_base_addr,
	223	gic_addrspace_size);
0b271f56	224	gic_irq_base = irqbase;
39b8d525 RB	225
	226	GICREAD(GIC_REG(SHARED, GIC_SH_CONFIG), gicconfig);
	227	numintrs = (gicconfig & GIC_SH_CONFIG_NUMINTRS_MSK) >>
	228	GIC_SH_CONFIG_NUMINTRS_SHF;
	229	numintrs = ((numintrs + 1) * 8);
	230
	231	numvpes = (gicconfig & GIC_SH_CONFIG_NUMVPES_MSK) >>
	232	GIC_SH_CONFIG_NUMVPES_SHF;
	233
7098f748	234	gic_basic_init(numintrs, numvpes, intr_map, intr_map_size);
0b271f56 SH	235
0b271f56 SH	236	gic_platform_init(numintrs, &gic_irq_controller);
39b8d525	237	}