[mirror_ubuntu-zesty-kernel.git] / arch / mips / kernel / irq-msc01.c

/*
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 *
 * Copyright (c) 2004 MIPS Inc
 * Author: chris@mips.com
 *
 * Copyright (C) 2004, 06 Ralf Baechle <ralf@linux-mips.org>
 */
#include <linux/module.h>
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/kernel_stat.h>
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/msc01_ic.h>
#include <asm/traps.h>

static unsigned long _icctrl_msc;
#define MSC01_IC_REG_BASE	_icctrl_msc

#define MSCIC_WRITE(reg, data)	do { *(volatile u32 *)(reg) = data; } while (0)
#define MSCIC_READ(reg, data)	do { data = *(volatile u32 *)(reg); } while (0)

static unsigned int irq_base;

/* mask off an interrupt */
static inline void mask_msc_irq(unsigned int irq)
{
	if (irq < (irq_base + 32))
		MSCIC_WRITE(MSC01_IC_DISL, 1<<(irq - irq_base));
	else
		MSCIC_WRITE(MSC01_IC_DISH, 1<<(irq - irq_base - 32));
}

/* unmask an interrupt */
static inline void unmask_msc_irq(unsigned int irq)
{
	if (irq < (irq_base + 32))
		MSCIC_WRITE(MSC01_IC_ENAL, 1<<(irq - irq_base));
	else
		MSCIC_WRITE(MSC01_IC_ENAH, 1<<(irq - irq_base - 32));
}

/*
 * Masks and ACKs an IRQ
 */
static void level_mask_and_ack_msc_irq(unsigned int irq)
{
	mask_msc_irq(irq);
	if (!cpu_has_veic)
		MSCIC_WRITE(MSC01_IC_EOI, 0);
	/* This actually needs to be a call into platform code */
	smtc_im_ack_irq(irq);
}

/*
 * Masks and ACKs an IRQ
 */
static void edge_mask_and_ack_msc_irq(unsigned int irq)
{
	mask_msc_irq(irq);
	if (!cpu_has_veic)
		MSCIC_WRITE(MSC01_IC_EOI, 0);
	else {
		u32 r;
		MSCIC_READ(MSC01_IC_SUP+irq*8, r);
		MSCIC_WRITE(MSC01_IC_SUP+irq*8, r | ~MSC01_IC_SUP_EDGE_BIT);
		MSCIC_WRITE(MSC01_IC_SUP+irq*8, r);
	}
	smtc_im_ack_irq(irq);
}

/*
 * End IRQ processing
 */
static void end_msc_irq(unsigned int irq)
{
	if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
		unmask_msc_irq(irq);
}

/*
 * Interrupt handler for interrupts coming from SOC-it.
 */
void ll_msc_irq(void)
{
 	unsigned int irq;

	/* read the interrupt vector register */
	MSCIC_READ(MSC01_IC_VEC, irq);
	if (irq < 64)
		do_IRQ(irq + irq_base);
	else {
		/* Ignore spurious interrupt */
	}
}

static void msc_bind_eic_interrupt(int irq, int set)
{
	MSCIC_WRITE(MSC01_IC_RAMW,
		    (irq<<MSC01_IC_RAMW_ADDR_SHF) | (set<<MSC01_IC_RAMW_DATA_SHF));
}

static struct irq_chip msc_levelirq_type = {
	.name = "SOC-it-Level",
	.ack = level_mask_and_ack_msc_irq,
	.mask = mask_msc_irq,
	.mask_ack = level_mask_and_ack_msc_irq,
	.unmask = unmask_msc_irq,
	.eoi = unmask_msc_irq,
	.end = end_msc_irq,
};

static struct irq_chip msc_edgeirq_type = {
	.name = "SOC-it-Edge",
	.ack = edge_mask_and_ack_msc_irq,
	.mask = mask_msc_irq,
	.mask_ack = edge_mask_and_ack_msc_irq,
	.unmask = unmask_msc_irq,
	.eoi = unmask_msc_irq,
	.end = end_msc_irq,
};


void __init init_msc_irqs(unsigned long icubase, unsigned int irqbase, msc_irqmap_t *imp, int nirq)
{
	_icctrl_msc = (unsigned long) ioremap(icubase, 0x40000);

	/* Reset interrupt controller - initialises all registers to 0 */
	MSCIC_WRITE(MSC01_IC_RST, MSC01_IC_RST_RST_BIT);

	board_bind_eic_interrupt = &msc_bind_eic_interrupt;

	for (; nirq >= 0; nirq--, imp++) {
		int n = imp->im_irq;

		switch (imp->im_type) {
		case MSC01_IRQ_EDGE:
			set_irq_chip_and_handler_name(irqbase + n,
				&msc_edgeirq_type, handle_edge_irq, "edge");
			if (cpu_has_veic)
				MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT);
			else
				MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT | imp->im_lvl);
			break;
		case MSC01_IRQ_LEVEL:
			set_irq_chip_and_handler_name(irqbase+n,
				&msc_levelirq_type, handle_level_irq, "level");
			if (cpu_has_veic)
				MSCIC_WRITE(MSC01_IC_SUP+n*8, 0);
			else
				MSCIC_WRITE(MSC01_IC_SUP+n*8, imp->im_lvl);
		}
	}

	irq_base = irqbase;

	MSCIC_WRITE(MSC01_IC_GENA, MSC01_IC_GENA_GENA_BIT);	/* Enable interrupt generation */

}
Commit	Line	Data
1da177e4	1	/*
1da177e4 LT	2	* This program is free software; you can redistribute it and/or modify it
	3	* under the terms of the GNU General Public License as published by the
	4	* Free Software Foundation; either version 2 of the License, or (at your
	5	* option) any later version.
27f76819 RB	6	*
	7	* Copyright (c) 2004 MIPS Inc
	8	* Author: chris@mips.com
	9	*
	10	* Copyright (C) 2004, 06 Ralf Baechle <ralf@linux-mips.org>
1da177e4 LT	11	*/
	12	#include <linux/module.h>
	13	#include <linux/interrupt.h>
	14	#include <linux/kernel.h>
1da177e4 LT	15	#include <linux/sched.h>
	16	#include <linux/kernel_stat.h>
	17	#include <asm/io.h>
	18	#include <asm/irq.h>
	19	#include <asm/msc01_ic.h>
411ba7fc	20	#include <asm/traps.h>
1da177e4 LT	21
	22	static unsigned long _icctrl_msc;
	23	#define MSC01_IC_REG_BASE _icctrl_msc
	24
	25	#define MSCIC_WRITE(reg, data) do { (volatile u32 )(reg) = data; } while (0)
	26	#define MSCIC_READ(reg, data) do { data = (volatile u32 )(reg); } while (0)
	27
	28	static unsigned int irq_base;
	29
	30	/* mask off an interrupt */
	31	static inline void mask_msc_irq(unsigned int irq)
	32	{
	33	if (irq < (irq_base + 32))
	34	MSCIC_WRITE(MSC01_IC_DISL, 1<<(irq - irq_base));
	35	else
	36	MSCIC_WRITE(MSC01_IC_DISH, 1<<(irq - irq_base - 32));
	37	}
	38
	39	/* unmask an interrupt */
	40	static inline void unmask_msc_irq(unsigned int irq)
	41	{
	42	if (irq < (irq_base + 32))
	43	MSCIC_WRITE(MSC01_IC_ENAL, 1<<(irq - irq_base));
	44	else
	45	MSCIC_WRITE(MSC01_IC_ENAH, 1<<(irq - irq_base - 32));
	46	}
	47
1da177e4 LT	48	/*
	49	* Masks and ACKs an IRQ
	50	*/
	51	static void level_mask_and_ack_msc_irq(unsigned int irq)
	52	{
	53	mask_msc_irq(irq);
e01402b1	54	if (!cpu_has_veic)
1da177e4	55	MSCIC_WRITE(MSC01_IC_EOI, 0);
41c594ab	56	/* This actually needs to be a call into platform code */
1146fe30	57	smtc_im_ack_irq(irq);
1da177e4 LT	58	}
	59
	60	/*
	61	* Masks and ACKs an IRQ
	62	*/
	63	static void edge_mask_and_ack_msc_irq(unsigned int irq)
	64	{
	65	mask_msc_irq(irq);
e01402b1	66	if (!cpu_has_veic)
1da177e4 LT	67	MSCIC_WRITE(MSC01_IC_EOI, 0);
	68	else {
	69	u32 r;
	70	MSCIC_READ(MSC01_IC_SUP+irq*8, r);
	71	MSCIC_WRITE(MSC01_IC_SUP+irq*8, r \| ~MSC01_IC_SUP_EDGE_BIT);
	72	MSCIC_WRITE(MSC01_IC_SUP+irq*8, r);
	73	}
1146fe30	74	smtc_im_ack_irq(irq);
1da177e4 LT	75	}
	76
	77	/*
	78	* End IRQ processing
	79	*/
	80	static void end_msc_irq(unsigned int irq)
	81	{
	82	if (!(irq_desc[irq].status & (IRQ_DISABLED\|IRQ_INPROGRESS)))
	83	unmask_msc_irq(irq);
	84	}
	85
	86	/*
	87	* Interrupt handler for interrupts coming from SOC-it.
	88	*/
937a8015	89	void ll_msc_irq(void)
1da177e4 LT	90	{
	91	unsigned int irq;
	92
	93	/* read the interrupt vector register */
	94	MSCIC_READ(MSC01_IC_VEC, irq);
	95	if (irq < 64)
937a8015	96	do_IRQ(irq + irq_base);
1da177e4 LT	97	else {
	98	/* Ignore spurious interrupt */
	99	}
	100	}
	101
411ba7fc	102	static void msc_bind_eic_interrupt(int irq, int set)
1da177e4 LT	103	{
	104	MSCIC_WRITE(MSC01_IC_RAMW,
	105	(irq<<MSC01_IC_RAMW_ADDR_SHF) \| (set<<MSC01_IC_RAMW_DATA_SHF));
	106	}
	107
411ba7fc	108	static struct irq_chip msc_levelirq_type = {
70d21cde	109	.name = "SOC-it-Level",
8ab00b9a	110	.ack = level_mask_and_ack_msc_irq,
1603b5ac AN	111	.mask = mask_msc_irq,
	112	.mask_ack = level_mask_and_ack_msc_irq,
	113	.unmask = unmask_msc_irq,
1417836e	114	.eoi = unmask_msc_irq,
8ab00b9a	115	.end = end_msc_irq,
1da177e4 LT	116	};
1da177e4 LT	117
411ba7fc	118	static struct irq_chip msc_edgeirq_type = {
70d21cde	119	.name = "SOC-it-Edge",
8ab00b9a	120	.ack = edge_mask_and_ack_msc_irq,
1603b5ac AN	121	.mask = mask_msc_irq,
	122	.mask_ack = edge_mask_and_ack_msc_irq,
	123	.unmask = unmask_msc_irq,
1417836e	124	.eoi = unmask_msc_irq,
8ab00b9a	125	.end = end_msc_irq,
1da177e4 LT	126	};
	127
	128
d725cf38	129	void __init init_msc_irqs(unsigned long icubase, unsigned int irqbase, msc_irqmap_t *imp, int nirq)
1da177e4	130	{
49a89efb	131	_icctrl_msc = (unsigned long) ioremap(icubase, 0x40000);
1da177e4 LT	132
	133	/* Reset interrupt controller - initialises all registers to 0 */
	134	MSCIC_WRITE(MSC01_IC_RST, MSC01_IC_RST_RST_BIT);
	135
	136	board_bind_eic_interrupt = &msc_bind_eic_interrupt;
	137
	138	for (; nirq >= 0; nirq--, imp++) {
	139	int n = imp->im_irq;
	140
	141	switch (imp->im_type) {
	142	case MSC01_IRQ_EDGE:
c87e0909 RB	143	set_irq_chip_and_handler_name(irqbase + n,
c87e0909 RB	144	&msc_edgeirq_type, handle_edge_irq, "edge");
e01402b1	145	if (cpu_has_veic)
1da177e4 LT	146	MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT);
	147	else
	148	MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT \| imp->im_lvl);
	149	break;
	150	case MSC01_IRQ_LEVEL:
c87e0909 RB	151	set_irq_chip_and_handler_name(irqbase+n,
c87e0909 RB	152	&msc_levelirq_type, handle_level_irq, "level");
e01402b1	153	if (cpu_has_veic)
1da177e4 LT	154	MSCIC_WRITE(MSC01_IC_SUP+n*8, 0);
	155	else
	156	MSCIC_WRITE(MSC01_IC_SUP+n*8, imp->im_lvl);
	157	}
	158	}
	159
d725cf38	160	irq_base = irqbase;
1da177e4 LT	161
	162	MSCIC_WRITE(MSC01_IC_GENA, MSC01_IC_GENA_GENA_BIT); /* Enable interrupt generation */
	163
	164	}