[mirror_ubuntu-artful-kernel.git] / arch / mips / kernel / irq-msc01.c

/*
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 *
 * Copyright (c) 2004 MIPS Inc
 * Author: chris@mips.com
 *
 * Copyright (C) 2004, 06 Ralf Baechle <ralf@linux-mips.org>
 */
#include <linux/module.h>
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/kernel_stat.h>
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/msc01_ic.h>
#include <asm/traps.h>

static unsigned long _icctrl_msc;
#define MSC01_IC_REG_BASE	_icctrl_msc

#define MSCIC_WRITE(reg, data)	do { *(volatile u32 *)(reg) = data; } while (0)
#define MSCIC_READ(reg, data)	do { data = *(volatile u32 *)(reg); } while (0)

static unsigned int irq_base;

/* mask off an interrupt */
static inline void mask_msc_irq(struct irq_data *d)
{
	unsigned int irq = d->irq;

	if (irq < (irq_base + 32))
		MSCIC_WRITE(MSC01_IC_DISL, 1<<(irq - irq_base));
	else
		MSCIC_WRITE(MSC01_IC_DISH, 1<<(irq - irq_base - 32));
}

/* unmask an interrupt */
static inline void unmask_msc_irq(struct irq_data *d)
{
	unsigned int irq = d->irq;

	if (irq < (irq_base + 32))
		MSCIC_WRITE(MSC01_IC_ENAL, 1<<(irq - irq_base));
	else
		MSCIC_WRITE(MSC01_IC_ENAH, 1<<(irq - irq_base - 32));
}

/*
 * Masks and ACKs an IRQ
 */
static void level_mask_and_ack_msc_irq(struct irq_data *d)
{
	unsigned int irq = d->irq;

	mask_msc_irq(d);
	if (!cpu_has_veic)
		MSCIC_WRITE(MSC01_IC_EOI, 0);
	/* This actually needs to be a call into platform code */
	smtc_im_ack_irq(irq);
}

/*
 * Masks and ACKs an IRQ
 */
static void edge_mask_and_ack_msc_irq(struct irq_data *d)
{
	unsigned int irq = d->irq;

	mask_msc_irq(d);
	if (!cpu_has_veic)
		MSCIC_WRITE(MSC01_IC_EOI, 0);
	else {
		u32 r;
		MSCIC_READ(MSC01_IC_SUP+irq*8, r);
		MSCIC_WRITE(MSC01_IC_SUP+irq*8, r | ~MSC01_IC_SUP_EDGE_BIT);
		MSCIC_WRITE(MSC01_IC_SUP+irq*8, r);
	}
	smtc_im_ack_irq(irq);
}

/*
 * Interrupt handler for interrupts coming from SOC-it.
 */
void ll_msc_irq(void)
{
 	unsigned int irq;

	/* read the interrupt vector register */
	MSCIC_READ(MSC01_IC_VEC, irq);
	if (irq < 64)
		do_IRQ(irq + irq_base);
	else {
		/* Ignore spurious interrupt */
	}
}

static void msc_bind_eic_interrupt(int irq, int set)
{
	MSCIC_WRITE(MSC01_IC_RAMW,
		    (irq<<MSC01_IC_RAMW_ADDR_SHF) | (set<<MSC01_IC_RAMW_DATA_SHF));
}

static struct irq_chip msc_levelirq_type = {
	.name = "SOC-it-Level",
	.irq_ack = level_mask_and_ack_msc_irq,
	.irq_mask = mask_msc_irq,
	.irq_mask_ack = level_mask_and_ack_msc_irq,
	.irq_unmask = unmask_msc_irq,
	.irq_eoi = unmask_msc_irq,
};

static struct irq_chip msc_edgeirq_type = {
	.name = "SOC-it-Edge",
	.irq_ack = edge_mask_and_ack_msc_irq,
	.irq_mask = mask_msc_irq,
	.irq_mask_ack = edge_mask_and_ack_msc_irq,
	.irq_unmask = unmask_msc_irq,
	.irq_eoi = unmask_msc_irq,
};


void __init init_msc_irqs(unsigned long icubase, unsigned int irqbase, msc_irqmap_t *imp, int nirq)
{
	_icctrl_msc = (unsigned long) ioremap(icubase, 0x40000);

	/* Reset interrupt controller - initialises all registers to 0 */
	MSCIC_WRITE(MSC01_IC_RST, MSC01_IC_RST_RST_BIT);

	board_bind_eic_interrupt = &msc_bind_eic_interrupt;

	for (; nirq >= 0; nirq--, imp++) {
		int n = imp->im_irq;

		switch (imp->im_type) {
		case MSC01_IRQ_EDGE:
			irq_set_chip_and_handler_name(irqbase + n,
						      &msc_edgeirq_type,
						      handle_edge_irq,
						      "edge");
			if (cpu_has_veic)
				MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT);
			else
				MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT | imp->im_lvl);
			break;
		case MSC01_IRQ_LEVEL:
			irq_set_chip_and_handler_name(irqbase + n,
						      &msc_levelirq_type,
						      handle_level_irq,
						      "level");
			if (cpu_has_veic)
				MSCIC_WRITE(MSC01_IC_SUP+n*8, 0);
			else
				MSCIC_WRITE(MSC01_IC_SUP+n*8, imp->im_lvl);
		}
	}

	irq_base = irqbase;

	MSCIC_WRITE(MSC01_IC_GENA, MSC01_IC_GENA_GENA_BIT);	/* Enable interrupt generation */

}
Commit	Line	Data
1da177e4	1	/*
1da177e4 LT	2	* This program is free software; you can redistribute it and/or modify it
	3	* under the terms of the GNU General Public License as published by the
	4	* Free Software Foundation; either version 2 of the License, or (at your
	5	* option) any later version.
27f76819 RB	6	*
	7	* Copyright (c) 2004 MIPS Inc
	8	* Author: chris@mips.com
	9	*
	10	* Copyright (C) 2004, 06 Ralf Baechle <ralf@linux-mips.org>
1da177e4 LT	11	*/
	12	#include <linux/module.h>
	13	#include <linux/interrupt.h>
	14	#include <linux/kernel.h>
1da177e4 LT	15	#include <linux/sched.h>
	16	#include <linux/kernel_stat.h>
	17	#include <asm/io.h>
	18	#include <asm/irq.h>
	19	#include <asm/msc01_ic.h>
411ba7fc	20	#include <asm/traps.h>
1da177e4 LT	21
	22	static unsigned long _icctrl_msc;
	23	#define MSC01_IC_REG_BASE _icctrl_msc
	24
	25	#define MSCIC_WRITE(reg, data) do { (volatile u32 )(reg) = data; } while (0)
	26	#define MSCIC_READ(reg, data) do { data = (volatile u32 )(reg); } while (0)
	27
	28	static unsigned int irq_base;
	29
	30	/* mask off an interrupt */
e15883da	31	static inline void mask_msc_irq(struct irq_data *d)
1da177e4	32	{
e15883da TG	33	unsigned int irq = d->irq;
e15883da TG	34
1da177e4 LT	35	if (irq < (irq_base + 32))
	36	MSCIC_WRITE(MSC01_IC_DISL, 1<<(irq - irq_base));
	37	else
	38	MSCIC_WRITE(MSC01_IC_DISH, 1<<(irq - irq_base - 32));
	39	}
	40
	41	/* unmask an interrupt */
e15883da	42	static inline void unmask_msc_irq(struct irq_data *d)
1da177e4	43	{
e15883da TG	44	unsigned int irq = d->irq;
e15883da TG	45
1da177e4 LT	46	if (irq < (irq_base + 32))
	47	MSCIC_WRITE(MSC01_IC_ENAL, 1<<(irq - irq_base));
	48	else
	49	MSCIC_WRITE(MSC01_IC_ENAH, 1<<(irq - irq_base - 32));
	50	}
	51
1da177e4 LT	52	/*
	53	* Masks and ACKs an IRQ
	54	*/
e15883da	55	static void level_mask_and_ack_msc_irq(struct irq_data *d)
1da177e4	56	{
e15883da TG	57	unsigned int irq = d->irq;
	58
	59	mask_msc_irq(d);
e01402b1	60	if (!cpu_has_veic)
1da177e4	61	MSCIC_WRITE(MSC01_IC_EOI, 0);
41c594ab	62	/* This actually needs to be a call into platform code */
1146fe30	63	smtc_im_ack_irq(irq);
1da177e4 LT	64	}
	65
	66	/*
	67	* Masks and ACKs an IRQ
	68	*/
e15883da	69	static void edge_mask_and_ack_msc_irq(struct irq_data *d)
1da177e4	70	{
e15883da TG	71	unsigned int irq = d->irq;
	72
	73	mask_msc_irq(d);
e01402b1	74	if (!cpu_has_veic)
1da177e4 LT	75	MSCIC_WRITE(MSC01_IC_EOI, 0);
	76	else {
	77	u32 r;
	78	MSCIC_READ(MSC01_IC_SUP+irq*8, r);
	79	MSCIC_WRITE(MSC01_IC_SUP+irq*8, r \| ~MSC01_IC_SUP_EDGE_BIT);
	80	MSCIC_WRITE(MSC01_IC_SUP+irq*8, r);
	81	}
1146fe30	82	smtc_im_ack_irq(irq);
1da177e4 LT	83	}
1da177e4 LT	84
1da177e4 LT	85	/*
	86	* Interrupt handler for interrupts coming from SOC-it.
	87	*/
937a8015	88	void ll_msc_irq(void)
1da177e4 LT	89	{
	90	unsigned int irq;
	91
	92	/* read the interrupt vector register */
	93	MSCIC_READ(MSC01_IC_VEC, irq);
	94	if (irq < 64)
937a8015	95	do_IRQ(irq + irq_base);
1da177e4 LT	96	else {
	97	/* Ignore spurious interrupt */
	98	}
	99	}
	100
411ba7fc	101	static void msc_bind_eic_interrupt(int irq, int set)
1da177e4 LT	102	{
	103	MSCIC_WRITE(MSC01_IC_RAMW,
	104	(irq<<MSC01_IC_RAMW_ADDR_SHF) \| (set<<MSC01_IC_RAMW_DATA_SHF));
	105	}
	106
411ba7fc	107	static struct irq_chip msc_levelirq_type = {
70d21cde	108	.name = "SOC-it-Level",
e15883da TG	109	.irq_ack = level_mask_and_ack_msc_irq,
	110	.irq_mask = mask_msc_irq,
	111	.irq_mask_ack = level_mask_and_ack_msc_irq,
	112	.irq_unmask = unmask_msc_irq,
	113	.irq_eoi = unmask_msc_irq,
1da177e4 LT	114	};
1da177e4 LT	115
411ba7fc	116	static struct irq_chip msc_edgeirq_type = {
70d21cde	117	.name = "SOC-it-Edge",
e15883da TG	118	.irq_ack = edge_mask_and_ack_msc_irq,
	119	.irq_mask = mask_msc_irq,
	120	.irq_mask_ack = edge_mask_and_ack_msc_irq,
	121	.irq_unmask = unmask_msc_irq,
	122	.irq_eoi = unmask_msc_irq,
1da177e4 LT	123	};
	124
	125
d725cf38	126	void __init init_msc_irqs(unsigned long icubase, unsigned int irqbase, msc_irqmap_t *imp, int nirq)
1da177e4	127	{
49a89efb	128	_icctrl_msc = (unsigned long) ioremap(icubase, 0x40000);
1da177e4 LT	129
	130	/* Reset interrupt controller - initialises all registers to 0 */
	131	MSCIC_WRITE(MSC01_IC_RST, MSC01_IC_RST_RST_BIT);
	132
	133	board_bind_eic_interrupt = &msc_bind_eic_interrupt;
	134
	135	for (; nirq >= 0; nirq--, imp++) {
	136	int n = imp->im_irq;
	137
	138	switch (imp->im_type) {
	139	case MSC01_IRQ_EDGE:
e4ec7989 TG	140	irq_set_chip_and_handler_name(irqbase + n,
	141	&msc_edgeirq_type,
	142	handle_edge_irq,
	143	"edge");
e01402b1	144	if (cpu_has_veic)
1da177e4 LT	145	MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT);
	146	else
	147	MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT \| imp->im_lvl);
	148	break;
	149	case MSC01_IRQ_LEVEL:
e4ec7989 TG	150	irq_set_chip_and_handler_name(irqbase + n,
	151	&msc_levelirq_type,
	152	handle_level_irq,
	153	"level");
e01402b1	154	if (cpu_has_veic)
1da177e4 LT	155	MSCIC_WRITE(MSC01_IC_SUP+n*8, 0);
	156	else
	157	MSCIC_WRITE(MSC01_IC_SUP+n*8, imp->im_lvl);
	158	}
	159	}
	160
d725cf38	161	irq_base = irqbase;
1da177e4 LT	162
	163	MSCIC_WRITE(MSC01_IC_GENA, MSC01_IC_GENA_GENA_BIT); /* Enable interrupt generation */
	164
	165	}