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2874c5fd | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
1da177e4 | 2 | /* |
27f76819 RB |
3 | * |
4 | * Copyright (c) 2004 MIPS Inc | |
5 | * Author: chris@mips.com | |
6 | * | |
7 | * Copyright (C) 2004, 06 Ralf Baechle <ralf@linux-mips.org> | |
1da177e4 | 8 | */ |
1da177e4 LT |
9 | #include <linux/interrupt.h> |
10 | #include <linux/kernel.h> | |
1da177e4 LT |
11 | #include <linux/sched.h> |
12 | #include <linux/kernel_stat.h> | |
13 | #include <asm/io.h> | |
14 | #include <asm/irq.h> | |
15 | #include <asm/msc01_ic.h> | |
411ba7fc | 16 | #include <asm/traps.h> |
1da177e4 LT |
17 | |
18 | static unsigned long _icctrl_msc; | |
19 | #define MSC01_IC_REG_BASE _icctrl_msc | |
20 | ||
21 | #define MSCIC_WRITE(reg, data) do { *(volatile u32 *)(reg) = data; } while (0) | |
22 | #define MSCIC_READ(reg, data) do { data = *(volatile u32 *)(reg); } while (0) | |
23 | ||
24 | static unsigned int irq_base; | |
25 | ||
26 | /* mask off an interrupt */ | |
e15883da | 27 | static inline void mask_msc_irq(struct irq_data *d) |
1da177e4 | 28 | { |
e15883da TG |
29 | unsigned int irq = d->irq; |
30 | ||
1da177e4 LT |
31 | if (irq < (irq_base + 32)) |
32 | MSCIC_WRITE(MSC01_IC_DISL, 1<<(irq - irq_base)); | |
33 | else | |
34 | MSCIC_WRITE(MSC01_IC_DISH, 1<<(irq - irq_base - 32)); | |
35 | } | |
36 | ||
37 | /* unmask an interrupt */ | |
e15883da | 38 | static inline void unmask_msc_irq(struct irq_data *d) |
1da177e4 | 39 | { |
e15883da TG |
40 | unsigned int irq = d->irq; |
41 | ||
1da177e4 LT |
42 | if (irq < (irq_base + 32)) |
43 | MSCIC_WRITE(MSC01_IC_ENAL, 1<<(irq - irq_base)); | |
44 | else | |
45 | MSCIC_WRITE(MSC01_IC_ENAH, 1<<(irq - irq_base - 32)); | |
46 | } | |
47 | ||
1da177e4 LT |
48 | /* |
49 | * Masks and ACKs an IRQ | |
50 | */ | |
e15883da | 51 | static void level_mask_and_ack_msc_irq(struct irq_data *d) |
1da177e4 | 52 | { |
e15883da | 53 | mask_msc_irq(d); |
e01402b1 | 54 | if (!cpu_has_veic) |
1da177e4 LT |
55 | MSCIC_WRITE(MSC01_IC_EOI, 0); |
56 | } | |
57 | ||
58 | /* | |
59 | * Masks and ACKs an IRQ | |
60 | */ | |
e15883da | 61 | static void edge_mask_and_ack_msc_irq(struct irq_data *d) |
1da177e4 | 62 | { |
e15883da TG |
63 | unsigned int irq = d->irq; |
64 | ||
65 | mask_msc_irq(d); | |
e01402b1 | 66 | if (!cpu_has_veic) |
1da177e4 LT |
67 | MSCIC_WRITE(MSC01_IC_EOI, 0); |
68 | else { | |
69 | u32 r; | |
70 | MSCIC_READ(MSC01_IC_SUP+irq*8, r); | |
71 | MSCIC_WRITE(MSC01_IC_SUP+irq*8, r | ~MSC01_IC_SUP_EDGE_BIT); | |
72 | MSCIC_WRITE(MSC01_IC_SUP+irq*8, r); | |
73 | } | |
74 | } | |
75 | ||
1da177e4 LT |
76 | /* |
77 | * Interrupt handler for interrupts coming from SOC-it. | |
78 | */ | |
937a8015 | 79 | void ll_msc_irq(void) |
1da177e4 | 80 | { |
70342287 | 81 | unsigned int irq; |
1da177e4 LT |
82 | |
83 | /* read the interrupt vector register */ | |
84 | MSCIC_READ(MSC01_IC_VEC, irq); | |
85 | if (irq < 64) | |
937a8015 | 86 | do_IRQ(irq + irq_base); |
1da177e4 LT |
87 | else { |
88 | /* Ignore spurious interrupt */ | |
89 | } | |
90 | } | |
91 | ||
411ba7fc | 92 | static void msc_bind_eic_interrupt(int irq, int set) |
1da177e4 LT |
93 | { |
94 | MSCIC_WRITE(MSC01_IC_RAMW, | |
95 | (irq<<MSC01_IC_RAMW_ADDR_SHF) | (set<<MSC01_IC_RAMW_DATA_SHF)); | |
96 | } | |
97 | ||
411ba7fc | 98 | static struct irq_chip msc_levelirq_type = { |
70d21cde | 99 | .name = "SOC-it-Level", |
e15883da TG |
100 | .irq_ack = level_mask_and_ack_msc_irq, |
101 | .irq_mask = mask_msc_irq, | |
102 | .irq_mask_ack = level_mask_and_ack_msc_irq, | |
103 | .irq_unmask = unmask_msc_irq, | |
104 | .irq_eoi = unmask_msc_irq, | |
1da177e4 LT |
105 | }; |
106 | ||
411ba7fc | 107 | static struct irq_chip msc_edgeirq_type = { |
70d21cde | 108 | .name = "SOC-it-Edge", |
e15883da TG |
109 | .irq_ack = edge_mask_and_ack_msc_irq, |
110 | .irq_mask = mask_msc_irq, | |
111 | .irq_mask_ack = edge_mask_and_ack_msc_irq, | |
112 | .irq_unmask = unmask_msc_irq, | |
113 | .irq_eoi = unmask_msc_irq, | |
1da177e4 LT |
114 | }; |
115 | ||
116 | ||
d725cf38 | 117 | void __init init_msc_irqs(unsigned long icubase, unsigned int irqbase, msc_irqmap_t *imp, int nirq) |
1da177e4 | 118 | { |
49a89efb | 119 | _icctrl_msc = (unsigned long) ioremap(icubase, 0x40000); |
1da177e4 LT |
120 | |
121 | /* Reset interrupt controller - initialises all registers to 0 */ | |
122 | MSCIC_WRITE(MSC01_IC_RST, MSC01_IC_RST_RST_BIT); | |
123 | ||
124 | board_bind_eic_interrupt = &msc_bind_eic_interrupt; | |
125 | ||
ab6c15bc | 126 | for (; nirq > 0; nirq--, imp++) { |
1da177e4 LT |
127 | int n = imp->im_irq; |
128 | ||
129 | switch (imp->im_type) { | |
130 | case MSC01_IRQ_EDGE: | |
e4ec7989 TG |
131 | irq_set_chip_and_handler_name(irqbase + n, |
132 | &msc_edgeirq_type, | |
133 | handle_edge_irq, | |
134 | "edge"); | |
e01402b1 | 135 | if (cpu_has_veic) |
1da177e4 LT |
136 | MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT); |
137 | else | |
138 | MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT | imp->im_lvl); | |
139 | break; | |
140 | case MSC01_IRQ_LEVEL: | |
e4ec7989 TG |
141 | irq_set_chip_and_handler_name(irqbase + n, |
142 | &msc_levelirq_type, | |
143 | handle_level_irq, | |
144 | "level"); | |
e01402b1 | 145 | if (cpu_has_veic) |
1da177e4 LT |
146 | MSCIC_WRITE(MSC01_IC_SUP+n*8, 0); |
147 | else | |
148 | MSCIC_WRITE(MSC01_IC_SUP+n*8, imp->im_lvl); | |
149 | } | |
150 | } | |
151 | ||
d725cf38 | 152 | irq_base = irqbase; |
1da177e4 LT |
153 | |
154 | MSCIC_WRITE(MSC01_IC_GENA, MSC01_IC_GENA_GENA_BIT); /* Enable interrupt generation */ | |
155 | ||
156 | } |