[mirror_ubuntu-focal-kernel.git] / arch / mips / kernel / octeon_switch.S

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 1994, 1995, 1996, 1998, 1999, 2002, 2003 Ralf Baechle
 * Copyright (C) 1996 David S. Miller (davem@davemloft.net)
 * Copyright (C) 1994, 1995, 1996, by Andreas Busse
 * Copyright (C) 1999 Silicon Graphics, Inc.
 * Copyright (C) 2000 MIPS Technologies, Inc.
 *    written by Carsten Langgaard, carstenl@mips.com
 */
#include <asm/asm.h>
#include <asm/export.h>
#include <asm/asm-offsets.h>
#include <asm/mipsregs.h>
#include <asm/regdef.h>
#include <asm/stackframe.h>

/*
 * task_struct *resume(task_struct *prev, task_struct *next,
 *		       struct thread_info *next_ti)
 */
	.align	7
	LEAF(resume)
	.set arch=octeon
	mfc0	t1, CP0_STATUS
	LONG_S	t1, THREAD_STATUS(a0)
	cpu_save_nonscratch a0
	LONG_S	ra, THREAD_REG31(a0)

#if CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0
	/* Check if we need to store CVMSEG state */
	dmfc0	t0, $11,7	/* CvmMemCtl */
	bbit0	t0, 6, 3f	/* Is user access enabled? */

	/* Store the CVMSEG state */
	/* Extract the size of CVMSEG */
	andi	t0, 0x3f
	/* Multiply * (cache line size/sizeof(long)/2) */
	sll	t0, 7-LONGLOG-1
	li	t1, -32768	/* Base address of CVMSEG */
	LONG_ADDI t2, a0, THREAD_CVMSEG /* Where to store CVMSEG to */
	synciobdma
2:
	.set noreorder
	LONG_L	t8, 0(t1)	/* Load from CVMSEG */
	subu	t0, 1		/* Decrement loop var */
	LONG_L	t9, LONGSIZE(t1)/* Load from CVMSEG */
	LONG_ADDU t1, LONGSIZE*2 /* Increment loc in CVMSEG */
	LONG_S	t8, 0(t2)	/* Store CVMSEG to thread storage */
	LONG_ADDU t2, LONGSIZE*2 /* Increment loc in thread storage */
	bnez	t0, 2b		/* Loop until we've copied it all */
	 LONG_S t9, -LONGSIZE(t2)/* Store CVMSEG to thread storage */
	.set reorder

	/* Disable access to CVMSEG */
	dmfc0	t0, $11,7	/* CvmMemCtl */
	xori	t0, t0, 0x40	/* Bit 6 is CVMSEG user enable */
	dmtc0	t0, $11,7	/* CvmMemCtl */
#endif
3:

#if defined(CONFIG_STACKPROTECTOR) && !defined(CONFIG_SMP)
	PTR_LA	t8, __stack_chk_guard
	LONG_L	t9, TASK_STACK_CANARY(a1)
	LONG_S	t9, 0(t8)
#endif

	/*
	 * The order of restoring the registers takes care of the race
	 * updating $28, $29 and kernelsp without disabling ints.
	 */
	move	$28, a2
	cpu_restore_nonscratch a1

	PTR_ADDU	t0, $28, _THREAD_SIZE - 32
	set_saved_sp	t0, t1, t2

	mfc0	t1, CP0_STATUS		/* Do we really need this? */
	li	a3, 0xff01
	and	t1, a3
	LONG_L	a2, THREAD_STATUS(a1)
	nor	a3, $0, a3
	and	a2, a3
	or	a2, t1
	mtc0	a2, CP0_STATUS
	move	v0, a0
	jr	ra
	END(resume)

/*
 * void octeon_cop2_save(struct octeon_cop2_state *a0)
 */
	.align	7
	.set push
	.set noreorder
	LEAF(octeon_cop2_save)

	dmfc0	t9, $9,7	/* CvmCtl register. */

	/* Save the COP2 CRC state */
	dmfc2	t0, 0x0201
	dmfc2	t1, 0x0202
	dmfc2	t2, 0x0200
	sd	t0, OCTEON_CP2_CRC_IV(a0)
	sd	t1, OCTEON_CP2_CRC_LENGTH(a0)
	/* Skip next instructions if CvmCtl[NODFA_CP2] set */
	bbit1	t9, 28, 1f
	 sd	t2, OCTEON_CP2_CRC_POLY(a0)

	/* Save the LLM state */
	dmfc2	t0, 0x0402
	dmfc2	t1, 0x040A
	sd	t0, OCTEON_CP2_LLM_DAT(a0)

1:	bbit1	t9, 26, 3f	/* done if CvmCtl[NOCRYPTO] set */
	 sd	t1, OCTEON_CP2_LLM_DAT+8(a0)

	/* Save the COP2 crypto state */
	/* this part is mostly common to both pass 1 and later revisions */
	dmfc2	t0, 0x0084
	dmfc2	t1, 0x0080
	dmfc2	t2, 0x0081
	dmfc2	t3, 0x0082
	sd	t0, OCTEON_CP2_3DES_IV(a0)
	dmfc2	t0, 0x0088
	sd	t1, OCTEON_CP2_3DES_KEY(a0)
	dmfc2	t1, 0x0111			/* only necessary for pass 1 */
	sd	t2, OCTEON_CP2_3DES_KEY+8(a0)
	dmfc2	t2, 0x0102
	sd	t3, OCTEON_CP2_3DES_KEY+16(a0)
	dmfc2	t3, 0x0103
	sd	t0, OCTEON_CP2_3DES_RESULT(a0)
	dmfc2	t0, 0x0104
	sd	t1, OCTEON_CP2_AES_INP0(a0)	/* only necessary for pass 1 */
	dmfc2	t1, 0x0105
	sd	t2, OCTEON_CP2_AES_IV(a0)
	dmfc2	t2, 0x0106
	sd	t3, OCTEON_CP2_AES_IV+8(a0)
	dmfc2	t3, 0x0107
	sd	t0, OCTEON_CP2_AES_KEY(a0)
	dmfc2	t0, 0x0110
	sd	t1, OCTEON_CP2_AES_KEY+8(a0)
	dmfc2	t1, 0x0100
	sd	t2, OCTEON_CP2_AES_KEY+16(a0)
	dmfc2	t2, 0x0101
	sd	t3, OCTEON_CP2_AES_KEY+24(a0)
	mfc0	v0, $15,0	/* Get the processor ID register */
	sd	t0, OCTEON_CP2_AES_KEYLEN(a0)
	li	v1, 0x000d0000	/* This is the processor ID of Octeon Pass1 */
	sd	t1, OCTEON_CP2_AES_RESULT(a0)
	/* Skip to the Pass1 version of the remainder of the COP2 state */
	beq	v0, v1, 2f
	 sd	t2, OCTEON_CP2_AES_RESULT+8(a0)

	/* the non-pass1 state when !CvmCtl[NOCRYPTO] */
	dmfc2	t1, 0x0240
	dmfc2	t2, 0x0241
	ori	v1, v1, 0x9500 /* lowest OCTEON III PrId*/
	dmfc2	t3, 0x0242
	subu	v1, v0, v1 /* prid - lowest OCTEON III PrId */
	dmfc2	t0, 0x0243
	sd	t1, OCTEON_CP2_HSH_DATW(a0)
	dmfc2	t1, 0x0244
	sd	t2, OCTEON_CP2_HSH_DATW+8(a0)
	dmfc2	t2, 0x0245
	sd	t3, OCTEON_CP2_HSH_DATW+16(a0)
	dmfc2	t3, 0x0246
	sd	t0, OCTEON_CP2_HSH_DATW+24(a0)
	dmfc2	t0, 0x0247
	sd	t1, OCTEON_CP2_HSH_DATW+32(a0)
	dmfc2	t1, 0x0248
	sd	t2, OCTEON_CP2_HSH_DATW+40(a0)
	dmfc2	t2, 0x0249
	sd	t3, OCTEON_CP2_HSH_DATW+48(a0)
	dmfc2	t3, 0x024A
	sd	t0, OCTEON_CP2_HSH_DATW+56(a0)
	dmfc2	t0, 0x024B
	sd	t1, OCTEON_CP2_HSH_DATW+64(a0)
	dmfc2	t1, 0x024C
	sd	t2, OCTEON_CP2_HSH_DATW+72(a0)
	dmfc2	t2, 0x024D
	sd	t3, OCTEON_CP2_HSH_DATW+80(a0)
	dmfc2	t3, 0x024E
	sd	t0, OCTEON_CP2_HSH_DATW+88(a0)
	dmfc2	t0, 0x0250
	sd	t1, OCTEON_CP2_HSH_DATW+96(a0)
	dmfc2	t1, 0x0251
	sd	t2, OCTEON_CP2_HSH_DATW+104(a0)
	dmfc2	t2, 0x0252
	sd	t3, OCTEON_CP2_HSH_DATW+112(a0)
	dmfc2	t3, 0x0253
	sd	t0, OCTEON_CP2_HSH_IVW(a0)
	dmfc2	t0, 0x0254
	sd	t1, OCTEON_CP2_HSH_IVW+8(a0)
	dmfc2	t1, 0x0255
	sd	t2, OCTEON_CP2_HSH_IVW+16(a0)
	dmfc2	t2, 0x0256
	sd	t3, OCTEON_CP2_HSH_IVW+24(a0)
	dmfc2	t3, 0x0257
	sd	t0, OCTEON_CP2_HSH_IVW+32(a0)
	dmfc2	t0, 0x0258
	sd	t1, OCTEON_CP2_HSH_IVW+40(a0)
	dmfc2	t1, 0x0259
	sd	t2, OCTEON_CP2_HSH_IVW+48(a0)
	dmfc2	t2, 0x025E
	sd	t3, OCTEON_CP2_HSH_IVW+56(a0)
	dmfc2	t3, 0x025A
	sd	t0, OCTEON_CP2_GFM_MULT(a0)
	dmfc2	t0, 0x025B
	sd	t1, OCTEON_CP2_GFM_MULT+8(a0)
	sd	t2, OCTEON_CP2_GFM_POLY(a0)
	sd	t3, OCTEON_CP2_GFM_RESULT(a0)
	bltz	v1, 4f
	 sd	t0, OCTEON_CP2_GFM_RESULT+8(a0)
	/* OCTEON III things*/
	dmfc2	t0, 0x024F
	dmfc2	t1, 0x0050
	sd	t0, OCTEON_CP2_SHA3(a0)
	sd	t1, OCTEON_CP2_SHA3+8(a0)
4:
	jr	ra
	 nop

2:	/* pass 1 special stuff when !CvmCtl[NOCRYPTO] */
	dmfc2	t3, 0x0040
	dmfc2	t0, 0x0041
	dmfc2	t1, 0x0042
	dmfc2	t2, 0x0043
	sd	t3, OCTEON_CP2_HSH_DATW(a0)
	dmfc2	t3, 0x0044
	sd	t0, OCTEON_CP2_HSH_DATW+8(a0)
	dmfc2	t0, 0x0045
	sd	t1, OCTEON_CP2_HSH_DATW+16(a0)
	dmfc2	t1, 0x0046
	sd	t2, OCTEON_CP2_HSH_DATW+24(a0)
	dmfc2	t2, 0x0048
	sd	t3, OCTEON_CP2_HSH_DATW+32(a0)
	dmfc2	t3, 0x0049
	sd	t0, OCTEON_CP2_HSH_DATW+40(a0)
	dmfc2	t0, 0x004A
	sd	t1, OCTEON_CP2_HSH_DATW+48(a0)
	sd	t2, OCTEON_CP2_HSH_IVW(a0)
	sd	t3, OCTEON_CP2_HSH_IVW+8(a0)
	sd	t0, OCTEON_CP2_HSH_IVW+16(a0)

3:	/* pass 1 or CvmCtl[NOCRYPTO] set */
	jr	ra
	 nop
	END(octeon_cop2_save)
	.set pop

/*
 * void octeon_cop2_restore(struct octeon_cop2_state *a0)
 */
	.align	7
	.set push
	.set noreorder
	LEAF(octeon_cop2_restore)
	/* First cache line was prefetched before the call */
	pref	4,  128(a0)
	dmfc0	t9, $9,7	/* CvmCtl register. */

	pref	4,  256(a0)
	ld	t0, OCTEON_CP2_CRC_IV(a0)
	pref	4,  384(a0)
	ld	t1, OCTEON_CP2_CRC_LENGTH(a0)
	ld	t2, OCTEON_CP2_CRC_POLY(a0)

	/* Restore the COP2 CRC state */
	dmtc2	t0, 0x0201
	dmtc2	t1, 0x1202
	bbit1	t9, 28, 2f	/* Skip LLM if CvmCtl[NODFA_CP2] is set */
	 dmtc2	t2, 0x4200

	/* Restore the LLM state */
	ld	t0, OCTEON_CP2_LLM_DAT(a0)
	ld	t1, OCTEON_CP2_LLM_DAT+8(a0)
	dmtc2	t0, 0x0402
	dmtc2	t1, 0x040A

2:
	bbit1	t9, 26, done_restore	/* done if CvmCtl[NOCRYPTO] set */
	 nop

	/* Restore the COP2 crypto state common to pass 1 and pass 2 */
	ld	t0, OCTEON_CP2_3DES_IV(a0)
	ld	t1, OCTEON_CP2_3DES_KEY(a0)
	ld	t2, OCTEON_CP2_3DES_KEY+8(a0)
	dmtc2	t0, 0x0084
	ld	t0, OCTEON_CP2_3DES_KEY+16(a0)
	dmtc2	t1, 0x0080
	ld	t1, OCTEON_CP2_3DES_RESULT(a0)
	dmtc2	t2, 0x0081
	ld	t2, OCTEON_CP2_AES_INP0(a0) /* only really needed for pass 1 */
	dmtc2	t0, 0x0082
	ld	t0, OCTEON_CP2_AES_IV(a0)
	dmtc2	t1, 0x0098
	ld	t1, OCTEON_CP2_AES_IV+8(a0)
	dmtc2	t2, 0x010A		    /* only really needed for pass 1 */
	ld	t2, OCTEON_CP2_AES_KEY(a0)
	dmtc2	t0, 0x0102
	ld	t0, OCTEON_CP2_AES_KEY+8(a0)
	dmtc2	t1, 0x0103
	ld	t1, OCTEON_CP2_AES_KEY+16(a0)
	dmtc2	t2, 0x0104
	ld	t2, OCTEON_CP2_AES_KEY+24(a0)
	dmtc2	t0, 0x0105
	ld	t0, OCTEON_CP2_AES_KEYLEN(a0)
	dmtc2	t1, 0x0106
	ld	t1, OCTEON_CP2_AES_RESULT(a0)
	dmtc2	t2, 0x0107
	ld	t2, OCTEON_CP2_AES_RESULT+8(a0)
	mfc0	t3, $15,0	/* Get the processor ID register */
	dmtc2	t0, 0x0110
	li	v0, 0x000d0000	/* This is the processor ID of Octeon Pass1 */
	dmtc2	t1, 0x0100
	bne	v0, t3, 3f	/* Skip the next stuff for non-pass1 */
	 dmtc2	t2, 0x0101

	/* this code is specific for pass 1 */
	ld	t0, OCTEON_CP2_HSH_DATW(a0)
	ld	t1, OCTEON_CP2_HSH_DATW+8(a0)
	ld	t2, OCTEON_CP2_HSH_DATW+16(a0)
	dmtc2	t0, 0x0040
	ld	t0, OCTEON_CP2_HSH_DATW+24(a0)
	dmtc2	t1, 0x0041
	ld	t1, OCTEON_CP2_HSH_DATW+32(a0)
	dmtc2	t2, 0x0042
	ld	t2, OCTEON_CP2_HSH_DATW+40(a0)
	dmtc2	t0, 0x0043
	ld	t0, OCTEON_CP2_HSH_DATW+48(a0)
	dmtc2	t1, 0x0044
	ld	t1, OCTEON_CP2_HSH_IVW(a0)
	dmtc2	t2, 0x0045
	ld	t2, OCTEON_CP2_HSH_IVW+8(a0)
	dmtc2	t0, 0x0046
	ld	t0, OCTEON_CP2_HSH_IVW+16(a0)
	dmtc2	t1, 0x0048
	dmtc2	t2, 0x0049
	b done_restore	 /* unconditional branch */
	 dmtc2	t0, 0x004A

3:	/* this is post-pass1 code */
	ld	t2, OCTEON_CP2_HSH_DATW(a0)
	ori	v0, v0, 0x9500 /* lowest OCTEON III PrId*/
	ld	t0, OCTEON_CP2_HSH_DATW+8(a0)
	ld	t1, OCTEON_CP2_HSH_DATW+16(a0)
	dmtc2	t2, 0x0240
	ld	t2, OCTEON_CP2_HSH_DATW+24(a0)
	dmtc2	t0, 0x0241
	ld	t0, OCTEON_CP2_HSH_DATW+32(a0)
	dmtc2	t1, 0x0242
	ld	t1, OCTEON_CP2_HSH_DATW+40(a0)
	dmtc2	t2, 0x0243
	ld	t2, OCTEON_CP2_HSH_DATW+48(a0)
	dmtc2	t0, 0x0244
	ld	t0, OCTEON_CP2_HSH_DATW+56(a0)
	dmtc2	t1, 0x0245
	ld	t1, OCTEON_CP2_HSH_DATW+64(a0)
	dmtc2	t2, 0x0246
	ld	t2, OCTEON_CP2_HSH_DATW+72(a0)
	dmtc2	t0, 0x0247
	ld	t0, OCTEON_CP2_HSH_DATW+80(a0)
	dmtc2	t1, 0x0248
	ld	t1, OCTEON_CP2_HSH_DATW+88(a0)
	dmtc2	t2, 0x0249
	ld	t2, OCTEON_CP2_HSH_DATW+96(a0)
	dmtc2	t0, 0x024A
	ld	t0, OCTEON_CP2_HSH_DATW+104(a0)
	dmtc2	t1, 0x024B
	ld	t1, OCTEON_CP2_HSH_DATW+112(a0)
	dmtc2	t2, 0x024C
	ld	t2, OCTEON_CP2_HSH_IVW(a0)
	dmtc2	t0, 0x024D
	ld	t0, OCTEON_CP2_HSH_IVW+8(a0)
	dmtc2	t1, 0x024E
	ld	t1, OCTEON_CP2_HSH_IVW+16(a0)
	dmtc2	t2, 0x0250
	ld	t2, OCTEON_CP2_HSH_IVW+24(a0)
	dmtc2	t0, 0x0251
	ld	t0, OCTEON_CP2_HSH_IVW+32(a0)
	dmtc2	t1, 0x0252
	ld	t1, OCTEON_CP2_HSH_IVW+40(a0)
	dmtc2	t2, 0x0253
	ld	t2, OCTEON_CP2_HSH_IVW+48(a0)
	dmtc2	t0, 0x0254
	ld	t0, OCTEON_CP2_HSH_IVW+56(a0)
	dmtc2	t1, 0x0255
	ld	t1, OCTEON_CP2_GFM_MULT(a0)
	dmtc2	t2, 0x0256
	ld	t2, OCTEON_CP2_GFM_MULT+8(a0)
	dmtc2	t0, 0x0257
	ld	t0, OCTEON_CP2_GFM_POLY(a0)
	dmtc2	t1, 0x0258
	ld	t1, OCTEON_CP2_GFM_RESULT(a0)
	dmtc2	t2, 0x0259
	ld	t2, OCTEON_CP2_GFM_RESULT+8(a0)
	dmtc2	t0, 0x025E
	subu	v0, t3, v0 /* prid - lowest OCTEON III PrId */
	dmtc2	t1, 0x025A
	bltz	v0, done_restore
	 dmtc2	t2, 0x025B
	/* OCTEON III things*/
	ld	t0, OCTEON_CP2_SHA3(a0)
	ld	t1, OCTEON_CP2_SHA3+8(a0)
	dmtc2	t0, 0x0051
	dmtc2	t1, 0x0050
done_restore:
	jr	ra
	 nop
	END(octeon_cop2_restore)
	.set pop

/*
 * void octeon_mult_save()
 * sp is assumed to point to a struct pt_regs
 *
 * NOTE: This is called in SAVE_TEMP in stackframe.h. It can
 *       safely modify v1,k0, k1,$10-$15, and $24.  It will
 *	 be overwritten with a processor specific version of the code.
 */
	.p2align 7
	.set push
	.set noreorder
	LEAF(octeon_mult_save)
	jr	ra
	 nop
	.space 30 * 4, 0
octeon_mult_save_end:
	EXPORT(octeon_mult_save_end)
	END(octeon_mult_save)

	LEAF(octeon_mult_save2)
	/* Save the multiplier state OCTEON II and earlier*/
	v3mulu	k0, $0, $0
	v3mulu	k1, $0, $0
	sd	k0, PT_MTP(sp)	      /* PT_MTP	   has P0 */
	v3mulu	k0, $0, $0
	sd	k1, PT_MTP+8(sp)      /* PT_MTP+8  has P1 */
	ori	k1, $0, 1
	v3mulu	k1, k1, $0
	sd	k0, PT_MTP+16(sp)     /* PT_MTP+16 has P2 */
	v3mulu	k0, $0, $0
	sd	k1, PT_MPL(sp)	      /* PT_MPL	   has MPL0 */
	v3mulu	k1, $0, $0
	sd	k0, PT_MPL+8(sp)      /* PT_MPL+8  has MPL1 */
	jr	ra
	 sd	k1, PT_MPL+16(sp)     /* PT_MPL+16 has MPL2 */
octeon_mult_save2_end:
	EXPORT(octeon_mult_save2_end)
	END(octeon_mult_save2)

	LEAF(octeon_mult_save3)
	/* Save the multiplier state OCTEON III */
	v3mulu	$10, $0, $0		/* read P0 */
	v3mulu	$11, $0, $0		/* read P1 */
	v3mulu	$12, $0, $0		/* read P2 */
	sd	$10, PT_MTP+(0*8)(sp)	/* store P0 */
	v3mulu	$10, $0, $0		/* read P3 */
	sd	$11, PT_MTP+(1*8)(sp)	/*  store P1 */
	v3mulu	$11, $0, $0		/* read P4 */
	sd	$12, PT_MTP+(2*8)(sp)	/* store P2 */
	ori	$13, $0, 1
	v3mulu	$12, $0, $0		/* read P5 */
	sd	$10, PT_MTP+(3*8)(sp)	/* store P3 */
	v3mulu	$13, $13, $0		/* P4-P0 = MPL5-MPL1, $13 = MPL0 */
	sd	$11, PT_MTP+(4*8)(sp)	/* store P4 */
	v3mulu	$10, $0, $0		/* read MPL1 */
	sd	$12, PT_MTP+(5*8)(sp)	/* store P5 */
	v3mulu	$11, $0, $0		/* read MPL2 */
	sd	$13, PT_MPL+(0*8)(sp)	/* store MPL0 */
	v3mulu	$12, $0, $0		/* read MPL3 */
	sd	$10, PT_MPL+(1*8)(sp)	/* store MPL1 */
	v3mulu	$10, $0, $0		/* read MPL4 */
	sd	$11, PT_MPL+(2*8)(sp)	/* store MPL2 */
	v3mulu	$11, $0, $0		/* read MPL5 */
	sd	$12, PT_MPL+(3*8)(sp)	/* store MPL3 */
	sd	$10, PT_MPL+(4*8)(sp)	/* store MPL4 */
	jr	ra
	 sd	$11, PT_MPL+(5*8)(sp)	/* store MPL5 */
octeon_mult_save3_end:
	EXPORT(octeon_mult_save3_end)
	END(octeon_mult_save3)
	.set pop

/*
 * void octeon_mult_restore()
 * sp is assumed to point to a struct pt_regs
 *
 * NOTE: This is called in RESTORE_TEMP in stackframe.h.
 */
	.p2align 7
	.set push
	.set noreorder
	LEAF(octeon_mult_restore)
	jr	ra
	 nop
	.space 30 * 4, 0
octeon_mult_restore_end:
	EXPORT(octeon_mult_restore_end)
	END(octeon_mult_restore)

	LEAF(octeon_mult_restore2)
	ld	v0, PT_MPL(sp)        	/* MPL0 */
	ld	v1, PT_MPL+8(sp)      	/* MPL1 */
	ld	k0, PT_MPL+16(sp)     	/* MPL2 */
	/* Restore the multiplier state */
	ld	k1, PT_MTP+16(sp)     	/* P2 */
	mtm0	v0			/* MPL0 */
	ld	v0, PT_MTP+8(sp)	/* P1 */
	mtm1	v1			/* MPL1 */
	ld	v1, PT_MTP(sp)   	/* P0 */
	mtm2	k0			/* MPL2 */
	mtp2	k1			/* P2 */
	mtp1	v0			/* P1 */
	jr	ra
	 mtp0	v1			/* P0 */
octeon_mult_restore2_end:
	EXPORT(octeon_mult_restore2_end)
	END(octeon_mult_restore2)

	LEAF(octeon_mult_restore3)
	ld	$12, PT_MPL+(0*8)(sp)	/* read MPL0 */
	ld	$13, PT_MPL+(3*8)(sp)	/* read MPL3 */
	ld	$10, PT_MPL+(1*8)(sp)	/* read MPL1 */
	ld	$11, PT_MPL+(4*8)(sp)	/* read MPL4 */
	.word	0x718d0008
	/* mtm0	$12, $13		   restore MPL0 and MPL3 */
	ld	$12, PT_MPL+(2*8)(sp)	/* read MPL2 */
	.word	0x714b000c
	/* mtm1	$10, $11		   restore MPL1 and MPL4 */
	ld	$13, PT_MPL+(5*8)(sp)	/* read MPL5 */
	ld	$10, PT_MTP+(0*8)(sp)	/* read P0 */
	ld	$11, PT_MTP+(3*8)(sp)	/* read P3 */
	.word	0x718d000d
	/* mtm2	$12, $13		   restore MPL2 and MPL5 */
	ld	$12, PT_MTP+(1*8)(sp)	/* read P1 */
	.word	0x714b0009
	/* mtp0	$10, $11		   restore P0 and P3 */
	ld	$13, PT_MTP+(4*8)(sp)	/* read P4 */
	ld	$10, PT_MTP+(2*8)(sp)	/* read P2 */
	ld	$11, PT_MTP+(5*8)(sp)	/* read P5 */
	.word	0x718d000a
	/* mtp1	$12, $13		   restore P1 and P4 */
	jr	ra
	.word	0x714b000b
	/* mtp2	$10, $11		   restore P2 and P5 */

octeon_mult_restore3_end:
	EXPORT(octeon_mult_restore3_end)
	END(octeon_mult_restore3)
	.set pop
Commit	Line	Data
5b3b1688 DD	1	/*
	2	* This file is subject to the terms and conditions of the GNU General Public
	3	* License. See the file "COPYING" in the main directory of this archive
	4	* for more details.
	5	*
	6	* Copyright (C) 1994, 1995, 1996, 1998, 1999, 2002, 2003 Ralf Baechle
79add627	7	* Copyright (C) 1996 David S. Miller (davem@davemloft.net)
5b3b1688 DD	8	* Copyright (C) 1994, 1995, 1996, by Andreas Busse
	9	* Copyright (C) 1999 Silicon Graphics, Inc.
	10	* Copyright (C) 2000 MIPS Technologies, Inc.
	11	* written by Carsten Langgaard, carstenl@mips.com
	12	*/
a2aea699 PB	13	#include <asm/asm.h>
	14	#include <asm/export.h>
	15	#include <asm/asm-offsets.h>
	16	#include <asm/mipsregs.h>
	17	#include <asm/regdef.h>
	18	#include <asm/stackframe.h>
5b3b1688 DD	19
	20	/*
	21	* task_struct resume(task_struct prev, task_struct *next,
0fa24340	22	* struct thread_info *next_ti)
5b3b1688 DD	23	*/
	24	.align 7
	25	LEAF(resume)
	26	.set arch=octeon
5b3b1688 DD	27	mfc0 t1, CP0_STATUS
	28	LONG_S t1, THREAD_STATUS(a0)
	29	cpu_save_nonscratch a0
	30	LONG_S ra, THREAD_REG31(a0)
	31
5b3b1688 DD	32	#if CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0
5b3b1688 DD	33	/* Check if we need to store CVMSEG state */
2d98cae6	34	dmfc0 t0, $11,7 /* CvmMemCtl */
5b3b1688 DD	35	bbit0 t0, 6, 3f /* Is user access enabled? */
	36
	37	/* Store the CVMSEG state */
	38	/* Extract the size of CVMSEG */
	39	andi t0, 0x3f
	40	/* Multiply * (cache line size/sizeof(long)/2) */
	41	sll t0, 7-LONGLOG-1
70342287 RB	42	li t1, -32768 /* Base address of CVMSEG */
70342287 RB	43	LONG_ADDI t2, a0, THREAD_CVMSEG /* Where to store CVMSEG to */
5b3b1688 DD	44	synciobdma
	45	2:
	46	.set noreorder
	47	LONG_L t8, 0(t1) /* Load from CVMSEG */
	48	subu t0, 1 /* Decrement loop var */
	49	LONG_L t9, LONGSIZE(t1)/* Load from CVMSEG */
	50	LONG_ADDU t1, LONGSIZE2 / Increment loc in CVMSEG */
	51	LONG_S t8, 0(t2) /* Store CVMSEG to thread storage */
	52	LONG_ADDU t2, LONGSIZE2 / Increment loc in thread storage */
	53	bnez t0, 2b /* Loop until we've copied it all */
70342287	54	LONG_S t9, -LONGSIZE(t2)/* Store CVMSEG to thread storage */
5b3b1688 DD	55	.set reorder
	56
	57	/* Disable access to CVMSEG */
2d98cae6	58	dmfc0 t0, $11,7 /* CvmMemCtl */
5b3b1688	59	xori t0, t0, 0x40 /* Bit 6 is CVMSEG user enable */
2d98cae6	60	dmtc0 t0, $11,7 /* CvmMemCtl */
5b3b1688 DD	61	#endif
5b3b1688 DD	62	3:
1400eb65	63
050e9baa	64	#if defined(CONFIG_STACKPROTECTOR) && !defined(CONFIG_SMP)
8b3c569a	65	PTR_LA t8, __stack_chk_guard
1400eb65 GF	66	LONG_L t9, TASK_STACK_CANARY(a1)
	67	LONG_S t9, 0(t8)
	68	#endif
	69
5b3b1688 DD	70	/*
	71	* The order of restoring the registers takes care of the race
	72	* updating $28, $29 and kernelsp without disabling ints.
	73	*/
	74	move $28, a2
	75	cpu_restore_nonscratch a1
	76
a36d8225	77	PTR_ADDU t0, $28, _THREAD_SIZE - 32
5b3b1688 DD	78	set_saved_sp t0, t1, t2
	79
	80	mfc0 t1, CP0_STATUS /* Do we really need this? */
	81	li a3, 0xff01
	82	and t1, a3
	83	LONG_L a2, THREAD_STATUS(a1)
	84	nor a3, $0, a3
	85	and a2, a3
	86	or a2, t1
	87	mtc0 a2, CP0_STATUS
	88	move v0, a0
	89	jr ra
	90	END(resume)
	91
	92	/*
	93	* void octeon_cop2_save(struct octeon_cop2_state *a0)
	94	*/
	95	.align 7
6b3a287e DD	96	.set push
6b3a287e DD	97	.set noreorder
5b3b1688 DD	98	LEAF(octeon_cop2_save)
	99
	100	dmfc0 t9, $9,7 /* CvmCtl register. */
	101
70342287	102	/* Save the COP2 CRC state */
5b3b1688 DD	103	dmfc2 t0, 0x0201
	104	dmfc2 t1, 0x0202
	105	dmfc2 t2, 0x0200
	106	sd t0, OCTEON_CP2_CRC_IV(a0)
	107	sd t1, OCTEON_CP2_CRC_LENGTH(a0)
5b3b1688 DD	108	/* Skip next instructions if CvmCtl[NODFA_CP2] set */
5b3b1688 DD	109	bbit1 t9, 28, 1f
6b3a287e	110	sd t2, OCTEON_CP2_CRC_POLY(a0)
5b3b1688 DD	111
	112	/* Save the LLM state */
	113	dmfc2 t0, 0x0402
	114	dmfc2 t1, 0x040A
	115	sd t0, OCTEON_CP2_LLM_DAT(a0)
5b3b1688	116
70342287	117	1: bbit1 t9, 26, 3f /* done if CvmCtl[NOCRYPTO] set */
6b3a287e	118	sd t1, OCTEON_CP2_LLM_DAT+8(a0)
5b3b1688 DD	119
5b3b1688 DD	120	/* Save the COP2 crypto state */
70342287 RB	121	/* this part is mostly common to both pass 1 and later revisions */
	122	dmfc2 t0, 0x0084
	123	dmfc2 t1, 0x0080
	124	dmfc2 t2, 0x0081
	125	dmfc2 t3, 0x0082
5b3b1688	126	sd t0, OCTEON_CP2_3DES_IV(a0)
70342287	127	dmfc2 t0, 0x0088
5b3b1688	128	sd t1, OCTEON_CP2_3DES_KEY(a0)
70342287	129	dmfc2 t1, 0x0111 /* only necessary for pass 1 */
5b3b1688	130	sd t2, OCTEON_CP2_3DES_KEY+8(a0)
70342287	131	dmfc2 t2, 0x0102
5b3b1688	132	sd t3, OCTEON_CP2_3DES_KEY+16(a0)
70342287	133	dmfc2 t3, 0x0103
5b3b1688	134	sd t0, OCTEON_CP2_3DES_RESULT(a0)
70342287 RB	135	dmfc2 t0, 0x0104
	136	sd t1, OCTEON_CP2_AES_INP0(a0) /* only necessary for pass 1 */
	137	dmfc2 t1, 0x0105
5b3b1688 DD	138	sd t2, OCTEON_CP2_AES_IV(a0)
	139	dmfc2 t2, 0x0106
	140	sd t3, OCTEON_CP2_AES_IV+8(a0)
70342287	141	dmfc2 t3, 0x0107
5b3b1688 DD	142	sd t0, OCTEON_CP2_AES_KEY(a0)
	143	dmfc2 t0, 0x0110
	144	sd t1, OCTEON_CP2_AES_KEY+8(a0)
	145	dmfc2 t1, 0x0100
	146	sd t2, OCTEON_CP2_AES_KEY+16(a0)
	147	dmfc2 t2, 0x0101
	148	sd t3, OCTEON_CP2_AES_KEY+24(a0)
6b3a287e	149	mfc0 v0, $15,0 /* Get the processor ID register */
5b3b1688	150	sd t0, OCTEON_CP2_AES_KEYLEN(a0)
6b3a287e	151	li v1, 0x000d0000 /* This is the processor ID of Octeon Pass1 */
5b3b1688	152	sd t1, OCTEON_CP2_AES_RESULT(a0)
5b3b1688	153	/* Skip to the Pass1 version of the remainder of the COP2 state */
6b3a287e DD	154	beq v0, v1, 2f
6b3a287e DD	155	sd t2, OCTEON_CP2_AES_RESULT+8(a0)
5b3b1688	156
70342287	157	/* the non-pass1 state when !CvmCtl[NOCRYPTO] */
5b3b1688 DD	158	dmfc2 t1, 0x0240
5b3b1688 DD	159	dmfc2 t2, 0x0241
6b3a287e	160	ori v1, v1, 0x9500 /* lowest OCTEON III PrId*/
5b3b1688	161	dmfc2 t3, 0x0242
6b3a287e	162	subu v1, v0, v1 /* prid - lowest OCTEON III PrId */
5b3b1688 DD	163	dmfc2 t0, 0x0243
	164	sd t1, OCTEON_CP2_HSH_DATW(a0)
	165	dmfc2 t1, 0x0244
	166	sd t2, OCTEON_CP2_HSH_DATW+8(a0)
	167	dmfc2 t2, 0x0245
	168	sd t3, OCTEON_CP2_HSH_DATW+16(a0)
	169	dmfc2 t3, 0x0246
	170	sd t0, OCTEON_CP2_HSH_DATW+24(a0)
	171	dmfc2 t0, 0x0247
	172	sd t1, OCTEON_CP2_HSH_DATW+32(a0)
	173	dmfc2 t1, 0x0248
	174	sd t2, OCTEON_CP2_HSH_DATW+40(a0)
	175	dmfc2 t2, 0x0249
	176	sd t3, OCTEON_CP2_HSH_DATW+48(a0)
	177	dmfc2 t3, 0x024A
	178	sd t0, OCTEON_CP2_HSH_DATW+56(a0)
	179	dmfc2 t0, 0x024B
	180	sd t1, OCTEON_CP2_HSH_DATW+64(a0)
	181	dmfc2 t1, 0x024C
	182	sd t2, OCTEON_CP2_HSH_DATW+72(a0)
	183	dmfc2 t2, 0x024D
	184	sd t3, OCTEON_CP2_HSH_DATW+80(a0)
70342287	185	dmfc2 t3, 0x024E
5b3b1688 DD	186	sd t0, OCTEON_CP2_HSH_DATW+88(a0)
	187	dmfc2 t0, 0x0250
	188	sd t1, OCTEON_CP2_HSH_DATW+96(a0)
	189	dmfc2 t1, 0x0251
	190	sd t2, OCTEON_CP2_HSH_DATW+104(a0)
	191	dmfc2 t2, 0x0252
	192	sd t3, OCTEON_CP2_HSH_DATW+112(a0)
	193	dmfc2 t3, 0x0253
	194	sd t0, OCTEON_CP2_HSH_IVW(a0)
	195	dmfc2 t0, 0x0254
	196	sd t1, OCTEON_CP2_HSH_IVW+8(a0)
	197	dmfc2 t1, 0x0255
	198	sd t2, OCTEON_CP2_HSH_IVW+16(a0)
	199	dmfc2 t2, 0x0256
	200	sd t3, OCTEON_CP2_HSH_IVW+24(a0)
	201	dmfc2 t3, 0x0257
	202	sd t0, OCTEON_CP2_HSH_IVW+32(a0)
70342287	203	dmfc2 t0, 0x0258
5b3b1688	204	sd t1, OCTEON_CP2_HSH_IVW+40(a0)
70342287	205	dmfc2 t1, 0x0259
5b3b1688 DD	206	sd t2, OCTEON_CP2_HSH_IVW+48(a0)
	207	dmfc2 t2, 0x025E
	208	sd t3, OCTEON_CP2_HSH_IVW+56(a0)
	209	dmfc2 t3, 0x025A
	210	sd t0, OCTEON_CP2_GFM_MULT(a0)
	211	dmfc2 t0, 0x025B
	212	sd t1, OCTEON_CP2_GFM_MULT+8(a0)
	213	sd t2, OCTEON_CP2_GFM_POLY(a0)
	214	sd t3, OCTEON_CP2_GFM_RESULT(a0)
6b3a287e DD	215	bltz v1, 4f
	216	sd t0, OCTEON_CP2_GFM_RESULT+8(a0)
	217	/* OCTEON III things*/
	218	dmfc2 t0, 0x024F
	219	dmfc2 t1, 0x0050
	220	sd t0, OCTEON_CP2_SHA3(a0)
	221	sd t1, OCTEON_CP2_SHA3+8(a0)
	222	4:
5b3b1688	223	jr ra
6b3a287e	224	nop
5b3b1688	225
70342287	226	2: /* pass 1 special stuff when !CvmCtl[NOCRYPTO] */
5b3b1688 DD	227	dmfc2 t3, 0x0040
	228	dmfc2 t0, 0x0041
	229	dmfc2 t1, 0x0042
	230	dmfc2 t2, 0x0043
	231	sd t3, OCTEON_CP2_HSH_DATW(a0)
	232	dmfc2 t3, 0x0044
	233	sd t0, OCTEON_CP2_HSH_DATW+8(a0)
	234	dmfc2 t0, 0x0045
	235	sd t1, OCTEON_CP2_HSH_DATW+16(a0)
	236	dmfc2 t1, 0x0046
	237	sd t2, OCTEON_CP2_HSH_DATW+24(a0)
	238	dmfc2 t2, 0x0048
	239	sd t3, OCTEON_CP2_HSH_DATW+32(a0)
	240	dmfc2 t3, 0x0049
	241	sd t0, OCTEON_CP2_HSH_DATW+40(a0)
	242	dmfc2 t0, 0x004A
	243	sd t1, OCTEON_CP2_HSH_DATW+48(a0)
	244	sd t2, OCTEON_CP2_HSH_IVW(a0)
	245	sd t3, OCTEON_CP2_HSH_IVW+8(a0)
	246	sd t0, OCTEON_CP2_HSH_IVW+16(a0)
	247
70342287	248	3: /* pass 1 or CvmCtl[NOCRYPTO] set */
5b3b1688	249	jr ra
6b3a287e	250	nop
5b3b1688	251	END(octeon_cop2_save)
6b3a287e	252	.set pop
5b3b1688 DD	253
	254	/*
	255	* void octeon_cop2_restore(struct octeon_cop2_state *a0)
	256	*/
	257	.align 7
	258	.set push
	259	.set noreorder
	260	LEAF(octeon_cop2_restore)
70342287 RB	261	/* First cache line was prefetched before the call */
70342287 RB	262	pref 4, 128(a0)
5b3b1688 DD	263	dmfc0 t9, $9,7 /* CvmCtl register. */
5b3b1688 DD	264
70342287	265	pref 4, 256(a0)
5b3b1688	266	ld t0, OCTEON_CP2_CRC_IV(a0)
70342287	267	pref 4, 384(a0)
5b3b1688 DD	268	ld t1, OCTEON_CP2_CRC_LENGTH(a0)
	269	ld t2, OCTEON_CP2_CRC_POLY(a0)
	270
	271	/* Restore the COP2 CRC state */
	272	dmtc2 t0, 0x0201
70342287	273	dmtc2 t1, 0x1202
5b3b1688 DD	274	bbit1 t9, 28, 2f /* Skip LLM if CvmCtl[NODFA_CP2] is set */
	275	dmtc2 t2, 0x4200
	276
	277	/* Restore the LLM state */
	278	ld t0, OCTEON_CP2_LLM_DAT(a0)
	279	ld t1, OCTEON_CP2_LLM_DAT+8(a0)
	280	dmtc2 t0, 0x0402
	281	dmtc2 t1, 0x040A
	282
	283	2:
	284	bbit1 t9, 26, done_restore /* done if CvmCtl[NOCRYPTO] set */
	285	nop
	286
	287	/* Restore the COP2 crypto state common to pass 1 and pass 2 */
	288	ld t0, OCTEON_CP2_3DES_IV(a0)
	289	ld t1, OCTEON_CP2_3DES_KEY(a0)
	290	ld t2, OCTEON_CP2_3DES_KEY+8(a0)
70342287	291	dmtc2 t0, 0x0084
5b3b1688	292	ld t0, OCTEON_CP2_3DES_KEY+16(a0)
70342287	293	dmtc2 t1, 0x0080
5b3b1688	294	ld t1, OCTEON_CP2_3DES_RESULT(a0)
70342287	295	dmtc2 t2, 0x0081
5b3b1688 DD	296	ld t2, OCTEON_CP2_AES_INP0(a0) /* only really needed for pass 1 */
	297	dmtc2 t0, 0x0082
	298	ld t0, OCTEON_CP2_AES_IV(a0)
70342287	299	dmtc2 t1, 0x0098
5b3b1688	300	ld t1, OCTEON_CP2_AES_IV+8(a0)
70342287	301	dmtc2 t2, 0x010A /* only really needed for pass 1 */
5b3b1688	302	ld t2, OCTEON_CP2_AES_KEY(a0)
70342287	303	dmtc2 t0, 0x0102
5b3b1688 DD	304	ld t0, OCTEON_CP2_AES_KEY+8(a0)
	305	dmtc2 t1, 0x0103
	306	ld t1, OCTEON_CP2_AES_KEY+16(a0)
	307	dmtc2 t2, 0x0104
	308	ld t2, OCTEON_CP2_AES_KEY+24(a0)
	309	dmtc2 t0, 0x0105
	310	ld t0, OCTEON_CP2_AES_KEYLEN(a0)
	311	dmtc2 t1, 0x0106
	312	ld t1, OCTEON_CP2_AES_RESULT(a0)
	313	dmtc2 t2, 0x0107
	314	ld t2, OCTEON_CP2_AES_RESULT+8(a0)
70342287	315	mfc0 t3, $15,0 /* Get the processor ID register */
5b3b1688	316	dmtc2 t0, 0x0110
6b3a287e	317	li v0, 0x000d0000 /* This is the processor ID of Octeon Pass1 */
5b3b1688	318	dmtc2 t1, 0x0100
6b3a287e	319	bne v0, t3, 3f /* Skip the next stuff for non-pass1 */
5b3b1688 DD	320	dmtc2 t2, 0x0101
5b3b1688 DD	321
70342287	322	/* this code is specific for pass 1 */
5b3b1688 DD	323	ld t0, OCTEON_CP2_HSH_DATW(a0)
	324	ld t1, OCTEON_CP2_HSH_DATW+8(a0)
	325	ld t2, OCTEON_CP2_HSH_DATW+16(a0)
	326	dmtc2 t0, 0x0040
	327	ld t0, OCTEON_CP2_HSH_DATW+24(a0)
	328	dmtc2 t1, 0x0041
	329	ld t1, OCTEON_CP2_HSH_DATW+32(a0)
	330	dmtc2 t2, 0x0042
	331	ld t2, OCTEON_CP2_HSH_DATW+40(a0)
	332	dmtc2 t0, 0x0043
	333	ld t0, OCTEON_CP2_HSH_DATW+48(a0)
	334	dmtc2 t1, 0x0044
	335	ld t1, OCTEON_CP2_HSH_IVW(a0)
	336	dmtc2 t2, 0x0045
	337	ld t2, OCTEON_CP2_HSH_IVW+8(a0)
	338	dmtc2 t0, 0x0046
	339	ld t0, OCTEON_CP2_HSH_IVW+16(a0)
	340	dmtc2 t1, 0x0048
	341	dmtc2 t2, 0x0049
70342287	342	b done_restore /* unconditional branch */
5b3b1688 DD	343	dmtc2 t0, 0x004A
5b3b1688 DD	344
70342287	345	3: /* this is post-pass1 code */
5b3b1688	346	ld t2, OCTEON_CP2_HSH_DATW(a0)
6b3a287e	347	ori v0, v0, 0x9500 /* lowest OCTEON III PrId*/
5b3b1688 DD	348	ld t0, OCTEON_CP2_HSH_DATW+8(a0)
	349	ld t1, OCTEON_CP2_HSH_DATW+16(a0)
	350	dmtc2 t2, 0x0240
	351	ld t2, OCTEON_CP2_HSH_DATW+24(a0)
	352	dmtc2 t0, 0x0241
	353	ld t0, OCTEON_CP2_HSH_DATW+32(a0)
	354	dmtc2 t1, 0x0242
	355	ld t1, OCTEON_CP2_HSH_DATW+40(a0)
	356	dmtc2 t2, 0x0243
	357	ld t2, OCTEON_CP2_HSH_DATW+48(a0)
	358	dmtc2 t0, 0x0244
	359	ld t0, OCTEON_CP2_HSH_DATW+56(a0)
	360	dmtc2 t1, 0x0245
	361	ld t1, OCTEON_CP2_HSH_DATW+64(a0)
	362	dmtc2 t2, 0x0246
	363	ld t2, OCTEON_CP2_HSH_DATW+72(a0)
	364	dmtc2 t0, 0x0247
	365	ld t0, OCTEON_CP2_HSH_DATW+80(a0)
	366	dmtc2 t1, 0x0248
	367	ld t1, OCTEON_CP2_HSH_DATW+88(a0)
	368	dmtc2 t2, 0x0249
	369	ld t2, OCTEON_CP2_HSH_DATW+96(a0)
	370	dmtc2 t0, 0x024A
	371	ld t0, OCTEON_CP2_HSH_DATW+104(a0)
	372	dmtc2 t1, 0x024B
	373	ld t1, OCTEON_CP2_HSH_DATW+112(a0)
	374	dmtc2 t2, 0x024C
	375	ld t2, OCTEON_CP2_HSH_IVW(a0)
	376	dmtc2 t0, 0x024D
	377	ld t0, OCTEON_CP2_HSH_IVW+8(a0)
	378	dmtc2 t1, 0x024E
	379	ld t1, OCTEON_CP2_HSH_IVW+16(a0)
	380	dmtc2 t2, 0x0250
	381	ld t2, OCTEON_CP2_HSH_IVW+24(a0)
	382	dmtc2 t0, 0x0251
	383	ld t0, OCTEON_CP2_HSH_IVW+32(a0)
	384	dmtc2 t1, 0x0252
	385	ld t1, OCTEON_CP2_HSH_IVW+40(a0)
	386	dmtc2 t2, 0x0253
	387	ld t2, OCTEON_CP2_HSH_IVW+48(a0)
	388	dmtc2 t0, 0x0254
	389	ld t0, OCTEON_CP2_HSH_IVW+56(a0)
	390	dmtc2 t1, 0x0255
	391	ld t1, OCTEON_CP2_GFM_MULT(a0)
	392	dmtc2 t2, 0x0256
	393	ld t2, OCTEON_CP2_GFM_MULT+8(a0)
	394	dmtc2 t0, 0x0257
	395	ld t0, OCTEON_CP2_GFM_POLY(a0)
	396	dmtc2 t1, 0x0258
	397	ld t1, OCTEON_CP2_GFM_RESULT(a0)
	398	dmtc2 t2, 0x0259
	399	ld t2, OCTEON_CP2_GFM_RESULT+8(a0)
	400	dmtc2 t0, 0x025E
6b3a287e	401	subu v0, t3, v0 /* prid - lowest OCTEON III PrId */
5b3b1688	402	dmtc2 t1, 0x025A
6b3a287e DD	403	bltz v0, done_restore
	404	dmtc2 t2, 0x025B
	405	/* OCTEON III things*/
	406	ld t0, OCTEON_CP2_SHA3(a0)
	407	ld t1, OCTEON_CP2_SHA3+8(a0)
	408	dmtc2 t0, 0x0051
	409	dmtc2 t1, 0x0050
5b3b1688 DD	410	done_restore:
	411	jr ra
	412	nop
	413	END(octeon_cop2_restore)
	414	.set pop
	415
	416	/*
	417	* void octeon_mult_save()
	418	* sp is assumed to point to a struct pt_regs
	419	*
ac655fb7 DD	420	* NOTE: This is called in SAVE_TEMP in stackframe.h. It can
	421	* safely modify v1,k0, k1,$10-$15, and $24. It will
	422	* be overwritten with a processor specific version of the code.
5b3b1688	423	*/
ac655fb7	424	.p2align 7
5b3b1688 DD	425	.set push
	426	.set noreorder
	427	LEAF(octeon_mult_save)
ac655fb7	428	jr ra
5b3b1688	429	nop
ac655fb7 DD	430	.space 30 * 4, 0
	431	octeon_mult_save_end:
	432	EXPORT(octeon_mult_save_end)
	433	END(octeon_mult_save)
5b3b1688	434
ac655fb7 DD	435	LEAF(octeon_mult_save2)
ac655fb7 DD	436	/* Save the multiplier state OCTEON II and earlier*/
5b3b1688 DD	437	v3mulu k0, $0, $0
5b3b1688 DD	438	v3mulu k1, $0, $0
70342287	439	sd k0, PT_MTP(sp) /* PT_MTP has P0 */
5b3b1688 DD	440	v3mulu k0, $0, $0
	441	sd k1, PT_MTP+8(sp) /* PT_MTP+8 has P1 */
	442	ori k1, $0, 1
	443	v3mulu k1, k1, $0
	444	sd k0, PT_MTP+16(sp) /* PT_MTP+16 has P2 */
	445	v3mulu k0, $0, $0
70342287	446	sd k1, PT_MPL(sp) /* PT_MPL has MPL0 */
5b3b1688 DD	447	v3mulu k1, $0, $0
	448	sd k0, PT_MPL+8(sp) /* PT_MPL+8 has MPL1 */
	449	jr ra
	450	sd k1, PT_MPL+16(sp) /* PT_MPL+16 has MPL2 */
ac655fb7 DD	451	octeon_mult_save2_end:
	452	EXPORT(octeon_mult_save2_end)
	453	END(octeon_mult_save2)
	454
	455	LEAF(octeon_mult_save3)
	456	/* Save the multiplier state OCTEON III */
	457	v3mulu $10, $0, $0 /* read P0 */
	458	v3mulu $11, $0, $0 /* read P1 */
	459	v3mulu $12, $0, $0 /* read P2 */
	460	sd $10, PT_MTP+(08)(sp) / store P0 */
	461	v3mulu $10, $0, $0 /* read P3 */
	462	sd $11, PT_MTP+(18)(sp) / store P1 */
	463	v3mulu $11, $0, $0 /* read P4 */
	464	sd $12, PT_MTP+(28)(sp) / store P2 */
	465	ori $13, $0, 1
	466	v3mulu $12, $0, $0 /* read P5 */
	467	sd $10, PT_MTP+(38)(sp) / store P3 */
	468	v3mulu $13, $13, $0 /* P4-P0 = MPL5-MPL1, $13 = MPL0 */
	469	sd $11, PT_MTP+(48)(sp) / store P4 */
	470	v3mulu $10, $0, $0 /* read MPL1 */
	471	sd $12, PT_MTP+(58)(sp) / store P5 */
	472	v3mulu $11, $0, $0 /* read MPL2 */
	473	sd $13, PT_MPL+(08)(sp) / store MPL0 */
	474	v3mulu $12, $0, $0 /* read MPL3 */
	475	sd $10, PT_MPL+(18)(sp) / store MPL1 */
	476	v3mulu $10, $0, $0 /* read MPL4 */
	477	sd $11, PT_MPL+(28)(sp) / store MPL2 */
	478	v3mulu $11, $0, $0 /* read MPL5 */
	479	sd $12, PT_MPL+(38)(sp) / store MPL3 */
	480	sd $10, PT_MPL+(48)(sp) / store MPL4 */
5b3b1688	481	jr ra
ac655fb7 DD	482	sd $11, PT_MPL+(58)(sp) / store MPL5 */
	483	octeon_mult_save3_end:
	484	EXPORT(octeon_mult_save3_end)
	485	END(octeon_mult_save3)
5b3b1688 DD	486	.set pop
	487
	488	/*
	489	* void octeon_mult_restore()
	490	* sp is assumed to point to a struct pt_regs
	491	*
ac655fb7	492	* NOTE: This is called in RESTORE_TEMP in stackframe.h.
5b3b1688	493	*/
ac655fb7	494	.p2align 7
5b3b1688 DD	495	.set push
	496	.set noreorder
	497	LEAF(octeon_mult_restore)
ac655fb7 DD	498	jr ra
	499	nop
	500	.space 30 * 4, 0
	501	octeon_mult_restore_end:
	502	EXPORT(octeon_mult_restore_end)
	503	END(octeon_mult_restore)
5b3b1688	504
ac655fb7 DD	505	LEAF(octeon_mult_restore2)
	506	ld v0, PT_MPL(sp) /* MPL0 */
	507	ld v1, PT_MPL+8(sp) /* MPL1 */
	508	ld k0, PT_MPL+16(sp) /* MPL2 */
5b3b1688	509	/* Restore the multiplier state */
ac655fb7 DD	510	ld k1, PT_MTP+16(sp) /* P2 */
ac655fb7 DD	511	mtm0 v0 /* MPL0 */
5b3b1688	512	ld v0, PT_MTP+8(sp) /* P1 */
ac655fb7 DD	513	mtm1 v1 /* MPL1 */
	514	ld v1, PT_MTP(sp) /* P0 */
	515	mtm2 k0 /* MPL2 */
	516	mtp2 k1 /* P2 */
	517	mtp1 v0 /* P1 */
5b3b1688	518	jr ra
ac655fb7 DD	519	mtp0 v1 /* P0 */
	520	octeon_mult_restore2_end:
	521	EXPORT(octeon_mult_restore2_end)
	522	END(octeon_mult_restore2)
	523
	524	LEAF(octeon_mult_restore3)
	525	ld $12, PT_MPL+(08)(sp) / read MPL0 */
	526	ld $13, PT_MPL+(38)(sp) / read MPL3 */
	527	ld $10, PT_MPL+(18)(sp) / read MPL1 */
	528	ld $11, PT_MPL+(48)(sp) / read MPL4 */
	529	.word 0x718d0008
	530	/* mtm0 $12, $13 restore MPL0 and MPL3 */
	531	ld $12, PT_MPL+(28)(sp) / read MPL2 */
	532	.word 0x714b000c
	533	/* mtm1 $10, $11 restore MPL1 and MPL4 */
	534	ld $13, PT_MPL+(58)(sp) / read MPL5 */
	535	ld $10, PT_MTP+(08)(sp) / read P0 */
	536	ld $11, PT_MTP+(38)(sp) / read P3 */
	537	.word 0x718d000d
	538	/* mtm2 $12, $13 restore MPL2 and MPL5 */
	539	ld $12, PT_MTP+(18)(sp) / read P1 */
	540	.word 0x714b0009
	541	/* mtp0 $10, $11 restore P0 and P3 */
	542	ld $13, PT_MTP+(48)(sp) / read P4 */
	543	ld $10, PT_MTP+(28)(sp) / read P2 */
	544	ld $11, PT_MTP+(58)(sp) / read P5 */
	545	.word 0x718d000a
	546	/* mtp1 $12, $13 restore P1 and P4 */
5b3b1688	547	jr ra
ac655fb7 DD	548	.word 0x714b000b
	549	/* mtp2 $10, $11 restore P2 and P5 */
	550
	551	octeon_mult_restore3_end:
	552	EXPORT(octeon_mult_restore3_end)
	553	END(octeon_mult_restore3)
5b3b1688	554	.set pop