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Commit | Line | Data |
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1da177e4 | 1 | /* |
1da177e4 | 2 | * Copyright (C) 1995, 1996, 2001 Ralf Baechle |
4194318c | 3 | * Copyright (C) 2001, 2004 MIPS Technologies, Inc. |
70342287 | 4 | * Copyright (C) 2004 Maciej W. Rozycki |
1da177e4 | 5 | */ |
1da177e4 LT |
6 | #include <linux/delay.h> |
7 | #include <linux/kernel.h> | |
8 | #include <linux/sched.h> | |
9 | #include <linux/seq_file.h> | |
10 | #include <asm/bootinfo.h> | |
11 | #include <asm/cpu.h> | |
12 | #include <asm/cpu-features.h> | |
bdc92d74 | 13 | #include <asm/idle.h> |
1da177e4 LT |
14 | #include <asm/mipsregs.h> |
15 | #include <asm/processor.h> | |
9169a5d0 | 16 | #include <asm/prom.h> |
1da177e4 LT |
17 | |
18 | unsigned int vced_count, vcei_count; | |
19 | ||
d6d3c9af RB |
20 | /* |
21 | * * No lock; only written during early bootup by CPU 0. | |
22 | * */ | |
23 | static RAW_NOTIFIER_HEAD(proc_cpuinfo_chain); | |
24 | ||
25 | int __ref register_proc_cpuinfo_notifier(struct notifier_block *nb) | |
26 | { | |
27 | return raw_notifier_chain_register(&proc_cpuinfo_chain, nb); | |
28 | } | |
29 | ||
30 | int proc_cpuinfo_notifier_call_chain(unsigned long val, void *v) | |
31 | { | |
32 | return raw_notifier_call_chain(&proc_cpuinfo_chain, val, v); | |
33 | } | |
34 | ||
1da177e4 LT |
35 | static int show_cpuinfo(struct seq_file *m, void *v) |
36 | { | |
d6d3c9af | 37 | struct proc_cpuinfo_notifier_args proc_cpuinfo_notifier_args; |
1da177e4 | 38 | unsigned long n = (unsigned long) v - 1; |
31aa3665 KJK |
39 | unsigned int version = cpu_data[n].processor_id; |
40 | unsigned int fp_vers = cpu_data[n].fpu_id; | |
1da177e4 | 41 | char fmt [64]; |
654f57bf | 42 | int i; |
1da177e4 LT |
43 | |
44 | #ifdef CONFIG_SMP | |
0b5f9c00 | 45 | if (!cpu_online(n)) |
1da177e4 LT |
46 | return 0; |
47 | #endif | |
48 | ||
49 | /* | |
50 | * For the first processor also print the system type | |
51 | */ | |
487d70d0 | 52 | if (n == 0) { |
1da177e4 | 53 | seq_printf(m, "system type\t\t: %s\n", get_system_type()); |
487d70d0 GJ |
54 | if (mips_get_machine_name()) |
55 | seq_printf(m, "machine\t\t\t: %s\n", | |
56 | mips_get_machine_name()); | |
57 | } | |
1da177e4 LT |
58 | |
59 | seq_printf(m, "processor\t\t: %ld\n", n); | |
60 | sprintf(fmt, "cpu model\t\t: %%s V%%d.%%d%s\n", | |
03751e79 | 61 | cpu_data[n].options & MIPS_CPU_FPU ? " FPU V%d.%d" : ""); |
e47c659b | 62 | seq_printf(m, fmt, __cpu_name[n], |
03751e79 SH |
63 | (version >> 4) & 0x0f, version & 0x0f, |
64 | (fp_vers >> 4) & 0x0f, fp_vers & 0x0f); | |
5636919b | 65 | seq_printf(m, "BogoMIPS\t\t: %u.%02u\n", |
03751e79 SH |
66 | cpu_data[n].udelay_val / (500000/HZ), |
67 | (cpu_data[n].udelay_val / (5000/HZ)) % 100); | |
1da177e4 LT |
68 | seq_printf(m, "wait instruction\t: %s\n", cpu_wait ? "yes" : "no"); |
69 | seq_printf(m, "microsecond timers\t: %s\n", | |
03751e79 | 70 | cpu_has_counter ? "yes" : "no"); |
31aa3665 | 71 | seq_printf(m, "tlb_entries\t\t: %d\n", cpu_data[n].tlbsize); |
1da177e4 | 72 | seq_printf(m, "extra interrupt vector\t: %s\n", |
03751e79 | 73 | cpu_has_divec ? "yes" : "no"); |
654f57bf | 74 | seq_printf(m, "hardware watchpoint\t: %s", |
03751e79 | 75 | cpu_has_watch ? "yes, " : "no\n"); |
654f57bf DD |
76 | if (cpu_has_watch) { |
77 | seq_printf(m, "count: %d, address/irw mask: [", | |
03751e79 | 78 | cpu_data[n].watch_reg_count); |
654f57bf DD |
79 | for (i = 0; i < cpu_data[n].watch_reg_count; i++) |
80 | seq_printf(m, "%s0x%04x", i ? ", " : "" , | |
03751e79 | 81 | cpu_data[n].watch_reg_masks[i]); |
654f57bf DD |
82 | seq_printf(m, "]\n"); |
83 | } | |
41315b6e AK |
84 | |
85 | seq_printf(m, "isa\t\t\t: mips1"); | |
86 | if (cpu_has_mips_2) | |
87 | seq_printf(m, "%s", " mips2"); | |
88 | if (cpu_has_mips_3) | |
89 | seq_printf(m, "%s", " mips3"); | |
90 | if (cpu_has_mips_4) | |
91 | seq_printf(m, "%s", " mips4"); | |
92 | if (cpu_has_mips_5) | |
93 | seq_printf(m, "%s", " mips5"); | |
94 | if (cpu_has_mips32r1) | |
95 | seq_printf(m, "%s", " mips32r1"); | |
96 | if (cpu_has_mips32r2) | |
97 | seq_printf(m, "%s", " mips32r2"); | |
98 | if (cpu_has_mips64r1) | |
99 | seq_printf(m, "%s", " mips64r1"); | |
100 | if (cpu_has_mips64r2) | |
101 | seq_printf(m, "%s", " mips64r2"); | |
102 | seq_printf(m, "\n"); | |
981ef0de RB |
103 | |
104 | seq_printf(m, "ASEs implemented\t:"); | |
105 | if (cpu_has_mips16) seq_printf(m, "%s", " mips16"); | |
106 | if (cpu_has_mdmx) seq_printf(m, "%s", " mdmx"); | |
107 | if (cpu_has_mips3d) seq_printf(m, "%s", " mips3d"); | |
108 | if (cpu_has_smartmips) seq_printf(m, "%s", " smartmips"); | |
109 | if (cpu_has_dsp) seq_printf(m, "%s", " dsp"); | |
110 | if (cpu_has_dsp2) seq_printf(m, "%s", " dsp2"); | |
111 | if (cpu_has_mipsmt) seq_printf(m, "%s", " mt"); | |
f8fa4811 | 112 | if (cpu_has_mmips) seq_printf(m, "%s", " micromips"); |
1e7decdb | 113 | if (cpu_has_vz) seq_printf(m, "%s", " vz"); |
a5e9a69e | 114 | if (cpu_has_msa) seq_printf(m, "%s", " msa"); |
91119686 | 115 | if (cpu_has_eva) seq_printf(m, "%s", " eva"); |
e647e6b5 | 116 | if (cpu_has_htw) seq_printf(m, "%s", " htw"); |
981ef0de RB |
117 | seq_printf(m, "\n"); |
118 | ||
bce86083 SH |
119 | if (cpu_has_mmips) { |
120 | seq_printf(m, "micromips kernel\t: %s\n", | |
121 | (read_c0_config3() & MIPS_CONF3_ISA_OE) ? "yes" : "no"); | |
122 | } | |
f6771dbb | 123 | seq_printf(m, "shadow register sets\t: %d\n", |
03751e79 | 124 | cpu_data[n].srsets); |
e77c32fe | 125 | seq_printf(m, "kscratch registers\t: %d\n", |
03751e79 | 126 | hweight8(cpu_data[n].kscratch_mask)); |
bda4584c | 127 | seq_printf(m, "package\t\t\t: %d\n", cpu_data[n].package); |
0ab7aefc | 128 | seq_printf(m, "core\t\t\t: %d\n", cpu_data[n].core); |
5508d456 | 129 | |
1da177e4 | 130 | sprintf(fmt, "VCE%%c exceptions\t\t: %s\n", |
03751e79 | 131 | cpu_has_vce ? "%u" : "not available"); |
1da177e4 LT |
132 | seq_printf(m, fmt, 'D', vced_count); |
133 | seq_printf(m, fmt, 'I', vcei_count); | |
d6d3c9af RB |
134 | |
135 | proc_cpuinfo_notifier_args.m = m; | |
136 | proc_cpuinfo_notifier_args.n = n; | |
137 | ||
138 | raw_notifier_call_chain(&proc_cpuinfo_chain, 0, | |
139 | &proc_cpuinfo_notifier_args); | |
140 | ||
17256052 | 141 | seq_printf(m, "\n"); |
1da177e4 LT |
142 | |
143 | return 0; | |
144 | } | |
145 | ||
146 | static void *c_start(struct seq_file *m, loff_t *pos) | |
147 | { | |
148 | unsigned long i = *pos; | |
149 | ||
150 | return i < NR_CPUS ? (void *) (i + 1) : NULL; | |
151 | } | |
152 | ||
153 | static void *c_next(struct seq_file *m, void *v, loff_t *pos) | |
154 | { | |
155 | ++*pos; | |
156 | return c_start(m, pos); | |
157 | } | |
158 | ||
159 | static void c_stop(struct seq_file *m, void *v) | |
160 | { | |
161 | } | |
162 | ||
12323cac | 163 | const struct seq_operations cpuinfo_op = { |
1da177e4 LT |
164 | .start = c_start, |
165 | .next = c_next, | |
166 | .stop = c_stop, | |
167 | .show = show_cpuinfo, | |
168 | }; |