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Commit | Line | Data |
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1da177e4 | 1 | /* |
1da177e4 | 2 | * Copyright (C) 1995, 1996, 2001 Ralf Baechle |
4194318c | 3 | * Copyright (C) 2001, 2004 MIPS Technologies, Inc. |
70342287 | 4 | * Copyright (C) 2004 Maciej W. Rozycki |
1da177e4 | 5 | */ |
1da177e4 LT |
6 | #include <linux/delay.h> |
7 | #include <linux/kernel.h> | |
8 | #include <linux/sched.h> | |
9 | #include <linux/seq_file.h> | |
10 | #include <asm/bootinfo.h> | |
11 | #include <asm/cpu.h> | |
12 | #include <asm/cpu-features.h> | |
bdc92d74 | 13 | #include <asm/idle.h> |
1da177e4 LT |
14 | #include <asm/mipsregs.h> |
15 | #include <asm/processor.h> | |
9169a5d0 | 16 | #include <asm/prom.h> |
1da177e4 LT |
17 | |
18 | unsigned int vced_count, vcei_count; | |
19 | ||
1da177e4 LT |
20 | static int show_cpuinfo(struct seq_file *m, void *v) |
21 | { | |
1da177e4 | 22 | unsigned long n = (unsigned long) v - 1; |
31aa3665 KJK |
23 | unsigned int version = cpu_data[n].processor_id; |
24 | unsigned int fp_vers = cpu_data[n].fpu_id; | |
1da177e4 | 25 | char fmt [64]; |
654f57bf | 26 | int i; |
1da177e4 LT |
27 | |
28 | #ifdef CONFIG_SMP | |
0b5f9c00 | 29 | if (!cpu_online(n)) |
1da177e4 LT |
30 | return 0; |
31 | #endif | |
32 | ||
33 | /* | |
34 | * For the first processor also print the system type | |
35 | */ | |
487d70d0 | 36 | if (n == 0) { |
1da177e4 | 37 | seq_printf(m, "system type\t\t: %s\n", get_system_type()); |
487d70d0 GJ |
38 | if (mips_get_machine_name()) |
39 | seq_printf(m, "machine\t\t\t: %s\n", | |
40 | mips_get_machine_name()); | |
41 | } | |
1da177e4 LT |
42 | |
43 | seq_printf(m, "processor\t\t: %ld\n", n); | |
44 | sprintf(fmt, "cpu model\t\t: %%s V%%d.%%d%s\n", | |
03751e79 | 45 | cpu_data[n].options & MIPS_CPU_FPU ? " FPU V%d.%d" : ""); |
e47c659b | 46 | seq_printf(m, fmt, __cpu_name[n], |
03751e79 SH |
47 | (version >> 4) & 0x0f, version & 0x0f, |
48 | (fp_vers >> 4) & 0x0f, fp_vers & 0x0f); | |
5636919b | 49 | seq_printf(m, "BogoMIPS\t\t: %u.%02u\n", |
03751e79 SH |
50 | cpu_data[n].udelay_val / (500000/HZ), |
51 | (cpu_data[n].udelay_val / (5000/HZ)) % 100); | |
1da177e4 LT |
52 | seq_printf(m, "wait instruction\t: %s\n", cpu_wait ? "yes" : "no"); |
53 | seq_printf(m, "microsecond timers\t: %s\n", | |
03751e79 | 54 | cpu_has_counter ? "yes" : "no"); |
31aa3665 | 55 | seq_printf(m, "tlb_entries\t\t: %d\n", cpu_data[n].tlbsize); |
1da177e4 | 56 | seq_printf(m, "extra interrupt vector\t: %s\n", |
03751e79 | 57 | cpu_has_divec ? "yes" : "no"); |
654f57bf | 58 | seq_printf(m, "hardware watchpoint\t: %s", |
03751e79 | 59 | cpu_has_watch ? "yes, " : "no\n"); |
654f57bf DD |
60 | if (cpu_has_watch) { |
61 | seq_printf(m, "count: %d, address/irw mask: [", | |
03751e79 | 62 | cpu_data[n].watch_reg_count); |
654f57bf DD |
63 | for (i = 0; i < cpu_data[n].watch_reg_count; i++) |
64 | seq_printf(m, "%s0x%04x", i ? ", " : "" , | |
03751e79 | 65 | cpu_data[n].watch_reg_masks[i]); |
654f57bf DD |
66 | seq_printf(m, "]\n"); |
67 | } | |
41315b6e AK |
68 | |
69 | seq_printf(m, "isa\t\t\t: mips1"); | |
70 | if (cpu_has_mips_2) | |
71 | seq_printf(m, "%s", " mips2"); | |
72 | if (cpu_has_mips_3) | |
73 | seq_printf(m, "%s", " mips3"); | |
74 | if (cpu_has_mips_4) | |
75 | seq_printf(m, "%s", " mips4"); | |
76 | if (cpu_has_mips_5) | |
77 | seq_printf(m, "%s", " mips5"); | |
78 | if (cpu_has_mips32r1) | |
79 | seq_printf(m, "%s", " mips32r1"); | |
80 | if (cpu_has_mips32r2) | |
81 | seq_printf(m, "%s", " mips32r2"); | |
82 | if (cpu_has_mips64r1) | |
83 | seq_printf(m, "%s", " mips64r1"); | |
84 | if (cpu_has_mips64r2) | |
85 | seq_printf(m, "%s", " mips64r2"); | |
86 | seq_printf(m, "\n"); | |
981ef0de RB |
87 | |
88 | seq_printf(m, "ASEs implemented\t:"); | |
89 | if (cpu_has_mips16) seq_printf(m, "%s", " mips16"); | |
90 | if (cpu_has_mdmx) seq_printf(m, "%s", " mdmx"); | |
91 | if (cpu_has_mips3d) seq_printf(m, "%s", " mips3d"); | |
92 | if (cpu_has_smartmips) seq_printf(m, "%s", " smartmips"); | |
93 | if (cpu_has_dsp) seq_printf(m, "%s", " dsp"); | |
94 | if (cpu_has_dsp2) seq_printf(m, "%s", " dsp2"); | |
95 | if (cpu_has_mipsmt) seq_printf(m, "%s", " mt"); | |
f8fa4811 | 96 | if (cpu_has_mmips) seq_printf(m, "%s", " micromips"); |
1e7decdb | 97 | if (cpu_has_vz) seq_printf(m, "%s", " vz"); |
981ef0de RB |
98 | seq_printf(m, "\n"); |
99 | ||
bce86083 SH |
100 | if (cpu_has_mmips) { |
101 | seq_printf(m, "micromips kernel\t: %s\n", | |
102 | (read_c0_config3() & MIPS_CONF3_ISA_OE) ? "yes" : "no"); | |
103 | } | |
f6771dbb | 104 | seq_printf(m, "shadow register sets\t: %d\n", |
03751e79 | 105 | cpu_data[n].srsets); |
e77c32fe | 106 | seq_printf(m, "kscratch registers\t: %d\n", |
03751e79 | 107 | hweight8(cpu_data[n].kscratch_mask)); |
0ab7aefc | 108 | seq_printf(m, "core\t\t\t: %d\n", cpu_data[n].core); |
795038a6 MC |
109 | #if defined(CONFIG_MIPS_MT_SMP) || defined(CONFIG_MIPS_MT_SMTC) |
110 | if (cpu_has_mipsmt) { | |
111 | seq_printf(m, "VPE\t\t\t: %d\n", cpu_data[n].vpe_id); | |
112 | #if defined(CONFIG_MIPS_MT_SMTC) | |
113 | seq_printf(m, "TC\t\t\t: %d\n", cpu_data[n].tc_id); | |
114 | #endif | |
115 | } | |
116 | #endif | |
1da177e4 | 117 | sprintf(fmt, "VCE%%c exceptions\t\t: %s\n", |
03751e79 | 118 | cpu_has_vce ? "%u" : "not available"); |
1da177e4 LT |
119 | seq_printf(m, fmt, 'D', vced_count); |
120 | seq_printf(m, fmt, 'I', vcei_count); | |
17256052 | 121 | seq_printf(m, "\n"); |
1da177e4 LT |
122 | |
123 | return 0; | |
124 | } | |
125 | ||
126 | static void *c_start(struct seq_file *m, loff_t *pos) | |
127 | { | |
128 | unsigned long i = *pos; | |
129 | ||
130 | return i < NR_CPUS ? (void *) (i + 1) : NULL; | |
131 | } | |
132 | ||
133 | static void *c_next(struct seq_file *m, void *v, loff_t *pos) | |
134 | { | |
135 | ++*pos; | |
136 | return c_start(m, pos); | |
137 | } | |
138 | ||
139 | static void c_stop(struct seq_file *m, void *v) | |
140 | { | |
141 | } | |
142 | ||
12323cac | 143 | const struct seq_operations cpuinfo_op = { |
1da177e4 LT |
144 | .start = c_start, |
145 | .next = c_next, | |
146 | .stop = c_stop, | |
147 | .show = show_cpuinfo, | |
148 | }; |