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MIPS: Prevent unaligned accesses during stack unwinding
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CommitLineData
1da177e4
LT
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1994 - 1999, 2000 by Ralf Baechle and others.
40ac5d47 7 * Copyright (C) 2005, 2006 by Ralf Baechle (ralf@linux-mips.org)
1da177e4
LT
8 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
9 * Copyright (C) 2004 Thiemo Seufer
34c2f668 10 * Copyright (C) 2013 Imagination Technologies Ltd.
1da177e4 11 */
1da177e4 12#include <linux/errno.h>
1da177e4 13#include <linux/sched.h>
7bcf7717 14#include <linux/tick.h>
1da177e4
LT
15#include <linux/kernel.h>
16#include <linux/mm.h>
17#include <linux/stddef.h>
18#include <linux/unistd.h>
cae39d13 19#include <linux/export.h>
1da177e4 20#include <linux/ptrace.h>
1da177e4
LT
21#include <linux/mman.h>
22#include <linux/personality.h>
23#include <linux/sys.h>
1da177e4
LT
24#include <linux/init.h>
25#include <linux/completion.h>
63077519 26#include <linux/kallsyms.h>
94109102 27#include <linux/random.h>
9791554b 28#include <linux/prctl.h>
1da177e4 29
94109102 30#include <asm/asm.h>
1da177e4
LT
31#include <asm/bootinfo.h>
32#include <asm/cpu.h>
432c6bac 33#include <asm/dsemul.h>
e50c0a8f 34#include <asm/dsp.h>
1da177e4 35#include <asm/fpu.h>
d42d8d10 36#include <asm/irq.h>
1db1af84 37#include <asm/msa.h>
1da177e4 38#include <asm/pgtable.h>
1da177e4
LT
39#include <asm/mipsregs.h>
40#include <asm/processor.h>
60be939c 41#include <asm/reg.h>
7c0f6ba6 42#include <linux/uaccess.h>
1da177e4
LT
43#include <asm/io.h>
44#include <asm/elf.h>
45#include <asm/isadep.h>
46#include <asm/inst.h>
1df0f0ff 47#include <asm/stacktrace.h>
856839b7 48#include <asm/irq_regs.h>
1da177e4 49
cdbedc61
TG
50#ifdef CONFIG_HOTPLUG_CPU
51void arch_cpu_idle_dead(void)
1da177e4 52{
cdbedc61 53 /* What the heck is this check doing ? */
8dd92891 54 if (!cpumask_test_cpu(smp_processor_id(), &cpu_callin_map))
cdbedc61
TG
55 play_dead();
56}
57#endif
1b2bc75c 58
1da177e4 59asmlinkage void ret_from_fork(void);
8f54bcac 60asmlinkage void ret_from_kernel_thread(void);
1da177e4
LT
61
62void start_thread(struct pt_regs * regs, unsigned long pc, unsigned long sp)
63{
64 unsigned long status;
65
66 /* New thread loses kernel privileges. */
bbaf238b 67 status = regs->cp0_status & ~(ST0_CU0|ST0_CU1|ST0_FR|KU_MASK);
1da177e4
LT
68 status |= KU_USER;
69 regs->cp0_status = status;
76e5846d
JH
70 lose_fpu(0);
71 clear_thread_flag(TIF_MSA_CTX_LIVE);
1da177e4 72 clear_used_math();
432c6bac 73 atomic_set(&current->thread.bd_emu_frame, BD_EMUFRAME_NONE);
a3056b1c 74 init_dsp();
1da177e4
LT
75 regs->cp0_epc = pc;
76 regs->regs[29] = sp;
1da177e4
LT
77}
78
432c6bac
PB
79void exit_thread(struct task_struct *tsk)
80{
81 /*
82 * User threads may have allocated a delay slot emulation frame.
83 * If so, clean up that allocation.
84 */
85 if (!(current->flags & PF_KTHREAD))
86 dsemul_thread_cleanup(tsk);
87}
88
39148e94
JH
89int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
90{
91 /*
92 * Save any process state which is live in hardware registers to the
93 * parent context prior to duplication. This prevents the new child
94 * state becoming stale if the parent is preempted before copy_thread()
95 * gets a chance to save the parent's live hardware registers to the
96 * child context.
97 */
98 preempt_disable();
99
100 if (is_msa_enabled())
101 save_msa(current);
102 else if (is_fpu_owner())
103 _save_fp(current);
104
105 save_dsp(current);
106
107 preempt_enable();
108
109 *dst = *src;
110 return 0;
111}
112
e2c5aaa5
AD
113/*
114 * Copy architecture-specific thread state
115 */
6f2c55b8 116int copy_thread(unsigned long clone_flags, unsigned long usp,
e2c5aaa5 117 unsigned long kthread_arg, struct task_struct *p)
1da177e4 118{
75bb07e7 119 struct thread_info *ti = task_thread_info(p);
afa86fc4 120 struct pt_regs *childregs, *regs = current_pt_regs();
484889fc 121 unsigned long childksp;
3c37026d 122 p->set_child_tid = p->clear_child_tid = NULL;
1da177e4 123
75bb07e7 124 childksp = (unsigned long)task_stack_page(p) + THREAD_SIZE - 32;
1da177e4 125
1da177e4
LT
126 /* set up new TSS. */
127 childregs = (struct pt_regs *) childksp - 1;
484889fc
DD
128 /* Put the stack after the struct pt_regs. */
129 childksp = (unsigned long) childregs;
8f54bcac
AV
130 p->thread.cp0_status = read_c0_status() & ~(ST0_CU2|ST0_CU1);
131 if (unlikely(p->flags & PF_KTHREAD)) {
e2c5aaa5 132 /* kernel thread */
8f54bcac
AV
133 unsigned long status = p->thread.cp0_status;
134 memset(childregs, 0, sizeof(struct pt_regs));
135 ti->addr_limit = KERNEL_DS;
136 p->thread.reg16 = usp; /* fn */
e2c5aaa5 137 p->thread.reg17 = kthread_arg;
8f54bcac
AV
138 p->thread.reg29 = childksp;
139 p->thread.reg31 = (unsigned long) ret_from_kernel_thread;
140#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
141 status = (status & ~(ST0_KUP | ST0_IEP | ST0_IEC)) |
142 ((status & (ST0_KUC | ST0_IEC)) << 2);
143#else
144 status |= ST0_EXL;
145#endif
146 childregs->cp0_status = status;
147 return 0;
148 }
e2c5aaa5
AD
149
150 /* user thread */
1da177e4 151 *childregs = *regs;
70342287
RB
152 childregs->regs[7] = 0; /* Clear error flag */
153 childregs->regs[2] = 0; /* Child gets zero as return value */
64b3122d
AV
154 if (usp)
155 childregs->regs[29] = usp;
8f54bcac 156 ti->addr_limit = USER_DS;
1da177e4 157
1da177e4
LT
158 p->thread.reg29 = (unsigned long) childregs;
159 p->thread.reg31 = (unsigned long) ret_from_fork;
160
161 /*
162 * New tasks lose permission to use the fpu. This accelerates context
163 * switching for most programs since they don't use the fpu.
164 */
1da177e4 165 childregs->cp0_status &= ~(ST0_CU2|ST0_CU1);
1da177e4 166
1da177e4 167 clear_tsk_thread_flag(p, TIF_USEDFPU);
7daef8f2
PB
168 clear_tsk_thread_flag(p, TIF_USEDMSA);
169 clear_tsk_thread_flag(p, TIF_MSA_CTX_LIVE);
1da177e4 170
f088fc84 171#ifdef CONFIG_MIPS_MT_FPAFF
6657fe0a 172 clear_tsk_thread_flag(p, TIF_FPUBOUND);
f088fc84
RB
173#endif /* CONFIG_MIPS_MT_FPAFF */
174
432c6bac
PB
175 atomic_set(&p->thread.bd_emu_frame, BD_EMUFRAME_NONE);
176
3c37026d
RB
177 if (clone_flags & CLONE_SETTLS)
178 ti->tp_value = regs->regs[7];
179
1da177e4
LT
180 return 0;
181}
182
36ecafc5
GF
183#ifdef CONFIG_CC_STACKPROTECTOR
184#include <linux/stackprotector.h>
185unsigned long __stack_chk_guard __read_mostly;
186EXPORT_SYMBOL(__stack_chk_guard);
187#endif
188
b5943182
FBH
189struct mips_frame_info {
190 void *func;
191 unsigned long func_size;
192 int frame_size;
193 int pc_offset;
194};
dc953df1 195
5000653e
TW
196#define J_TARGET(pc,target) \
197 (((unsigned long)(pc) & 0xf0000000) | ((target) << 2))
198
c0efbb6d
FBH
199static inline int is_ra_save_ins(union mips_instruction *ip)
200{
34c2f668 201#ifdef CONFIG_CPU_MICROMIPS
34c2f668
LY
202 /*
203 * swsp ra,offset
204 * swm16 reglist,offset(sp)
205 * swm32 reglist,offset(sp)
206 * sw32 ra,offset(sp)
207 * jradiussp - NOT SUPPORTED
208 *
209 * microMIPS is way more fun...
210 */
a3552dac
PB
211 if (mm_insn_16bit(ip->halfword[1])) {
212 return (ip->mm16_r5_format.opcode == mm_swsp16_op &&
213 ip->mm16_r5_format.rt == 31) ||
214 (ip->mm16_m_format.opcode == mm_pool16c_op &&
215 ip->mm16_m_format.func == mm_swm16_op);
34c2f668
LY
216 }
217 else {
a3552dac
PB
218 return (ip->mm_m_format.opcode == mm_pool32b_op &&
219 ip->mm_m_format.rd > 9 &&
220 ip->mm_m_format.base == 29 &&
221 ip->mm_m_format.func == mm_swm32_func) ||
222 (ip->i_format.opcode == mm_sw32_op &&
223 ip->i_format.rs == 29 &&
224 ip->i_format.rt == 31);
34c2f668
LY
225 }
226#else
c0efbb6d
FBH
227 /* sw / sd $ra, offset($sp) */
228 return (ip->i_format.opcode == sw_op || ip->i_format.opcode == sd_op) &&
229 ip->i_format.rs == 29 &&
230 ip->i_format.rt == 31;
34c2f668 231#endif
c0efbb6d
FBH
232}
233
e7438c4b 234static inline int is_jump_ins(union mips_instruction *ip)
c0efbb6d 235{
34c2f668
LY
236#ifdef CONFIG_CPU_MICROMIPS
237 /*
238 * jr16,jrc,jalr16,jalr16
239 * jal
240 * jalr/jr,jalr.hb/jr.hb,jalrs,jalrs.hb
241 * jraddiusp - NOT SUPPORTED
242 *
243 * microMIPS is kind of more fun...
244 */
a3552dac
PB
245 if ((ip->mm16_r5_format.opcode == mm_pool16c_op &&
246 (ip->mm16_r5_format.rt & mm_jr16_op) == mm_jr16_op) ||
34c2f668
LY
247 ip->j_format.opcode == mm_jal32_op)
248 return 1;
249 if (ip->r_format.opcode != mm_pool32a_op ||
250 ip->r_format.func != mm_pool32axf_op)
251 return 0;
635c9907 252 return ((ip->u_format.uimmediate >> 6) & mm_jalr_op) == mm_jalr_op;
34c2f668 253#else
e7438c4b
TW
254 if (ip->j_format.opcode == j_op)
255 return 1;
c0efbb6d
FBH
256 if (ip->j_format.opcode == jal_op)
257 return 1;
258 if (ip->r_format.opcode != spec_op)
259 return 0;
260 return ip->r_format.func == jalr_op || ip->r_format.func == jr_op;
34c2f668 261#endif
c0efbb6d
FBH
262}
263
264static inline int is_sp_move_ins(union mips_instruction *ip)
265{
34c2f668
LY
266#ifdef CONFIG_CPU_MICROMIPS
267 /*
268 * addiusp -imm
269 * addius5 sp,-imm
270 * addiu32 sp,sp,-imm
271 * jradiussp - NOT SUPPORTED
272 *
273 * microMIPS is not more fun...
274 */
a3552dac
PB
275 if (mm_insn_16bit(ip->halfword[1])) {
276 return (ip->mm16_r3_format.opcode == mm_pool16d_op &&
277 ip->mm16_r3_format.simmediate && mm_addiusp_func) ||
278 (ip->mm16_r5_format.opcode == mm_pool16d_op &&
279 ip->mm16_r5_format.rt == 29);
34c2f668 280 }
a3552dac 281
635c9907
RB
282 return ip->mm_i_format.opcode == mm_addiu32_op &&
283 ip->mm_i_format.rt == 29 && ip->mm_i_format.rs == 29;
34c2f668 284#else
c0efbb6d
FBH
285 /* addiu/daddiu sp,sp,-imm */
286 if (ip->i_format.rs != 29 || ip->i_format.rt != 29)
287 return 0;
288 if (ip->i_format.opcode == addiu_op || ip->i_format.opcode == daddiu_op)
289 return 1;
34c2f668 290#endif
c0efbb6d
FBH
291 return 0;
292}
293
f66686f7 294static int get_frame_info(struct mips_frame_info *info)
1da177e4 295{
a3552dac
PB
296 bool is_mmips = IS_ENABLED(CONFIG_CPU_MICROMIPS);
297 union mips_instruction insn, *ip;
29b376ff
FBH
298 unsigned max_insns = info->func_size / sizeof(union mips_instruction);
299 unsigned i;
c0efbb6d 300
1da177e4 301 info->pc_offset = -1;
63077519 302 info->frame_size = 0;
1da177e4 303
ccaf7caf 304 ip = (void *)msk_isa16_mode((ulong)info->func);
29b376ff
FBH
305 if (!ip)
306 goto err;
307
308 if (max_insns == 0)
309 max_insns = 128U; /* unknown function size */
310 max_insns = min(128U, max_insns);
311
c0efbb6d 312 for (i = 0; i < max_insns; i++, ip++) {
a3552dac
PB
313 if (is_mmips && mm_insn_16bit(ip->halfword[0])) {
314 insn.halfword[0] = 0;
315 insn.halfword[1] = ip->halfword[0];
316 } else if (is_mmips) {
317 insn.halfword[0] = ip->halfword[1];
318 insn.halfword[1] = ip->halfword[0];
319 } else {
320 insn.word = ip->word;
321 }
c0efbb6d 322
a3552dac 323 if (is_jump_ins(&insn))
63077519 324 break;
a3552dac 325
0cceb4aa 326 if (!info->frame_size) {
a3552dac 327 if (is_sp_move_ins(&insn))
34c2f668
LY
328 {
329#ifdef CONFIG_CPU_MICROMIPS
330 if (mm_insn_16bit(ip->halfword[0]))
331 {
332 unsigned short tmp;
333
334 if (ip->halfword[0] & mm_addiusp_func)
335 {
336 tmp = (((ip->halfword[0] >> 1) & 0x1ff) << 2);
337 info->frame_size = -(signed short)(tmp | ((tmp & 0x100) ? 0xfe00 : 0));
338 } else {
339 tmp = (ip->halfword[0] >> 1);
340 info->frame_size = -(signed short)(tmp & 0xf);
341 }
342 ip = (void *) &ip->halfword[1];
343 ip--;
344 } else
345#endif
0cceb4aa 346 info->frame_size = - ip->i_format.simmediate;
34c2f668 347 }
0cceb4aa 348 continue;
63077519 349 }
a3552dac 350 if (info->pc_offset == -1 && is_ra_save_ins(&insn)) {
63077519
AN
351 info->pc_offset =
352 ip->i_format.simmediate / sizeof(long);
0cceb4aa 353 break;
1da177e4
LT
354 }
355 }
f66686f7
AN
356 if (info->frame_size && info->pc_offset >= 0) /* nested */
357 return 0;
358 if (info->pc_offset < 0) /* leaf */
359 return 1;
a90c59e6 360 /* prologue seems bogus... */
29b376ff 361err:
f66686f7 362 return -1;
1da177e4
LT
363}
364
b5943182
FBH
365static struct mips_frame_info schedule_mfi __read_mostly;
366
5000653e
TW
367#ifdef CONFIG_KALLSYMS
368static unsigned long get___schedule_addr(void)
369{
370 return kallsyms_lookup_name("__schedule");
371}
372#else
373static unsigned long get___schedule_addr(void)
374{
375 union mips_instruction *ip = (void *)schedule;
376 int max_insns = 8;
377 int i;
378
379 for (i = 0; i < max_insns; i++, ip++) {
380 if (ip->j_format.opcode == j_op)
381 return J_TARGET(ip, ip->j_format.target);
382 }
383 return 0;
384}
385#endif
386
1da177e4
LT
387static int __init frame_info_init(void)
388{
b5943182 389 unsigned long size = 0;
63077519 390#ifdef CONFIG_KALLSYMS
b5943182 391 unsigned long ofs;
5000653e
TW
392#endif
393 unsigned long addr;
b5943182 394
5000653e
TW
395 addr = get___schedule_addr();
396 if (!addr)
397 addr = (unsigned long)schedule;
398
399#ifdef CONFIG_KALLSYMS
400 kallsyms_lookup_size_offset(addr, &size, &ofs);
63077519 401#endif
5000653e 402 schedule_mfi.func = (void *)addr;
b5943182
FBH
403 schedule_mfi.func_size = size;
404
405 get_frame_info(&schedule_mfi);
6057a798
FBH
406
407 /*
408 * Without schedule() frame info, result given by
409 * thread_saved_pc() and get_wchan() are not reliable.
410 */
b5943182 411 if (schedule_mfi.pc_offset < 0)
6057a798 412 printk("Can't analyze schedule() prologue at %p\n", schedule);
63077519 413
1da177e4
LT
414 return 0;
415}
416
417arch_initcall(frame_info_init);
418
419/*
420 * Return saved PC of a blocked thread.
421 */
422unsigned long thread_saved_pc(struct task_struct *tsk)
423{
424 struct thread_struct *t = &tsk->thread;
425
426 /* New born processes are a special case */
427 if (t->reg31 == (unsigned long) ret_from_fork)
428 return t->reg31;
b5943182 429 if (schedule_mfi.pc_offset < 0)
1da177e4 430 return 0;
b5943182 431 return ((unsigned long *)t->reg29)[schedule_mfi.pc_offset];
1da177e4
LT
432}
433
1da177e4 434
f66686f7 435#ifdef CONFIG_KALLSYMS
94ea09c6
DK
436/* generic stack unwinding function */
437unsigned long notrace unwind_stack_by_address(unsigned long stack_page,
438 unsigned long *sp,
439 unsigned long pc,
440 unsigned long *ra)
f66686f7 441{
f66686f7 442 struct mips_frame_info info;
f66686f7 443 unsigned long size, ofs;
4d157d5e 444 int leaf;
1924600c
AN
445 extern void ret_from_irq(void);
446 extern void ret_from_exception(void);
f66686f7 447
f66686f7
AN
448 if (!stack_page)
449 return 0;
450
1924600c
AN
451 /*
452 * If we reached the bottom of interrupt context,
453 * return saved pc in pt_regs.
454 */
455 if (pc == (unsigned long)ret_from_irq ||
456 pc == (unsigned long)ret_from_exception) {
457 struct pt_regs *regs;
458 if (*sp >= stack_page &&
459 *sp + sizeof(*regs) <= stack_page + THREAD_SIZE - 32) {
460 regs = (struct pt_regs *)*sp;
461 pc = regs->cp0_epc;
a816b306 462 if (!user_mode(regs) && __kernel_text_address(pc)) {
1924600c
AN
463 *sp = regs->regs[29];
464 *ra = regs->regs[31];
465 return pc;
466 }
467 }
468 return 0;
469 }
55b74283 470 if (!kallsyms_lookup_size_offset(pc, &size, &ofs))
f66686f7 471 return 0;
1fd69098 472 /*
25985edc 473 * Return ra if an exception occurred at the first instruction
1fd69098 474 */
1924600c
AN
475 if (unlikely(ofs == 0)) {
476 pc = *ra;
477 *ra = 0;
478 return pc;
479 }
f66686f7
AN
480
481 info.func = (void *)(pc - ofs);
482 info.func_size = ofs; /* analyze from start to ofs */
4d157d5e
FBH
483 leaf = get_frame_info(&info);
484 if (leaf < 0)
f66686f7 485 return 0;
4d157d5e
FBH
486
487 if (*sp < stack_page ||
488 *sp + info.frame_size > stack_page + THREAD_SIZE - 32)
f66686f7
AN
489 return 0;
490
4d157d5e
FBH
491 if (leaf)
492 /*
493 * For some extreme cases, get_frame_info() can
494 * consider wrongly a nested function as a leaf
495 * one. In that cases avoid to return always the
496 * same value.
497 */
1924600c 498 pc = pc != *ra ? *ra : 0;
4d157d5e
FBH
499 else
500 pc = ((unsigned long *)(*sp))[info.pc_offset];
501
502 *sp += info.frame_size;
1924600c 503 *ra = 0;
4d157d5e 504 return __kernel_text_address(pc) ? pc : 0;
f66686f7 505}
94ea09c6
DK
506EXPORT_SYMBOL(unwind_stack_by_address);
507
508/* used by show_backtrace() */
509unsigned long unwind_stack(struct task_struct *task, unsigned long *sp,
510 unsigned long pc, unsigned long *ra)
511{
d42d8d10
MR
512 unsigned long stack_page = 0;
513 int cpu;
514
515 for_each_possible_cpu(cpu) {
516 if (on_irq_stack(cpu, *sp)) {
517 stack_page = (unsigned long)irq_stack[cpu];
518 break;
519 }
520 }
521
522 if (!stack_page)
523 stack_page = (unsigned long)task_stack_page(task);
524
94ea09c6
DK
525 return unwind_stack_by_address(stack_page, sp, pc, ra);
526}
f66686f7 527#endif
b5943182
FBH
528
529/*
530 * get_wchan - a maintenance nightmare^W^Wpain in the ass ...
531 */
532unsigned long get_wchan(struct task_struct *task)
533{
534 unsigned long pc = 0;
535#ifdef CONFIG_KALLSYMS
536 unsigned long sp;
1924600c 537 unsigned long ra = 0;
b5943182
FBH
538#endif
539
540 if (!task || task == current || task->state == TASK_RUNNING)
541 goto out;
542 if (!task_stack_page(task))
543 goto out;
544
545 pc = thread_saved_pc(task);
546
547#ifdef CONFIG_KALLSYMS
548 sp = task->thread.reg29 + schedule_mfi.frame_size;
549
550 while (in_sched_functions(pc))
1924600c 551 pc = unwind_stack(task, &sp, pc, &ra);
b5943182
FBH
552#endif
553
554out:
555 return pc;
556}
94109102
FBH
557
558/*
559 * Don't forget that the stack pointer must be aligned on a 8 bytes
560 * boundary for 32-bits ABI and 16 bytes for 64-bits ABI.
561 */
562unsigned long arch_align_stack(unsigned long sp)
563{
564 if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
565 sp -= get_random_int() & ~PAGE_MASK;
566
567 return sp & ALMASK;
568}
856839b7
ES
569
570static void arch_dump_stack(void *info)
571{
572 struct pt_regs *regs;
573
574 regs = get_irq_regs();
575
576 if (regs)
577 show_regs(regs);
578
579 dump_stack();
580}
581
9a01c3ed 582void arch_trigger_cpumask_backtrace(const cpumask_t *mask, bool exclude_self)
856839b7 583{
9a01c3ed
CM
584 long this_cpu = get_cpu();
585
586 if (cpumask_test_cpu(this_cpu, mask) && !exclude_self)
587 dump_stack();
588
589 smp_call_function_many(mask, arch_dump_stack, NULL, 1);
590
591 put_cpu();
856839b7 592}
9791554b
PB
593
594int mips_get_process_fp_mode(struct task_struct *task)
595{
596 int value = 0;
597
598 if (!test_tsk_thread_flag(task, TIF_32BIT_FPREGS))
599 value |= PR_FP_MODE_FR;
600 if (test_tsk_thread_flag(task, TIF_HYBRID_FPREGS))
601 value |= PR_FP_MODE_FRE;
602
603 return value;
604}
605
6b832257
PB
606static void prepare_for_fp_mode_switch(void *info)
607{
608 struct mm_struct *mm = info;
609
610 if (current->mm == mm)
611 lose_fpu(1);
612}
613
9791554b
PB
614int mips_set_process_fp_mode(struct task_struct *task, unsigned int value)
615{
616 const unsigned int known_bits = PR_FP_MODE_FR | PR_FP_MODE_FRE;
9791554b 617 struct task_struct *t;
6b832257 618 int max_users;
9791554b
PB
619
620 /* Check the value is valid */
621 if (value & ~known_bits)
622 return -EOPNOTSUPP;
623
624 /* Avoid inadvertently triggering emulation */
b244614a
MN
625 if ((value & PR_FP_MODE_FR) && raw_cpu_has_fpu &&
626 !(raw_current_cpu_data.fpu_id & MIPS_FPIR_F64))
9791554b 627 return -EOPNOTSUPP;
b244614a 628 if ((value & PR_FP_MODE_FRE) && raw_cpu_has_fpu && !cpu_has_fre)
9791554b
PB
629 return -EOPNOTSUPP;
630
13e45f09 631 /* FR = 0 not supported in MIPS R6 */
b244614a 632 if (!(value & PR_FP_MODE_FR) && raw_cpu_has_fpu && cpu_has_mips_r6)
13e45f09
MC
633 return -EOPNOTSUPP;
634
bd239f1e
PB
635 /* Proceed with the mode switch */
636 preempt_disable();
637
9791554b
PB
638 /* Save FP & vector context, then disable FPU & MSA */
639 if (task->signal == current->signal)
640 lose_fpu(1);
641
642 /* Prevent any threads from obtaining live FP context */
643 atomic_set(&task->mm->context.fp_mode_switching, 1);
644 smp_mb__after_atomic();
645
646 /*
6b832257
PB
647 * If there are multiple online CPUs then force any which are running
648 * threads in this process to lose their FPU context, which they can't
649 * regain until fp_mode_switching is cleared later.
9791554b
PB
650 */
651 if (num_online_cpus() > 1) {
6b832257
PB
652 /* No need to send an IPI for the local CPU */
653 max_users = (task->mm == current->mm) ? 1 : 0;
9791554b 654
6b832257
PB
655 if (atomic_read(&current->mm->mm_users) > max_users)
656 smp_call_function(prepare_for_fp_mode_switch,
657 (void *)current->mm, 1);
9791554b
PB
658 }
659
660 /*
661 * There are now no threads of the process with live FP context, so it
662 * is safe to proceed with the FP mode switch.
663 */
664 for_each_thread(task, t) {
665 /* Update desired FP register width */
666 if (value & PR_FP_MODE_FR) {
667 clear_tsk_thread_flag(t, TIF_32BIT_FPREGS);
668 } else {
669 set_tsk_thread_flag(t, TIF_32BIT_FPREGS);
670 clear_tsk_thread_flag(t, TIF_MSA_CTX_LIVE);
671 }
672
673 /* Update desired FP single layout */
674 if (value & PR_FP_MODE_FRE)
675 set_tsk_thread_flag(t, TIF_HYBRID_FPREGS);
676 else
677 clear_tsk_thread_flag(t, TIF_HYBRID_FPREGS);
678 }
679
680 /* Allow threads to use FP again */
681 atomic_set(&task->mm->context.fp_mode_switching, 0);
bd239f1e 682 preempt_enable();
9791554b
PB
683
684 return 0;
685}