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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public | |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
6 | * Copyright (C) 1994 - 1999, 2000 by Ralf Baechle and others. | |
40ac5d47 | 7 | * Copyright (C) 2005, 2006 by Ralf Baechle (ralf@linux-mips.org) |
1da177e4 LT |
8 | * Copyright (C) 1999, 2000 Silicon Graphics, Inc. |
9 | * Copyright (C) 2004 Thiemo Seufer | |
34c2f668 | 10 | * Copyright (C) 2013 Imagination Technologies Ltd. |
1da177e4 | 11 | */ |
1da177e4 | 12 | #include <linux/errno.h> |
1da177e4 | 13 | #include <linux/sched.h> |
b17b0153 | 14 | #include <linux/sched/debug.h> |
29930025 | 15 | #include <linux/sched/task.h> |
68db0cf1 | 16 | #include <linux/sched/task_stack.h> |
7bcf7717 | 17 | #include <linux/tick.h> |
1da177e4 LT |
18 | #include <linux/kernel.h> |
19 | #include <linux/mm.h> | |
20 | #include <linux/stddef.h> | |
21 | #include <linux/unistd.h> | |
cae39d13 | 22 | #include <linux/export.h> |
1da177e4 | 23 | #include <linux/ptrace.h> |
1da177e4 LT |
24 | #include <linux/mman.h> |
25 | #include <linux/personality.h> | |
26 | #include <linux/sys.h> | |
1da177e4 LT |
27 | #include <linux/init.h> |
28 | #include <linux/completion.h> | |
63077519 | 29 | #include <linux/kallsyms.h> |
94109102 | 30 | #include <linux/random.h> |
9791554b | 31 | #include <linux/prctl.h> |
1da177e4 | 32 | |
94109102 | 33 | #include <asm/asm.h> |
1da177e4 LT |
34 | #include <asm/bootinfo.h> |
35 | #include <asm/cpu.h> | |
432c6bac | 36 | #include <asm/dsemul.h> |
e50c0a8f | 37 | #include <asm/dsp.h> |
1da177e4 | 38 | #include <asm/fpu.h> |
d42d8d10 | 39 | #include <asm/irq.h> |
1db1af84 | 40 | #include <asm/msa.h> |
1da177e4 | 41 | #include <asm/pgtable.h> |
1da177e4 LT |
42 | #include <asm/mipsregs.h> |
43 | #include <asm/processor.h> | |
60be939c | 44 | #include <asm/reg.h> |
7c0f6ba6 | 45 | #include <linux/uaccess.h> |
1da177e4 LT |
46 | #include <asm/io.h> |
47 | #include <asm/elf.h> | |
48 | #include <asm/isadep.h> | |
49 | #include <asm/inst.h> | |
1df0f0ff | 50 | #include <asm/stacktrace.h> |
856839b7 | 51 | #include <asm/irq_regs.h> |
1da177e4 | 52 | |
cdbedc61 TG |
53 | #ifdef CONFIG_HOTPLUG_CPU |
54 | void arch_cpu_idle_dead(void) | |
1da177e4 | 55 | { |
a00eeede | 56 | play_dead(); |
cdbedc61 TG |
57 | } |
58 | #endif | |
1b2bc75c | 59 | |
1da177e4 | 60 | asmlinkage void ret_from_fork(void); |
8f54bcac | 61 | asmlinkage void ret_from_kernel_thread(void); |
1da177e4 LT |
62 | |
63 | void start_thread(struct pt_regs * regs, unsigned long pc, unsigned long sp) | |
64 | { | |
65 | unsigned long status; | |
66 | ||
67 | /* New thread loses kernel privileges. */ | |
bbaf238b | 68 | status = regs->cp0_status & ~(ST0_CU0|ST0_CU1|ST0_FR|KU_MASK); |
1da177e4 LT |
69 | status |= KU_USER; |
70 | regs->cp0_status = status; | |
76e5846d JH |
71 | lose_fpu(0); |
72 | clear_thread_flag(TIF_MSA_CTX_LIVE); | |
1da177e4 | 73 | clear_used_math(); |
432c6bac | 74 | atomic_set(¤t->thread.bd_emu_frame, BD_EMUFRAME_NONE); |
a3056b1c | 75 | init_dsp(); |
1da177e4 LT |
76 | regs->cp0_epc = pc; |
77 | regs->regs[29] = sp; | |
1da177e4 LT |
78 | } |
79 | ||
432c6bac PB |
80 | void exit_thread(struct task_struct *tsk) |
81 | { | |
82 | /* | |
83 | * User threads may have allocated a delay slot emulation frame. | |
84 | * If so, clean up that allocation. | |
85 | */ | |
86 | if (!(current->flags & PF_KTHREAD)) | |
87 | dsemul_thread_cleanup(tsk); | |
88 | } | |
89 | ||
39148e94 JH |
90 | int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src) |
91 | { | |
92 | /* | |
93 | * Save any process state which is live in hardware registers to the | |
94 | * parent context prior to duplication. This prevents the new child | |
95 | * state becoming stale if the parent is preempted before copy_thread() | |
96 | * gets a chance to save the parent's live hardware registers to the | |
97 | * child context. | |
98 | */ | |
99 | preempt_disable(); | |
100 | ||
101 | if (is_msa_enabled()) | |
102 | save_msa(current); | |
103 | else if (is_fpu_owner()) | |
104 | _save_fp(current); | |
105 | ||
106 | save_dsp(current); | |
107 | ||
108 | preempt_enable(); | |
109 | ||
110 | *dst = *src; | |
111 | return 0; | |
112 | } | |
113 | ||
e2c5aaa5 AD |
114 | /* |
115 | * Copy architecture-specific thread state | |
116 | */ | |
f9c4e3a6 JC |
117 | int copy_thread_tls(unsigned long clone_flags, unsigned long usp, |
118 | unsigned long kthread_arg, struct task_struct *p, unsigned long tls) | |
1da177e4 | 119 | { |
75bb07e7 | 120 | struct thread_info *ti = task_thread_info(p); |
afa86fc4 | 121 | struct pt_regs *childregs, *regs = current_pt_regs(); |
484889fc | 122 | unsigned long childksp; |
1da177e4 | 123 | |
75bb07e7 | 124 | childksp = (unsigned long)task_stack_page(p) + THREAD_SIZE - 32; |
1da177e4 | 125 | |
1da177e4 LT |
126 | /* set up new TSS. */ |
127 | childregs = (struct pt_regs *) childksp - 1; | |
484889fc DD |
128 | /* Put the stack after the struct pt_regs. */ |
129 | childksp = (unsigned long) childregs; | |
8f54bcac AV |
130 | p->thread.cp0_status = read_c0_status() & ~(ST0_CU2|ST0_CU1); |
131 | if (unlikely(p->flags & PF_KTHREAD)) { | |
e2c5aaa5 | 132 | /* kernel thread */ |
8f54bcac AV |
133 | unsigned long status = p->thread.cp0_status; |
134 | memset(childregs, 0, sizeof(struct pt_regs)); | |
135 | ti->addr_limit = KERNEL_DS; | |
136 | p->thread.reg16 = usp; /* fn */ | |
e2c5aaa5 | 137 | p->thread.reg17 = kthread_arg; |
8f54bcac AV |
138 | p->thread.reg29 = childksp; |
139 | p->thread.reg31 = (unsigned long) ret_from_kernel_thread; | |
140 | #if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) | |
141 | status = (status & ~(ST0_KUP | ST0_IEP | ST0_IEC)) | | |
142 | ((status & (ST0_KUC | ST0_IEC)) << 2); | |
143 | #else | |
144 | status |= ST0_EXL; | |
145 | #endif | |
146 | childregs->cp0_status = status; | |
147 | return 0; | |
148 | } | |
e2c5aaa5 AD |
149 | |
150 | /* user thread */ | |
1da177e4 | 151 | *childregs = *regs; |
70342287 RB |
152 | childregs->regs[7] = 0; /* Clear error flag */ |
153 | childregs->regs[2] = 0; /* Child gets zero as return value */ | |
64b3122d AV |
154 | if (usp) |
155 | childregs->regs[29] = usp; | |
8f54bcac | 156 | ti->addr_limit = USER_DS; |
1da177e4 | 157 | |
1da177e4 LT |
158 | p->thread.reg29 = (unsigned long) childregs; |
159 | p->thread.reg31 = (unsigned long) ret_from_fork; | |
160 | ||
161 | /* | |
162 | * New tasks lose permission to use the fpu. This accelerates context | |
163 | * switching for most programs since they don't use the fpu. | |
164 | */ | |
1da177e4 | 165 | childregs->cp0_status &= ~(ST0_CU2|ST0_CU1); |
1da177e4 | 166 | |
1da177e4 | 167 | clear_tsk_thread_flag(p, TIF_USEDFPU); |
7daef8f2 PB |
168 | clear_tsk_thread_flag(p, TIF_USEDMSA); |
169 | clear_tsk_thread_flag(p, TIF_MSA_CTX_LIVE); | |
1da177e4 | 170 | |
f088fc84 | 171 | #ifdef CONFIG_MIPS_MT_FPAFF |
6657fe0a | 172 | clear_tsk_thread_flag(p, TIF_FPUBOUND); |
f088fc84 RB |
173 | #endif /* CONFIG_MIPS_MT_FPAFF */ |
174 | ||
432c6bac PB |
175 | atomic_set(&p->thread.bd_emu_frame, BD_EMUFRAME_NONE); |
176 | ||
3c37026d | 177 | if (clone_flags & CLONE_SETTLS) |
f9c4e3a6 | 178 | ti->tp_value = tls; |
3c37026d | 179 | |
1da177e4 LT |
180 | return 0; |
181 | } | |
182 | ||
36ecafc5 GF |
183 | #ifdef CONFIG_CC_STACKPROTECTOR |
184 | #include <linux/stackprotector.h> | |
185 | unsigned long __stack_chk_guard __read_mostly; | |
186 | EXPORT_SYMBOL(__stack_chk_guard); | |
187 | #endif | |
188 | ||
b5943182 FBH |
189 | struct mips_frame_info { |
190 | void *func; | |
191 | unsigned long func_size; | |
192 | int frame_size; | |
193 | int pc_offset; | |
194 | }; | |
dc953df1 | 195 | |
5000653e TW |
196 | #define J_TARGET(pc,target) \ |
197 | (((unsigned long)(pc) & 0xf0000000) | ((target) << 2)) | |
198 | ||
bb9bc468 | 199 | static inline int is_ra_save_ins(union mips_instruction *ip, int *poff) |
c0efbb6d | 200 | { |
34c2f668 | 201 | #ifdef CONFIG_CPU_MICROMIPS |
34c2f668 LY |
202 | /* |
203 | * swsp ra,offset | |
204 | * swm16 reglist,offset(sp) | |
205 | * swm32 reglist,offset(sp) | |
206 | * sw32 ra,offset(sp) | |
207 | * jradiussp - NOT SUPPORTED | |
208 | * | |
209 | * microMIPS is way more fun... | |
210 | */ | |
a3552dac | 211 | if (mm_insn_16bit(ip->halfword[1])) { |
bb9bc468 PB |
212 | switch (ip->mm16_r5_format.opcode) { |
213 | case mm_swsp16_op: | |
214 | if (ip->mm16_r5_format.rt != 31) | |
215 | return 0; | |
216 | ||
cea8cd49 | 217 | *poff = ip->mm16_r5_format.imm; |
bb9bc468 PB |
218 | *poff = (*poff << 2) / sizeof(ulong); |
219 | return 1; | |
220 | ||
221 | case mm_pool16c_op: | |
222 | switch (ip->mm16_m_format.func) { | |
223 | case mm_swm16_op: | |
224 | *poff = ip->mm16_m_format.imm; | |
225 | *poff += 1 + ip->mm16_m_format.rlist; | |
226 | *poff = (*poff << 2) / sizeof(ulong); | |
227 | return 1; | |
228 | ||
229 | default: | |
230 | return 0; | |
231 | } | |
232 | ||
233 | default: | |
234 | return 0; | |
235 | } | |
34c2f668 | 236 | } |
bb9bc468 PB |
237 | |
238 | switch (ip->i_format.opcode) { | |
239 | case mm_sw32_op: | |
240 | if (ip->i_format.rs != 29) | |
241 | return 0; | |
242 | if (ip->i_format.rt != 31) | |
243 | return 0; | |
244 | ||
245 | *poff = ip->i_format.simmediate / sizeof(ulong); | |
246 | return 1; | |
247 | ||
248 | case mm_pool32b_op: | |
249 | switch (ip->mm_m_format.func) { | |
250 | case mm_swm32_func: | |
251 | if (ip->mm_m_format.rd < 0x10) | |
252 | return 0; | |
253 | if (ip->mm_m_format.base != 29) | |
254 | return 0; | |
255 | ||
256 | *poff = ip->mm_m_format.simmediate; | |
257 | *poff += (ip->mm_m_format.rd & 0xf) * sizeof(u32); | |
258 | *poff /= sizeof(ulong); | |
259 | return 1; | |
260 | default: | |
261 | return 0; | |
262 | } | |
263 | ||
264 | default: | |
265 | return 0; | |
34c2f668 LY |
266 | } |
267 | #else | |
c0efbb6d | 268 | /* sw / sd $ra, offset($sp) */ |
bb9bc468 PB |
269 | if ((ip->i_format.opcode == sw_op || ip->i_format.opcode == sd_op) && |
270 | ip->i_format.rs == 29 && ip->i_format.rt == 31) { | |
271 | *poff = ip->i_format.simmediate / sizeof(ulong); | |
272 | return 1; | |
273 | } | |
274 | ||
275 | return 0; | |
34c2f668 | 276 | #endif |
c0efbb6d FBH |
277 | } |
278 | ||
e7438c4b | 279 | static inline int is_jump_ins(union mips_instruction *ip) |
c0efbb6d | 280 | { |
34c2f668 LY |
281 | #ifdef CONFIG_CPU_MICROMIPS |
282 | /* | |
283 | * jr16,jrc,jalr16,jalr16 | |
284 | * jal | |
285 | * jalr/jr,jalr.hb/jr.hb,jalrs,jalrs.hb | |
286 | * jraddiusp - NOT SUPPORTED | |
287 | * | |
288 | * microMIPS is kind of more fun... | |
289 | */ | |
67c75057 PB |
290 | if (mm_insn_16bit(ip->halfword[1])) { |
291 | if ((ip->mm16_r5_format.opcode == mm_pool16c_op && | |
292 | (ip->mm16_r5_format.rt & mm_jr16_op) == mm_jr16_op)) | |
293 | return 1; | |
294 | return 0; | |
295 | } | |
296 | ||
096a0de4 PB |
297 | if (ip->j_format.opcode == mm_j32_op) |
298 | return 1; | |
67c75057 | 299 | if (ip->j_format.opcode == mm_jal32_op) |
34c2f668 LY |
300 | return 1; |
301 | if (ip->r_format.opcode != mm_pool32a_op || | |
302 | ip->r_format.func != mm_pool32axf_op) | |
303 | return 0; | |
635c9907 | 304 | return ((ip->u_format.uimmediate >> 6) & mm_jalr_op) == mm_jalr_op; |
34c2f668 | 305 | #else |
e7438c4b TW |
306 | if (ip->j_format.opcode == j_op) |
307 | return 1; | |
c0efbb6d FBH |
308 | if (ip->j_format.opcode == jal_op) |
309 | return 1; | |
310 | if (ip->r_format.opcode != spec_op) | |
311 | return 0; | |
312 | return ip->r_format.func == jalr_op || ip->r_format.func == jr_op; | |
34c2f668 | 313 | #endif |
c0efbb6d FBH |
314 | } |
315 | ||
316 | static inline int is_sp_move_ins(union mips_instruction *ip) | |
317 | { | |
34c2f668 LY |
318 | #ifdef CONFIG_CPU_MICROMIPS |
319 | /* | |
320 | * addiusp -imm | |
321 | * addius5 sp,-imm | |
322 | * addiu32 sp,sp,-imm | |
323 | * jradiussp - NOT SUPPORTED | |
324 | * | |
325 | * microMIPS is not more fun... | |
326 | */ | |
a3552dac PB |
327 | if (mm_insn_16bit(ip->halfword[1])) { |
328 | return (ip->mm16_r3_format.opcode == mm_pool16d_op && | |
b332fec0 | 329 | ip->mm16_r3_format.simmediate & mm_addiusp_func) || |
a3552dac PB |
330 | (ip->mm16_r5_format.opcode == mm_pool16d_op && |
331 | ip->mm16_r5_format.rt == 29); | |
34c2f668 | 332 | } |
a3552dac | 333 | |
635c9907 RB |
334 | return ip->mm_i_format.opcode == mm_addiu32_op && |
335 | ip->mm_i_format.rt == 29 && ip->mm_i_format.rs == 29; | |
34c2f668 | 336 | #else |
c0efbb6d FBH |
337 | /* addiu/daddiu sp,sp,-imm */ |
338 | if (ip->i_format.rs != 29 || ip->i_format.rt != 29) | |
339 | return 0; | |
340 | if (ip->i_format.opcode == addiu_op || ip->i_format.opcode == daddiu_op) | |
341 | return 1; | |
34c2f668 | 342 | #endif |
c0efbb6d FBH |
343 | return 0; |
344 | } | |
345 | ||
f66686f7 | 346 | static int get_frame_info(struct mips_frame_info *info) |
1da177e4 | 347 | { |
a3552dac | 348 | bool is_mmips = IS_ENABLED(CONFIG_CPU_MICROMIPS); |
b6c7a324 PB |
349 | union mips_instruction insn, *ip, *ip_end; |
350 | const unsigned int max_insns = 128; | |
11887ed1 | 351 | unsigned int last_insn_size = 0; |
b6c7a324 | 352 | unsigned int i; |
aee16625 | 353 | bool saw_jump = false; |
c0efbb6d | 354 | |
1da177e4 | 355 | info->pc_offset = -1; |
63077519 | 356 | info->frame_size = 0; |
1da177e4 | 357 | |
ccaf7caf | 358 | ip = (void *)msk_isa16_mode((ulong)info->func); |
29b376ff FBH |
359 | if (!ip) |
360 | goto err; | |
361 | ||
b6c7a324 | 362 | ip_end = (void *)ip + info->func_size; |
29b376ff | 363 | |
11887ed1 MR |
364 | for (i = 0; i < max_insns && ip < ip_end; i++) { |
365 | ip = (void *)ip + last_insn_size; | |
a3552dac PB |
366 | if (is_mmips && mm_insn_16bit(ip->halfword[0])) { |
367 | insn.halfword[0] = 0; | |
368 | insn.halfword[1] = ip->halfword[0]; | |
11887ed1 | 369 | last_insn_size = 2; |
a3552dac PB |
370 | } else if (is_mmips) { |
371 | insn.halfword[0] = ip->halfword[1]; | |
372 | insn.halfword[1] = ip->halfword[0]; | |
11887ed1 | 373 | last_insn_size = 4; |
a3552dac PB |
374 | } else { |
375 | insn.word = ip->word; | |
11887ed1 | 376 | last_insn_size = 4; |
a3552dac | 377 | } |
c0efbb6d | 378 | |
0cceb4aa | 379 | if (!info->frame_size) { |
a3552dac | 380 | if (is_sp_move_ins(&insn)) |
34c2f668 LY |
381 | { |
382 | #ifdef CONFIG_CPU_MICROMIPS | |
383 | if (mm_insn_16bit(ip->halfword[0])) | |
384 | { | |
385 | unsigned short tmp; | |
386 | ||
a0ae2b08 | 387 | if (ip->mm16_r3_format.simmediate & mm_addiusp_func) |
34c2f668 | 388 | { |
a0ae2b08 MR |
389 | tmp = ip->mm_b0_format.simmediate >> 1; |
390 | tmp = ((tmp & 0x1ff) ^ 0x100) - 0x100; | |
391 | /* 0x0,0x1,0x1fe,0x1ff are special */ | |
392 | if ((tmp + 2) < 4) | |
393 | tmp ^= 0x100; | |
394 | info->frame_size = -(signed short)(tmp << 2); | |
34c2f668 LY |
395 | } else { |
396 | tmp = (ip->halfword[0] >> 1); | |
397 | info->frame_size = -(signed short)(tmp & 0xf); | |
398 | } | |
34c2f668 LY |
399 | } else |
400 | #endif | |
0cceb4aa | 401 | info->frame_size = - ip->i_format.simmediate; |
34c2f668 | 402 | } |
0cceb4aa | 403 | continue; |
aee16625 CM |
404 | } else if (!saw_jump && is_jump_ins(ip)) { |
405 | /* | |
406 | * If we see a jump instruction, we are finished | |
407 | * with the frame save. | |
408 | * | |
409 | * Some functions can have a shortcut return at | |
410 | * the beginning of the function, so don't start | |
411 | * looking for jump instruction until we see the | |
412 | * frame setup. | |
413 | * | |
414 | * The RA save instruction can get put into the | |
415 | * delay slot of the jump instruction, so look | |
416 | * at the next instruction, too. | |
417 | */ | |
418 | saw_jump = true; | |
419 | continue; | |
63077519 | 420 | } |
bb9bc468 PB |
421 | if (info->pc_offset == -1 && |
422 | is_ra_save_ins(&insn, &info->pc_offset)) | |
0cceb4aa | 423 | break; |
aee16625 CM |
424 | if (saw_jump) |
425 | break; | |
1da177e4 | 426 | } |
f66686f7 AN |
427 | if (info->frame_size && info->pc_offset >= 0) /* nested */ |
428 | return 0; | |
429 | if (info->pc_offset < 0) /* leaf */ | |
430 | return 1; | |
a90c59e6 | 431 | /* prologue seems bogus... */ |
29b376ff | 432 | err: |
f66686f7 | 433 | return -1; |
1da177e4 LT |
434 | } |
435 | ||
b5943182 FBH |
436 | static struct mips_frame_info schedule_mfi __read_mostly; |
437 | ||
5000653e TW |
438 | #ifdef CONFIG_KALLSYMS |
439 | static unsigned long get___schedule_addr(void) | |
440 | { | |
441 | return kallsyms_lookup_name("__schedule"); | |
442 | } | |
443 | #else | |
444 | static unsigned long get___schedule_addr(void) | |
445 | { | |
446 | union mips_instruction *ip = (void *)schedule; | |
447 | int max_insns = 8; | |
448 | int i; | |
449 | ||
450 | for (i = 0; i < max_insns; i++, ip++) { | |
451 | if (ip->j_format.opcode == j_op) | |
452 | return J_TARGET(ip, ip->j_format.target); | |
453 | } | |
454 | return 0; | |
455 | } | |
456 | #endif | |
457 | ||
1da177e4 LT |
458 | static int __init frame_info_init(void) |
459 | { | |
b5943182 | 460 | unsigned long size = 0; |
63077519 | 461 | #ifdef CONFIG_KALLSYMS |
b5943182 | 462 | unsigned long ofs; |
5000653e TW |
463 | #endif |
464 | unsigned long addr; | |
b5943182 | 465 | |
5000653e TW |
466 | addr = get___schedule_addr(); |
467 | if (!addr) | |
468 | addr = (unsigned long)schedule; | |
469 | ||
470 | #ifdef CONFIG_KALLSYMS | |
471 | kallsyms_lookup_size_offset(addr, &size, &ofs); | |
63077519 | 472 | #endif |
5000653e | 473 | schedule_mfi.func = (void *)addr; |
b5943182 FBH |
474 | schedule_mfi.func_size = size; |
475 | ||
476 | get_frame_info(&schedule_mfi); | |
6057a798 FBH |
477 | |
478 | /* | |
479 | * Without schedule() frame info, result given by | |
480 | * thread_saved_pc() and get_wchan() are not reliable. | |
481 | */ | |
b5943182 | 482 | if (schedule_mfi.pc_offset < 0) |
6057a798 | 483 | printk("Can't analyze schedule() prologue at %p\n", schedule); |
63077519 | 484 | |
1da177e4 LT |
485 | return 0; |
486 | } | |
487 | ||
488 | arch_initcall(frame_info_init); | |
489 | ||
490 | /* | |
491 | * Return saved PC of a blocked thread. | |
492 | */ | |
493 | unsigned long thread_saved_pc(struct task_struct *tsk) | |
494 | { | |
495 | struct thread_struct *t = &tsk->thread; | |
496 | ||
497 | /* New born processes are a special case */ | |
498 | if (t->reg31 == (unsigned long) ret_from_fork) | |
499 | return t->reg31; | |
b5943182 | 500 | if (schedule_mfi.pc_offset < 0) |
1da177e4 | 501 | return 0; |
b5943182 | 502 | return ((unsigned long *)t->reg29)[schedule_mfi.pc_offset]; |
1da177e4 LT |
503 | } |
504 | ||
1da177e4 | 505 | |
f66686f7 | 506 | #ifdef CONFIG_KALLSYMS |
94ea09c6 DK |
507 | /* generic stack unwinding function */ |
508 | unsigned long notrace unwind_stack_by_address(unsigned long stack_page, | |
509 | unsigned long *sp, | |
510 | unsigned long pc, | |
511 | unsigned long *ra) | |
f66686f7 | 512 | { |
db8466c5 | 513 | unsigned long low, high, irq_stack_high; |
f66686f7 | 514 | struct mips_frame_info info; |
f66686f7 | 515 | unsigned long size, ofs; |
db8466c5 | 516 | struct pt_regs *regs; |
4d157d5e | 517 | int leaf; |
f66686f7 | 518 | |
f66686f7 AN |
519 | if (!stack_page) |
520 | return 0; | |
521 | ||
1924600c | 522 | /* |
db8466c5 MR |
523 | * IRQ stacks start at IRQ_STACK_START |
524 | * task stacks at THREAD_SIZE - 32 | |
1924600c | 525 | */ |
db8466c5 MR |
526 | low = stack_page; |
527 | if (!preemptible() && on_irq_stack(raw_smp_processor_id(), *sp)) { | |
528 | high = stack_page + IRQ_STACK_START; | |
529 | irq_stack_high = high; | |
530 | } else { | |
531 | high = stack_page + THREAD_SIZE - 32; | |
532 | irq_stack_high = 0; | |
533 | } | |
534 | ||
535 | /* | |
536 | * If we reached the top of the interrupt stack, start unwinding | |
537 | * the interrupted task stack. | |
538 | */ | |
539 | if (unlikely(*sp == irq_stack_high)) { | |
540 | unsigned long task_sp = *(unsigned long *)*sp; | |
541 | ||
542 | /* | |
543 | * Check that the pointer saved in the IRQ stack head points to | |
544 | * something within the stack of the current task | |
545 | */ | |
546 | if (!object_is_on_stack((void *)task_sp)) | |
547 | return 0; | |
548 | ||
549 | /* | |
550 | * Follow pointer to tasks kernel stack frame where interrupted | |
551 | * state was saved. | |
552 | */ | |
553 | regs = (struct pt_regs *)task_sp; | |
554 | pc = regs->cp0_epc; | |
555 | if (!user_mode(regs) && __kernel_text_address(pc)) { | |
556 | *sp = regs->regs[29]; | |
557 | *ra = regs->regs[31]; | |
558 | return pc; | |
1924600c AN |
559 | } |
560 | return 0; | |
561 | } | |
55b74283 | 562 | if (!kallsyms_lookup_size_offset(pc, &size, &ofs)) |
f66686f7 | 563 | return 0; |
1fd69098 | 564 | /* |
25985edc | 565 | * Return ra if an exception occurred at the first instruction |
1fd69098 | 566 | */ |
1924600c AN |
567 | if (unlikely(ofs == 0)) { |
568 | pc = *ra; | |
569 | *ra = 0; | |
570 | return pc; | |
571 | } | |
f66686f7 AN |
572 | |
573 | info.func = (void *)(pc - ofs); | |
574 | info.func_size = ofs; /* analyze from start to ofs */ | |
4d157d5e FBH |
575 | leaf = get_frame_info(&info); |
576 | if (leaf < 0) | |
f66686f7 | 577 | return 0; |
4d157d5e | 578 | |
db8466c5 | 579 | if (*sp < low || *sp + info.frame_size > high) |
f66686f7 AN |
580 | return 0; |
581 | ||
4d157d5e FBH |
582 | if (leaf) |
583 | /* | |
584 | * For some extreme cases, get_frame_info() can | |
585 | * consider wrongly a nested function as a leaf | |
586 | * one. In that cases avoid to return always the | |
587 | * same value. | |
588 | */ | |
1924600c | 589 | pc = pc != *ra ? *ra : 0; |
4d157d5e FBH |
590 | else |
591 | pc = ((unsigned long *)(*sp))[info.pc_offset]; | |
592 | ||
593 | *sp += info.frame_size; | |
1924600c | 594 | *ra = 0; |
4d157d5e | 595 | return __kernel_text_address(pc) ? pc : 0; |
f66686f7 | 596 | } |
94ea09c6 DK |
597 | EXPORT_SYMBOL(unwind_stack_by_address); |
598 | ||
599 | /* used by show_backtrace() */ | |
600 | unsigned long unwind_stack(struct task_struct *task, unsigned long *sp, | |
601 | unsigned long pc, unsigned long *ra) | |
602 | { | |
d42d8d10 MR |
603 | unsigned long stack_page = 0; |
604 | int cpu; | |
605 | ||
606 | for_each_possible_cpu(cpu) { | |
607 | if (on_irq_stack(cpu, *sp)) { | |
608 | stack_page = (unsigned long)irq_stack[cpu]; | |
609 | break; | |
610 | } | |
611 | } | |
612 | ||
613 | if (!stack_page) | |
614 | stack_page = (unsigned long)task_stack_page(task); | |
615 | ||
94ea09c6 DK |
616 | return unwind_stack_by_address(stack_page, sp, pc, ra); |
617 | } | |
f66686f7 | 618 | #endif |
b5943182 FBH |
619 | |
620 | /* | |
621 | * get_wchan - a maintenance nightmare^W^Wpain in the ass ... | |
622 | */ | |
623 | unsigned long get_wchan(struct task_struct *task) | |
624 | { | |
625 | unsigned long pc = 0; | |
626 | #ifdef CONFIG_KALLSYMS | |
627 | unsigned long sp; | |
1924600c | 628 | unsigned long ra = 0; |
b5943182 FBH |
629 | #endif |
630 | ||
631 | if (!task || task == current || task->state == TASK_RUNNING) | |
632 | goto out; | |
633 | if (!task_stack_page(task)) | |
634 | goto out; | |
635 | ||
636 | pc = thread_saved_pc(task); | |
637 | ||
638 | #ifdef CONFIG_KALLSYMS | |
639 | sp = task->thread.reg29 + schedule_mfi.frame_size; | |
640 | ||
641 | while (in_sched_functions(pc)) | |
1924600c | 642 | pc = unwind_stack(task, &sp, pc, &ra); |
b5943182 FBH |
643 | #endif |
644 | ||
645 | out: | |
646 | return pc; | |
647 | } | |
94109102 FBH |
648 | |
649 | /* | |
650 | * Don't forget that the stack pointer must be aligned on a 8 bytes | |
651 | * boundary for 32-bits ABI and 16 bytes for 64-bits ABI. | |
652 | */ | |
653 | unsigned long arch_align_stack(unsigned long sp) | |
654 | { | |
655 | if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space) | |
656 | sp -= get_random_int() & ~PAGE_MASK; | |
657 | ||
658 | return sp & ALMASK; | |
659 | } | |
856839b7 ES |
660 | |
661 | static void arch_dump_stack(void *info) | |
662 | { | |
663 | struct pt_regs *regs; | |
664 | ||
665 | regs = get_irq_regs(); | |
666 | ||
667 | if (regs) | |
668 | show_regs(regs); | |
669 | ||
670 | dump_stack(); | |
671 | } | |
672 | ||
9a01c3ed | 673 | void arch_trigger_cpumask_backtrace(const cpumask_t *mask, bool exclude_self) |
856839b7 | 674 | { |
9a01c3ed CM |
675 | long this_cpu = get_cpu(); |
676 | ||
677 | if (cpumask_test_cpu(this_cpu, mask) && !exclude_self) | |
678 | dump_stack(); | |
679 | ||
680 | smp_call_function_many(mask, arch_dump_stack, NULL, 1); | |
681 | ||
682 | put_cpu(); | |
856839b7 | 683 | } |
9791554b PB |
684 | |
685 | int mips_get_process_fp_mode(struct task_struct *task) | |
686 | { | |
687 | int value = 0; | |
688 | ||
689 | if (!test_tsk_thread_flag(task, TIF_32BIT_FPREGS)) | |
690 | value |= PR_FP_MODE_FR; | |
691 | if (test_tsk_thread_flag(task, TIF_HYBRID_FPREGS)) | |
692 | value |= PR_FP_MODE_FRE; | |
693 | ||
694 | return value; | |
695 | } | |
696 | ||
6b832257 PB |
697 | static void prepare_for_fp_mode_switch(void *info) |
698 | { | |
699 | struct mm_struct *mm = info; | |
700 | ||
701 | if (current->mm == mm) | |
702 | lose_fpu(1); | |
703 | } | |
704 | ||
9791554b PB |
705 | int mips_set_process_fp_mode(struct task_struct *task, unsigned int value) |
706 | { | |
707 | const unsigned int known_bits = PR_FP_MODE_FR | PR_FP_MODE_FRE; | |
9791554b | 708 | struct task_struct *t; |
6b832257 | 709 | int max_users; |
9791554b PB |
710 | |
711 | /* Check the value is valid */ | |
712 | if (value & ~known_bits) | |
713 | return -EOPNOTSUPP; | |
714 | ||
715 | /* Avoid inadvertently triggering emulation */ | |
b244614a MN |
716 | if ((value & PR_FP_MODE_FR) && raw_cpu_has_fpu && |
717 | !(raw_current_cpu_data.fpu_id & MIPS_FPIR_F64)) | |
9791554b | 718 | return -EOPNOTSUPP; |
b244614a | 719 | if ((value & PR_FP_MODE_FRE) && raw_cpu_has_fpu && !cpu_has_fre) |
9791554b PB |
720 | return -EOPNOTSUPP; |
721 | ||
13e45f09 | 722 | /* FR = 0 not supported in MIPS R6 */ |
b244614a | 723 | if (!(value & PR_FP_MODE_FR) && raw_cpu_has_fpu && cpu_has_mips_r6) |
13e45f09 MC |
724 | return -EOPNOTSUPP; |
725 | ||
bd239f1e PB |
726 | /* Proceed with the mode switch */ |
727 | preempt_disable(); | |
728 | ||
9791554b PB |
729 | /* Save FP & vector context, then disable FPU & MSA */ |
730 | if (task->signal == current->signal) | |
731 | lose_fpu(1); | |
732 | ||
733 | /* Prevent any threads from obtaining live FP context */ | |
734 | atomic_set(&task->mm->context.fp_mode_switching, 1); | |
735 | smp_mb__after_atomic(); | |
736 | ||
737 | /* | |
6b832257 PB |
738 | * If there are multiple online CPUs then force any which are running |
739 | * threads in this process to lose their FPU context, which they can't | |
740 | * regain until fp_mode_switching is cleared later. | |
9791554b PB |
741 | */ |
742 | if (num_online_cpus() > 1) { | |
6b832257 PB |
743 | /* No need to send an IPI for the local CPU */ |
744 | max_users = (task->mm == current->mm) ? 1 : 0; | |
9791554b | 745 | |
6b832257 PB |
746 | if (atomic_read(¤t->mm->mm_users) > max_users) |
747 | smp_call_function(prepare_for_fp_mode_switch, | |
748 | (void *)current->mm, 1); | |
9791554b PB |
749 | } |
750 | ||
751 | /* | |
752 | * There are now no threads of the process with live FP context, so it | |
753 | * is safe to proceed with the FP mode switch. | |
754 | */ | |
755 | for_each_thread(task, t) { | |
756 | /* Update desired FP register width */ | |
757 | if (value & PR_FP_MODE_FR) { | |
758 | clear_tsk_thread_flag(t, TIF_32BIT_FPREGS); | |
759 | } else { | |
760 | set_tsk_thread_flag(t, TIF_32BIT_FPREGS); | |
761 | clear_tsk_thread_flag(t, TIF_MSA_CTX_LIVE); | |
762 | } | |
763 | ||
764 | /* Update desired FP single layout */ | |
765 | if (value & PR_FP_MODE_FRE) | |
766 | set_tsk_thread_flag(t, TIF_HYBRID_FPREGS); | |
767 | else | |
768 | clear_tsk_thread_flag(t, TIF_HYBRID_FPREGS); | |
769 | } | |
770 | ||
771 | /* Allow threads to use FP again */ | |
772 | atomic_set(&task->mm->context.fp_mode_switching, 0); | |
bd239f1e | 773 | preempt_enable(); |
9791554b PB |
774 | |
775 | return 0; | |
776 | } | |
08c941bf MN |
777 | |
778 | #if defined(CONFIG_32BIT) || defined(CONFIG_MIPS32_O32) | |
779 | void mips_dump_regs32(u32 *uregs, const struct pt_regs *regs) | |
780 | { | |
781 | unsigned int i; | |
782 | ||
783 | for (i = MIPS32_EF_R1; i <= MIPS32_EF_R31; i++) { | |
784 | /* k0/k1 are copied as zero. */ | |
785 | if (i == MIPS32_EF_R26 || i == MIPS32_EF_R27) | |
786 | uregs[i] = 0; | |
787 | else | |
788 | uregs[i] = regs->regs[i - MIPS32_EF_R0]; | |
789 | } | |
790 | ||
791 | uregs[MIPS32_EF_LO] = regs->lo; | |
792 | uregs[MIPS32_EF_HI] = regs->hi; | |
793 | uregs[MIPS32_EF_CP0_EPC] = regs->cp0_epc; | |
794 | uregs[MIPS32_EF_CP0_BADVADDR] = regs->cp0_badvaddr; | |
795 | uregs[MIPS32_EF_CP0_STATUS] = regs->cp0_status; | |
796 | uregs[MIPS32_EF_CP0_CAUSE] = regs->cp0_cause; | |
797 | } | |
798 | #endif /* CONFIG_32BIT || CONFIG_MIPS32_O32 */ | |
799 | ||
800 | #ifdef CONFIG_64BIT | |
801 | void mips_dump_regs64(u64 *uregs, const struct pt_regs *regs) | |
802 | { | |
803 | unsigned int i; | |
804 | ||
805 | for (i = MIPS64_EF_R1; i <= MIPS64_EF_R31; i++) { | |
806 | /* k0/k1 are copied as zero. */ | |
807 | if (i == MIPS64_EF_R26 || i == MIPS64_EF_R27) | |
808 | uregs[i] = 0; | |
809 | else | |
810 | uregs[i] = regs->regs[i - MIPS64_EF_R0]; | |
811 | } | |
812 | ||
813 | uregs[MIPS64_EF_LO] = regs->lo; | |
814 | uregs[MIPS64_EF_HI] = regs->hi; | |
815 | uregs[MIPS64_EF_CP0_EPC] = regs->cp0_epc; | |
816 | uregs[MIPS64_EF_CP0_BADVADDR] = regs->cp0_badvaddr; | |
817 | uregs[MIPS64_EF_CP0_STATUS] = regs->cp0_status; | |
818 | uregs[MIPS64_EF_CP0_CAUSE] = regs->cp0_cause; | |
819 | } | |
820 | #endif /* CONFIG_64BIT */ |