[mirror_ubuntu-artful-kernel.git] / arch / mips / kernel / ptrace32.c

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 1992 Ross Biro
 * Copyright (C) Linus Torvalds
 * Copyright (C) 1994, 95, 96, 97, 98, 2000 Ralf Baechle
 * Copyright (C) 1996 David S. Miller
 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
 * Copyright (C) 1999 MIPS Technologies, Inc.
 * Copyright (C) 2000 Ulf Carlsson
 *
 * At this time Linux/MIPS64 only supports syscall tracing, even for 32-bit
 * binaries.
 */
#include <linux/compiler.h>
#include <linux/compat.h>
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/sched/task_stack.h>
#include <linux/mm.h>
#include <linux/errno.h>
#include <linux/ptrace.h>
#include <linux/smp.h>
#include <linux/security.h>

#include <asm/cpu.h>
#include <asm/dsp.h>
#include <asm/fpu.h>
#include <asm/mipsregs.h>
#include <asm/mipsmtregs.h>
#include <asm/pgtable.h>
#include <asm/page.h>
#include <asm/reg.h>
#include <linux/uaccess.h>
#include <asm/bootinfo.h>

/*
 * Tracing a 32-bit process with a 64-bit strace and vice versa will not
 * work.  I don't know how to fix this.
 */
long compat_arch_ptrace(struct task_struct *child, compat_long_t request,
			compat_ulong_t caddr, compat_ulong_t cdata)
{
	int addr = caddr;
	int data = cdata;
	int ret;

	switch (request) {

	/*
	 * Read 4 bytes of the other process' storage
	 *  data is a pointer specifying where the user wants the
	 *	4 bytes copied into
	 *  addr is a pointer in the user's storage that contains an 8 byte
	 *	address in the other process of the 4 bytes that is to be read
	 * (this is run in a 32-bit process looking at a 64-bit process)
	 * when I and D space are separate, these will need to be fixed.
	 */
	case PTRACE_PEEKTEXT_3264:
	case PTRACE_PEEKDATA_3264: {
		u32 tmp;
		int copied;
		u32 __user * addrOthers;

		ret = -EIO;

		/* Get the addr in the other process that we want to read */
		if (get_user(addrOthers, (u32 __user * __user *) (unsigned long) addr) != 0)
			break;

		copied = ptrace_access_vm(child, (u64)addrOthers, &tmp,
				sizeof(tmp), FOLL_FORCE);
		if (copied != sizeof(tmp))
			break;
		ret = put_user(tmp, (u32 __user *) (unsigned long) data);
		break;
	}

	/* Read the word at location addr in the USER area. */
	case PTRACE_PEEKUSR: {
		struct pt_regs *regs;
		union fpureg *fregs;
		unsigned int tmp;

		regs = task_pt_regs(child);
		ret = 0;  /* Default return value. */

		switch (addr) {
		case 0 ... 31:
			tmp = regs->regs[addr];
			break;
		case FPR_BASE ... FPR_BASE + 31:
			if (!tsk_used_math(child)) {
				/* FP not yet used */
				tmp = -1;
				break;
			}
			fregs = get_fpu_regs(child);
			if (test_thread_flag(TIF_32BIT_FPREGS)) {
				/*
				 * The odd registers are actually the high
				 * order bits of the values stored in the even
				 * registers - unless we're using r2k_switch.S.
				 */
				tmp = get_fpr32(&fregs[(addr & ~1) - FPR_BASE],
						addr & 1);
				break;
			}
			tmp = get_fpr32(&fregs[addr - FPR_BASE], 0);
			break;
		case PC:
			tmp = regs->cp0_epc;
			break;
		case CAUSE:
			tmp = regs->cp0_cause;
			break;
		case BADVADDR:
			tmp = regs->cp0_badvaddr;
			break;
		case MMHI:
			tmp = regs->hi;
			break;
		case MMLO:
			tmp = regs->lo;
			break;
		case FPC_CSR:
			tmp = child->thread.fpu.fcr31;
			break;
		case FPC_EIR:
			/* implementation / version register */
			tmp = boot_cpu_data.fpu_id;
			break;
		case DSP_BASE ... DSP_BASE + 5: {
			dspreg_t *dregs;

			if (!cpu_has_dsp) {
				tmp = 0;
				ret = -EIO;
				goto out;
			}
			dregs = __get_dsp_regs(child);
			tmp = (unsigned long) (dregs[addr - DSP_BASE]);
			break;
		}
		case DSP_CONTROL:
			if (!cpu_has_dsp) {
				tmp = 0;
				ret = -EIO;
				goto out;
			}
			tmp = child->thread.dsp.dspcontrol;
			break;
		default:
			tmp = 0;
			ret = -EIO;
			goto out;
		}
		ret = put_user(tmp, (unsigned __user *) (unsigned long) data);
		break;
	}

	/*
	 * Write 4 bytes into the other process' storage
	 *  data is the 4 bytes that the user wants written
	 *  addr is a pointer in the user's storage that contains an
	 *	8 byte address in the other process where the 4 bytes
	 *	that is to be written
	 * (this is run in a 32-bit process looking at a 64-bit process)
	 * when I and D space are separate, these will need to be fixed.
	 */
	case PTRACE_POKETEXT_3264:
	case PTRACE_POKEDATA_3264: {
		u32 __user * addrOthers;

		/* Get the addr in the other process that we want to write into */
		ret = -EIO;
		if (get_user(addrOthers, (u32 __user * __user *) (unsigned long) addr) != 0)
			break;
		ret = 0;
		if (ptrace_access_vm(child, (u64)addrOthers, &data,
					sizeof(data),
					FOLL_FORCE | FOLL_WRITE) == sizeof(data))
			break;
		ret = -EIO;
		break;
	}

	case PTRACE_POKEUSR: {
		struct pt_regs *regs;
		ret = 0;
		regs = task_pt_regs(child);

		switch (addr) {
		case 0 ... 31:
			regs->regs[addr] = data;
			break;
		case FPR_BASE ... FPR_BASE + 31: {
			union fpureg *fregs = get_fpu_regs(child);

			if (!tsk_used_math(child)) {
				/* FP not yet used  */
				memset(&child->thread.fpu, ~0,
				       sizeof(child->thread.fpu));
				child->thread.fpu.fcr31 = 0;
			}
			if (test_thread_flag(TIF_32BIT_FPREGS)) {
				/*
				 * The odd registers are actually the high
				 * order bits of the values stored in the even
				 * registers - unless we're using r2k_switch.S.
				 */
				set_fpr32(&fregs[(addr & ~1) - FPR_BASE],
					  addr & 1, data);
				break;
			}
			set_fpr64(&fregs[addr - FPR_BASE], 0, data);
			break;
		}
		case PC:
			regs->cp0_epc = data;
			break;
		case MMHI:
			regs->hi = data;
			break;
		case MMLO:
			regs->lo = data;
			break;
		case FPC_CSR:
			child->thread.fpu.fcr31 = data;
			break;
		case DSP_BASE ... DSP_BASE + 5: {
			dspreg_t *dregs;

			if (!cpu_has_dsp) {
				ret = -EIO;
				break;
			}

			dregs = __get_dsp_regs(child);
			dregs[addr - DSP_BASE] = data;
			break;
		}
		case DSP_CONTROL:
			if (!cpu_has_dsp) {
				ret = -EIO;
				break;
			}
			child->thread.dsp.dspcontrol = data;
			break;
		default:
			/* The rest are not allowed. */
			ret = -EIO;
			break;
		}
		break;
		}

	case PTRACE_GETREGS:
		ret = ptrace_getregs(child,
				(struct user_pt_regs __user *) (__u64) data);
		break;

	case PTRACE_SETREGS:
		ret = ptrace_setregs(child,
				(struct user_pt_regs __user *) (__u64) data);
		break;

	case PTRACE_GETFPREGS:
		ret = ptrace_getfpregs(child, (__u32 __user *) (__u64) data);
		break;

	case PTRACE_SETFPREGS:
		ret = ptrace_setfpregs(child, (__u32 __user *) (__u64) data);
		break;

	case PTRACE_GET_THREAD_AREA:
		ret = put_user(task_thread_info(child)->tp_value,
				(unsigned int __user *) (unsigned long) data);
		break;

	case PTRACE_GET_THREAD_AREA_3264:
		ret = put_user(task_thread_info(child)->tp_value,
				(unsigned long __user *) (unsigned long) data);
		break;

	case PTRACE_GET_WATCH_REGS:
		ret = ptrace_get_watch_regs(child,
			(struct pt_watch_regs __user *) (unsigned long) addr);
		break;

	case PTRACE_SET_WATCH_REGS:
		ret = ptrace_set_watch_regs(child,
			(struct pt_watch_regs __user *) (unsigned long) addr);
		break;

	default:
		ret = compat_ptrace_request(child, request, addr, data);
		break;
	}
out:
	return ret;
}
Commit	Line	Data
1da177e4 LT	1	/*
	2	* This file is subject to the terms and conditions of the GNU General Public
	3	* License. See the file "COPYING" in the main directory of this archive
	4	* for more details.
	5	*
	6	* Copyright (C) 1992 Ross Biro
	7	* Copyright (C) Linus Torvalds
	8	* Copyright (C) 1994, 95, 96, 97, 98, 2000 Ralf Baechle
	9	* Copyright (C) 1996 David S. Miller
	10	* Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
	11	* Copyright (C) 1999 MIPS Technologies, Inc.
	12	* Copyright (C) 2000 Ulf Carlsson
	13	*
	14	* At this time Linux/MIPS64 only supports syscall tracing, even for 32-bit
	15	* binaries.
	16	*/
	17	#include <linux/compiler.h>
5d9a76cd	18	#include <linux/compat.h>
1da177e4 LT	19	#include <linux/kernel.h>
1da177e4 LT	20	#include <linux/sched.h>
68db0cf1	21	#include <linux/sched/task_stack.h>
1da177e4 LT	22	#include <linux/mm.h>
	23	#include <linux/errno.h>
	24	#include <linux/ptrace.h>
	25	#include <linux/smp.h>
1da177e4 LT	26	#include <linux/security.h>
	27
	28	#include <asm/cpu.h>
e50c0a8f	29	#include <asm/dsp.h>
1da177e4 LT	30	#include <asm/fpu.h>
1da177e4 LT	31	#include <asm/mipsregs.h>
101b3531	32	#include <asm/mipsmtregs.h>
1da177e4 LT	33	#include <asm/pgtable.h>
1da177e4 LT	34	#include <asm/page.h>
60be939c	35	#include <asm/reg.h>
7c0f6ba6	36	#include <linux/uaccess.h>
1da177e4 LT	37	#include <asm/bootinfo.h>
	38
	39	/*
	40	* Tracing a 32-bit process with a 64-bit strace and vice versa will not
	41	* work. I don't know how to fix this.
	42	*/
5d9a76cd TB	43	long compat_arch_ptrace(struct task_struct *child, compat_long_t request,
5d9a76cd TB	44	compat_ulong_t caddr, compat_ulong_t cdata)
1da177e4	45	{
5d9a76cd TB	46	int addr = caddr;
5d9a76cd TB	47	int data = cdata;
1da177e4 LT	48	int ret;
1da177e4 LT	49
1da177e4	50	switch (request) {
1da177e4	51
ea3d710f DJ	52	/*
	53	* Read 4 bytes of the other process' storage
	54	* data is a pointer specifying where the user wants the
	55	* 4 bytes copied into
	56	* addr is a pointer in the user's storage that contains an 8 byte
	57	* address in the other process of the 4 bytes that is to be read
	58	* (this is run in a 32-bit process looking at a 64-bit process)
	59	* when I and D space are separate, these will need to be fixed.
	60	*/
	61	case PTRACE_PEEKTEXT_3264:
	62	case PTRACE_PEEKDATA_3264: {
	63	u32 tmp;
	64	int copied;
	65	u32 __user * addrOthers;
	66
	67	ret = -EIO;
	68
	69	/* Get the addr in the other process that we want to read */
	70	if (get_user(addrOthers, (u32 __user * __user *) (unsigned long) addr) != 0)
	71	break;
	72
84d77d3f	73	copied = ptrace_access_vm(child, (u64)addrOthers, &tmp,
f307ab6d	74	sizeof(tmp), FOLL_FORCE);
ea3d710f DJ	75	if (copied != sizeof(tmp))
	76	break;
	77	ret = put_user(tmp, (u32 __user *) (unsigned long) data);
	78	break;
	79	}
	80
1da177e4 LT	81	/* Read the word at location addr in the USER area. */
	82	case PTRACE_PEEKUSR: {
	83	struct pt_regs *regs;
bbd426f5	84	union fpureg *fregs;
1da177e4 LT	85	unsigned int tmp;
1da177e4 LT	86
40bc9c67	87	regs = task_pt_regs(child);
1da177e4 LT	88	ret = 0; /* Default return value. */
	89
	90	switch (addr) {
	91	case 0 ... 31:
	92	tmp = regs->regs[addr];
	93	break;
	94	case FPR_BASE ... FPR_BASE + 31:
597ce172 PB	95	if (!tsk_used_math(child)) {
	96	/* FP not yet used */
	97	tmp = -1;
	98	break;
	99	}
	100	fregs = get_fpu_regs(child);
	101	if (test_thread_flag(TIF_32BIT_FPREGS)) {
1da177e4 LT	102	/*
	103	* The odd registers are actually the high
	104	* order bits of the values stored in the even
	105	* registers - unless we're using r2k_switch.S.
	106	*/
bbd426f5 PB	107	tmp = get_fpr32(&fregs[(addr & ~1) - FPR_BASE],
bbd426f5 PB	108	addr & 1);
597ce172	109	break;
1da177e4	110	}
bbd426f5	111	tmp = get_fpr32(&fregs[addr - FPR_BASE], 0);
1da177e4 LT	112	break;
	113	case PC:
	114	tmp = regs->cp0_epc;
	115	break;
	116	case CAUSE:
	117	tmp = regs->cp0_cause;
	118	break;
	119	case BADVADDR:
	120	tmp = regs->cp0_badvaddr;
	121	break;
	122	case MMHI:
	123	tmp = regs->hi;
	124	break;
	125	case MMLO:
	126	tmp = regs->lo;
	127	break;
	128	case FPC_CSR:
eae89076	129	tmp = child->thread.fpu.fcr31;
1da177e4	130	break;
3351047f PB	131	case FPC_EIR:
3351047f PB	132	/* implementation / version register */
656ff9be	133	tmp = boot_cpu_data.fpu_id;
1da177e4	134	break;
3055acb0 AN	135	case DSP_BASE ... DSP_BASE + 5: {
	136	dspreg_t *dregs;
	137
e50c0a8f RB	138	if (!cpu_has_dsp) {
	139	tmp = 0;
	140	ret = -EIO;
5d9a76cd	141	goto out;
e50c0a8f	142	}
3055acb0	143	dregs = __get_dsp_regs(child);
6c355852	144	tmp = (unsigned long) (dregs[addr - DSP_BASE]);
e50c0a8f	145	break;
3055acb0	146	}
e50c0a8f RB	147	case DSP_CONTROL:
	148	if (!cpu_has_dsp) {
	149	tmp = 0;
	150	ret = -EIO;
5d9a76cd	151	goto out;
e50c0a8f RB	152	}
	153	tmp = child->thread.dsp.dspcontrol;
	154	break;
1da177e4 LT	155	default:
	156	tmp = 0;
	157	ret = -EIO;
5d9a76cd	158	goto out;
1da177e4	159	}
3055acb0	160	ret = put_user(tmp, (unsigned __user *) (unsigned long) data);
1da177e4 LT	161	break;
	162	}
	163
ea3d710f DJ	164	/*
	165	* Write 4 bytes into the other process' storage
	166	* data is the 4 bytes that the user wants written
	167	* addr is a pointer in the user's storage that contains an
	168	* 8 byte address in the other process where the 4 bytes
	169	* that is to be written
	170	* (this is run in a 32-bit process looking at a 64-bit process)
	171	* when I and D space are separate, these will need to be fixed.
	172	*/
	173	case PTRACE_POKETEXT_3264:
	174	case PTRACE_POKEDATA_3264: {
	175	u32 __user * addrOthers;
	176
	177	/* Get the addr in the other process that we want to write into */
	178	ret = -EIO;
	179	if (get_user(addrOthers, (u32 __user * __user *) (unsigned long) addr) != 0)
	180	break;
	181	ret = 0;
84d77d3f	182	if (ptrace_access_vm(child, (u64)addrOthers, &data,
f307ab6d LS	183	sizeof(data),
f307ab6d LS	184	FOLL_FORCE \| FOLL_WRITE) == sizeof(data))
ea3d710f DJ	185	break;
	186	ret = -EIO;
	187	break;
	188	}
	189
1da177e4 LT	190	case PTRACE_POKEUSR: {
	191	struct pt_regs *regs;
	192	ret = 0;
40bc9c67	193	regs = task_pt_regs(child);
1da177e4 LT	194
	195	switch (addr) {
	196	case 0 ... 31:
	197	regs->regs[addr] = data;
	198	break;
	199	case FPR_BASE ... FPR_BASE + 31: {
bbd426f5	200	union fpureg *fregs = get_fpu_regs(child);
1da177e4 LT	201
	202	if (!tsk_used_math(child)) {
	203	/* FP not yet used */
eae89076 AN	204	memset(&child->thread.fpu, ~0,
	205	sizeof(child->thread.fpu));
	206	child->thread.fpu.fcr31 = 0;
1da177e4	207	}
597ce172 PB	208	if (test_thread_flag(TIF_32BIT_FPREGS)) {
	209	/*
	210	* The odd registers are actually the high
	211	* order bits of the values stored in the even
	212	* registers - unless we're using r2k_switch.S.
	213	*/
bbd426f5 PB	214	set_fpr32(&fregs[(addr & ~1) - FPR_BASE],
bbd426f5 PB	215	addr & 1, data);
597ce172	216	break;
1da177e4	217	}
bbd426f5	218	set_fpr64(&fregs[addr - FPR_BASE], 0, data);
1da177e4 LT	219	break;
	220	}
	221	case PC:
	222	regs->cp0_epc = data;
	223	break;
	224	case MMHI:
	225	regs->hi = data;
	226	break;
	227	case MMLO:
	228	regs->lo = data;
	229	break;
	230	case FPC_CSR:
eae89076	231	child->thread.fpu.fcr31 = data;
1da177e4	232	break;
3055acb0 AN	233	case DSP_BASE ... DSP_BASE + 5: {
	234	dspreg_t *dregs;
	235
e50c0a8f RB	236	if (!cpu_has_dsp) {
	237	ret = -EIO;
	238	break;
	239	}
	240
3055acb0	241	dregs = __get_dsp_regs(child);
e50c0a8f RB	242	dregs[addr - DSP_BASE] = data;
e50c0a8f RB	243	break;
3055acb0	244	}
e50c0a8f RB	245	case DSP_CONTROL:
	246	if (!cpu_has_dsp) {
	247	ret = -EIO;
	248	break;
	249	}
	250	child->thread.dsp.dspcontrol = data;
	251	break;
1da177e4 LT	252	default:
	253	/* The rest are not allowed. */
	254	ret = -EIO;
	255	break;
	256	}
	257	break;
	258	}
	259
ea3d710f	260	case PTRACE_GETREGS:
a79ebea6 AS	261	ret = ptrace_getregs(child,
a79ebea6 AS	262	(struct user_pt_regs __user *) (__u64) data);
ea3d710f DJ	263	break;
	264
	265	case PTRACE_SETREGS:
a79ebea6 AS	266	ret = ptrace_setregs(child,
a79ebea6 AS	267	(struct user_pt_regs __user *) (__u64) data);
ea3d710f DJ	268	break;
	269
	270	case PTRACE_GETFPREGS:
49a89efb	271	ret = ptrace_getfpregs(child, (__u32 __user *) (__u64) data);
ea3d710f DJ	272	break;
	273
	274	case PTRACE_SETFPREGS:
49a89efb	275	ret = ptrace_setfpregs(child, (__u32 __user *) (__u64) data);
ea3d710f DJ	276	break;
ea3d710f DJ	277
3c37026d	278	case PTRACE_GET_THREAD_AREA:
dc8f6029	279	ret = put_user(task_thread_info(child)->tp_value,
3c37026d RB	280	(unsigned int __user *) (unsigned long) data);
	281	break;
	282
ea3d710f	283	case PTRACE_GET_THREAD_AREA_3264:
dc8f6029	284	ret = put_user(task_thread_info(child)->tp_value,
ea3d710f DJ	285	(unsigned long __user *) (unsigned long) data);
	286	break;
	287
0926bf95 DD	288	case PTRACE_GET_WATCH_REGS:
	289	ret = ptrace_get_watch_regs(child,
	290	(struct pt_watch_regs __user *) (unsigned long) addr);
	291	break;
	292
	293	case PTRACE_SET_WATCH_REGS:
	294	ret = ptrace_set_watch_regs(child,
	295	(struct pt_watch_regs __user *) (unsigned long) addr);
	296	break;
	297
1da177e4	298	default:
797c3f32	299	ret = compat_ptrace_request(child, request, addr, data);
1da177e4 LT	300	break;
1da177e4 LT	301	}
1da177e4	302	out:
1da177e4 LT	303	return ret;
1da177e4 LT	304	}