[mirror_ubuntu-artful-kernel.git] / arch / mips / kernel / ptrace32.c

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 1992 Ross Biro
 * Copyright (C) Linus Torvalds
 * Copyright (C) 1994, 95, 96, 97, 98, 2000 Ralf Baechle
 * Copyright (C) 1996 David S. Miller
 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
 * Copyright (C) 1999 MIPS Technologies, Inc.
 * Copyright (C) 2000 Ulf Carlsson
 *
 * At this time Linux/MIPS64 only supports syscall tracing, even for 32-bit
 * binaries.
 */
#include <linux/compiler.h>
#include <linux/compat.h>
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/mm.h>
#include <linux/errno.h>
#include <linux/ptrace.h>
#include <linux/smp.h>
#include <linux/security.h>

#include <asm/cpu.h>
#include <asm/dsp.h>
#include <asm/fpu.h>
#include <asm/mipsregs.h>
#include <asm/mipsmtregs.h>
#include <asm/pgtable.h>
#include <asm/page.h>
#include <asm/reg.h>
#include <linux/uaccess.h>
#include <asm/bootinfo.h>

/*
 * Tracing a 32-bit process with a 64-bit strace and vice versa will not
 * work.  I don't know how to fix this.
 */
long compat_arch_ptrace(struct task_struct *child, compat_long_t request,
			compat_ulong_t caddr, compat_ulong_t cdata)
{
	int addr = caddr;
	int data = cdata;
	int ret;

	switch (request) {

	/*
	 * Read 4 bytes of the other process' storage
	 *  data is a pointer specifying where the user wants the
	 *	4 bytes copied into
	 *  addr is a pointer in the user's storage that contains an 8 byte
	 *	address in the other process of the 4 bytes that is to be read
	 * (this is run in a 32-bit process looking at a 64-bit process)
	 * when I and D space are separate, these will need to be fixed.
	 */
	case PTRACE_PEEKTEXT_3264:
	case PTRACE_PEEKDATA_3264: {
		u32 tmp;
		int copied;
		u32 __user * addrOthers;

		ret = -EIO;

		/* Get the addr in the other process that we want to read */
		if (get_user(addrOthers, (u32 __user * __user *) (unsigned long) addr) != 0)
			break;

		copied = ptrace_access_vm(child, (u64)addrOthers, &tmp,
				sizeof(tmp), FOLL_FORCE);
		if (copied != sizeof(tmp))
			break;
		ret = put_user(tmp, (u32 __user *) (unsigned long) data);
		break;
	}

	/* Read the word at location addr in the USER area. */
	case PTRACE_PEEKUSR: {
		struct pt_regs *regs;
		union fpureg *fregs;
		unsigned int tmp;

		regs = task_pt_regs(child);
		ret = 0;  /* Default return value. */

		switch (addr) {
		case 0 ... 31:
			tmp = regs->regs[addr];
			break;
		case FPR_BASE ... FPR_BASE + 31:
			if (!tsk_used_math(child)) {
				/* FP not yet used */
				tmp = -1;
				break;
			}
			fregs = get_fpu_regs(child);
			if (test_thread_flag(TIF_32BIT_FPREGS)) {
				/*
				 * The odd registers are actually the high
				 * order bits of the values stored in the even
				 * registers - unless we're using r2k_switch.S.
				 */
				tmp = get_fpr32(&fregs[(addr & ~1) - FPR_BASE],
						addr & 1);
				break;
			}
			tmp = get_fpr32(&fregs[addr - FPR_BASE], 0);
			break;
		case PC:
			tmp = regs->cp0_epc;
			break;
		case CAUSE:
			tmp = regs->cp0_cause;
			break;
		case BADVADDR:
			tmp = regs->cp0_badvaddr;
			break;
		case MMHI:
			tmp = regs->hi;
			break;
		case MMLO:
			tmp = regs->lo;
			break;
		case FPC_CSR:
			tmp = child->thread.fpu.fcr31;
			break;
		case FPC_EIR:
			/* implementation / version register */
			tmp = boot_cpu_data.fpu_id;
			break;
		case DSP_BASE ... DSP_BASE + 5: {
			dspreg_t *dregs;

			if (!cpu_has_dsp) {
				tmp = 0;
				ret = -EIO;
				goto out;
			}
			dregs = __get_dsp_regs(child);
			tmp = (unsigned long) (dregs[addr - DSP_BASE]);
			break;
		}
		case DSP_CONTROL:
			if (!cpu_has_dsp) {
				tmp = 0;
				ret = -EIO;
				goto out;
			}
			tmp = child->thread.dsp.dspcontrol;
			break;
		default:
			tmp = 0;
			ret = -EIO;
			goto out;
		}
		ret = put_user(tmp, (unsigned __user *) (unsigned long) data);
		break;
	}

	/*
	 * Write 4 bytes into the other process' storage
	 *  data is the 4 bytes that the user wants written
	 *  addr is a pointer in the user's storage that contains an
	 *	8 byte address in the other process where the 4 bytes
	 *	that is to be written
	 * (this is run in a 32-bit process looking at a 64-bit process)
	 * when I and D space are separate, these will need to be fixed.
	 */
	case PTRACE_POKETEXT_3264:
	case PTRACE_POKEDATA_3264: {
		u32 __user * addrOthers;

		/* Get the addr in the other process that we want to write into */
		ret = -EIO;
		if (get_user(addrOthers, (u32 __user * __user *) (unsigned long) addr) != 0)
			break;
		ret = 0;
		if (ptrace_access_vm(child, (u64)addrOthers, &data,
					sizeof(data),
					FOLL_FORCE | FOLL_WRITE) == sizeof(data))
			break;
		ret = -EIO;
		break;
	}

	case PTRACE_POKEUSR: {
		struct pt_regs *regs;
		ret = 0;
		regs = task_pt_regs(child);

		switch (addr) {
		case 0 ... 31:
			regs->regs[addr] = data;
			break;
		case FPR_BASE ... FPR_BASE + 31: {
			union fpureg *fregs = get_fpu_regs(child);

			if (!tsk_used_math(child)) {
				/* FP not yet used  */
				memset(&child->thread.fpu, ~0,
				       sizeof(child->thread.fpu));
				child->thread.fpu.fcr31 = 0;
			}
			if (test_thread_flag(TIF_32BIT_FPREGS)) {
				/*
				 * The odd registers are actually the high
				 * order bits of the values stored in the even
				 * registers - unless we're using r2k_switch.S.
				 */
				set_fpr32(&fregs[(addr & ~1) - FPR_BASE],
					  addr & 1, data);
				break;
			}
			set_fpr64(&fregs[addr - FPR_BASE], 0, data);
			break;
		}
		case PC:
			regs->cp0_epc = data;
			break;
		case MMHI:
			regs->hi = data;
			break;
		case MMLO:
			regs->lo = data;
			break;
		case FPC_CSR:
			child->thread.fpu.fcr31 = data;
			break;
		case DSP_BASE ... DSP_BASE + 5: {
			dspreg_t *dregs;

			if (!cpu_has_dsp) {
				ret = -EIO;
				break;
			}

			dregs = __get_dsp_regs(child);
			dregs[addr - DSP_BASE] = data;
			break;
		}
		case DSP_CONTROL:
			if (!cpu_has_dsp) {
				ret = -EIO;
				break;
			}
			child->thread.dsp.dspcontrol = data;
			break;
		default:
			/* The rest are not allowed. */
			ret = -EIO;
			break;
		}
		break;
		}

	case PTRACE_GETREGS:
		ret = ptrace_getregs(child,
				(struct user_pt_regs __user *) (__u64) data);
		break;

	case PTRACE_SETREGS:
		ret = ptrace_setregs(child,
				(struct user_pt_regs __user *) (__u64) data);
		break;

	case PTRACE_GETFPREGS:
		ret = ptrace_getfpregs(child, (__u32 __user *) (__u64) data);
		break;

	case PTRACE_SETFPREGS:
		ret = ptrace_setfpregs(child, (__u32 __user *) (__u64) data);
		break;

	case PTRACE_GET_THREAD_AREA:
		ret = put_user(task_thread_info(child)->tp_value,
				(unsigned int __user *) (unsigned long) data);
		break;

	case PTRACE_GET_THREAD_AREA_3264:
		ret = put_user(task_thread_info(child)->tp_value,
				(unsigned long __user *) (unsigned long) data);
		break;

	case PTRACE_GET_WATCH_REGS:
		ret = ptrace_get_watch_regs(child,
			(struct pt_watch_regs __user *) (unsigned long) addr);
		break;

	case PTRACE_SET_WATCH_REGS:
		ret = ptrace_set_watch_regs(child,
			(struct pt_watch_regs __user *) (unsigned long) addr);
		break;

	default:
		ret = compat_ptrace_request(child, request, addr, data);
		break;
	}
out:
	return ret;
}
Commit	Line	Data
1da177e4 LT	1	/*
	2	* This file is subject to the terms and conditions of the GNU General Public
	3	* License. See the file "COPYING" in the main directory of this archive
	4	* for more details.
	5	*
	6	* Copyright (C) 1992 Ross Biro
	7	* Copyright (C) Linus Torvalds
	8	* Copyright (C) 1994, 95, 96, 97, 98, 2000 Ralf Baechle
	9	* Copyright (C) 1996 David S. Miller
	10	* Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
	11	* Copyright (C) 1999 MIPS Technologies, Inc.
	12	* Copyright (C) 2000 Ulf Carlsson
	13	*
	14	* At this time Linux/MIPS64 only supports syscall tracing, even for 32-bit
	15	* binaries.
	16	*/
	17	#include <linux/compiler.h>
5d9a76cd	18	#include <linux/compat.h>
1da177e4 LT	19	#include <linux/kernel.h>
	20	#include <linux/sched.h>
	21	#include <linux/mm.h>
	22	#include <linux/errno.h>
	23	#include <linux/ptrace.h>
	24	#include <linux/smp.h>
1da177e4 LT	25	#include <linux/security.h>
	26
	27	#include <asm/cpu.h>
e50c0a8f	28	#include <asm/dsp.h>
1da177e4 LT	29	#include <asm/fpu.h>
1da177e4 LT	30	#include <asm/mipsregs.h>
101b3531	31	#include <asm/mipsmtregs.h>
1da177e4 LT	32	#include <asm/pgtable.h>
1da177e4 LT	33	#include <asm/page.h>
60be939c	34	#include <asm/reg.h>
7c0f6ba6	35	#include <linux/uaccess.h>
1da177e4 LT	36	#include <asm/bootinfo.h>
	37
	38	/*
	39	* Tracing a 32-bit process with a 64-bit strace and vice versa will not
	40	* work. I don't know how to fix this.
	41	*/
5d9a76cd TB	42	long compat_arch_ptrace(struct task_struct *child, compat_long_t request,
5d9a76cd TB	43	compat_ulong_t caddr, compat_ulong_t cdata)
1da177e4	44	{
5d9a76cd TB	45	int addr = caddr;
5d9a76cd TB	46	int data = cdata;
1da177e4 LT	47	int ret;
1da177e4 LT	48
1da177e4	49	switch (request) {
1da177e4	50
ea3d710f DJ	51	/*
	52	* Read 4 bytes of the other process' storage
	53	* data is a pointer specifying where the user wants the
	54	* 4 bytes copied into
	55	* addr is a pointer in the user's storage that contains an 8 byte
	56	* address in the other process of the 4 bytes that is to be read
	57	* (this is run in a 32-bit process looking at a 64-bit process)
	58	* when I and D space are separate, these will need to be fixed.
	59	*/
	60	case PTRACE_PEEKTEXT_3264:
	61	case PTRACE_PEEKDATA_3264: {
	62	u32 tmp;
	63	int copied;
	64	u32 __user * addrOthers;
	65
	66	ret = -EIO;
	67
	68	/* Get the addr in the other process that we want to read */
	69	if (get_user(addrOthers, (u32 __user * __user *) (unsigned long) addr) != 0)
	70	break;
	71
84d77d3f	72	copied = ptrace_access_vm(child, (u64)addrOthers, &tmp,
f307ab6d	73	sizeof(tmp), FOLL_FORCE);
ea3d710f DJ	74	if (copied != sizeof(tmp))
	75	break;
	76	ret = put_user(tmp, (u32 __user *) (unsigned long) data);
	77	break;
	78	}
	79
1da177e4 LT	80	/* Read the word at location addr in the USER area. */
	81	case PTRACE_PEEKUSR: {
	82	struct pt_regs *regs;
bbd426f5	83	union fpureg *fregs;
1da177e4 LT	84	unsigned int tmp;
1da177e4 LT	85
40bc9c67	86	regs = task_pt_regs(child);
1da177e4 LT	87	ret = 0; /* Default return value. */
	88
	89	switch (addr) {
	90	case 0 ... 31:
	91	tmp = regs->regs[addr];
	92	break;
	93	case FPR_BASE ... FPR_BASE + 31:
597ce172 PB	94	if (!tsk_used_math(child)) {
	95	/* FP not yet used */
	96	tmp = -1;
	97	break;
	98	}
	99	fregs = get_fpu_regs(child);
	100	if (test_thread_flag(TIF_32BIT_FPREGS)) {
1da177e4 LT	101	/*
	102	* The odd registers are actually the high
	103	* order bits of the values stored in the even
	104	* registers - unless we're using r2k_switch.S.
	105	*/
bbd426f5 PB	106	tmp = get_fpr32(&fregs[(addr & ~1) - FPR_BASE],
bbd426f5 PB	107	addr & 1);
597ce172	108	break;
1da177e4	109	}
bbd426f5	110	tmp = get_fpr32(&fregs[addr - FPR_BASE], 0);
1da177e4 LT	111	break;
	112	case PC:
	113	tmp = regs->cp0_epc;
	114	break;
	115	case CAUSE:
	116	tmp = regs->cp0_cause;
	117	break;
	118	case BADVADDR:
	119	tmp = regs->cp0_badvaddr;
	120	break;
	121	case MMHI:
	122	tmp = regs->hi;
	123	break;
	124	case MMLO:
	125	tmp = regs->lo;
	126	break;
	127	case FPC_CSR:
eae89076	128	tmp = child->thread.fpu.fcr31;
1da177e4	129	break;
3351047f PB	130	case FPC_EIR:
3351047f PB	131	/* implementation / version register */
656ff9be	132	tmp = boot_cpu_data.fpu_id;
1da177e4	133	break;
3055acb0 AN	134	case DSP_BASE ... DSP_BASE + 5: {
	135	dspreg_t *dregs;
	136
e50c0a8f RB	137	if (!cpu_has_dsp) {
	138	tmp = 0;
	139	ret = -EIO;
5d9a76cd	140	goto out;
e50c0a8f	141	}
3055acb0	142	dregs = __get_dsp_regs(child);
6c355852	143	tmp = (unsigned long) (dregs[addr - DSP_BASE]);
e50c0a8f	144	break;
3055acb0	145	}
e50c0a8f RB	146	case DSP_CONTROL:
	147	if (!cpu_has_dsp) {
	148	tmp = 0;
	149	ret = -EIO;
5d9a76cd	150	goto out;
e50c0a8f RB	151	}
	152	tmp = child->thread.dsp.dspcontrol;
	153	break;
1da177e4 LT	154	default:
	155	tmp = 0;
	156	ret = -EIO;
5d9a76cd	157	goto out;
1da177e4	158	}
3055acb0	159	ret = put_user(tmp, (unsigned __user *) (unsigned long) data);
1da177e4 LT	160	break;
	161	}
	162
ea3d710f DJ	163	/*
	164	* Write 4 bytes into the other process' storage
	165	* data is the 4 bytes that the user wants written
	166	* addr is a pointer in the user's storage that contains an
	167	* 8 byte address in the other process where the 4 bytes
	168	* that is to be written
	169	* (this is run in a 32-bit process looking at a 64-bit process)
	170	* when I and D space are separate, these will need to be fixed.
	171	*/
	172	case PTRACE_POKETEXT_3264:
	173	case PTRACE_POKEDATA_3264: {
	174	u32 __user * addrOthers;
	175
	176	/* Get the addr in the other process that we want to write into */
	177	ret = -EIO;
	178	if (get_user(addrOthers, (u32 __user * __user *) (unsigned long) addr) != 0)
	179	break;
	180	ret = 0;
84d77d3f	181	if (ptrace_access_vm(child, (u64)addrOthers, &data,
f307ab6d LS	182	sizeof(data),
f307ab6d LS	183	FOLL_FORCE \| FOLL_WRITE) == sizeof(data))
ea3d710f DJ	184	break;
	185	ret = -EIO;
	186	break;
	187	}
	188
1da177e4 LT	189	case PTRACE_POKEUSR: {
	190	struct pt_regs *regs;
	191	ret = 0;
40bc9c67	192	regs = task_pt_regs(child);
1da177e4 LT	193
	194	switch (addr) {
	195	case 0 ... 31:
	196	regs->regs[addr] = data;
	197	break;
	198	case FPR_BASE ... FPR_BASE + 31: {
bbd426f5	199	union fpureg *fregs = get_fpu_regs(child);
1da177e4 LT	200
	201	if (!tsk_used_math(child)) {
	202	/* FP not yet used */
eae89076 AN	203	memset(&child->thread.fpu, ~0,
	204	sizeof(child->thread.fpu));
	205	child->thread.fpu.fcr31 = 0;
1da177e4	206	}
597ce172 PB	207	if (test_thread_flag(TIF_32BIT_FPREGS)) {
	208	/*
	209	* The odd registers are actually the high
	210	* order bits of the values stored in the even
	211	* registers - unless we're using r2k_switch.S.
	212	*/
bbd426f5 PB	213	set_fpr32(&fregs[(addr & ~1) - FPR_BASE],
bbd426f5 PB	214	addr & 1, data);
597ce172	215	break;
1da177e4	216	}
bbd426f5	217	set_fpr64(&fregs[addr - FPR_BASE], 0, data);
1da177e4 LT	218	break;
	219	}
	220	case PC:
	221	regs->cp0_epc = data;
	222	break;
	223	case MMHI:
	224	regs->hi = data;
	225	break;
	226	case MMLO:
	227	regs->lo = data;
	228	break;
	229	case FPC_CSR:
eae89076	230	child->thread.fpu.fcr31 = data;
1da177e4	231	break;
3055acb0 AN	232	case DSP_BASE ... DSP_BASE + 5: {
	233	dspreg_t *dregs;
	234
e50c0a8f RB	235	if (!cpu_has_dsp) {
	236	ret = -EIO;
	237	break;
	238	}
	239
3055acb0	240	dregs = __get_dsp_regs(child);
e50c0a8f RB	241	dregs[addr - DSP_BASE] = data;
e50c0a8f RB	242	break;
3055acb0	243	}
e50c0a8f RB	244	case DSP_CONTROL:
	245	if (!cpu_has_dsp) {
	246	ret = -EIO;
	247	break;
	248	}
	249	child->thread.dsp.dspcontrol = data;
	250	break;
1da177e4 LT	251	default:
	252	/* The rest are not allowed. */
	253	ret = -EIO;
	254	break;
	255	}
	256	break;
	257	}
	258
ea3d710f	259	case PTRACE_GETREGS:
a79ebea6 AS	260	ret = ptrace_getregs(child,
a79ebea6 AS	261	(struct user_pt_regs __user *) (__u64) data);
ea3d710f DJ	262	break;
	263
	264	case PTRACE_SETREGS:
a79ebea6 AS	265	ret = ptrace_setregs(child,
a79ebea6 AS	266	(struct user_pt_regs __user *) (__u64) data);
ea3d710f DJ	267	break;
	268
	269	case PTRACE_GETFPREGS:
49a89efb	270	ret = ptrace_getfpregs(child, (__u32 __user *) (__u64) data);
ea3d710f DJ	271	break;
	272
	273	case PTRACE_SETFPREGS:
49a89efb	274	ret = ptrace_setfpregs(child, (__u32 __user *) (__u64) data);
ea3d710f DJ	275	break;
ea3d710f DJ	276
3c37026d	277	case PTRACE_GET_THREAD_AREA:
dc8f6029	278	ret = put_user(task_thread_info(child)->tp_value,
3c37026d RB	279	(unsigned int __user *) (unsigned long) data);
	280	break;
	281
ea3d710f	282	case PTRACE_GET_THREAD_AREA_3264:
dc8f6029	283	ret = put_user(task_thread_info(child)->tp_value,
ea3d710f DJ	284	(unsigned long __user *) (unsigned long) data);
	285	break;
	286
0926bf95 DD	287	case PTRACE_GET_WATCH_REGS:
	288	ret = ptrace_get_watch_regs(child,
	289	(struct pt_watch_regs __user *) (unsigned long) addr);
	290	break;
	291
	292	case PTRACE_SET_WATCH_REGS:
	293	ret = ptrace_set_watch_regs(child,
	294	(struct pt_watch_regs __user *) (unsigned long) addr);
	295	break;
	296
1da177e4	297	default:
797c3f32	298	ret = compat_ptrace_request(child, request, addr, data);
1da177e4 LT	299	break;
1da177e4 LT	300	}
1da177e4	301	out:
1da177e4 LT	302	return ret;
1da177e4 LT	303	}