[mirror_ubuntu-jammy-kernel.git] / arch / mips / kernel / r4k_switch.S

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 1994, 1995, 1996, 1998, 1999, 2002, 2003 Ralf Baechle
 * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
 * Copyright (C) 1994, 1995, 1996, by Andreas Busse
 * Copyright (C) 1999 Silicon Graphics, Inc.
 * Copyright (C) 2000 MIPS Technologies, Inc.
 *    written by Carsten Langgaard, carstenl@mips.com
 */
#include <asm/asm.h>
#include <asm/cachectl.h>
#include <asm/fpregdef.h>
#include <asm/mipsregs.h>
#include <asm/asm-offsets.h>
#include <asm/page.h>
#include <asm/pgtable-bits.h>
#include <asm/regdef.h>
#include <asm/stackframe.h>
#include <asm/thread_info.h>

#include <asm/asmmacro.h>

/*
 * Offset to the current process status flags, the first 32 bytes of the
 * stack are not used.
 */
#define ST_OFF (_THREAD_SIZE - 32 - PT_SIZE + PT_STATUS)

/*
 * FPU context is saved iff the process has used it's FPU in the current
 * time slice as indicated by _TIF_USEDFPU.  In any case, the CU1 bit for user
 * space STATUS register should be 0, so that a process *always* starts its
 * userland with FPU disabled after each context switch.
 *
 * FPU will be enabled as soon as the process accesses FPU again, through
 * do_cpu() trap.
 */

/*
 * task_struct *resume(task_struct *prev, task_struct *next,
 *                     struct thread_info *next_ti)
 */
	.align	5
	LEAF(resume)
#ifndef CONFIG_CPU_HAS_LLSC
	sw	zero, ll_bit
#endif
	mfc0	t1, CP0_STATUS
	LONG_S	t1, THREAD_STATUS(a0)
	cpu_save_nonscratch a0
	LONG_S	ra, THREAD_REG31(a0)

	/*
	 * check if we need to save FPU registers
	 */
	PTR_L	t3, TASK_THREAD_INFO(a0)
	LONG_L	t0, TI_FLAGS(t3)
	li	t1, _TIF_USEDFPU
	and	t2, t0, t1
	beqz	t2, 1f
	nor	t1, zero, t1

	and	t0, t0, t1
	LONG_S	t0, TI_FLAGS(t3)

	/*
	 * clear saved user stack CU1 bit
	 */
	LONG_L	t0, ST_OFF(t3)
	li	t1, ~ST0_CU1
	and	t0, t0, t1
	LONG_S	t0, ST_OFF(t3)

	fpu_save_double a0 t0 t1		# c0_status passed in t0
						# clobbers t1
1:

	/*
	 * The order of restoring the registers takes care of the race
	 * updating $28, $29 and kernelsp without disabling ints.
	 */
	move	$28, a2
	cpu_restore_nonscratch a1

	PTR_ADDIU	t0, $28, _THREAD_SIZE - 32
	set_saved_sp	t0, t1, t2
#ifdef CONFIG_MIPS_MT_SMTC
	/* Read-modify-writes of Status must be atomic on a VPE */
	mfc0	t2, CP0_TCSTATUS
	ori	t1, t2, TCSTATUS_IXMT
	mtc0	t1, CP0_TCSTATUS
	andi	t2, t2, TCSTATUS_IXMT
	_ehb
	DMT	8				# dmt	t0
	move	t1,ra
	jal	mips_ihb
	move	ra,t1
#endif /* CONFIG_MIPS_MT_SMTC */
	mfc0	t1, CP0_STATUS		/* Do we really need this? */
	li	a3, 0xff01
	and	t1, a3
	LONG_L	a2, THREAD_STATUS(a1)
	nor	a3, $0, a3
	and	a2, a3
	or	a2, t1
	mtc0	a2, CP0_STATUS
#ifdef CONFIG_MIPS_MT_SMTC
	_ehb
	andi	t0, t0, VPECONTROL_TE
	beqz	t0, 1f
	emt
1:
	mfc0	t1, CP0_TCSTATUS
	xori	t1, t1, TCSTATUS_IXMT
	or	t1, t1, t2
	mtc0	t1, CP0_TCSTATUS
	_ehb
#endif /* CONFIG_MIPS_MT_SMTC */
	move	v0, a0
	jr	ra
	END(resume)

/*
 * Save a thread's fp context.
 */
LEAF(_save_fp)
#ifdef CONFIG_64BIT
	mfc0	t0, CP0_STATUS
#endif
	fpu_save_double a0 t0 t1		# clobbers t1
	jr	ra
	END(_save_fp)

/*
 * Restore a thread's fp context.
 */
LEAF(_restore_fp)
#ifdef CONFIG_64BIT
	mfc0	t0, CP0_STATUS
#endif
	fpu_restore_double a0 t0 t1		# clobbers t1
	jr	ra
	END(_restore_fp)

/*
 * Load the FPU with signalling NANS.  This bit pattern we're using has
 * the property that no matter whether considered as single or as double
 * precision represents signaling NANS.
 *
 * We initialize fcr31 to rounding to nearest, no exceptions.
 */

#define FPU_DEFAULT  0x00000000

LEAF(_init_fpu)
#ifdef CONFIG_MIPS_MT_SMTC
	/* Rather than manipulate per-VPE Status, set per-TC bit in TCStatus */
	mfc0	t0, CP0_TCSTATUS
	/* Bit position is the same for Status, TCStatus */
	li	t1, ST0_CU1
	or	t0, t1
	mtc0	t0, CP0_TCSTATUS
#else /* Normal MIPS CU1 enable */
	mfc0	t0, CP0_STATUS
	li	t1, ST0_CU1
	or	t0, t1
	mtc0	t0, CP0_STATUS
#endif /* CONFIG_MIPS_MT_SMTC */
	fpu_enable_hazard

	li	t1, FPU_DEFAULT
	ctc1	t1, fcr31

	li	t1, -1				# SNaN

#ifdef CONFIG_64BIT
	sll	t0, t0, 5
	bgez	t0, 1f				# 16 / 32 register mode?

	dmtc1	t1, $f1
	dmtc1	t1, $f3
	dmtc1	t1, $f5
	dmtc1	t1, $f7
	dmtc1	t1, $f9
	dmtc1	t1, $f11
	dmtc1	t1, $f13
	dmtc1	t1, $f15
	dmtc1	t1, $f17
	dmtc1	t1, $f19
	dmtc1	t1, $f21
	dmtc1	t1, $f23
	dmtc1	t1, $f25
	dmtc1	t1, $f27
	dmtc1	t1, $f29
	dmtc1	t1, $f31
1:
#endif

#ifdef CONFIG_CPU_MIPS32
	mtc1	t1, $f0
	mtc1	t1, $f1
	mtc1	t1, $f2
	mtc1	t1, $f3
	mtc1	t1, $f4
	mtc1	t1, $f5
	mtc1	t1, $f6
	mtc1	t1, $f7
	mtc1	t1, $f8
	mtc1	t1, $f9
	mtc1	t1, $f10
	mtc1	t1, $f11
	mtc1	t1, $f12
	mtc1	t1, $f13
	mtc1	t1, $f14
	mtc1	t1, $f15
	mtc1	t1, $f16
	mtc1	t1, $f17
	mtc1	t1, $f18
	mtc1	t1, $f19
	mtc1	t1, $f20
	mtc1	t1, $f21
	mtc1	t1, $f22
	mtc1	t1, $f23
	mtc1	t1, $f24
	mtc1	t1, $f25
	mtc1	t1, $f26
	mtc1	t1, $f27
	mtc1	t1, $f28
	mtc1	t1, $f29
	mtc1	t1, $f30
	mtc1	t1, $f31
#else
	.set	mips3
	dmtc1	t1, $f0
	dmtc1	t1, $f2
	dmtc1	t1, $f4
	dmtc1	t1, $f6
	dmtc1	t1, $f8
	dmtc1	t1, $f10
	dmtc1	t1, $f12
	dmtc1	t1, $f14
	dmtc1	t1, $f16
	dmtc1	t1, $f18
	dmtc1	t1, $f20
	dmtc1	t1, $f22
	dmtc1	t1, $f24
	dmtc1	t1, $f26
	dmtc1	t1, $f28
	dmtc1	t1, $f30
#endif
	jr	ra
	END(_init_fpu)
Commit	Line	Data
1da177e4 LT	1	/*
	2	* This file is subject to the terms and conditions of the GNU General Public
	3	* License. See the file "COPYING" in the main directory of this archive
	4	* for more details.
	5	*
	6	* Copyright (C) 1994, 1995, 1996, 1998, 1999, 2002, 2003 Ralf Baechle
	7	* Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
	8	* Copyright (C) 1994, 1995, 1996, by Andreas Busse
	9	* Copyright (C) 1999 Silicon Graphics, Inc.
	10	* Copyright (C) 2000 MIPS Technologies, Inc.
	11	* written by Carsten Langgaard, carstenl@mips.com
	12	*/
1da177e4 LT	13	#include <asm/asm.h>
	14	#include <asm/cachectl.h>
	15	#include <asm/fpregdef.h>
	16	#include <asm/mipsregs.h>
048eb582	17	#include <asm/asm-offsets.h>
1da177e4 LT	18	#include <asm/page.h>
	19	#include <asm/pgtable-bits.h>
	20	#include <asm/regdef.h>
	21	#include <asm/stackframe.h>
	22	#include <asm/thread_info.h>
	23
	24	#include <asm/asmmacro.h>
	25
	26	/*
	27	* Offset to the current process status flags, the first 32 bytes of the
	28	* stack are not used.
	29	*/
	30	#define ST_OFF (_THREAD_SIZE - 32 - PT_SIZE + PT_STATUS)
	31
	32	/*
	33	* FPU context is saved iff the process has used it's FPU in the current
	34	* time slice as indicated by _TIF_USEDFPU. In any case, the CU1 bit for user
42a3b4f2	35	* space STATUS register should be 0, so that a process always starts its
1da177e4 LT	36	* userland with FPU disabled after each context switch.
	37	*
	38	* FPU will be enabled as soon as the process accesses FPU again, through
	39	* do_cpu() trap.
	40	*/
	41
	42	/*
	43	* task_struct resume(task_struct prev, task_struct *next,
	44	* struct thread_info *next_ti)
	45	*/
	46	.align 5
	47	LEAF(resume)
	48	#ifndef CONFIG_CPU_HAS_LLSC
	49	sw zero, ll_bit
	50	#endif
	51	mfc0 t1, CP0_STATUS
	52	LONG_S t1, THREAD_STATUS(a0)
	53	cpu_save_nonscratch a0
	54	LONG_S ra, THREAD_REG31(a0)
	55
	56	/*
	57	* check if we need to save FPU registers
	58	*/
	59	PTR_L t3, TASK_THREAD_INFO(a0)
	60	LONG_L t0, TI_FLAGS(t3)
	61	li t1, _TIF_USEDFPU
	62	and t2, t0, t1
	63	beqz t2, 1f
	64	nor t1, zero, t1
	65
	66	and t0, t0, t1
	67	LONG_S t0, TI_FLAGS(t3)
	68
	69	/*
	70	* clear saved user stack CU1 bit
	71	*/
	72	LONG_L t0, ST_OFF(t3)
	73	li t1, ~ST0_CU1
	74	and t0, t0, t1
	75	LONG_S t0, ST_OFF(t3)
	76
c138e12f AN	77	fpu_save_double a0 t0 t1 # c0_status passed in t0
c138e12f AN	78	# clobbers t1
1da177e4 LT	79	1:
	80
	81	/*
	82	* The order of restoring the registers takes care of the race
	83	* updating $28, $29 and kernelsp without disabling ints.
	84	*/
	85	move $28, a2
	86	cpu_restore_nonscratch a1
	87
	88	PTR_ADDIU t0, $28, _THREAD_SIZE - 32
	89	set_saved_sp t0, t1, t2
41c594ab RB	90	#ifdef CONFIG_MIPS_MT_SMTC
	91	/* Read-modify-writes of Status must be atomic on a VPE */
	92	mfc0 t2, CP0_TCSTATUS
	93	ori t1, t2, TCSTATUS_IXMT
	94	mtc0 t1, CP0_TCSTATUS
	95	andi t2, t2, TCSTATUS_IXMT
4277ff5e	96	_ehb
41c594ab RB	97	DMT 8 # dmt t0
	98	move t1,ra
	99	jal mips_ihb
	100	move ra,t1
	101	#endif /* CONFIG_MIPS_MT_SMTC */
1da177e4 LT	102	mfc0 t1, CP0_STATUS /* Do we really need this? */
	103	li a3, 0xff01
	104	and t1, a3
	105	LONG_L a2, THREAD_STATUS(a1)
	106	nor a3, $0, a3
	107	and a2, a3
	108	or a2, t1
	109	mtc0 a2, CP0_STATUS
41c594ab	110	#ifdef CONFIG_MIPS_MT_SMTC
4277ff5e	111	_ehb
41c594ab RB	112	andi t0, t0, VPECONTROL_TE
	113	beqz t0, 1f
	114	emt
	115	1:
	116	mfc0 t1, CP0_TCSTATUS
	117	xori t1, t1, TCSTATUS_IXMT
	118	or t1, t1, t2
	119	mtc0 t1, CP0_TCSTATUS
4277ff5e	120	_ehb
41c594ab	121	#endif /* CONFIG_MIPS_MT_SMTC */
1da177e4 LT	122	move v0, a0
	123	jr ra
	124	END(resume)
	125
	126	/*
	127	* Save a thread's fp context.
	128	*/
	129	LEAF(_save_fp)
875d43e7	130	#ifdef CONFIG_64BIT
c138e12f	131	mfc0 t0, CP0_STATUS
1da177e4	132	#endif
c138e12f	133	fpu_save_double a0 t0 t1 # clobbers t1
1da177e4 LT	134	jr ra
	135	END(_save_fp)
	136
	137	/*
	138	* Restore a thread's fp context.
	139	*/
	140	LEAF(_restore_fp)
c138e12f AN	141	#ifdef CONFIG_64BIT
	142	mfc0 t0, CP0_STATUS
	143	#endif
	144	fpu_restore_double a0 t0 t1 # clobbers t1
1da177e4 LT	145	jr ra
	146	END(_restore_fp)
	147
	148	/*
	149	* Load the FPU with signalling NANS. This bit pattern we're using has
	150	* the property that no matter whether considered as single or as double
	151	* precision represents signaling NANS.
	152	*
	153	* We initialize fcr31 to rounding to nearest, no exceptions.
	154	*/
	155
	156	#define FPU_DEFAULT 0x00000000
	157
	158	LEAF(_init_fpu)
41c594ab RB	159	#ifdef CONFIG_MIPS_MT_SMTC
	160	/* Rather than manipulate per-VPE Status, set per-TC bit in TCStatus */
	161	mfc0 t0, CP0_TCSTATUS
	162	/* Bit position is the same for Status, TCStatus */
	163	li t1, ST0_CU1
	164	or t0, t1
	165	mtc0 t0, CP0_TCSTATUS
	166	#else /* Normal MIPS CU1 enable */
1da177e4 LT	167	mfc0 t0, CP0_STATUS
	168	li t1, ST0_CU1
	169	or t0, t1
	170	mtc0 t0, CP0_STATUS
41c594ab	171	#endif /* CONFIG_MIPS_MT_SMTC */
1da177e4 LT	172	fpu_enable_hazard
	173
	174	li t1, FPU_DEFAULT
	175	ctc1 t1, fcr31
	176
	177	li t1, -1 # SNaN
	178
875d43e7	179	#ifdef CONFIG_64BIT
1da177e4 LT	180	sll t0, t0, 5
	181	bgez t0, 1f # 16 / 32 register mode?
	182
	183	dmtc1 t1, $f1
	184	dmtc1 t1, $f3
	185	dmtc1 t1, $f5
	186	dmtc1 t1, $f7
	187	dmtc1 t1, $f9
	188	dmtc1 t1, $f11
	189	dmtc1 t1, $f13
	190	dmtc1 t1, $f15
	191	dmtc1 t1, $f17
	192	dmtc1 t1, $f19
	193	dmtc1 t1, $f21
	194	dmtc1 t1, $f23
	195	dmtc1 t1, $f25
	196	dmtc1 t1, $f27
	197	dmtc1 t1, $f29
	198	dmtc1 t1, $f31
	199	1:
	200	#endif
42a3b4f2	201
1da177e4 LT	202	#ifdef CONFIG_CPU_MIPS32
	203	mtc1 t1, $f0
	204	mtc1 t1, $f1
	205	mtc1 t1, $f2
	206	mtc1 t1, $f3
	207	mtc1 t1, $f4
	208	mtc1 t1, $f5
	209	mtc1 t1, $f6
	210	mtc1 t1, $f7
	211	mtc1 t1, $f8
	212	mtc1 t1, $f9
	213	mtc1 t1, $f10
	214	mtc1 t1, $f11
	215	mtc1 t1, $f12
	216	mtc1 t1, $f13
	217	mtc1 t1, $f14
	218	mtc1 t1, $f15
	219	mtc1 t1, $f16
	220	mtc1 t1, $f17
	221	mtc1 t1, $f18
	222	mtc1 t1, $f19
	223	mtc1 t1, $f20
	224	mtc1 t1, $f21
	225	mtc1 t1, $f22
	226	mtc1 t1, $f23
	227	mtc1 t1, $f24
	228	mtc1 t1, $f25
	229	mtc1 t1, $f26
	230	mtc1 t1, $f27
	231	mtc1 t1, $f28
	232	mtc1 t1, $f29
	233	mtc1 t1, $f30
	234	mtc1 t1, $f31
	235	#else
	236	.set mips3
	237	dmtc1 t1, $f0
	238	dmtc1 t1, $f2
	239	dmtc1 t1, $f4
	240	dmtc1 t1, $f6
	241	dmtc1 t1, $f8
	242	dmtc1 t1, $f10
	243	dmtc1 t1, $f12
	244	dmtc1 t1, $f14
	245	dmtc1 t1, $f16
	246	dmtc1 t1, $f18
	247	dmtc1 t1, $f20
	248	dmtc1 t1, $f22
	249	dmtc1 t1, $f24
	250	dmtc1 t1, $f26
	251	dmtc1 t1, $f28
	252	dmtc1 t1, $f30
	253	#endif
	254	jr ra
	255	END(_init_fpu)