[mirror_ubuntu-bionic-kernel.git] / arch / mips / kernel / smp-bmips.c

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 2011 by Kevin Cernekee (cernekee@gmail.com)
 *
 * SMP support for BMIPS
 */

#include <linux/init.h>
#include <linux/sched.h>
#include <linux/sched/hotplug.h>
#include <linux/sched/task_stack.h>
#include <linux/mm.h>
#include <linux/delay.h>
#include <linux/smp.h>
#include <linux/interrupt.h>
#include <linux/spinlock.h>
#include <linux/cpu.h>
#include <linux/cpumask.h>
#include <linux/reboot.h>
#include <linux/io.h>
#include <linux/compiler.h>
#include <linux/linkage.h>
#include <linux/bug.h>
#include <linux/kernel.h>

#include <asm/time.h>
#include <asm/pgtable.h>
#include <asm/processor.h>
#include <asm/bootinfo.h>
#include <asm/pmon.h>
#include <asm/cacheflush.h>
#include <asm/tlbflush.h>
#include <asm/mipsregs.h>
#include <asm/bmips.h>
#include <asm/traps.h>
#include <asm/barrier.h>
#include <asm/cpu-features.h>

static int __maybe_unused max_cpus = 1;

/* these may be configured by the platform code */
int bmips_smp_enabled = 1;
int bmips_cpu_offset;
cpumask_t bmips_booted_mask;
unsigned long bmips_tp1_irqs = IE_IRQ1;

#define RESET_FROM_KSEG0		0x80080800
#define RESET_FROM_KSEG1		0xa0080800

static void bmips_set_reset_vec(int cpu, u32 val);

#ifdef CONFIG_SMP

/* initial $sp, $gp - used by arch/mips/kernel/bmips_vec.S */
unsigned long bmips_smp_boot_sp;
unsigned long bmips_smp_boot_gp;

static void bmips43xx_send_ipi_single(int cpu, unsigned int action);
static void bmips5000_send_ipi_single(int cpu, unsigned int action);
static irqreturn_t bmips43xx_ipi_interrupt(int irq, void *dev_id);
static irqreturn_t bmips5000_ipi_interrupt(int irq, void *dev_id);

/* SW interrupts 0,1 are used for interprocessor signaling */
#define IPI0_IRQ			(MIPS_CPU_IRQ_BASE + 0)
#define IPI1_IRQ			(MIPS_CPU_IRQ_BASE + 1)

#define CPUNUM(cpu, shift)		(((cpu) + bmips_cpu_offset) << (shift))
#define ACTION_CLR_IPI(cpu, ipi)	(0x2000 | CPUNUM(cpu, 9) | ((ipi) << 8))
#define ACTION_SET_IPI(cpu, ipi)	(0x3000 | CPUNUM(cpu, 9) | ((ipi) << 8))
#define ACTION_BOOT_THREAD(cpu)		(0x08 | CPUNUM(cpu, 0))

static void __init bmips_smp_setup(void)
{
	int i, cpu = 1, boot_cpu = 0;
	int cpu_hw_intr;

	switch (current_cpu_type()) {
	case CPU_BMIPS4350:
	case CPU_BMIPS4380:
		/* arbitration priority */
		clear_c0_brcm_cmt_ctrl(0x30);

		/* NBK and weak order flags */
		set_c0_brcm_config_0(0x30000);

		/* Find out if we are running on TP0 or TP1 */
		boot_cpu = !!(read_c0_brcm_cmt_local() & (1 << 31));

		/*
		 * MIPS interrupts 0,1 (SW INT 0,1) cross over to the other
		 * thread
		 * MIPS interrupt 2 (HW INT 0) is the CPU0 L1 controller output
		 * MIPS interrupt 3 (HW INT 1) is the CPU1 L1 controller output
		 */
		if (boot_cpu == 0)
			cpu_hw_intr = 0x02;
		else
			cpu_hw_intr = 0x1d;

		change_c0_brcm_cmt_intr(0xf8018000,
					(cpu_hw_intr << 27) | (0x03 << 15));

		/* single core, 2 threads (2 pipelines) */
		max_cpus = 2;

		break;
	case CPU_BMIPS5000:
		/* enable raceless SW interrupts */
		set_c0_brcm_config(0x03 << 22);

		/* route HW interrupt 0 to CPU0, HW interrupt 1 to CPU1 */
		change_c0_brcm_mode(0x1f << 27, 0x02 << 27);

		/* N cores, 2 threads per core */
		max_cpus = (((read_c0_brcm_config() >> 6) & 0x03) + 1) << 1;

		/* clear any pending SW interrupts */
		for (i = 0; i < max_cpus; i++) {
			write_c0_brcm_action(ACTION_CLR_IPI(i, 0));
			write_c0_brcm_action(ACTION_CLR_IPI(i, 1));
		}

		break;
	default:
		max_cpus = 1;
	}

	if (!bmips_smp_enabled)
		max_cpus = 1;

	/* this can be overridden by the BSP */
	if (!board_ebase_setup)
		board_ebase_setup = &bmips_ebase_setup;

	__cpu_number_map[boot_cpu] = 0;
	__cpu_logical_map[0] = boot_cpu;

	for (i = 0; i < max_cpus; i++) {
		if (i != boot_cpu) {
			__cpu_number_map[i] = cpu;
			__cpu_logical_map[cpu] = i;
			cpu++;
		}
		set_cpu_possible(i, 1);
		set_cpu_present(i, 1);
	}
}

/*
 * IPI IRQ setup - runs on CPU0
 */
static void bmips_prepare_cpus(unsigned int max_cpus)
{
	irqreturn_t (*bmips_ipi_interrupt)(int irq, void *dev_id);

	switch (current_cpu_type()) {
	case CPU_BMIPS4350:
	case CPU_BMIPS4380:
		bmips_ipi_interrupt = bmips43xx_ipi_interrupt;
		break;
	case CPU_BMIPS5000:
		bmips_ipi_interrupt = bmips5000_ipi_interrupt;
		break;
	default:
		return;
	}

	if (request_irq(IPI0_IRQ, bmips_ipi_interrupt, IRQF_PERCPU,
			"smp_ipi0", NULL))
		panic("Can't request IPI0 interrupt");
	if (request_irq(IPI1_IRQ, bmips_ipi_interrupt, IRQF_PERCPU,
			"smp_ipi1", NULL))
		panic("Can't request IPI1 interrupt");
}

/*
 * Tell the hardware to boot CPUx - runs on CPU0
 */
static void bmips_boot_secondary(int cpu, struct task_struct *idle)
{
	bmips_smp_boot_sp = __KSTK_TOS(idle);
	bmips_smp_boot_gp = (unsigned long)task_thread_info(idle);
	mb();

	/*
	 * Initial boot sequence for secondary CPU:
	 *   bmips_reset_nmi_vec @ a000_0000 ->
	 *   bmips_smp_entry ->
	 *   plat_wired_tlb_setup (cached function call; optional) ->
	 *   start_secondary (cached jump)
	 *
	 * Warm restart sequence:
	 *   play_dead WAIT loop ->
	 *   bmips_smp_int_vec @ BMIPS_WARM_RESTART_VEC ->
	 *   eret to play_dead ->
	 *   bmips_secondary_reentry ->
	 *   start_secondary
	 */

	pr_info("SMP: Booting CPU%d...\n", cpu);

	if (cpumask_test_cpu(cpu, &bmips_booted_mask)) {
		/* kseg1 might not exist if this CPU enabled XKS01 */
		bmips_set_reset_vec(cpu, RESET_FROM_KSEG0);

		switch (current_cpu_type()) {
		case CPU_BMIPS4350:
		case CPU_BMIPS4380:
			bmips43xx_send_ipi_single(cpu, 0);
			break;
		case CPU_BMIPS5000:
			bmips5000_send_ipi_single(cpu, 0);
			break;
		}
	} else {
		bmips_set_reset_vec(cpu, RESET_FROM_KSEG1);

		switch (current_cpu_type()) {
		case CPU_BMIPS4350:
		case CPU_BMIPS4380:
			/* Reset slave TP1 if booting from TP0 */
			if (cpu_logical_map(cpu) == 1)
				set_c0_brcm_cmt_ctrl(0x01);
			break;
		case CPU_BMIPS5000:
			write_c0_brcm_action(ACTION_BOOT_THREAD(cpu));
			break;
		}
		cpumask_set_cpu(cpu, &bmips_booted_mask);
	}
}

/*
 * Early setup - runs on secondary CPU after cache probe
 */
static void bmips_init_secondary(void)
{
	switch (current_cpu_type()) {
	case CPU_BMIPS4350:
	case CPU_BMIPS4380:
		clear_c0_cause(smp_processor_id() ? C_SW1 : C_SW0);
		break;
	case CPU_BMIPS5000:
		write_c0_brcm_action(ACTION_CLR_IPI(smp_processor_id(), 0));
		current_cpu_data.core = (read_c0_brcm_config() >> 25) & 3;
		break;
	}
}

/*
 * Late setup - runs on secondary CPU before entering the idle loop
 */
static void bmips_smp_finish(void)
{
	pr_info("SMP: CPU%d is running\n", smp_processor_id());

	/* make sure there won't be a timer interrupt for a little while */
	write_c0_compare(read_c0_count() + mips_hpt_frequency / HZ);

	irq_enable_hazard();
	set_c0_status(IE_SW0 | IE_SW1 | bmips_tp1_irqs | IE_IRQ5 | ST0_IE);
	irq_enable_hazard();
}

/*
 * BMIPS5000 raceless IPIs
 *
 * Each CPU has two inbound SW IRQs which are independent of all other CPUs.
 * IPI0 is used for SMP_RESCHEDULE_YOURSELF
 * IPI1 is used for SMP_CALL_FUNCTION
 */

static void bmips5000_send_ipi_single(int cpu, unsigned int action)
{
	write_c0_brcm_action(ACTION_SET_IPI(cpu, action == SMP_CALL_FUNCTION));
}

static irqreturn_t bmips5000_ipi_interrupt(int irq, void *dev_id)
{
	int action = irq - IPI0_IRQ;

	write_c0_brcm_action(ACTION_CLR_IPI(smp_processor_id(), action));

	if (action == 0)
		scheduler_ipi();
	else
		generic_smp_call_function_interrupt();

	return IRQ_HANDLED;
}

static void bmips5000_send_ipi_mask(const struct cpumask *mask,
	unsigned int action)
{
	unsigned int i;

	for_each_cpu(i, mask)
		bmips5000_send_ipi_single(i, action);
}

/*
 * BMIPS43xx racey IPIs
 *
 * We use one inbound SW IRQ for each CPU.
 *
 * A spinlock must be held in order to keep CPUx from accidentally clearing
 * an incoming IPI when it writes CP0 CAUSE to raise an IPI on CPUy.  The
 * same spinlock is used to protect the action masks.
 */

static DEFINE_SPINLOCK(ipi_lock);
static DEFINE_PER_CPU(int, ipi_action_mask);

static void bmips43xx_send_ipi_single(int cpu, unsigned int action)
{
	unsigned long flags;

	spin_lock_irqsave(&ipi_lock, flags);
	set_c0_cause(cpu ? C_SW1 : C_SW0);
	per_cpu(ipi_action_mask, cpu) |= action;
	irq_enable_hazard();
	spin_unlock_irqrestore(&ipi_lock, flags);
}

static irqreturn_t bmips43xx_ipi_interrupt(int irq, void *dev_id)
{
	unsigned long flags;
	int action, cpu = irq - IPI0_IRQ;

	spin_lock_irqsave(&ipi_lock, flags);
	action = __this_cpu_read(ipi_action_mask);
	per_cpu(ipi_action_mask, cpu) = 0;
	clear_c0_cause(cpu ? C_SW1 : C_SW0);
	spin_unlock_irqrestore(&ipi_lock, flags);

	if (action & SMP_RESCHEDULE_YOURSELF)
		scheduler_ipi();
	if (action & SMP_CALL_FUNCTION)
		generic_smp_call_function_interrupt();

	return IRQ_HANDLED;
}

static void bmips43xx_send_ipi_mask(const struct cpumask *mask,
	unsigned int action)
{
	unsigned int i;

	for_each_cpu(i, mask)
		bmips43xx_send_ipi_single(i, action);
}

#ifdef CONFIG_HOTPLUG_CPU

static int bmips_cpu_disable(void)
{
	unsigned int cpu = smp_processor_id();

	if (cpu == 0)
		return -EBUSY;

	pr_info("SMP: CPU%d is offline\n", cpu);

	set_cpu_online(cpu, false);
	calculate_cpu_foreign_map();
	irq_cpu_offline();
	clear_c0_status(IE_IRQ5);

	local_flush_tlb_all();
	local_flush_icache_range(0, ~0);

	return 0;
}

static void bmips_cpu_die(unsigned int cpu)
{
}

void __ref play_dead(void)
{
	idle_task_exit();

	/* flush data cache */
	_dma_cache_wback_inv(0, ~0);

	/*
	 * Wakeup is on SW0 or SW1; disable everything else
	 * Use BEV !IV (BMIPS_WARM_RESTART_VEC) to avoid the regular Linux
	 * IRQ handlers; this clears ST0_IE and returns immediately.
	 */
	clear_c0_cause(CAUSEF_IV | C_SW0 | C_SW1);
	change_c0_status(
		IE_IRQ5 | bmips_tp1_irqs | IE_SW0 | IE_SW1 | ST0_IE | ST0_BEV,
		IE_SW0 | IE_SW1 | ST0_IE | ST0_BEV);
	irq_disable_hazard();

	/*
	 * wait for SW interrupt from bmips_boot_secondary(), then jump
	 * back to start_secondary()
	 */
	__asm__ __volatile__(
	"	wait\n"
	"	j	bmips_secondary_reentry\n"
	: : : "memory");
}

#endif /* CONFIG_HOTPLUG_CPU */

struct plat_smp_ops bmips43xx_smp_ops = {
	.smp_setup		= bmips_smp_setup,
	.prepare_cpus		= bmips_prepare_cpus,
	.boot_secondary		= bmips_boot_secondary,
	.smp_finish		= bmips_smp_finish,
	.init_secondary		= bmips_init_secondary,
	.send_ipi_single	= bmips43xx_send_ipi_single,
	.send_ipi_mask		= bmips43xx_send_ipi_mask,
#ifdef CONFIG_HOTPLUG_CPU
	.cpu_disable		= bmips_cpu_disable,
	.cpu_die		= bmips_cpu_die,
#endif
};

struct plat_smp_ops bmips5000_smp_ops = {
	.smp_setup		= bmips_smp_setup,
	.prepare_cpus		= bmips_prepare_cpus,
	.boot_secondary		= bmips_boot_secondary,
	.smp_finish		= bmips_smp_finish,
	.init_secondary		= bmips_init_secondary,
	.send_ipi_single	= bmips5000_send_ipi_single,
	.send_ipi_mask		= bmips5000_send_ipi_mask,
#ifdef CONFIG_HOTPLUG_CPU
	.cpu_disable		= bmips_cpu_disable,
	.cpu_die		= bmips_cpu_die,
#endif
};

#endif /* CONFIG_SMP */

/***********************************************************************
 * BMIPS vector relocation
 * This is primarily used for SMP boot, but it is applicable to some
 * UP BMIPS systems as well.
 ***********************************************************************/

static void bmips_wr_vec(unsigned long dst, char *start, char *end)
{
	memcpy((void *)dst, start, end - start);
	dma_cache_wback(dst, end - start);
	local_flush_icache_range(dst, dst + (end - start));
	instruction_hazard();
}

static inline void bmips_nmi_handler_setup(void)
{
	bmips_wr_vec(BMIPS_NMI_RESET_VEC, &bmips_reset_nmi_vec,
		&bmips_reset_nmi_vec_end);
	bmips_wr_vec(BMIPS_WARM_RESTART_VEC, &bmips_smp_int_vec,
		&bmips_smp_int_vec_end);
}

struct reset_vec_info {
	int cpu;
	u32 val;
};

static void bmips_set_reset_vec_remote(void *vinfo)
{
	struct reset_vec_info *info = vinfo;
	int shift = info->cpu & 0x01 ? 16 : 0;
	u32 mask = ~(0xffff << shift), val = info->val >> 16;

	preempt_disable();
	if (smp_processor_id() > 0) {
		smp_call_function_single(0, &bmips_set_reset_vec_remote,
					 info, 1);
	} else {
		if (info->cpu & 0x02) {
			/* BMIPS5200 "should" use mask/shift, but it's buggy */
			bmips_write_zscm_reg(0xa0, (val << 16) | val);
			bmips_read_zscm_reg(0xa0);
		} else {
			write_c0_brcm_bootvec((read_c0_brcm_bootvec() & mask) |
					      (val << shift));
		}
	}
	preempt_enable();
}

static void bmips_set_reset_vec(int cpu, u32 val)
{
	struct reset_vec_info info;

	if (current_cpu_type() == CPU_BMIPS5000) {
		/* this needs to run from CPU0 (which is always online) */
		info.cpu = cpu;
		info.val = val;
		bmips_set_reset_vec_remote(&info);
	} else {
		void __iomem *cbr = BMIPS_GET_CBR();

		if (cpu == 0)
			__raw_writel(val, cbr + BMIPS_RELO_VECTOR_CONTROL_0);
		else {
			if (current_cpu_type() != CPU_BMIPS4380)
				return;
			__raw_writel(val, cbr + BMIPS_RELO_VECTOR_CONTROL_1);
		}
	}
	__sync();
	back_to_back_c0_hazard();
}

void bmips_ebase_setup(void)
{
	unsigned long new_ebase = ebase;

	BUG_ON(ebase != CKSEG0);

	switch (current_cpu_type()) {
	case CPU_BMIPS4350:
		/*
		 * BMIPS4350 cannot relocate the normal vectors, but it
		 * can relocate the BEV=1 vectors.  So CPU1 starts up at
		 * the relocated BEV=1, IV=0 general exception vector @
		 * 0xa000_0380.
		 *
		 * set_uncached_handler() is used here because:
		 *  - CPU1 will run this from uncached space
		 *  - None of the cacheflush functions are set up yet
		 */
		set_uncached_handler(BMIPS_WARM_RESTART_VEC - CKSEG0,
			&bmips_smp_int_vec, 0x80);
		__sync();
		return;
	case CPU_BMIPS3300:
	case CPU_BMIPS4380:
		/*
		 * 0x8000_0000: reset/NMI (initially in kseg1)
		 * 0x8000_0400: normal vectors
		 */
		new_ebase = 0x80000400;
		bmips_set_reset_vec(0, RESET_FROM_KSEG0);
		break;
	case CPU_BMIPS5000:
		/*
		 * 0x8000_0000: reset/NMI (initially in kseg1)
		 * 0x8000_1000: normal vectors
		 */
		new_ebase = 0x80001000;
		bmips_set_reset_vec(0, RESET_FROM_KSEG0);
		write_c0_ebase(new_ebase);
		break;
	default:
		return;
	}

	board_nmi_handler_setup = &bmips_nmi_handler_setup;
	ebase = new_ebase;
}

asmlinkage void __weak plat_wired_tlb_setup(void)
{
	/*
	 * Called when starting/restarting a secondary CPU.
	 * Kernel stacks and other important data might only be accessible
	 * once the wired entries are present.
	 */
}

void __init bmips_cpu_setup(void)
{
	void __iomem __maybe_unused *cbr = BMIPS_GET_CBR();
	u32 __maybe_unused cfg;

	switch (current_cpu_type()) {
	case CPU_BMIPS3300:
		/* Set BIU to async mode */
		set_c0_brcm_bus_pll(BIT(22));
		__sync();

		/* put the BIU back in sync mode */
		clear_c0_brcm_bus_pll(BIT(22));

		/* clear BHTD to enable branch history table */
		clear_c0_brcm_reset(BIT(16));

		/* Flush and enable RAC */
		cfg = __raw_readl(cbr + BMIPS_RAC_CONFIG);
		__raw_writel(cfg | 0x100, BMIPS_RAC_CONFIG);
		__raw_readl(cbr + BMIPS_RAC_CONFIG);

		cfg = __raw_readl(cbr + BMIPS_RAC_CONFIG);
		__raw_writel(cfg | 0xf, BMIPS_RAC_CONFIG);
		__raw_readl(cbr + BMIPS_RAC_CONFIG);

		cfg = __raw_readl(cbr + BMIPS_RAC_ADDRESS_RANGE);
		__raw_writel(cfg | 0x0fff0000, cbr + BMIPS_RAC_ADDRESS_RANGE);
		__raw_readl(cbr + BMIPS_RAC_ADDRESS_RANGE);
		break;

	case CPU_BMIPS4380:
		/* CBG workaround for early BMIPS4380 CPUs */
		switch (read_c0_prid()) {
		case 0x2a040:
		case 0x2a042:
		case 0x2a044:
		case 0x2a060:
			cfg = __raw_readl(cbr + BMIPS_L2_CONFIG);
			__raw_writel(cfg & ~0x07000000, cbr + BMIPS_L2_CONFIG);
			__raw_readl(cbr + BMIPS_L2_CONFIG);
		}

		/* clear BHTD to enable branch history table */
		clear_c0_brcm_config_0(BIT(21));

		/* XI/ROTR enable */
		set_c0_brcm_config_0(BIT(23));
		set_c0_brcm_cmt_ctrl(BIT(15));
		break;

	case CPU_BMIPS5000:
		/* enable RDHWR, BRDHWR */
		set_c0_brcm_config(BIT(17) | BIT(21));

		/* Disable JTB */
		__asm__ __volatile__(
		"	.set	noreorder\n"
		"	li	$8, 0x5a455048\n"
		"	.word	0x4088b00f\n"	/* mtc0	t0, $22, 15 */
		"	.word	0x4008b008\n"	/* mfc0	t0, $22, 8 */
		"	li	$9, 0x00008000\n"
		"	or	$8, $8, $9\n"
		"	.word	0x4088b008\n"	/* mtc0	t0, $22, 8 */
		"	sync\n"
		"	li	$8, 0x0\n"
		"	.word	0x4088b00f\n"	/* mtc0	t0, $22, 15 */
		"	.set	reorder\n"
		: : : "$8", "$9");

		/* XI enable */
		set_c0_brcm_config(BIT(27));

		/* enable MIPS32R2 ROR instruction for XI TLB handlers */
		__asm__ __volatile__(
		"	li	$8, 0x5a455048\n"
		"	.word	0x4088b00f\n"	/* mtc0 $8, $22, 15 */
		"	nop; nop; nop\n"
		"	.word	0x4008b008\n"	/* mfc0 $8, $22, 8 */
		"	lui	$9, 0x0100\n"
		"	or	$8, $9\n"
		"	.word	0x4088b008\n"	/* mtc0 $8, $22, 8 */
		: : : "$8", "$9");
		break;
	}
}
Commit	Line	Data
df0ac8a4 KC	1	/*
	2	* This file is subject to the terms and conditions of the GNU General Public
	3	* License. See the file "COPYING" in the main directory of this archive
	4	* for more details.
	5	*
	6	* Copyright (C) 2011 by Kevin Cernekee (cernekee@gmail.com)
	7	*
	8	* SMP support for BMIPS
	9	*/
	10
df0ac8a4 KC	11	#include <linux/init.h>
df0ac8a4 KC	12	#include <linux/sched.h>
ef8bd77f	13	#include <linux/sched/hotplug.h>
fc69910f	14	#include <linux/sched/task_stack.h>
df0ac8a4 KC	15	#include <linux/mm.h>
	16	#include <linux/delay.h>
	17	#include <linux/smp.h>
	18	#include <linux/interrupt.h>
	19	#include <linux/spinlock.h>
df0ac8a4 KC	20	#include <linux/cpu.h>
	21	#include <linux/cpumask.h>
	22	#include <linux/reboot.h>
	23	#include <linux/io.h>
	24	#include <linux/compiler.h>
	25	#include <linux/linkage.h>
	26	#include <linux/bug.h>
	27	#include <linux/kernel.h>
	28
	29	#include <asm/time.h>
	30	#include <asm/pgtable.h>
	31	#include <asm/processor.h>
df0ac8a4 KC	32	#include <asm/bootinfo.h>
	33	#include <asm/pmon.h>
	34	#include <asm/cacheflush.h>
	35	#include <asm/tlbflush.h>
	36	#include <asm/mipsregs.h>
	37	#include <asm/bmips.h>
	38	#include <asm/traps.h>
	39	#include <asm/barrier.h>
fc455787	40	#include <asm/cpu-features.h>
df0ac8a4 KC	41
	42	static int __maybe_unused max_cpus = 1;
	43
	44	/* these may be configured by the platform code */
	45	int bmips_smp_enabled = 1;
	46	int bmips_cpu_offset;
	47	cpumask_t bmips_booted_mask;
d8010ceb	48	unsigned long bmips_tp1_irqs = IE_IRQ1;
df0ac8a4	49
fc455787 KC	50	#define RESET_FROM_KSEG0 0x80080800
	51	#define RESET_FROM_KSEG1 0xa0080800
	52
3677a283 KC	53	static void bmips_set_reset_vec(int cpu, u32 val);
3677a283 KC	54
df0ac8a4 KC	55	#ifdef CONFIG_SMP
	56
	57	/* initial $sp, $gp - used by arch/mips/kernel/bmips_vec.S */
	58	unsigned long bmips_smp_boot_sp;
	59	unsigned long bmips_smp_boot_gp;
	60
6465460c JG	61	static void bmips43xx_send_ipi_single(int cpu, unsigned int action);
	62	static void bmips5000_send_ipi_single(int cpu, unsigned int action);
	63	static irqreturn_t bmips43xx_ipi_interrupt(int irq, void *dev_id);
	64	static irqreturn_t bmips5000_ipi_interrupt(int irq, void *dev_id);
df0ac8a4 KC	65
	66	/* SW interrupts 0,1 are used for interprocessor signaling */
	67	#define IPI0_IRQ (MIPS_CPU_IRQ_BASE + 0)
	68	#define IPI1_IRQ (MIPS_CPU_IRQ_BASE + 1)
	69
	70	#define CPUNUM(cpu, shift) (((cpu) + bmips_cpu_offset) << (shift))
	71	#define ACTION_CLR_IPI(cpu, ipi) (0x2000 \| CPUNUM(cpu, 9) \| ((ipi) << 8))
	72	#define ACTION_SET_IPI(cpu, ipi) (0x3000 \| CPUNUM(cpu, 9) \| ((ipi) << 8))
	73	#define ACTION_BOOT_THREAD(cpu) (0x08 \| CPUNUM(cpu, 0))
	74
	75	static void __init bmips_smp_setup(void)
	76	{
4df715aa	77	int i, cpu = 1, boot_cpu = 0;
fcfa66de FF	78	int cpu_hw_intr;
fcfa66de FF	79
6465460c JG	80	switch (current_cpu_type()) {
	81	case CPU_BMIPS4350:
	82	case CPU_BMIPS4380:
	83	/* arbitration priority */
	84	clear_c0_brcm_cmt_ctrl(0x30);
	85
	86	/* NBK and weak order flags */
	87	set_c0_brcm_config_0(0x30000);
	88
	89	/* Find out if we are running on TP0 or TP1 */
	90	boot_cpu = !!(read_c0_brcm_cmt_local() & (1 << 31));
	91
	92	/*
	93	* MIPS interrupts 0,1 (SW INT 0,1) cross over to the other
	94	* thread
	95	* MIPS interrupt 2 (HW INT 0) is the CPU0 L1 controller output
	96	* MIPS interrupt 3 (HW INT 1) is the CPU1 L1 controller output
	97	*/
	98	if (boot_cpu == 0)
	99	cpu_hw_intr = 0x02;
	100	else
	101	cpu_hw_intr = 0x1d;
	102
	103	change_c0_brcm_cmt_intr(0xf8018000,
	104	(cpu_hw_intr << 27) \| (0x03 << 15));
	105
	106	/* single core, 2 threads (2 pipelines) */
	107	max_cpus = 2;
	108
	109	break;
	110	case CPU_BMIPS5000:
	111	/* enable raceless SW interrupts */
	112	set_c0_brcm_config(0x03 << 22);
	113
	114	/* route HW interrupt 0 to CPU0, HW interrupt 1 to CPU1 */
	115	change_c0_brcm_mode(0x1f << 27, 0x02 << 27);
	116
	117	/* N cores, 2 threads per core */
	118	max_cpus = (((read_c0_brcm_config() >> 6) & 0x03) + 1) << 1;
	119
	120	/* clear any pending SW interrupts */
	121	for (i = 0; i < max_cpus; i++) {
	122	write_c0_brcm_action(ACTION_CLR_IPI(i, 0));
	123	write_c0_brcm_action(ACTION_CLR_IPI(i, 1));
	124	}
df0ac8a4	125
6465460c JG	126	break;
	127	default:
	128	max_cpus = 1;
df0ac8a4	129	}
df0ac8a4 KC	130
	131	if (!bmips_smp_enabled)
	132	max_cpus = 1;
	133
	134	/* this can be overridden by the BSP */
	135	if (!board_ebase_setup)
	136	board_ebase_setup = &bmips_ebase_setup;
	137
4df715aa FF	138	__cpu_number_map[boot_cpu] = 0;
	139	__cpu_logical_map[0] = boot_cpu;
	140
df0ac8a4	141	for (i = 0; i < max_cpus; i++) {
4df715aa FF	142	if (i != boot_cpu) {
	143	__cpu_number_map[i] = cpu;
	144	__cpu_logical_map[cpu] = i;
	145	cpu++;
	146	}
df0ac8a4 KC	147	set_cpu_possible(i, 1);
	148	set_cpu_present(i, 1);
	149	}
	150	}
	151
	152	/*
	153	* IPI IRQ setup - runs on CPU0
	154	*/
	155	static void bmips_prepare_cpus(unsigned int max_cpus)
	156	{
6465460c JG	157	irqreturn_t (bmips_ipi_interrupt)(int irq, void dev_id);
	158
	159	switch (current_cpu_type()) {
	160	case CPU_BMIPS4350:
	161	case CPU_BMIPS4380:
	162	bmips_ipi_interrupt = bmips43xx_ipi_interrupt;
	163	break;
	164	case CPU_BMIPS5000:
	165	bmips_ipi_interrupt = bmips5000_ipi_interrupt;
	166	break;
	167	default:
	168	return;
	169	}
	170
df0ac8a4 KC	171	if (request_irq(IPI0_IRQ, bmips_ipi_interrupt, IRQF_PERCPU,
df0ac8a4 KC	172	"smp_ipi0", NULL))
f7777dcc	173	panic("Can't request IPI0 interrupt");
df0ac8a4 KC	174	if (request_irq(IPI1_IRQ, bmips_ipi_interrupt, IRQF_PERCPU,
df0ac8a4 KC	175	"smp_ipi1", NULL))
f7777dcc	176	panic("Can't request IPI1 interrupt");
df0ac8a4 KC	177	}
	178
	179	/*
	180	* Tell the hardware to boot CPUx - runs on CPU0
	181	*/
	182	static void bmips_boot_secondary(int cpu, struct task_struct *idle)
	183	{
	184	bmips_smp_boot_sp = __KSTK_TOS(idle);
	185	bmips_smp_boot_gp = (unsigned long)task_thread_info(idle);
	186	mb();
	187
	188	/*
	189	* Initial boot sequence for secondary CPU:
	190	* bmips_reset_nmi_vec @ a000_0000 ->
	191	* bmips_smp_entry ->
	192	* plat_wired_tlb_setup (cached function call; optional) ->
	193	* start_secondary (cached jump)
	194	*
	195	* Warm restart sequence:
	196	* play_dead WAIT loop ->
	197	* bmips_smp_int_vec @ BMIPS_WARM_RESTART_VEC ->
	198	* eret to play_dead ->
	199	* bmips_secondary_reentry ->
	200	* start_secondary
	201	*/
	202
	203	pr_info("SMP: Booting CPU%d...\n", cpu);
	204
6465460c	205	if (cpumask_test_cpu(cpu, &bmips_booted_mask)) {
3677a283 KC	206	/* kseg1 might not exist if this CPU enabled XKS01 */
	207	bmips_set_reset_vec(cpu, RESET_FROM_KSEG0);
	208
6465460c JG	209	switch (current_cpu_type()) {
	210	case CPU_BMIPS4350:
	211	case CPU_BMIPS4380:
	212	bmips43xx_send_ipi_single(cpu, 0);
	213	break;
	214	case CPU_BMIPS5000:
	215	bmips5000_send_ipi_single(cpu, 0);
	216	break;
	217	}
3677a283 KC	218	} else {
	219	bmips_set_reset_vec(cpu, RESET_FROM_KSEG1);
	220
6465460c JG	221	switch (current_cpu_type()) {
	222	case CPU_BMIPS4350:
	223	case CPU_BMIPS4380:
	224	/* Reset slave TP1 if booting from TP0 */
	225	if (cpu_logical_map(cpu) == 1)
	226	set_c0_brcm_cmt_ctrl(0x01);
	227	break;
	228	case CPU_BMIPS5000:
bdb2e05c	229	write_c0_brcm_action(ACTION_BOOT_THREAD(cpu));
6465460c	230	break;
df0ac8a4	231	}
df0ac8a4 KC	232	cpumask_set_cpu(cpu, &bmips_booted_mask);
	233	}
	234	}
	235
	236	/*
	237	* Early setup - runs on secondary CPU after cache probe
	238	*/
	239	static void bmips_init_secondary(void)
	240	{
6465460c JG	241	switch (current_cpu_type()) {
	242	case CPU_BMIPS4350:
	243	case CPU_BMIPS4380:
6465460c JG	244	clear_c0_cause(smp_processor_id() ? C_SW1 : C_SW0);
	245	break;
	246	case CPU_BMIPS5000:
6465460c	247	write_c0_brcm_action(ACTION_CLR_IPI(smp_processor_id(), 0));
f6cc0ee9	248	current_cpu_data.core = (read_c0_brcm_config() >> 25) & 3;
6465460c JG	249	break;
6465460c JG	250	}
df0ac8a4 KC	251	}
	252
	253	/*
	254	* Late setup - runs on secondary CPU before entering the idle loop
	255	*/
	256	static void bmips_smp_finish(void)
	257	{
	258	pr_info("SMP: CPU%d is running\n", smp_processor_id());
856ac3c6 YZ	259
	260	/* make sure there won't be a timer interrupt for a little while */
	261	write_c0_compare(read_c0_count() + mips_hpt_frequency / HZ);
	262
	263	irq_enable_hazard();
d8010ceb	264	set_c0_status(IE_SW0 \| IE_SW1 \| bmips_tp1_irqs \| IE_IRQ5 \| ST0_IE);
856ac3c6	265	irq_enable_hazard();
df0ac8a4 KC	266	}
df0ac8a4 KC	267
df0ac8a4 KC	268	/*
	269	* BMIPS5000 raceless IPIs
	270	*
	271	* Each CPU has two inbound SW IRQs which are independent of all other CPUs.
	272	* IPI0 is used for SMP_RESCHEDULE_YOURSELF
	273	* IPI1 is used for SMP_CALL_FUNCTION
	274	*/
	275
6465460c	276	static void bmips5000_send_ipi_single(int cpu, unsigned int action)
df0ac8a4 KC	277	{
	278	write_c0_brcm_action(ACTION_SET_IPI(cpu, action == SMP_CALL_FUNCTION));
	279	}
	280
6465460c	281	static irqreturn_t bmips5000_ipi_interrupt(int irq, void *dev_id)
df0ac8a4 KC	282	{
	283	int action = irq - IPI0_IRQ;
	284
	285	write_c0_brcm_action(ACTION_CLR_IPI(smp_processor_id(), action));
	286
	287	if (action == 0)
	288	scheduler_ipi();
	289	else
4ace6139	290	generic_smp_call_function_interrupt();
df0ac8a4 KC	291
	292	return IRQ_HANDLED;
	293	}
	294
6465460c JG	295	static void bmips5000_send_ipi_mask(const struct cpumask *mask,
	296	unsigned int action)
	297	{
	298	unsigned int i;
	299
	300	for_each_cpu(i, mask)
	301	bmips5000_send_ipi_single(i, action);
	302	}
df0ac8a4 KC	303
	304	/*
	305	* BMIPS43xx racey IPIs
	306	*
	307	* We use one inbound SW IRQ for each CPU.
	308	*
	309	* A spinlock must be held in order to keep CPUx from accidentally clearing
	310	* an incoming IPI when it writes CP0 CAUSE to raise an IPI on CPUy. The
	311	* same spinlock is used to protect the action masks.
	312	*/
	313
	314	static DEFINE_SPINLOCK(ipi_lock);
	315	static DEFINE_PER_CPU(int, ipi_action_mask);
	316
6465460c	317	static void bmips43xx_send_ipi_single(int cpu, unsigned int action)
df0ac8a4 KC	318	{
	319	unsigned long flags;
	320
	321	spin_lock_irqsave(&ipi_lock, flags);
	322	set_c0_cause(cpu ? C_SW1 : C_SW0);
	323	per_cpu(ipi_action_mask, cpu) \|= action;
	324	irq_enable_hazard();
	325	spin_unlock_irqrestore(&ipi_lock, flags);
	326	}
	327
6465460c	328	static irqreturn_t bmips43xx_ipi_interrupt(int irq, void *dev_id)
df0ac8a4 KC	329	{
	330	unsigned long flags;
	331	int action, cpu = irq - IPI0_IRQ;
	332
	333	spin_lock_irqsave(&ipi_lock, flags);
35898716	334	action = __this_cpu_read(ipi_action_mask);
df0ac8a4 KC	335	per_cpu(ipi_action_mask, cpu) = 0;
	336	clear_c0_cause(cpu ? C_SW1 : C_SW0);
	337	spin_unlock_irqrestore(&ipi_lock, flags);
	338
	339	if (action & SMP_RESCHEDULE_YOURSELF)
	340	scheduler_ipi();
	341	if (action & SMP_CALL_FUNCTION)
4ace6139	342	generic_smp_call_function_interrupt();
df0ac8a4 KC	343
	344	return IRQ_HANDLED;
	345	}
	346
6465460c	347	static void bmips43xx_send_ipi_mask(const struct cpumask *mask,
df0ac8a4 KC	348	unsigned int action)
	349	{
	350	unsigned int i;
	351
	352	for_each_cpu(i, mask)
6465460c	353	bmips43xx_send_ipi_single(i, action);
df0ac8a4 KC	354	}
	355
	356	#ifdef CONFIG_HOTPLUG_CPU
	357
	358	static int bmips_cpu_disable(void)
	359	{
	360	unsigned int cpu = smp_processor_id();
	361
	362	if (cpu == 0)
	363	return -EBUSY;
	364
	365	pr_info("SMP: CPU%d is offline\n", cpu);
	366
0b5f9c00	367	set_cpu_online(cpu, false);
826e99be	368	calculate_cpu_foreign_map();
51ad4ace	369	irq_cpu_offline();
230b6ff5	370	clear_c0_status(IE_IRQ5);
df0ac8a4 KC	371
	372	local_flush_tlb_all();
	373	local_flush_icache_range(0, ~0);
	374
	375	return 0;
	376	}
	377
	378	static void bmips_cpu_die(unsigned int cpu)
	379	{
	380	}
	381
	382	void __ref play_dead(void)
	383	{
	384	idle_task_exit();
	385
	386	/* flush data cache */
	387	_dma_cache_wback_inv(0, ~0);
	388
	389	/*
	390	* Wakeup is on SW0 or SW1; disable everything else
	391	* Use BEV !IV (BMIPS_WARM_RESTART_VEC) to avoid the regular Linux
	392	* IRQ handlers; this clears ST0_IE and returns immediately.
	393	*/
	394	clear_c0_cause(CAUSEF_IV \| C_SW0 \| C_SW1);
d8010ceb KC	395	change_c0_status(
d8010ceb KC	396	IE_IRQ5 \| bmips_tp1_irqs \| IE_SW0 \| IE_SW1 \| ST0_IE \| ST0_BEV,
df0ac8a4 KC	397	IE_SW0 \| IE_SW1 \| ST0_IE \| ST0_BEV);
	398	irq_disable_hazard();
	399
	400	/*
	401	* wait for SW interrupt from bmips_boot_secondary(), then jump
	402	* back to start_secondary()
	403	*/
	404	__asm__ __volatile__(
	405	" wait\n"
	406	" j bmips_secondary_reentry\n"
	407	: : : "memory");
	408	}
	409
	410	#endif /* CONFIG_HOTPLUG_CPU */
	411
6465460c JG	412	struct plat_smp_ops bmips43xx_smp_ops = {
	413	.smp_setup = bmips_smp_setup,
	414	.prepare_cpus = bmips_prepare_cpus,
	415	.boot_secondary = bmips_boot_secondary,
	416	.smp_finish = bmips_smp_finish,
	417	.init_secondary = bmips_init_secondary,
6465460c JG	418	.send_ipi_single = bmips43xx_send_ipi_single,
	419	.send_ipi_mask = bmips43xx_send_ipi_mask,
	420	#ifdef CONFIG_HOTPLUG_CPU
	421	.cpu_disable = bmips_cpu_disable,
	422	.cpu_die = bmips_cpu_die,
	423	#endif
	424	};
	425
	426	struct plat_smp_ops bmips5000_smp_ops = {
df0ac8a4 KC	427	.smp_setup = bmips_smp_setup,
	428	.prepare_cpus = bmips_prepare_cpus,
	429	.boot_secondary = bmips_boot_secondary,
	430	.smp_finish = bmips_smp_finish,
	431	.init_secondary = bmips_init_secondary,
6465460c JG	432	.send_ipi_single = bmips5000_send_ipi_single,
6465460c JG	433	.send_ipi_mask = bmips5000_send_ipi_mask,
df0ac8a4 KC	434	#ifdef CONFIG_HOTPLUG_CPU
	435	.cpu_disable = bmips_cpu_disable,
	436	.cpu_die = bmips_cpu_die,
	437	#endif
	438	};
	439
	440	#endif /* CONFIG_SMP */
	441
	442	/***********************************************************************
	443	* BMIPS vector relocation
	444	* This is primarily used for SMP boot, but it is applicable to some
	445	* UP BMIPS systems as well.
	446	***********************************************************************/
	447
078a55fc	448	static void bmips_wr_vec(unsigned long dst, char start, char end)
df0ac8a4 KC	449	{
df0ac8a4 KC	450	memcpy((void *)dst, start, end - start);
57b41758	451	dma_cache_wback(dst, end - start);
df0ac8a4 KC	452	local_flush_icache_range(dst, dst + (end - start));
	453	instruction_hazard();
	454	}
	455
078a55fc	456	static inline void bmips_nmi_handler_setup(void)
df0ac8a4 KC	457	{
	458	bmips_wr_vec(BMIPS_NMI_RESET_VEC, &bmips_reset_nmi_vec,
	459	&bmips_reset_nmi_vec_end);
	460	bmips_wr_vec(BMIPS_WARM_RESTART_VEC, &bmips_smp_int_vec,
	461	&bmips_smp_int_vec_end);
	462	}
	463
fc455787 KC	464	struct reset_vec_info {
	465	int cpu;
	466	u32 val;
	467	};
	468
	469	static void bmips_set_reset_vec_remote(void *vinfo)
	470	{
	471	struct reset_vec_info *info = vinfo;
	472	int shift = info->cpu & 0x01 ? 16 : 0;
	473	u32 mask = ~(0xffff << shift), val = info->val >> 16;
	474
	475	preempt_disable();
	476	if (smp_processor_id() > 0) {
	477	smp_call_function_single(0, &bmips_set_reset_vec_remote,
	478	info, 1);
	479	} else {
	480	if (info->cpu & 0x02) {
	481	/* BMIPS5200 "should" use mask/shift, but it's buggy */
	482	bmips_write_zscm_reg(0xa0, (val << 16) \| val);
	483	bmips_read_zscm_reg(0xa0);
	484	} else {
	485	write_c0_brcm_bootvec((read_c0_brcm_bootvec() & mask) \|
	486	(val << shift));
	487	}
	488	}
	489	preempt_enable();
	490	}
	491
	492	static void bmips_set_reset_vec(int cpu, u32 val)
	493	{
	494	struct reset_vec_info info;
	495
	496	if (current_cpu_type() == CPU_BMIPS5000) {
	497	/* this needs to run from CPU0 (which is always online) */
	498	info.cpu = cpu;
	499	info.val = val;
	500	bmips_set_reset_vec_remote(&info);
	501	} else {
	502	void __iomem *cbr = BMIPS_GET_CBR();
	503
	504	if (cpu == 0)
	505	__raw_writel(val, cbr + BMIPS_RELO_VECTOR_CONTROL_0);
	506	else {
	507	if (current_cpu_type() != CPU_BMIPS4380)
	508	return;
	509	__raw_writel(val, cbr + BMIPS_RELO_VECTOR_CONTROL_1);
	510	}
	511	}
	512	__sync();
	513	back_to_back_c0_hazard();
	514	}
	515
078a55fc	516	void bmips_ebase_setup(void)
df0ac8a4 KC	517	{
df0ac8a4 KC	518	unsigned long new_ebase = ebase;
df0ac8a4 KC	519
	520	BUG_ON(ebase != CKSEG0);
	521
6465460c JG	522	switch (current_cpu_type()) {
	523	case CPU_BMIPS4350:
	524	/*
	525	* BMIPS4350 cannot relocate the normal vectors, but it
	526	* can relocate the BEV=1 vectors. So CPU1 starts up at
	527	* the relocated BEV=1, IV=0 general exception vector @
	528	* 0xa000_0380.
	529	*
	530	* set_uncached_handler() is used here because:
	531	* - CPU1 will run this from uncached space
	532	* - None of the cacheflush functions are set up yet
	533	*/
	534	set_uncached_handler(BMIPS_WARM_RESTART_VEC - CKSEG0,
	535	&bmips_smp_int_vec, 0x80);
	536	__sync();
	537	return;
fa010672	538	case CPU_BMIPS3300:
6465460c JG	539	case CPU_BMIPS4380:
	540	/*
	541	* 0x8000_0000: reset/NMI (initially in kseg1)
	542	* 0x8000_0400: normal vectors
	543	*/
	544	new_ebase = 0x80000400;
fc455787	545	bmips_set_reset_vec(0, RESET_FROM_KSEG0);
6465460c JG	546	break;
	547	case CPU_BMIPS5000:
	548	/*
	549	* 0x8000_0000: reset/NMI (initially in kseg1)
	550	* 0x8000_1000: normal vectors
	551	*/
	552	new_ebase = 0x80001000;
fc455787	553	bmips_set_reset_vec(0, RESET_FROM_KSEG0);
6465460c	554	write_c0_ebase(new_ebase);
6465460c JG	555	break;
	556	default:
	557	return;
	558	}
	559
df0ac8a4 KC	560	board_nmi_handler_setup = &bmips_nmi_handler_setup;
	561	ebase = new_ebase;
	562	}
	563
	564	asmlinkage void __weak plat_wired_tlb_setup(void)
	565	{
	566	/*
	567	* Called when starting/restarting a secondary CPU.
	568	* Kernel stacks and other important data might only be accessible
	569	* once the wired entries are present.
	570	*/
	571	}
738a3f79 FF	572
	573	void __init bmips_cpu_setup(void)
	574	{
	575	void __iomem __maybe_unused *cbr = BMIPS_GET_CBR();
	576	u32 __maybe_unused cfg;
	577
	578	switch (current_cpu_type()) {
	579	case CPU_BMIPS3300:
	580	/* Set BIU to async mode */
	581	set_c0_brcm_bus_pll(BIT(22));
	582	__sync();
	583
	584	/* put the BIU back in sync mode */
	585	clear_c0_brcm_bus_pll(BIT(22));
	586
	587	/* clear BHTD to enable branch history table */
	588	clear_c0_brcm_reset(BIT(16));
	589
	590	/* Flush and enable RAC */
	591	cfg = __raw_readl(cbr + BMIPS_RAC_CONFIG);
	592	__raw_writel(cfg \| 0x100, BMIPS_RAC_CONFIG);
	593	__raw_readl(cbr + BMIPS_RAC_CONFIG);
	594
	595	cfg = __raw_readl(cbr + BMIPS_RAC_CONFIG);
	596	__raw_writel(cfg \| 0xf, BMIPS_RAC_CONFIG);
	597	__raw_readl(cbr + BMIPS_RAC_CONFIG);
	598
	599	cfg = __raw_readl(cbr + BMIPS_RAC_ADDRESS_RANGE);
	600	__raw_writel(cfg \| 0x0fff0000, cbr + BMIPS_RAC_ADDRESS_RANGE);
	601	__raw_readl(cbr + BMIPS_RAC_ADDRESS_RANGE);
	602	break;
	603
	604	case CPU_BMIPS4380:
	605	/* CBG workaround for early BMIPS4380 CPUs */
	606	switch (read_c0_prid()) {
	607	case 0x2a040:
	608	case 0x2a042:
	609	case 0x2a044:
	610	case 0x2a060:
	611	cfg = __raw_readl(cbr + BMIPS_L2_CONFIG);
	612	__raw_writel(cfg & ~0x07000000, cbr + BMIPS_L2_CONFIG);
	613	__raw_readl(cbr + BMIPS_L2_CONFIG);
	614	}
	615
	616	/* clear BHTD to enable branch history table */
	617	clear_c0_brcm_config_0(BIT(21));
	618
	619	/* XI/ROTR enable */
	620	set_c0_brcm_config_0(BIT(23));
	621	set_c0_brcm_cmt_ctrl(BIT(15));
	622	break;
	623
	624	case CPU_BMIPS5000:
	625	/* enable RDHWR, BRDHWR */
	626	set_c0_brcm_config(BIT(17) \| BIT(21));
	627
	628	/* Disable JTB */
	629	__asm__ __volatile__(
	630	" .set noreorder\n"
	631	" li $8, 0x5a455048\n"
	632	" .word 0x4088b00f\n" /* mtc0 t0, $22, 15 */
	633	" .word 0x4008b008\n" /* mfc0 t0, $22, 8 */
	634	" li $9, 0x00008000\n"
	635	" or $8, $8, $9\n"
636	" .word 0x4088b008\n" /* mtc0 t0, $22, 8 */
637	" sync\n"
638	" li $8, 0x0\n"
639	" .word 0x4088b00f\n" /* mtc0 t0, $22, 15 */
640	" .set reorder\n"
641	: : : "$8", "$9");
642
643	/* XI enable */
644	set_c0_brcm_config(BIT(27));
645
646	/* enable MIPS32R2 ROR instruction for XI TLB handlers */
647	__asm__ __volatile__(
648	" li $8, 0x5a455048\n"
649	" .word 0x4088b00f\n" /* mtc0 $8, $22, 15 */
650	" nop; nop; nop\n"
651	" .word 0x4008b008\n" /* mfc0 $8, $22, 8 */
652	" lui $9, 0x0100\n"
653	" or $8, $9\n"
654	" .word 0x4088b008\n" /* mtc0 $8, $22, 8 */
655	: : : "$8", "$9");
656	break;
657	}
658	}