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df0ac8a4 KC |
1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public | |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
6 | * Copyright (C) 2011 by Kevin Cernekee (cernekee@gmail.com) | |
7 | * | |
8 | * SMP support for BMIPS | |
9 | */ | |
10 | ||
df0ac8a4 KC |
11 | #include <linux/init.h> |
12 | #include <linux/sched.h> | |
13 | #include <linux/mm.h> | |
14 | #include <linux/delay.h> | |
15 | #include <linux/smp.h> | |
16 | #include <linux/interrupt.h> | |
17 | #include <linux/spinlock.h> | |
df0ac8a4 KC |
18 | #include <linux/cpu.h> |
19 | #include <linux/cpumask.h> | |
20 | #include <linux/reboot.h> | |
21 | #include <linux/io.h> | |
22 | #include <linux/compiler.h> | |
23 | #include <linux/linkage.h> | |
24 | #include <linux/bug.h> | |
25 | #include <linux/kernel.h> | |
26 | ||
27 | #include <asm/time.h> | |
28 | #include <asm/pgtable.h> | |
29 | #include <asm/processor.h> | |
df0ac8a4 KC |
30 | #include <asm/bootinfo.h> |
31 | #include <asm/pmon.h> | |
32 | #include <asm/cacheflush.h> | |
33 | #include <asm/tlbflush.h> | |
34 | #include <asm/mipsregs.h> | |
35 | #include <asm/bmips.h> | |
36 | #include <asm/traps.h> | |
37 | #include <asm/barrier.h> | |
fc455787 | 38 | #include <asm/cpu-features.h> |
df0ac8a4 KC |
39 | |
40 | static int __maybe_unused max_cpus = 1; | |
41 | ||
42 | /* these may be configured by the platform code */ | |
43 | int bmips_smp_enabled = 1; | |
44 | int bmips_cpu_offset; | |
45 | cpumask_t bmips_booted_mask; | |
d8010ceb | 46 | unsigned long bmips_tp1_irqs = IE_IRQ1; |
df0ac8a4 | 47 | |
fc455787 KC |
48 | #define RESET_FROM_KSEG0 0x80080800 |
49 | #define RESET_FROM_KSEG1 0xa0080800 | |
50 | ||
3677a283 KC |
51 | static void bmips_set_reset_vec(int cpu, u32 val); |
52 | ||
df0ac8a4 KC |
53 | #ifdef CONFIG_SMP |
54 | ||
55 | /* initial $sp, $gp - used by arch/mips/kernel/bmips_vec.S */ | |
56 | unsigned long bmips_smp_boot_sp; | |
57 | unsigned long bmips_smp_boot_gp; | |
58 | ||
6465460c JG |
59 | static void bmips43xx_send_ipi_single(int cpu, unsigned int action); |
60 | static void bmips5000_send_ipi_single(int cpu, unsigned int action); | |
61 | static irqreturn_t bmips43xx_ipi_interrupt(int irq, void *dev_id); | |
62 | static irqreturn_t bmips5000_ipi_interrupt(int irq, void *dev_id); | |
df0ac8a4 KC |
63 | |
64 | /* SW interrupts 0,1 are used for interprocessor signaling */ | |
65 | #define IPI0_IRQ (MIPS_CPU_IRQ_BASE + 0) | |
66 | #define IPI1_IRQ (MIPS_CPU_IRQ_BASE + 1) | |
67 | ||
68 | #define CPUNUM(cpu, shift) (((cpu) + bmips_cpu_offset) << (shift)) | |
69 | #define ACTION_CLR_IPI(cpu, ipi) (0x2000 | CPUNUM(cpu, 9) | ((ipi) << 8)) | |
70 | #define ACTION_SET_IPI(cpu, ipi) (0x3000 | CPUNUM(cpu, 9) | ((ipi) << 8)) | |
71 | #define ACTION_BOOT_THREAD(cpu) (0x08 | CPUNUM(cpu, 0)) | |
72 | ||
73 | static void __init bmips_smp_setup(void) | |
74 | { | |
4df715aa | 75 | int i, cpu = 1, boot_cpu = 0; |
fcfa66de FF |
76 | int cpu_hw_intr; |
77 | ||
6465460c JG |
78 | switch (current_cpu_type()) { |
79 | case CPU_BMIPS4350: | |
80 | case CPU_BMIPS4380: | |
81 | /* arbitration priority */ | |
82 | clear_c0_brcm_cmt_ctrl(0x30); | |
83 | ||
84 | /* NBK and weak order flags */ | |
85 | set_c0_brcm_config_0(0x30000); | |
86 | ||
87 | /* Find out if we are running on TP0 or TP1 */ | |
88 | boot_cpu = !!(read_c0_brcm_cmt_local() & (1 << 31)); | |
89 | ||
90 | /* | |
91 | * MIPS interrupts 0,1 (SW INT 0,1) cross over to the other | |
92 | * thread | |
93 | * MIPS interrupt 2 (HW INT 0) is the CPU0 L1 controller output | |
94 | * MIPS interrupt 3 (HW INT 1) is the CPU1 L1 controller output | |
95 | */ | |
96 | if (boot_cpu == 0) | |
97 | cpu_hw_intr = 0x02; | |
98 | else | |
99 | cpu_hw_intr = 0x1d; | |
100 | ||
101 | change_c0_brcm_cmt_intr(0xf8018000, | |
102 | (cpu_hw_intr << 27) | (0x03 << 15)); | |
103 | ||
104 | /* single core, 2 threads (2 pipelines) */ | |
105 | max_cpus = 2; | |
106 | ||
107 | break; | |
108 | case CPU_BMIPS5000: | |
109 | /* enable raceless SW interrupts */ | |
110 | set_c0_brcm_config(0x03 << 22); | |
111 | ||
112 | /* route HW interrupt 0 to CPU0, HW interrupt 1 to CPU1 */ | |
113 | change_c0_brcm_mode(0x1f << 27, 0x02 << 27); | |
114 | ||
115 | /* N cores, 2 threads per core */ | |
116 | max_cpus = (((read_c0_brcm_config() >> 6) & 0x03) + 1) << 1; | |
117 | ||
118 | /* clear any pending SW interrupts */ | |
119 | for (i = 0; i < max_cpus; i++) { | |
120 | write_c0_brcm_action(ACTION_CLR_IPI(i, 0)); | |
121 | write_c0_brcm_action(ACTION_CLR_IPI(i, 1)); | |
122 | } | |
df0ac8a4 | 123 | |
6465460c JG |
124 | break; |
125 | default: | |
126 | max_cpus = 1; | |
df0ac8a4 | 127 | } |
df0ac8a4 KC |
128 | |
129 | if (!bmips_smp_enabled) | |
130 | max_cpus = 1; | |
131 | ||
132 | /* this can be overridden by the BSP */ | |
133 | if (!board_ebase_setup) | |
134 | board_ebase_setup = &bmips_ebase_setup; | |
135 | ||
4df715aa FF |
136 | __cpu_number_map[boot_cpu] = 0; |
137 | __cpu_logical_map[0] = boot_cpu; | |
138 | ||
df0ac8a4 | 139 | for (i = 0; i < max_cpus; i++) { |
4df715aa FF |
140 | if (i != boot_cpu) { |
141 | __cpu_number_map[i] = cpu; | |
142 | __cpu_logical_map[cpu] = i; | |
143 | cpu++; | |
144 | } | |
df0ac8a4 KC |
145 | set_cpu_possible(i, 1); |
146 | set_cpu_present(i, 1); | |
147 | } | |
148 | } | |
149 | ||
150 | /* | |
151 | * IPI IRQ setup - runs on CPU0 | |
152 | */ | |
153 | static void bmips_prepare_cpus(unsigned int max_cpus) | |
154 | { | |
6465460c JG |
155 | irqreturn_t (*bmips_ipi_interrupt)(int irq, void *dev_id); |
156 | ||
157 | switch (current_cpu_type()) { | |
158 | case CPU_BMIPS4350: | |
159 | case CPU_BMIPS4380: | |
160 | bmips_ipi_interrupt = bmips43xx_ipi_interrupt; | |
161 | break; | |
162 | case CPU_BMIPS5000: | |
163 | bmips_ipi_interrupt = bmips5000_ipi_interrupt; | |
164 | break; | |
165 | default: | |
166 | return; | |
167 | } | |
168 | ||
df0ac8a4 KC |
169 | if (request_irq(IPI0_IRQ, bmips_ipi_interrupt, IRQF_PERCPU, |
170 | "smp_ipi0", NULL)) | |
f7777dcc | 171 | panic("Can't request IPI0 interrupt"); |
df0ac8a4 KC |
172 | if (request_irq(IPI1_IRQ, bmips_ipi_interrupt, IRQF_PERCPU, |
173 | "smp_ipi1", NULL)) | |
f7777dcc | 174 | panic("Can't request IPI1 interrupt"); |
df0ac8a4 KC |
175 | } |
176 | ||
177 | /* | |
178 | * Tell the hardware to boot CPUx - runs on CPU0 | |
179 | */ | |
180 | static void bmips_boot_secondary(int cpu, struct task_struct *idle) | |
181 | { | |
182 | bmips_smp_boot_sp = __KSTK_TOS(idle); | |
183 | bmips_smp_boot_gp = (unsigned long)task_thread_info(idle); | |
184 | mb(); | |
185 | ||
186 | /* | |
187 | * Initial boot sequence for secondary CPU: | |
188 | * bmips_reset_nmi_vec @ a000_0000 -> | |
189 | * bmips_smp_entry -> | |
190 | * plat_wired_tlb_setup (cached function call; optional) -> | |
191 | * start_secondary (cached jump) | |
192 | * | |
193 | * Warm restart sequence: | |
194 | * play_dead WAIT loop -> | |
195 | * bmips_smp_int_vec @ BMIPS_WARM_RESTART_VEC -> | |
196 | * eret to play_dead -> | |
197 | * bmips_secondary_reentry -> | |
198 | * start_secondary | |
199 | */ | |
200 | ||
201 | pr_info("SMP: Booting CPU%d...\n", cpu); | |
202 | ||
6465460c | 203 | if (cpumask_test_cpu(cpu, &bmips_booted_mask)) { |
3677a283 KC |
204 | /* kseg1 might not exist if this CPU enabled XKS01 */ |
205 | bmips_set_reset_vec(cpu, RESET_FROM_KSEG0); | |
206 | ||
6465460c JG |
207 | switch (current_cpu_type()) { |
208 | case CPU_BMIPS4350: | |
209 | case CPU_BMIPS4380: | |
210 | bmips43xx_send_ipi_single(cpu, 0); | |
211 | break; | |
212 | case CPU_BMIPS5000: | |
213 | bmips5000_send_ipi_single(cpu, 0); | |
214 | break; | |
215 | } | |
3677a283 KC |
216 | } else { |
217 | bmips_set_reset_vec(cpu, RESET_FROM_KSEG1); | |
218 | ||
6465460c JG |
219 | switch (current_cpu_type()) { |
220 | case CPU_BMIPS4350: | |
221 | case CPU_BMIPS4380: | |
222 | /* Reset slave TP1 if booting from TP0 */ | |
223 | if (cpu_logical_map(cpu) == 1) | |
224 | set_c0_brcm_cmt_ctrl(0x01); | |
225 | break; | |
226 | case CPU_BMIPS5000: | |
bdb2e05c | 227 | write_c0_brcm_action(ACTION_BOOT_THREAD(cpu)); |
6465460c | 228 | break; |
df0ac8a4 | 229 | } |
df0ac8a4 KC |
230 | cpumask_set_cpu(cpu, &bmips_booted_mask); |
231 | } | |
232 | } | |
233 | ||
234 | /* | |
235 | * Early setup - runs on secondary CPU after cache probe | |
236 | */ | |
237 | static void bmips_init_secondary(void) | |
238 | { | |
6465460c JG |
239 | switch (current_cpu_type()) { |
240 | case CPU_BMIPS4350: | |
241 | case CPU_BMIPS4380: | |
6465460c JG |
242 | clear_c0_cause(smp_processor_id() ? C_SW1 : C_SW0); |
243 | break; | |
244 | case CPU_BMIPS5000: | |
6465460c JG |
245 | write_c0_brcm_action(ACTION_CLR_IPI(smp_processor_id(), 0)); |
246 | break; | |
247 | } | |
df0ac8a4 KC |
248 | } |
249 | ||
250 | /* | |
251 | * Late setup - runs on secondary CPU before entering the idle loop | |
252 | */ | |
253 | static void bmips_smp_finish(void) | |
254 | { | |
255 | pr_info("SMP: CPU%d is running\n", smp_processor_id()); | |
856ac3c6 YZ |
256 | |
257 | /* make sure there won't be a timer interrupt for a little while */ | |
258 | write_c0_compare(read_c0_count() + mips_hpt_frequency / HZ); | |
259 | ||
260 | irq_enable_hazard(); | |
d8010ceb | 261 | set_c0_status(IE_SW0 | IE_SW1 | bmips_tp1_irqs | IE_IRQ5 | ST0_IE); |
856ac3c6 | 262 | irq_enable_hazard(); |
df0ac8a4 KC |
263 | } |
264 | ||
df0ac8a4 KC |
265 | /* |
266 | * BMIPS5000 raceless IPIs | |
267 | * | |
268 | * Each CPU has two inbound SW IRQs which are independent of all other CPUs. | |
269 | * IPI0 is used for SMP_RESCHEDULE_YOURSELF | |
270 | * IPI1 is used for SMP_CALL_FUNCTION | |
271 | */ | |
272 | ||
6465460c | 273 | static void bmips5000_send_ipi_single(int cpu, unsigned int action) |
df0ac8a4 KC |
274 | { |
275 | write_c0_brcm_action(ACTION_SET_IPI(cpu, action == SMP_CALL_FUNCTION)); | |
276 | } | |
277 | ||
6465460c | 278 | static irqreturn_t bmips5000_ipi_interrupt(int irq, void *dev_id) |
df0ac8a4 KC |
279 | { |
280 | int action = irq - IPI0_IRQ; | |
281 | ||
282 | write_c0_brcm_action(ACTION_CLR_IPI(smp_processor_id(), action)); | |
283 | ||
284 | if (action == 0) | |
285 | scheduler_ipi(); | |
286 | else | |
4ace6139 | 287 | generic_smp_call_function_interrupt(); |
df0ac8a4 KC |
288 | |
289 | return IRQ_HANDLED; | |
290 | } | |
291 | ||
6465460c JG |
292 | static void bmips5000_send_ipi_mask(const struct cpumask *mask, |
293 | unsigned int action) | |
294 | { | |
295 | unsigned int i; | |
296 | ||
297 | for_each_cpu(i, mask) | |
298 | bmips5000_send_ipi_single(i, action); | |
299 | } | |
df0ac8a4 KC |
300 | |
301 | /* | |
302 | * BMIPS43xx racey IPIs | |
303 | * | |
304 | * We use one inbound SW IRQ for each CPU. | |
305 | * | |
306 | * A spinlock must be held in order to keep CPUx from accidentally clearing | |
307 | * an incoming IPI when it writes CP0 CAUSE to raise an IPI on CPUy. The | |
308 | * same spinlock is used to protect the action masks. | |
309 | */ | |
310 | ||
311 | static DEFINE_SPINLOCK(ipi_lock); | |
312 | static DEFINE_PER_CPU(int, ipi_action_mask); | |
313 | ||
6465460c | 314 | static void bmips43xx_send_ipi_single(int cpu, unsigned int action) |
df0ac8a4 KC |
315 | { |
316 | unsigned long flags; | |
317 | ||
318 | spin_lock_irqsave(&ipi_lock, flags); | |
319 | set_c0_cause(cpu ? C_SW1 : C_SW0); | |
320 | per_cpu(ipi_action_mask, cpu) |= action; | |
321 | irq_enable_hazard(); | |
322 | spin_unlock_irqrestore(&ipi_lock, flags); | |
323 | } | |
324 | ||
6465460c | 325 | static irqreturn_t bmips43xx_ipi_interrupt(int irq, void *dev_id) |
df0ac8a4 KC |
326 | { |
327 | unsigned long flags; | |
328 | int action, cpu = irq - IPI0_IRQ; | |
329 | ||
330 | spin_lock_irqsave(&ipi_lock, flags); | |
35898716 | 331 | action = __this_cpu_read(ipi_action_mask); |
df0ac8a4 KC |
332 | per_cpu(ipi_action_mask, cpu) = 0; |
333 | clear_c0_cause(cpu ? C_SW1 : C_SW0); | |
334 | spin_unlock_irqrestore(&ipi_lock, flags); | |
335 | ||
336 | if (action & SMP_RESCHEDULE_YOURSELF) | |
337 | scheduler_ipi(); | |
338 | if (action & SMP_CALL_FUNCTION) | |
4ace6139 | 339 | generic_smp_call_function_interrupt(); |
df0ac8a4 KC |
340 | |
341 | return IRQ_HANDLED; | |
342 | } | |
343 | ||
6465460c | 344 | static void bmips43xx_send_ipi_mask(const struct cpumask *mask, |
df0ac8a4 KC |
345 | unsigned int action) |
346 | { | |
347 | unsigned int i; | |
348 | ||
349 | for_each_cpu(i, mask) | |
6465460c | 350 | bmips43xx_send_ipi_single(i, action); |
df0ac8a4 KC |
351 | } |
352 | ||
353 | #ifdef CONFIG_HOTPLUG_CPU | |
354 | ||
355 | static int bmips_cpu_disable(void) | |
356 | { | |
357 | unsigned int cpu = smp_processor_id(); | |
358 | ||
359 | if (cpu == 0) | |
360 | return -EBUSY; | |
361 | ||
362 | pr_info("SMP: CPU%d is offline\n", cpu); | |
363 | ||
0b5f9c00 | 364 | set_cpu_online(cpu, false); |
8dd92891 | 365 | cpumask_clear_cpu(cpu, &cpu_callin_map); |
230b6ff5 | 366 | clear_c0_status(IE_IRQ5); |
df0ac8a4 KC |
367 | |
368 | local_flush_tlb_all(); | |
369 | local_flush_icache_range(0, ~0); | |
370 | ||
371 | return 0; | |
372 | } | |
373 | ||
374 | static void bmips_cpu_die(unsigned int cpu) | |
375 | { | |
376 | } | |
377 | ||
378 | void __ref play_dead(void) | |
379 | { | |
380 | idle_task_exit(); | |
381 | ||
382 | /* flush data cache */ | |
383 | _dma_cache_wback_inv(0, ~0); | |
384 | ||
385 | /* | |
386 | * Wakeup is on SW0 or SW1; disable everything else | |
387 | * Use BEV !IV (BMIPS_WARM_RESTART_VEC) to avoid the regular Linux | |
388 | * IRQ handlers; this clears ST0_IE and returns immediately. | |
389 | */ | |
390 | clear_c0_cause(CAUSEF_IV | C_SW0 | C_SW1); | |
d8010ceb KC |
391 | change_c0_status( |
392 | IE_IRQ5 | bmips_tp1_irqs | IE_SW0 | IE_SW1 | ST0_IE | ST0_BEV, | |
df0ac8a4 KC |
393 | IE_SW0 | IE_SW1 | ST0_IE | ST0_BEV); |
394 | irq_disable_hazard(); | |
395 | ||
396 | /* | |
397 | * wait for SW interrupt from bmips_boot_secondary(), then jump | |
398 | * back to start_secondary() | |
399 | */ | |
400 | __asm__ __volatile__( | |
401 | " wait\n" | |
402 | " j bmips_secondary_reentry\n" | |
403 | : : : "memory"); | |
404 | } | |
405 | ||
406 | #endif /* CONFIG_HOTPLUG_CPU */ | |
407 | ||
6465460c JG |
408 | struct plat_smp_ops bmips43xx_smp_ops = { |
409 | .smp_setup = bmips_smp_setup, | |
410 | .prepare_cpus = bmips_prepare_cpus, | |
411 | .boot_secondary = bmips_boot_secondary, | |
412 | .smp_finish = bmips_smp_finish, | |
413 | .init_secondary = bmips_init_secondary, | |
6465460c JG |
414 | .send_ipi_single = bmips43xx_send_ipi_single, |
415 | .send_ipi_mask = bmips43xx_send_ipi_mask, | |
416 | #ifdef CONFIG_HOTPLUG_CPU | |
417 | .cpu_disable = bmips_cpu_disable, | |
418 | .cpu_die = bmips_cpu_die, | |
419 | #endif | |
420 | }; | |
421 | ||
422 | struct plat_smp_ops bmips5000_smp_ops = { | |
df0ac8a4 KC |
423 | .smp_setup = bmips_smp_setup, |
424 | .prepare_cpus = bmips_prepare_cpus, | |
425 | .boot_secondary = bmips_boot_secondary, | |
426 | .smp_finish = bmips_smp_finish, | |
427 | .init_secondary = bmips_init_secondary, | |
6465460c JG |
428 | .send_ipi_single = bmips5000_send_ipi_single, |
429 | .send_ipi_mask = bmips5000_send_ipi_mask, | |
df0ac8a4 KC |
430 | #ifdef CONFIG_HOTPLUG_CPU |
431 | .cpu_disable = bmips_cpu_disable, | |
432 | .cpu_die = bmips_cpu_die, | |
433 | #endif | |
434 | }; | |
435 | ||
436 | #endif /* CONFIG_SMP */ | |
437 | ||
438 | /*********************************************************************** | |
439 | * BMIPS vector relocation | |
440 | * This is primarily used for SMP boot, but it is applicable to some | |
441 | * UP BMIPS systems as well. | |
442 | ***********************************************************************/ | |
443 | ||
078a55fc | 444 | static void bmips_wr_vec(unsigned long dst, char *start, char *end) |
df0ac8a4 KC |
445 | { |
446 | memcpy((void *)dst, start, end - start); | |
57b41758 | 447 | dma_cache_wback(dst, end - start); |
df0ac8a4 KC |
448 | local_flush_icache_range(dst, dst + (end - start)); |
449 | instruction_hazard(); | |
450 | } | |
451 | ||
078a55fc | 452 | static inline void bmips_nmi_handler_setup(void) |
df0ac8a4 KC |
453 | { |
454 | bmips_wr_vec(BMIPS_NMI_RESET_VEC, &bmips_reset_nmi_vec, | |
455 | &bmips_reset_nmi_vec_end); | |
456 | bmips_wr_vec(BMIPS_WARM_RESTART_VEC, &bmips_smp_int_vec, | |
457 | &bmips_smp_int_vec_end); | |
458 | } | |
459 | ||
fc455787 KC |
460 | struct reset_vec_info { |
461 | int cpu; | |
462 | u32 val; | |
463 | }; | |
464 | ||
465 | static void bmips_set_reset_vec_remote(void *vinfo) | |
466 | { | |
467 | struct reset_vec_info *info = vinfo; | |
468 | int shift = info->cpu & 0x01 ? 16 : 0; | |
469 | u32 mask = ~(0xffff << shift), val = info->val >> 16; | |
470 | ||
471 | preempt_disable(); | |
472 | if (smp_processor_id() > 0) { | |
473 | smp_call_function_single(0, &bmips_set_reset_vec_remote, | |
474 | info, 1); | |
475 | } else { | |
476 | if (info->cpu & 0x02) { | |
477 | /* BMIPS5200 "should" use mask/shift, but it's buggy */ | |
478 | bmips_write_zscm_reg(0xa0, (val << 16) | val); | |
479 | bmips_read_zscm_reg(0xa0); | |
480 | } else { | |
481 | write_c0_brcm_bootvec((read_c0_brcm_bootvec() & mask) | | |
482 | (val << shift)); | |
483 | } | |
484 | } | |
485 | preempt_enable(); | |
486 | } | |
487 | ||
488 | static void bmips_set_reset_vec(int cpu, u32 val) | |
489 | { | |
490 | struct reset_vec_info info; | |
491 | ||
492 | if (current_cpu_type() == CPU_BMIPS5000) { | |
493 | /* this needs to run from CPU0 (which is always online) */ | |
494 | info.cpu = cpu; | |
495 | info.val = val; | |
496 | bmips_set_reset_vec_remote(&info); | |
497 | } else { | |
498 | void __iomem *cbr = BMIPS_GET_CBR(); | |
499 | ||
500 | if (cpu == 0) | |
501 | __raw_writel(val, cbr + BMIPS_RELO_VECTOR_CONTROL_0); | |
502 | else { | |
503 | if (current_cpu_type() != CPU_BMIPS4380) | |
504 | return; | |
505 | __raw_writel(val, cbr + BMIPS_RELO_VECTOR_CONTROL_1); | |
506 | } | |
507 | } | |
508 | __sync(); | |
509 | back_to_back_c0_hazard(); | |
510 | } | |
511 | ||
078a55fc | 512 | void bmips_ebase_setup(void) |
df0ac8a4 KC |
513 | { |
514 | unsigned long new_ebase = ebase; | |
df0ac8a4 KC |
515 | |
516 | BUG_ON(ebase != CKSEG0); | |
517 | ||
6465460c JG |
518 | switch (current_cpu_type()) { |
519 | case CPU_BMIPS4350: | |
520 | /* | |
521 | * BMIPS4350 cannot relocate the normal vectors, but it | |
522 | * can relocate the BEV=1 vectors. So CPU1 starts up at | |
523 | * the relocated BEV=1, IV=0 general exception vector @ | |
524 | * 0xa000_0380. | |
525 | * | |
526 | * set_uncached_handler() is used here because: | |
527 | * - CPU1 will run this from uncached space | |
528 | * - None of the cacheflush functions are set up yet | |
529 | */ | |
530 | set_uncached_handler(BMIPS_WARM_RESTART_VEC - CKSEG0, | |
531 | &bmips_smp_int_vec, 0x80); | |
532 | __sync(); | |
533 | return; | |
fa010672 | 534 | case CPU_BMIPS3300: |
6465460c JG |
535 | case CPU_BMIPS4380: |
536 | /* | |
537 | * 0x8000_0000: reset/NMI (initially in kseg1) | |
538 | * 0x8000_0400: normal vectors | |
539 | */ | |
540 | new_ebase = 0x80000400; | |
fc455787 | 541 | bmips_set_reset_vec(0, RESET_FROM_KSEG0); |
6465460c JG |
542 | break; |
543 | case CPU_BMIPS5000: | |
544 | /* | |
545 | * 0x8000_0000: reset/NMI (initially in kseg1) | |
546 | * 0x8000_1000: normal vectors | |
547 | */ | |
548 | new_ebase = 0x80001000; | |
fc455787 | 549 | bmips_set_reset_vec(0, RESET_FROM_KSEG0); |
6465460c | 550 | write_c0_ebase(new_ebase); |
6465460c JG |
551 | break; |
552 | default: | |
553 | return; | |
554 | } | |
555 | ||
df0ac8a4 KC |
556 | board_nmi_handler_setup = &bmips_nmi_handler_setup; |
557 | ebase = new_ebase; | |
558 | } | |
559 | ||
560 | asmlinkage void __weak plat_wired_tlb_setup(void) | |
561 | { | |
562 | /* | |
563 | * Called when starting/restarting a secondary CPU. | |
564 | * Kernel stacks and other important data might only be accessible | |
565 | * once the wired entries are present. | |
566 | */ | |
567 | } |