[mirror_ubuntu-focal-kernel.git] / arch / mips / kernel / smp-mt.c

/*
 *  This program is free software; you can distribute it and/or modify it
 *  under the terms of the GNU General Public License (Version 2) as
 *  published by the Free Software Foundation.
 *
 *  This program is distributed in the hope it will be useful, but WITHOUT
 *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
 *  for more details.
 *
 *  You should have received a copy of the GNU General Public License along
 *  with this program; if not, write to the Free Software Foundation, Inc.,
 *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
 *
 * Copyright (C) 2004, 05, 06 MIPS Technologies, Inc.
 *    Elizabeth Clarke (beth@mips.com)
 *    Ralf Baechle (ralf@linux-mips.org)
 * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org)
 */
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/cpumask.h>
#include <linux/interrupt.h>
#include <linux/compiler.h>
#include <linux/sched/task_stack.h>
#include <linux/smp.h>

#include <linux/atomic.h>
#include <asm/cacheflush.h>
#include <asm/cpu.h>
#include <asm/processor.h>
#include <asm/hardirq.h>
#include <asm/mmu_context.h>
#include <asm/time.h>
#include <asm/mipsregs.h>
#include <asm/mipsmtregs.h>
#include <asm/mips_mt.h>
#include <asm/mips-cps.h>

static void __init smvp_copy_vpe_config(void)
{
	write_vpe_c0_status(
		(read_c0_status() & ~(ST0_IM | ST0_IE | ST0_KSU)) | ST0_CU0);

	/* set config to be the same as vpe0, particularly kseg0 coherency alg */
	write_vpe_c0_config( read_c0_config());

	/* make sure there are no software interrupts pending */
	write_vpe_c0_cause(0);

	/* Propagate Config7 */
	write_vpe_c0_config7(read_c0_config7());

	write_vpe_c0_count(read_c0_count());
}

static unsigned int __init smvp_vpe_init(unsigned int tc, unsigned int mvpconf0,
	unsigned int ncpu)
{
	if (tc > ((mvpconf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT))
		return ncpu;

	/* Deactivate all but VPE 0 */
	if (tc != 0) {
		unsigned long tmp = read_vpe_c0_vpeconf0();

		tmp &= ~VPECONF0_VPA;

		/* master VPE */
		tmp |= VPECONF0_MVP;
		write_vpe_c0_vpeconf0(tmp);

		/* Record this as available CPU */
		set_cpu_possible(tc, true);
		set_cpu_present(tc, true);
		__cpu_number_map[tc]	= ++ncpu;
		__cpu_logical_map[ncpu] = tc;
	}

	/* Disable multi-threading with TC's */
	write_vpe_c0_vpecontrol(read_vpe_c0_vpecontrol() & ~VPECONTROL_TE);

	if (tc != 0)
		smvp_copy_vpe_config();

	cpu_set_vpe_id(&cpu_data[ncpu], tc);

	return ncpu;
}

static void __init smvp_tc_init(unsigned int tc, unsigned int mvpconf0)
{
	unsigned long tmp;

	if (!tc)
		return;

	/* bind a TC to each VPE, May as well put all excess TC's
	   on the last VPE */
	if (tc >= (((mvpconf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT)+1))
		write_tc_c0_tcbind(read_tc_c0_tcbind() | ((mvpconf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT));
	else {
		write_tc_c0_tcbind(read_tc_c0_tcbind() | tc);

		/* and set XTC */
		write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() | (tc << VPECONF0_XTC_SHIFT));
	}

	tmp = read_tc_c0_tcstatus();

	/* mark not allocated and not dynamically allocatable */
	tmp &= ~(TCSTATUS_A | TCSTATUS_DA);
	tmp |= TCSTATUS_IXMT;		/* interrupt exempt */
	write_tc_c0_tcstatus(tmp);

	write_tc_c0_tchalt(TCHALT_H);
}

static void vsmp_init_secondary(void)
{
	/* This is Malta specific: IPI,performance and timer interrupts */
	if (mips_gic_present())
		change_c0_status(ST0_IM, STATUSF_IP2 | STATUSF_IP3 |
					 STATUSF_IP4 | STATUSF_IP5 |
					 STATUSF_IP6 | STATUSF_IP7);
	else
		change_c0_status(ST0_IM, STATUSF_IP0 | STATUSF_IP1 |
					 STATUSF_IP6 | STATUSF_IP7);
}

static void vsmp_smp_finish(void)
{
	/* CDFIXME: remove this? */
	write_c0_compare(read_c0_count() + (8* mips_hpt_frequency/HZ));

#ifdef CONFIG_MIPS_MT_FPAFF
	/* If we have an FPU, enroll ourselves in the FPU-full mask */
	if (cpu_has_fpu)
		cpumask_set_cpu(smp_processor_id(), &mt_fpu_cpumask);
#endif /* CONFIG_MIPS_MT_FPAFF */

	local_irq_enable();
}

/*
 * Setup the PC, SP, and GP of a secondary processor and start it
 * running!
 * smp_bootstrap is the place to resume from
 * __KSTK_TOS(idle) is apparently the stack pointer
 * (unsigned long)idle->thread_info the gp
 * assumes a 1:1 mapping of TC => VPE
 */
static int vsmp_boot_secondary(int cpu, struct task_struct *idle)
{
	struct thread_info *gp = task_thread_info(idle);
	dvpe();
	set_c0_mvpcontrol(MVPCONTROL_VPC);

	settc(cpu);

	/* restart */
	write_tc_c0_tcrestart((unsigned long)&smp_bootstrap);

	/* enable the tc this vpe/cpu will be running */
	write_tc_c0_tcstatus((read_tc_c0_tcstatus() & ~TCSTATUS_IXMT) | TCSTATUS_A);

	write_tc_c0_tchalt(0);

	/* enable the VPE */
	write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() | VPECONF0_VPA);

	/* stack pointer */
	write_tc_gpr_sp( __KSTK_TOS(idle));

	/* global pointer */
	write_tc_gpr_gp((unsigned long)gp);

	flush_icache_range((unsigned long)gp,
			   (unsigned long)(gp + sizeof(struct thread_info)));

	/* finally out of configuration and into chaos */
	clear_c0_mvpcontrol(MVPCONTROL_VPC);

	evpe(EVPE_ENABLE);

	return 0;
}

/*
 * Common setup before any secondaries are started
 * Make sure all CPU's are in a sensible state before we boot any of the
 * secondaries
 */
static void __init vsmp_smp_setup(void)
{
	unsigned int mvpconf0, ntc, tc, ncpu = 0;
	unsigned int nvpe;

#ifdef CONFIG_MIPS_MT_FPAFF
	/* If we have an FPU, enroll ourselves in the FPU-full mask */
	if (cpu_has_fpu)
		cpumask_set_cpu(0, &mt_fpu_cpumask);
#endif /* CONFIG_MIPS_MT_FPAFF */
	if (!cpu_has_mipsmt)
		return;

	/* disable MT so we can configure */
	dvpe();
	dmt();

	/* Put MVPE's into 'configuration state' */
	set_c0_mvpcontrol(MVPCONTROL_VPC);

	mvpconf0 = read_c0_mvpconf0();
	ntc = (mvpconf0 & MVPCONF0_PTC) >> MVPCONF0_PTC_SHIFT;

	nvpe = ((mvpconf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT) + 1;
	smp_num_siblings = nvpe;

	/* we'll always have more TC's than VPE's, so loop setting everything
	   to a sensible state */
	for (tc = 0; tc <= ntc; tc++) {
		settc(tc);

		smvp_tc_init(tc, mvpconf0);
		ncpu = smvp_vpe_init(tc, mvpconf0, ncpu);
	}

	/* Release config state */
	clear_c0_mvpcontrol(MVPCONTROL_VPC);

	/* We'll wait until starting the secondaries before starting MVPE */

	printk(KERN_INFO "Detected %i available secondary CPU(s)\n", ncpu);
}

static void __init vsmp_prepare_cpus(unsigned int max_cpus)
{
	mips_mt_set_cpuoptions();
}

const struct plat_smp_ops vsmp_smp_ops = {
	.send_ipi_single	= mips_smp_send_ipi_single,
	.send_ipi_mask		= mips_smp_send_ipi_mask,
	.init_secondary		= vsmp_init_secondary,
	.smp_finish		= vsmp_smp_finish,
	.boot_secondary		= vsmp_boot_secondary,
	.smp_setup		= vsmp_smp_setup,
	.prepare_cpus		= vsmp_prepare_cpus,
};
Commit	Line	Data
340ee4b9	1	/*
340ee4b9 RB	2	* This program is free software; you can distribute it and/or modify it
	3	* under the terms of the GNU General Public License (Version 2) as
	4	* published by the Free Software Foundation.
	5	*
	6	* This program is distributed in the hope it will be useful, but WITHOUT
	7	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	8	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
	9	* for more details.
	10	*
	11	* You should have received a copy of the GNU General Public License along
	12	* with this program; if not, write to the Free Software Foundation, Inc.,
	13	* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
	14	*
41c594ab RB	15	* Copyright (C) 2004, 05, 06 MIPS Technologies, Inc.
	16	* Elizabeth Clarke (beth@mips.com)
	17	* Ralf Baechle (ralf@linux-mips.org)
	18	* Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org)
340ee4b9 RB	19	*/
	20	#include <linux/kernel.h>
	21	#include <linux/sched.h>
	22	#include <linux/cpumask.h>
	23	#include <linux/interrupt.h>
	24	#include <linux/compiler.h>
fc69910f	25	#include <linux/sched/task_stack.h>
0ab7aefc	26	#include <linux/smp.h>
340ee4b9	27
60063497	28	#include <linux/atomic.h>
41c594ab	29	#include <asm/cacheflush.h>
340ee4b9 RB	30	#include <asm/cpu.h>
340ee4b9 RB	31	#include <asm/processor.h>
340ee4b9 RB	32	#include <asm/hardirq.h>
340ee4b9 RB	33	#include <asm/mmu_context.h>
340ee4b9 RB	34	#include <asm/time.h>
	35	#include <asm/mipsregs.h>
	36	#include <asm/mipsmtregs.h>
41c594ab	37	#include <asm/mips_mt.h>
72eb2995	38	#include <asm/mips-cps.h>
340ee4b9	39
39b8d525	40	static void __init smvp_copy_vpe_config(void)
781b0f8d RB	41	{
	42	write_vpe_c0_status(
	43	(read_c0_status() & ~(ST0_IM \| ST0_IE \| ST0_KSU)) \| ST0_CU0);
	44
	45	/* set config to be the same as vpe0, particularly kseg0 coherency alg */
	46	write_vpe_c0_config( read_c0_config());
	47
	48	/* make sure there are no software interrupts pending */
	49	write_vpe_c0_cause(0);
	50
	51	/* Propagate Config7 */
	52	write_vpe_c0_config7(read_c0_config7());
70e46f48 RB	53
70e46f48 RB	54	write_vpe_c0_count(read_c0_count());
781b0f8d RB	55	}
781b0f8d RB	56
39b8d525	57	static unsigned int __init smvp_vpe_init(unsigned int tc, unsigned int mvpconf0,
781b0f8d RB	58	unsigned int ncpu)
	59	{
	60	if (tc > ((mvpconf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT))
	61	return ncpu;
	62
	63	/* Deactivate all but VPE 0 */
	64	if (tc != 0) {
	65	unsigned long tmp = read_vpe_c0_vpeconf0();
	66
	67	tmp &= ~VPECONF0_VPA;
	68
	69	/* master VPE */
	70	tmp \|= VPECONF0_MVP;
	71	write_vpe_c0_vpeconf0(tmp);
	72
	73	/* Record this as available CPU */
4037ac6e	74	set_cpu_possible(tc, true);
c2c2a644	75	set_cpu_present(tc, true);
781b0f8d	76	__cpu_number_map[tc] = ++ncpu;
70342287	77	__cpu_logical_map[ncpu] = tc;
781b0f8d RB	78	}
	79
	80	/* Disable multi-threading with TC's */
	81	write_vpe_c0_vpecontrol(read_vpe_c0_vpecontrol() & ~VPECONTROL_TE);
	82
	83	if (tc != 0)
39b8d525	84	smvp_copy_vpe_config();
781b0f8d	85
f875a832	86	cpu_set_vpe_id(&cpu_data[ncpu], tc);
1eed4004	87
781b0f8d RB	88	return ncpu;
	89	}
	90
39b8d525	91	static void __init smvp_tc_init(unsigned int tc, unsigned int mvpconf0)
781b0f8d RB	92	{
	93	unsigned long tmp;
	94
	95	if (!tc)
	96	return;
	97
	98	/* bind a TC to each VPE, May as well put all excess TC's
	99	on the last VPE */
	100	if (tc >= (((mvpconf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT)+1))
	101	write_tc_c0_tcbind(read_tc_c0_tcbind() \| ((mvpconf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT));
	102	else {
	103	write_tc_c0_tcbind(read_tc_c0_tcbind() \| tc);
	104
	105	/* and set XTC */
	106	write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() \| (tc << VPECONF0_XTC_SHIFT));
	107	}
	108
	109	tmp = read_tc_c0_tcstatus();
	110
	111	/* mark not allocated and not dynamically allocatable */
	112	tmp &= ~(TCSTATUS_A \| TCSTATUS_DA);
	113	tmp \|= TCSTATUS_IXMT; /* interrupt exempt */
	114	write_tc_c0_tcstatus(tmp);
	115
	116	write_tc_c0_tchalt(TCHALT_H);
	117	}
	118
078a55fc	119	static void vsmp_init_secondary(void)
87353d8a	120	{
d002aaad	121	/* This is Malta specific: IPI,performance and timer interrupts */
72eb2995	122	if (mips_gic_present())
c3f134fb JH	123	change_c0_status(ST0_IM, STATUSF_IP2 \| STATUSF_IP3 \|
c3f134fb JH	124	STATUSF_IP4 \| STATUSF_IP5 \|
39b8d525 RB	125	STATUSF_IP6 \| STATUSF_IP7);
	126	else
	127	change_c0_status(ST0_IM, STATUSF_IP0 \| STATUSF_IP1 \|
	128	STATUSF_IP6 \| STATUSF_IP7);
41c594ab	129	}
340ee4b9	130
078a55fc	131	static void vsmp_smp_finish(void)
41c594ab	132	{
39b8d525	133	/* CDFIXME: remove this? */
87353d8a	134	write_c0_compare(read_c0_count() + (8* mips_hpt_frequency/HZ));
340ee4b9	135
87353d8a RB	136	#ifdef CONFIG_MIPS_MT_FPAFF
	137	/* If we have an FPU, enroll ourselves in the FPU-full mask */
	138	if (cpu_has_fpu)
8dd92891	139	cpumask_set_cpu(smp_processor_id(), &mt_fpu_cpumask);
87353d8a	140	#endif /* CONFIG_MIPS_MT_FPAFF */
340ee4b9	141
87353d8a RB	142	local_irq_enable();
87353d8a RB	143	}
340ee4b9	144
340ee4b9 RB	145	/*
	146	* Setup the PC, SP, and GP of a secondary processor and start it
	147	* running!
	148	* smp_bootstrap is the place to resume from
	149	* __KSTK_TOS(idle) is apparently the stack pointer
	150	* (unsigned long)idle->thread_info the gp
	151	* assumes a 1:1 mapping of TC => VPE
	152	*/
d595d423	153	static int vsmp_boot_secondary(int cpu, struct task_struct *idle)
340ee4b9	154	{
dc8f6029	155	struct thread_info *gp = task_thread_info(idle);
340ee4b9 RB	156	dvpe();
	157	set_c0_mvpcontrol(MVPCONTROL_VPC);
	158
	159	settc(cpu);
	160
	161	/* restart */
	162	write_tc_c0_tcrestart((unsigned long)&smp_bootstrap);
	163
	164	/* enable the tc this vpe/cpu will be running */
	165	write_tc_c0_tcstatus((read_tc_c0_tcstatus() & ~TCSTATUS_IXMT) \| TCSTATUS_A);
	166
	167	write_tc_c0_tchalt(0);
	168
	169	/* enable the VPE */
	170	write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() \| VPECONF0_VPA);
	171
	172	/* stack pointer */
	173	write_tc_gpr_sp( __KSTK_TOS(idle));
	174
	175	/* global pointer */
dc8f6029	176	write_tc_gpr_gp((unsigned long)gp);
340ee4b9	177
41c594ab	178	flush_icache_range((unsigned long)gp,
70342287	179	(unsigned long)(gp + sizeof(struct thread_info)));
340ee4b9 RB	180
	181	/* finally out of configuration and into chaos */
	182	clear_c0_mvpcontrol(MVPCONTROL_VPC);
	183
	184	evpe(EVPE_ENABLE);
d595d423 PB	185
d595d423 PB	186	return 0;
340ee4b9 RB	187	}
340ee4b9 RB	188
87353d8a RB	189	/*
	190	* Common setup before any secondaries are started
	191	* Make sure all CPU's are in a sensible state before we boot any of the
39b8d525	192	* secondaries
87353d8a RB	193	*/
87353d8a RB	194	static void __init vsmp_smp_setup(void)
340ee4b9	195	{
87353d8a RB	196	unsigned int mvpconf0, ntc, tc, ncpu = 0;
87353d8a RB	197	unsigned int nvpe;
340ee4b9	198
f088fc84 RB	199	#ifdef CONFIG_MIPS_MT_FPAFF
	200	/* If we have an FPU, enroll ourselves in the FPU-full mask */
	201	if (cpu_has_fpu)
8dd92891	202	cpumask_set_cpu(0, &mt_fpu_cpumask);
f088fc84	203	#endif /* CONFIG_MIPS_MT_FPAFF */
87353d8a RB	204	if (!cpu_has_mipsmt)
87353d8a RB	205	return;
f088fc84	206
87353d8a RB	207	/* disable MT so we can configure */
	208	dvpe();
	209	dmt();
340ee4b9	210
87353d8a RB	211	/* Put MVPE's into 'configuration state' */
87353d8a RB	212	set_c0_mvpcontrol(MVPCONTROL_VPC);
340ee4b9	213
87353d8a RB	214	mvpconf0 = read_c0_mvpconf0();
87353d8a RB	215	ntc = (mvpconf0 & MVPCONF0_PTC) >> MVPCONF0_PTC_SHIFT;
340ee4b9	216
87353d8a RB	217	nvpe = ((mvpconf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT) + 1;
87353d8a RB	218	smp_num_siblings = nvpe;
340ee4b9	219
87353d8a RB	220	/* we'll always have more TC's than VPE's, so loop setting everything
	221	to a sensible state */
	222	for (tc = 0; tc <= ntc; tc++) {
	223	settc(tc);
340ee4b9	224
39b8d525 RB	225	smvp_tc_init(tc, mvpconf0);
39b8d525 RB	226	ncpu = smvp_vpe_init(tc, mvpconf0, ncpu);
87353d8a	227	}
340ee4b9	228
87353d8a RB	229	/* Release config state */
	230	clear_c0_mvpcontrol(MVPCONTROL_VPC);
	231
	232	/* We'll wait until starting the secondaries before starting MVPE */
	233
	234	printk(KERN_INFO "Detected %i available secondary CPU(s)\n", ncpu);
	235	}
	236
	237	static void __init vsmp_prepare_cpus(unsigned int max_cpus)
	238	{
	239	mips_mt_set_cpuoptions();
340ee4b9	240	}
87353d8a	241
ff2c8252	242	const struct plat_smp_ops vsmp_smp_ops = {
1eed4004 PB	243	.send_ipi_single = mips_smp_send_ipi_single,
1eed4004 PB	244	.send_ipi_mask = mips_smp_send_ipi_mask,
87353d8a RB	245	.init_secondary = vsmp_init_secondary,
87353d8a RB	246	.smp_finish = vsmp_smp_finish,
87353d8a RB	247	.boot_secondary = vsmp_boot_secondary,
	248	.smp_setup = vsmp_smp_setup,
	249	.prepare_cpus = vsmp_prepare_cpus,
	250	};
d6d3c9af	251