[mirror_ubuntu-focal-kernel.git] / arch / mips / kernel / smp-mt.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 *
 * Copyright (C) 2004, 05, 06 MIPS Technologies, Inc.
 *    Elizabeth Clarke (beth@mips.com)
 *    Ralf Baechle (ralf@linux-mips.org)
 * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org)
 */
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/cpumask.h>
#include <linux/interrupt.h>
#include <linux/compiler.h>
#include <linux/sched/task_stack.h>
#include <linux/smp.h>

#include <linux/atomic.h>
#include <asm/cacheflush.h>
#include <asm/cpu.h>
#include <asm/processor.h>
#include <asm/hardirq.h>
#include <asm/mmu_context.h>
#include <asm/time.h>
#include <asm/mipsregs.h>
#include <asm/mipsmtregs.h>
#include <asm/mips_mt.h>
#include <asm/mips-cps.h>

static void __init smvp_copy_vpe_config(void)
{
	write_vpe_c0_status(
		(read_c0_status() & ~(ST0_IM | ST0_IE | ST0_KSU)) | ST0_CU0);

	/* set config to be the same as vpe0, particularly kseg0 coherency alg */
	write_vpe_c0_config( read_c0_config());

	/* make sure there are no software interrupts pending */
	write_vpe_c0_cause(0);

	/* Propagate Config7 */
	write_vpe_c0_config7(read_c0_config7());

	write_vpe_c0_count(read_c0_count());
}

static unsigned int __init smvp_vpe_init(unsigned int tc, unsigned int mvpconf0,
	unsigned int ncpu)
{
	if (tc > ((mvpconf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT))
		return ncpu;

	/* Deactivate all but VPE 0 */
	if (tc != 0) {
		unsigned long tmp = read_vpe_c0_vpeconf0();

		tmp &= ~VPECONF0_VPA;

		/* master VPE */
		tmp |= VPECONF0_MVP;
		write_vpe_c0_vpeconf0(tmp);

		/* Record this as available CPU */
		set_cpu_possible(tc, true);
		set_cpu_present(tc, true);
		__cpu_number_map[tc]	= ++ncpu;
		__cpu_logical_map[ncpu] = tc;
	}

	/* Disable multi-threading with TC's */
	write_vpe_c0_vpecontrol(read_vpe_c0_vpecontrol() & ~VPECONTROL_TE);

	if (tc != 0)
		smvp_copy_vpe_config();

	cpu_set_vpe_id(&cpu_data[ncpu], tc);

	return ncpu;
}

static void __init smvp_tc_init(unsigned int tc, unsigned int mvpconf0)
{
	unsigned long tmp;

	if (!tc)
		return;

	/* bind a TC to each VPE, May as well put all excess TC's
	   on the last VPE */
	if (tc >= (((mvpconf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT)+1))
		write_tc_c0_tcbind(read_tc_c0_tcbind() | ((mvpconf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT));
	else {
		write_tc_c0_tcbind(read_tc_c0_tcbind() | tc);

		/* and set XTC */
		write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() | (tc << VPECONF0_XTC_SHIFT));
	}

	tmp = read_tc_c0_tcstatus();

	/* mark not allocated and not dynamically allocatable */
	tmp &= ~(TCSTATUS_A | TCSTATUS_DA);
	tmp |= TCSTATUS_IXMT;		/* interrupt exempt */
	write_tc_c0_tcstatus(tmp);

	write_tc_c0_tchalt(TCHALT_H);
}

static void vsmp_init_secondary(void)
{
	/* This is Malta specific: IPI,performance and timer interrupts */
	if (mips_gic_present())
		change_c0_status(ST0_IM, STATUSF_IP2 | STATUSF_IP3 |
					 STATUSF_IP4 | STATUSF_IP5 |
					 STATUSF_IP6 | STATUSF_IP7);
	else
		change_c0_status(ST0_IM, STATUSF_IP0 | STATUSF_IP1 |
					 STATUSF_IP6 | STATUSF_IP7);
}

static void vsmp_smp_finish(void)
{
	/* CDFIXME: remove this? */
	write_c0_compare(read_c0_count() + (8* mips_hpt_frequency/HZ));

#ifdef CONFIG_MIPS_MT_FPAFF
	/* If we have an FPU, enroll ourselves in the FPU-full mask */
	if (cpu_has_fpu)
		cpumask_set_cpu(smp_processor_id(), &mt_fpu_cpumask);
#endif /* CONFIG_MIPS_MT_FPAFF */

	local_irq_enable();
}

/*
 * Setup the PC, SP, and GP of a secondary processor and start it
 * running!
 * smp_bootstrap is the place to resume from
 * __KSTK_TOS(idle) is apparently the stack pointer
 * (unsigned long)idle->thread_info the gp
 * assumes a 1:1 mapping of TC => VPE
 */
static int vsmp_boot_secondary(int cpu, struct task_struct *idle)
{
	struct thread_info *gp = task_thread_info(idle);
	dvpe();
	set_c0_mvpcontrol(MVPCONTROL_VPC);

	settc(cpu);

	/* restart */
	write_tc_c0_tcrestart((unsigned long)&smp_bootstrap);

	/* enable the tc this vpe/cpu will be running */
	write_tc_c0_tcstatus((read_tc_c0_tcstatus() & ~TCSTATUS_IXMT) | TCSTATUS_A);

	write_tc_c0_tchalt(0);

	/* enable the VPE */
	write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() | VPECONF0_VPA);

	/* stack pointer */
	write_tc_gpr_sp( __KSTK_TOS(idle));

	/* global pointer */
	write_tc_gpr_gp((unsigned long)gp);

	flush_icache_range((unsigned long)gp,
			   (unsigned long)(gp + sizeof(struct thread_info)));

	/* finally out of configuration and into chaos */
	clear_c0_mvpcontrol(MVPCONTROL_VPC);

	evpe(EVPE_ENABLE);

	return 0;
}

/*
 * Common setup before any secondaries are started
 * Make sure all CPU's are in a sensible state before we boot any of the
 * secondaries
 */
static void __init vsmp_smp_setup(void)
{
	unsigned int mvpconf0, ntc, tc, ncpu = 0;
	unsigned int nvpe;

#ifdef CONFIG_MIPS_MT_FPAFF
	/* If we have an FPU, enroll ourselves in the FPU-full mask */
	if (cpu_has_fpu)
		cpumask_set_cpu(0, &mt_fpu_cpumask);
#endif /* CONFIG_MIPS_MT_FPAFF */
	if (!cpu_has_mipsmt)
		return;

	/* disable MT so we can configure */
	dvpe();
	dmt();

	/* Put MVPE's into 'configuration state' */
	set_c0_mvpcontrol(MVPCONTROL_VPC);

	mvpconf0 = read_c0_mvpconf0();
	ntc = (mvpconf0 & MVPCONF0_PTC) >> MVPCONF0_PTC_SHIFT;

	nvpe = ((mvpconf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT) + 1;
	smp_num_siblings = nvpe;

	/* we'll always have more TC's than VPE's, so loop setting everything
	   to a sensible state */
	for (tc = 0; tc <= ntc; tc++) {
		settc(tc);

		smvp_tc_init(tc, mvpconf0);
		ncpu = smvp_vpe_init(tc, mvpconf0, ncpu);
	}

	/* Release config state */
	clear_c0_mvpcontrol(MVPCONTROL_VPC);

	/* We'll wait until starting the secondaries before starting MVPE */

	printk(KERN_INFO "Detected %i available secondary CPU(s)\n", ncpu);
}

static void __init vsmp_prepare_cpus(unsigned int max_cpus)
{
	mips_mt_set_cpuoptions();
}

const struct plat_smp_ops vsmp_smp_ops = {
	.send_ipi_single	= mips_smp_send_ipi_single,
	.send_ipi_mask		= mips_smp_send_ipi_mask,
	.init_secondary		= vsmp_init_secondary,
	.smp_finish		= vsmp_smp_finish,
	.boot_secondary		= vsmp_boot_secondary,
	.smp_setup		= vsmp_smp_setup,
	.prepare_cpus		= vsmp_prepare_cpus,
};
Commit	Line	Data
41173abc	1	// SPDX-License-Identifier: GPL-2.0-only
340ee4b9	2	/*
340ee4b9	3	*
41c594ab RB	4	* Copyright (C) 2004, 05, 06 MIPS Technologies, Inc.
	5	* Elizabeth Clarke (beth@mips.com)
	6	* Ralf Baechle (ralf@linux-mips.org)
	7	* Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org)
340ee4b9 RB	8	*/
	9	#include <linux/kernel.h>
	10	#include <linux/sched.h>
	11	#include <linux/cpumask.h>
	12	#include <linux/interrupt.h>
	13	#include <linux/compiler.h>
fc69910f	14	#include <linux/sched/task_stack.h>
0ab7aefc	15	#include <linux/smp.h>
340ee4b9	16
60063497	17	#include <linux/atomic.h>
41c594ab	18	#include <asm/cacheflush.h>
340ee4b9 RB	19	#include <asm/cpu.h>
340ee4b9 RB	20	#include <asm/processor.h>
340ee4b9 RB	21	#include <asm/hardirq.h>
340ee4b9 RB	22	#include <asm/mmu_context.h>
340ee4b9 RB	23	#include <asm/time.h>
	24	#include <asm/mipsregs.h>
	25	#include <asm/mipsmtregs.h>
41c594ab	26	#include <asm/mips_mt.h>
72eb2995	27	#include <asm/mips-cps.h>
340ee4b9	28
39b8d525	29	static void __init smvp_copy_vpe_config(void)
781b0f8d RB	30	{
	31	write_vpe_c0_status(
	32	(read_c0_status() & ~(ST0_IM \| ST0_IE \| ST0_KSU)) \| ST0_CU0);
	33
	34	/* set config to be the same as vpe0, particularly kseg0 coherency alg */
	35	write_vpe_c0_config( read_c0_config());
	36
	37	/* make sure there are no software interrupts pending */
	38	write_vpe_c0_cause(0);
	39
	40	/* Propagate Config7 */
	41	write_vpe_c0_config7(read_c0_config7());
70e46f48 RB	42
70e46f48 RB	43	write_vpe_c0_count(read_c0_count());
781b0f8d RB	44	}
781b0f8d RB	45
39b8d525	46	static unsigned int __init smvp_vpe_init(unsigned int tc, unsigned int mvpconf0,
781b0f8d RB	47	unsigned int ncpu)
	48	{
	49	if (tc > ((mvpconf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT))
	50	return ncpu;
	51
	52	/* Deactivate all but VPE 0 */
	53	if (tc != 0) {
	54	unsigned long tmp = read_vpe_c0_vpeconf0();
	55
	56	tmp &= ~VPECONF0_VPA;
	57
	58	/* master VPE */
	59	tmp \|= VPECONF0_MVP;
	60	write_vpe_c0_vpeconf0(tmp);
	61
	62	/* Record this as available CPU */
4037ac6e	63	set_cpu_possible(tc, true);
c2c2a644	64	set_cpu_present(tc, true);
781b0f8d	65	__cpu_number_map[tc] = ++ncpu;
70342287	66	__cpu_logical_map[ncpu] = tc;
781b0f8d RB	67	}
	68
	69	/* Disable multi-threading with TC's */
	70	write_vpe_c0_vpecontrol(read_vpe_c0_vpecontrol() & ~VPECONTROL_TE);
	71
	72	if (tc != 0)
39b8d525	73	smvp_copy_vpe_config();
781b0f8d	74
f875a832	75	cpu_set_vpe_id(&cpu_data[ncpu], tc);
1eed4004	76
781b0f8d RB	77	return ncpu;
	78	}
	79
39b8d525	80	static void __init smvp_tc_init(unsigned int tc, unsigned int mvpconf0)
781b0f8d RB	81	{
	82	unsigned long tmp;
	83
	84	if (!tc)
	85	return;
	86
	87	/* bind a TC to each VPE, May as well put all excess TC's
	88	on the last VPE */
	89	if (tc >= (((mvpconf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT)+1))
	90	write_tc_c0_tcbind(read_tc_c0_tcbind() \| ((mvpconf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT));
	91	else {
	92	write_tc_c0_tcbind(read_tc_c0_tcbind() \| tc);
	93
	94	/* and set XTC */
	95	write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() \| (tc << VPECONF0_XTC_SHIFT));
	96	}
	97
	98	tmp = read_tc_c0_tcstatus();
	99
	100	/* mark not allocated and not dynamically allocatable */
	101	tmp &= ~(TCSTATUS_A \| TCSTATUS_DA);
	102	tmp \|= TCSTATUS_IXMT; /* interrupt exempt */
	103	write_tc_c0_tcstatus(tmp);
	104
	105	write_tc_c0_tchalt(TCHALT_H);
	106	}
	107
078a55fc	108	static void vsmp_init_secondary(void)
87353d8a	109	{
d002aaad	110	/* This is Malta specific: IPI,performance and timer interrupts */
72eb2995	111	if (mips_gic_present())
c3f134fb JH	112	change_c0_status(ST0_IM, STATUSF_IP2 \| STATUSF_IP3 \|
c3f134fb JH	113	STATUSF_IP4 \| STATUSF_IP5 \|
39b8d525 RB	114	STATUSF_IP6 \| STATUSF_IP7);
	115	else
	116	change_c0_status(ST0_IM, STATUSF_IP0 \| STATUSF_IP1 \|
	117	STATUSF_IP6 \| STATUSF_IP7);
41c594ab	118	}
340ee4b9	119
078a55fc	120	static void vsmp_smp_finish(void)
41c594ab	121	{
39b8d525	122	/* CDFIXME: remove this? */
87353d8a	123	write_c0_compare(read_c0_count() + (8* mips_hpt_frequency/HZ));
340ee4b9	124
87353d8a RB	125	#ifdef CONFIG_MIPS_MT_FPAFF
	126	/* If we have an FPU, enroll ourselves in the FPU-full mask */
	127	if (cpu_has_fpu)
8dd92891	128	cpumask_set_cpu(smp_processor_id(), &mt_fpu_cpumask);
87353d8a	129	#endif /* CONFIG_MIPS_MT_FPAFF */
340ee4b9	130
87353d8a RB	131	local_irq_enable();
87353d8a RB	132	}
340ee4b9	133
340ee4b9 RB	134	/*
	135	* Setup the PC, SP, and GP of a secondary processor and start it
	136	* running!
	137	* smp_bootstrap is the place to resume from
	138	* __KSTK_TOS(idle) is apparently the stack pointer
	139	* (unsigned long)idle->thread_info the gp
	140	* assumes a 1:1 mapping of TC => VPE
	141	*/
d595d423	142	static int vsmp_boot_secondary(int cpu, struct task_struct *idle)
340ee4b9	143	{
dc8f6029	144	struct thread_info *gp = task_thread_info(idle);
340ee4b9 RB	145	dvpe();
	146	set_c0_mvpcontrol(MVPCONTROL_VPC);
	147
	148	settc(cpu);
	149
	150	/* restart */
	151	write_tc_c0_tcrestart((unsigned long)&smp_bootstrap);
	152
	153	/* enable the tc this vpe/cpu will be running */
	154	write_tc_c0_tcstatus((read_tc_c0_tcstatus() & ~TCSTATUS_IXMT) \| TCSTATUS_A);
	155
	156	write_tc_c0_tchalt(0);
	157
	158	/* enable the VPE */
	159	write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() \| VPECONF0_VPA);
	160
	161	/* stack pointer */
	162	write_tc_gpr_sp( __KSTK_TOS(idle));
	163
	164	/* global pointer */
dc8f6029	165	write_tc_gpr_gp((unsigned long)gp);
340ee4b9	166
41c594ab	167	flush_icache_range((unsigned long)gp,
70342287	168	(unsigned long)(gp + sizeof(struct thread_info)));
340ee4b9 RB	169
	170	/* finally out of configuration and into chaos */
	171	clear_c0_mvpcontrol(MVPCONTROL_VPC);
	172
	173	evpe(EVPE_ENABLE);
d595d423 PB	174
d595d423 PB	175	return 0;
340ee4b9 RB	176	}
340ee4b9 RB	177
87353d8a RB	178	/*
	179	* Common setup before any secondaries are started
	180	* Make sure all CPU's are in a sensible state before we boot any of the
39b8d525	181	* secondaries
87353d8a RB	182	*/
87353d8a RB	183	static void __init vsmp_smp_setup(void)
340ee4b9	184	{
87353d8a RB	185	unsigned int mvpconf0, ntc, tc, ncpu = 0;
87353d8a RB	186	unsigned int nvpe;
340ee4b9	187
f088fc84 RB	188	#ifdef CONFIG_MIPS_MT_FPAFF
	189	/* If we have an FPU, enroll ourselves in the FPU-full mask */
	190	if (cpu_has_fpu)
8dd92891	191	cpumask_set_cpu(0, &mt_fpu_cpumask);
f088fc84	192	#endif /* CONFIG_MIPS_MT_FPAFF */
87353d8a RB	193	if (!cpu_has_mipsmt)
87353d8a RB	194	return;
f088fc84	195
87353d8a RB	196	/* disable MT so we can configure */
	197	dvpe();
	198	dmt();
340ee4b9	199
87353d8a RB	200	/* Put MVPE's into 'configuration state' */
87353d8a RB	201	set_c0_mvpcontrol(MVPCONTROL_VPC);
340ee4b9	202
87353d8a RB	203	mvpconf0 = read_c0_mvpconf0();
87353d8a RB	204	ntc = (mvpconf0 & MVPCONF0_PTC) >> MVPCONF0_PTC_SHIFT;
340ee4b9	205
87353d8a RB	206	nvpe = ((mvpconf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT) + 1;
87353d8a RB	207	smp_num_siblings = nvpe;
340ee4b9	208
87353d8a RB	209	/* we'll always have more TC's than VPE's, so loop setting everything
	210	to a sensible state */
	211	for (tc = 0; tc <= ntc; tc++) {
	212	settc(tc);
340ee4b9	213
39b8d525 RB	214	smvp_tc_init(tc, mvpconf0);
39b8d525 RB	215	ncpu = smvp_vpe_init(tc, mvpconf0, ncpu);
87353d8a	216	}
340ee4b9	217
87353d8a RB	218	/* Release config state */
	219	clear_c0_mvpcontrol(MVPCONTROL_VPC);
	220
	221	/* We'll wait until starting the secondaries before starting MVPE */
	222
	223	printk(KERN_INFO "Detected %i available secondary CPU(s)\n", ncpu);
	224	}
	225
	226	static void __init vsmp_prepare_cpus(unsigned int max_cpus)
	227	{
	228	mips_mt_set_cpuoptions();
340ee4b9	229	}
87353d8a	230
ff2c8252	231	const struct plat_smp_ops vsmp_smp_ops = {
1eed4004 PB	232	.send_ipi_single = mips_smp_send_ipi_single,
1eed4004 PB	233	.send_ipi_mask = mips_smp_send_ipi_mask,
87353d8a RB	234	.init_secondary = vsmp_init_secondary,
87353d8a RB	235	.smp_finish = vsmp_smp_finish,
87353d8a RB	236	.boot_secondary = vsmp_boot_secondary,
	237	.smp_setup = vsmp_smp_setup,
	238	.prepare_cpus = vsmp_prepare_cpus,
	239	};
d6d3c9af	240