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1da177e4 LT |
1 | /* |
2 | * This program is free software; you can redistribute it and/or | |
3 | * modify it under the terms of the GNU General Public License | |
4 | * as published by the Free Software Foundation; either version 2 | |
5 | * of the License, or (at your option) any later version. | |
6 | * | |
7 | * This program is distributed in the hope that it will be useful, | |
8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
10 | * GNU General Public License for more details. | |
11 | * | |
12 | * You should have received a copy of the GNU General Public License | |
13 | * along with this program; if not, write to the Free Software | |
14 | * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
15 | * | |
16 | * Copyright (C) 2000, 2001 Kanoj Sarcar | |
17 | * Copyright (C) 2000, 2001 Ralf Baechle | |
18 | * Copyright (C) 2000, 2001 Silicon Graphics, Inc. | |
19 | * Copyright (C) 2000, 2001, 2003 Broadcom Corporation | |
20 | */ | |
21 | #include <linux/cache.h> | |
22 | #include <linux/delay.h> | |
23 | #include <linux/init.h> | |
24 | #include <linux/interrupt.h> | |
631330f5 | 25 | #include <linux/smp.h> |
1da177e4 LT |
26 | #include <linux/spinlock.h> |
27 | #include <linux/threads.h> | |
28 | #include <linux/module.h> | |
29 | #include <linux/time.h> | |
30 | #include <linux/timex.h> | |
31 | #include <linux/sched.h> | |
32 | #include <linux/cpumask.h> | |
1e35aaba | 33 | #include <linux/cpu.h> |
4e950f6f | 34 | #include <linux/err.h> |
8f99a162 | 35 | #include <linux/ftrace.h> |
1da177e4 | 36 | |
60063497 | 37 | #include <linux/atomic.h> |
1da177e4 LT |
38 | #include <asm/cpu.h> |
39 | #include <asm/processor.h> | |
bdc92d74 | 40 | #include <asm/idle.h> |
39b8d525 | 41 | #include <asm/r4k-timer.h> |
1da177e4 | 42 | #include <asm/mmu_context.h> |
7bcf7717 | 43 | #include <asm/time.h> |
b81947c6 | 44 | #include <asm/setup.h> |
1da177e4 | 45 | |
1b2bc75c | 46 | volatile cpumask_t cpu_callin_map; /* Bitmask of started secondaries */ |
2dc2ae34 | 47 | |
1da177e4 | 48 | int __cpu_number_map[NR_CPUS]; /* Map physical to logical */ |
2dc2ae34 DD |
49 | EXPORT_SYMBOL(__cpu_number_map); |
50 | ||
1da177e4 | 51 | int __cpu_logical_map[NR_CPUS]; /* Map logical to physical */ |
2dc2ae34 | 52 | EXPORT_SYMBOL(__cpu_logical_map); |
1da177e4 | 53 | |
0ab7aefc RB |
54 | /* Number of TCs (or siblings in Intel speak) per CPU core */ |
55 | int smp_num_siblings = 1; | |
56 | EXPORT_SYMBOL(smp_num_siblings); | |
57 | ||
58 | /* representing the TCs (or siblings in Intel speak) of each logical CPU */ | |
59 | cpumask_t cpu_sibling_map[NR_CPUS] __read_mostly; | |
60 | EXPORT_SYMBOL(cpu_sibling_map); | |
61 | ||
bda4584c HC |
62 | /* representing the core map of multi-core chips of each logical CPU */ |
63 | cpumask_t cpu_core_map[NR_CPUS] __read_mostly; | |
64 | EXPORT_SYMBOL(cpu_core_map); | |
65 | ||
0ab7aefc RB |
66 | /* representing cpus for which sibling maps can be computed */ |
67 | static cpumask_t cpu_sibling_setup_map; | |
68 | ||
bda4584c HC |
69 | /* representing cpus for which core maps can be computed */ |
70 | static cpumask_t cpu_core_setup_map; | |
71 | ||
76306f42 PB |
72 | cpumask_t cpu_coherent_mask; |
73 | ||
0ab7aefc RB |
74 | static inline void set_cpu_sibling_map(int cpu) |
75 | { | |
76 | int i; | |
77 | ||
78 | cpu_set(cpu, cpu_sibling_setup_map); | |
79 | ||
80 | if (smp_num_siblings > 1) { | |
81 | for_each_cpu_mask(i, cpu_sibling_setup_map) { | |
bda4584c HC |
82 | if (cpu_data[cpu].package == cpu_data[i].package && |
83 | cpu_data[cpu].core == cpu_data[i].core) { | |
0ab7aefc RB |
84 | cpu_set(i, cpu_sibling_map[cpu]); |
85 | cpu_set(cpu, cpu_sibling_map[i]); | |
86 | } | |
87 | } | |
88 | } else | |
89 | cpu_set(cpu, cpu_sibling_map[cpu]); | |
90 | } | |
91 | ||
bda4584c HC |
92 | static inline void set_cpu_core_map(int cpu) |
93 | { | |
94 | int i; | |
95 | ||
96 | cpu_set(cpu, cpu_core_setup_map); | |
97 | ||
98 | for_each_cpu_mask(i, cpu_core_setup_map) { | |
99 | if (cpu_data[cpu].package == cpu_data[i].package) { | |
100 | cpu_set(i, cpu_core_map[cpu]); | |
101 | cpu_set(cpu, cpu_core_map[i]); | |
102 | } | |
103 | } | |
104 | } | |
105 | ||
87353d8a | 106 | struct plat_smp_ops *mp_ops; |
82d45de6 | 107 | EXPORT_SYMBOL(mp_ops); |
87353d8a | 108 | |
078a55fc | 109 | void register_smp_ops(struct plat_smp_ops *ops) |
87353d8a | 110 | { |
83738e30 TS |
111 | if (mp_ops) |
112 | printk(KERN_WARNING "Overriding previously set SMP ops\n"); | |
87353d8a RB |
113 | |
114 | mp_ops = ops; | |
115 | } | |
116 | ||
1da177e4 LT |
117 | /* |
118 | * First C code run on the secondary CPUs after being started up by | |
119 | * the master. | |
120 | */ | |
078a55fc | 121 | asmlinkage void start_secondary(void) |
1da177e4 | 122 | { |
5bfb5d69 | 123 | unsigned int cpu; |
1da177e4 LT |
124 | |
125 | cpu_probe(); | |
126 | cpu_report(); | |
6650df3c | 127 | per_cpu_trap_init(false); |
7bcf7717 | 128 | mips_clockevent_init(); |
87353d8a | 129 | mp_ops->init_secondary(); |
1da177e4 LT |
130 | |
131 | /* | |
132 | * XXX parity protection should be folded in here when it's converted | |
133 | * to an option instead of something based on .cputype | |
134 | */ | |
135 | ||
136 | calibrate_delay(); | |
5bfb5d69 NP |
137 | preempt_disable(); |
138 | cpu = smp_processor_id(); | |
1da177e4 LT |
139 | cpu_data[cpu].udelay_val = loops_per_jiffy; |
140 | ||
76306f42 | 141 | cpu_set(cpu, cpu_coherent_mask); |
e545a614 MS |
142 | notify_cpu_starting(cpu); |
143 | ||
b9a09a06 YZ |
144 | set_cpu_online(cpu, true); |
145 | ||
0ab7aefc | 146 | set_cpu_sibling_map(cpu); |
bda4584c | 147 | set_cpu_core_map(cpu); |
1da177e4 LT |
148 | |
149 | cpu_set(cpu, cpu_callin_map); | |
150 | ||
cf9bfe55 | 151 | synchronise_count_slave(cpu); |
39b8d525 | 152 | |
b789ad63 YZ |
153 | /* |
154 | * irq will be enabled in ->smp_finish(), enabling it too early | |
155 | * is dangerous. | |
156 | */ | |
157 | WARN_ON_ONCE(!irqs_disabled()); | |
5309bdac YZ |
158 | mp_ops->smp_finish(); |
159 | ||
cdbedc61 | 160 | cpu_startup_entry(CPUHP_ONLINE); |
1da177e4 LT |
161 | } |
162 | ||
2f304c0a JA |
163 | /* |
164 | * Call into both interrupt handlers, as we share the IPI for them | |
165 | */ | |
8f99a162 | 166 | void __irq_entry smp_call_function_interrupt(void) |
1da177e4 | 167 | { |
1da177e4 | 168 | irq_enter(); |
2f304c0a | 169 | generic_smp_call_function_interrupt(); |
1da177e4 | 170 | irq_exit(); |
b4b2917c PW |
171 | } |
172 | ||
1da177e4 LT |
173 | static void stop_this_cpu(void *dummy) |
174 | { | |
175 | /* | |
176 | * Remove this CPU: | |
177 | */ | |
0b5f9c00 | 178 | set_cpu_online(smp_processor_id(), false); |
7920c4d6 RB |
179 | for (;;) { |
180 | if (cpu_wait) | |
181 | (*cpu_wait)(); /* Wait if available. */ | |
182 | } | |
1da177e4 LT |
183 | } |
184 | ||
185 | void smp_send_stop(void) | |
186 | { | |
8691e5a8 | 187 | smp_call_function(stop_this_cpu, NULL, 0); |
1da177e4 LT |
188 | } |
189 | ||
190 | void __init smp_cpus_done(unsigned int max_cpus) | |
191 | { | |
1da177e4 LT |
192 | } |
193 | ||
194 | /* called from main before smp_init() */ | |
195 | void __init smp_prepare_cpus(unsigned int max_cpus) | |
196 | { | |
1da177e4 LT |
197 | init_new_context(current, &init_mm); |
198 | current_thread_info()->cpu = 0; | |
87353d8a | 199 | mp_ops->prepare_cpus(max_cpus); |
0ab7aefc | 200 | set_cpu_sibling_map(0); |
bda4584c | 201 | set_cpu_core_map(0); |
320e6aba | 202 | #ifndef CONFIG_HOTPLUG_CPU |
0b5f9c00 | 203 | init_cpu_present(cpu_possible_mask); |
320e6aba | 204 | #endif |
76306f42 | 205 | cpumask_copy(&cpu_coherent_mask, cpu_possible_mask); |
1da177e4 LT |
206 | } |
207 | ||
208 | /* preload SMP state for boot cpu */ | |
28eb0e46 | 209 | void smp_prepare_boot_cpu(void) |
1da177e4 | 210 | { |
4037ac6e RR |
211 | set_cpu_possible(0, true); |
212 | set_cpu_online(0, true); | |
1da177e4 LT |
213 | cpu_set(0, cpu_callin_map); |
214 | } | |
215 | ||
078a55fc | 216 | int __cpu_up(unsigned int cpu, struct task_struct *tidle) |
1da177e4 | 217 | { |
360014a3 | 218 | mp_ops->boot_secondary(cpu, tidle); |
1da177e4 | 219 | |
b727a602 RB |
220 | /* |
221 | * Trust is futile. We should really have timeouts ... | |
222 | */ | |
1da177e4 LT |
223 | while (!cpu_isset(cpu, cpu_callin_map)) |
224 | udelay(100); | |
1da177e4 | 225 | |
cf9bfe55 | 226 | synchronise_count_master(cpu); |
1da177e4 LT |
227 | return 0; |
228 | } | |
229 | ||
1da177e4 LT |
230 | /* Not really SMP stuff ... */ |
231 | int setup_profiling_timer(unsigned int multiplier) | |
232 | { | |
233 | return 0; | |
234 | } | |
235 | ||
236 | static void flush_tlb_all_ipi(void *info) | |
237 | { | |
238 | local_flush_tlb_all(); | |
239 | } | |
240 | ||
241 | void flush_tlb_all(void) | |
242 | { | |
15c8b6c1 | 243 | on_each_cpu(flush_tlb_all_ipi, NULL, 1); |
1da177e4 LT |
244 | } |
245 | ||
246 | static void flush_tlb_mm_ipi(void *mm) | |
247 | { | |
248 | local_flush_tlb_mm((struct mm_struct *)mm); | |
249 | } | |
250 | ||
25969354 RB |
251 | /* |
252 | * Special Variant of smp_call_function for use by TLB functions: | |
253 | * | |
254 | * o No return value | |
255 | * o collapses to normal function call on UP kernels | |
256 | * o collapses to normal function call on systems with a single shared | |
257 | * primary cache. | |
25969354 RB |
258 | */ |
259 | static inline void smp_on_other_tlbs(void (*func) (void *info), void *info) | |
260 | { | |
8691e5a8 | 261 | smp_call_function(func, info, 1); |
25969354 RB |
262 | } |
263 | ||
264 | static inline void smp_on_each_tlb(void (*func) (void *info), void *info) | |
265 | { | |
266 | preempt_disable(); | |
267 | ||
268 | smp_on_other_tlbs(func, info); | |
269 | func(info); | |
270 | ||
271 | preempt_enable(); | |
272 | } | |
273 | ||
1da177e4 LT |
274 | /* |
275 | * The following tlb flush calls are invoked when old translations are | |
276 | * being torn down, or pte attributes are changing. For single threaded | |
277 | * address spaces, a new context is obtained on the current cpu, and tlb | |
278 | * context on other cpus are invalidated to force a new context allocation | |
279 | * at switch_mm time, should the mm ever be used on other cpus. For | |
280 | * multithreaded address spaces, intercpu interrupts have to be sent. | |
281 | * Another case where intercpu interrupts are required is when the target | |
282 | * mm might be active on another cpu (eg debuggers doing the flushes on | |
283 | * behalf of debugees, kswapd stealing pages from another process etc). | |
284 | * Kanoj 07/00. | |
285 | */ | |
286 | ||
287 | void flush_tlb_mm(struct mm_struct *mm) | |
288 | { | |
289 | preempt_disable(); | |
290 | ||
291 | if ((atomic_read(&mm->mm_users) != 1) || (current->mm != mm)) { | |
c50cade9 | 292 | smp_on_other_tlbs(flush_tlb_mm_ipi, mm); |
1da177e4 | 293 | } else { |
b5eb5511 RB |
294 | unsigned int cpu; |
295 | ||
0b5f9c00 RR |
296 | for_each_online_cpu(cpu) { |
297 | if (cpu != smp_processor_id() && cpu_context(cpu, mm)) | |
b5eb5511 | 298 | cpu_context(cpu, mm) = 0; |
0b5f9c00 | 299 | } |
1da177e4 LT |
300 | } |
301 | local_flush_tlb_mm(mm); | |
302 | ||
303 | preempt_enable(); | |
304 | } | |
305 | ||
306 | struct flush_tlb_data { | |
307 | struct vm_area_struct *vma; | |
308 | unsigned long addr1; | |
309 | unsigned long addr2; | |
310 | }; | |
311 | ||
312 | static void flush_tlb_range_ipi(void *info) | |
313 | { | |
c50cade9 | 314 | struct flush_tlb_data *fd = info; |
1da177e4 LT |
315 | |
316 | local_flush_tlb_range(fd->vma, fd->addr1, fd->addr2); | |
317 | } | |
318 | ||
319 | void flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end) | |
320 | { | |
321 | struct mm_struct *mm = vma->vm_mm; | |
322 | ||
323 | preempt_disable(); | |
324 | if ((atomic_read(&mm->mm_users) != 1) || (current->mm != mm)) { | |
89a8a5a6 RB |
325 | struct flush_tlb_data fd = { |
326 | .vma = vma, | |
327 | .addr1 = start, | |
328 | .addr2 = end, | |
329 | }; | |
1da177e4 | 330 | |
c50cade9 | 331 | smp_on_other_tlbs(flush_tlb_range_ipi, &fd); |
1da177e4 | 332 | } else { |
b5eb5511 RB |
333 | unsigned int cpu; |
334 | ||
0b5f9c00 RR |
335 | for_each_online_cpu(cpu) { |
336 | if (cpu != smp_processor_id() && cpu_context(cpu, mm)) | |
b5eb5511 | 337 | cpu_context(cpu, mm) = 0; |
0b5f9c00 | 338 | } |
1da177e4 LT |
339 | } |
340 | local_flush_tlb_range(vma, start, end); | |
341 | preempt_enable(); | |
342 | } | |
343 | ||
344 | static void flush_tlb_kernel_range_ipi(void *info) | |
345 | { | |
c50cade9 | 346 | struct flush_tlb_data *fd = info; |
1da177e4 LT |
347 | |
348 | local_flush_tlb_kernel_range(fd->addr1, fd->addr2); | |
349 | } | |
350 | ||
351 | void flush_tlb_kernel_range(unsigned long start, unsigned long end) | |
352 | { | |
89a8a5a6 RB |
353 | struct flush_tlb_data fd = { |
354 | .addr1 = start, | |
355 | .addr2 = end, | |
356 | }; | |
1da177e4 | 357 | |
15c8b6c1 | 358 | on_each_cpu(flush_tlb_kernel_range_ipi, &fd, 1); |
1da177e4 LT |
359 | } |
360 | ||
361 | static void flush_tlb_page_ipi(void *info) | |
362 | { | |
c50cade9 | 363 | struct flush_tlb_data *fd = info; |
1da177e4 LT |
364 | |
365 | local_flush_tlb_page(fd->vma, fd->addr1); | |
366 | } | |
367 | ||
368 | void flush_tlb_page(struct vm_area_struct *vma, unsigned long page) | |
369 | { | |
370 | preempt_disable(); | |
371 | if ((atomic_read(&vma->vm_mm->mm_users) != 1) || (current->mm != vma->vm_mm)) { | |
89a8a5a6 RB |
372 | struct flush_tlb_data fd = { |
373 | .vma = vma, | |
374 | .addr1 = page, | |
375 | }; | |
1da177e4 | 376 | |
c50cade9 | 377 | smp_on_other_tlbs(flush_tlb_page_ipi, &fd); |
1da177e4 | 378 | } else { |
b5eb5511 RB |
379 | unsigned int cpu; |
380 | ||
0b5f9c00 RR |
381 | for_each_online_cpu(cpu) { |
382 | if (cpu != smp_processor_id() && cpu_context(cpu, vma->vm_mm)) | |
b5eb5511 | 383 | cpu_context(cpu, vma->vm_mm) = 0; |
0b5f9c00 | 384 | } |
1da177e4 LT |
385 | } |
386 | local_flush_tlb_page(vma, page); | |
387 | preempt_enable(); | |
388 | } | |
389 | ||
390 | static void flush_tlb_one_ipi(void *info) | |
391 | { | |
392 | unsigned long vaddr = (unsigned long) info; | |
393 | ||
394 | local_flush_tlb_one(vaddr); | |
395 | } | |
396 | ||
397 | void flush_tlb_one(unsigned long vaddr) | |
398 | { | |
25969354 | 399 | smp_on_each_tlb(flush_tlb_one_ipi, (void *) vaddr); |
1da177e4 LT |
400 | } |
401 | ||
402 | EXPORT_SYMBOL(flush_tlb_page); | |
403 | EXPORT_SYMBOL(flush_tlb_one); | |
7aa1c8f4 RB |
404 | |
405 | #if defined(CONFIG_KEXEC) | |
406 | void (*dump_ipi_function_ptr)(void *) = NULL; | |
407 | void dump_send_ipi(void (*dump_ipi_callback)(void *)) | |
408 | { | |
409 | int i; | |
410 | int cpu = smp_processor_id(); | |
411 | ||
412 | dump_ipi_function_ptr = dump_ipi_callback; | |
413 | smp_mb(); | |
414 | for_each_online_cpu(i) | |
415 | if (i != cpu) | |
416 | mp_ops->send_ipi_single(i, SMP_DUMP); | |
417 | ||
418 | } | |
419 | EXPORT_SYMBOL(dump_send_ipi); | |
420 | #endif | |
cc7964af PB |
421 | |
422 | #ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST | |
423 | ||
424 | static DEFINE_PER_CPU(atomic_t, tick_broadcast_count); | |
425 | static DEFINE_PER_CPU(struct call_single_data, tick_broadcast_csd); | |
426 | ||
427 | void tick_broadcast(const struct cpumask *mask) | |
428 | { | |
429 | atomic_t *count; | |
430 | struct call_single_data *csd; | |
431 | int cpu; | |
432 | ||
433 | for_each_cpu(cpu, mask) { | |
434 | count = &per_cpu(tick_broadcast_count, cpu); | |
435 | csd = &per_cpu(tick_broadcast_csd, cpu); | |
436 | ||
437 | if (atomic_inc_return(count) == 1) | |
438 | smp_call_function_single_async(cpu, csd); | |
439 | } | |
440 | } | |
441 | ||
442 | static void tick_broadcast_callee(void *info) | |
443 | { | |
444 | int cpu = smp_processor_id(); | |
445 | tick_receive_broadcast(); | |
446 | atomic_set(&per_cpu(tick_broadcast_count, cpu), 0); | |
447 | } | |
448 | ||
449 | static int __init tick_broadcast_init(void) | |
450 | { | |
451 | struct call_single_data *csd; | |
452 | int cpu; | |
453 | ||
454 | for (cpu = 0; cpu < NR_CPUS; cpu++) { | |
455 | csd = &per_cpu(tick_broadcast_csd, cpu); | |
456 | csd->func = tick_broadcast_callee; | |
457 | } | |
458 | ||
459 | return 0; | |
460 | } | |
461 | early_initcall(tick_broadcast_init); | |
462 | ||
463 | #endif /* CONFIG_GENERIC_CLOCKEVENTS_BROADCAST */ |