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1da177e4 LT |
1 | /* |
2 | * This program is free software; you can redistribute it and/or | |
3 | * modify it under the terms of the GNU General Public License | |
4 | * as published by the Free Software Foundation; either version 2 | |
5 | * of the License, or (at your option) any later version. | |
6 | * | |
7 | * This program is distributed in the hope that it will be useful, | |
8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
10 | * GNU General Public License for more details. | |
11 | * | |
12 | * You should have received a copy of the GNU General Public License | |
13 | * along with this program; if not, write to the Free Software | |
14 | * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
15 | * | |
16 | * Copyright (C) 2000, 2001 Kanoj Sarcar | |
17 | * Copyright (C) 2000, 2001 Ralf Baechle | |
18 | * Copyright (C) 2000, 2001 Silicon Graphics, Inc. | |
19 | * Copyright (C) 2000, 2001, 2003 Broadcom Corporation | |
20 | */ | |
21 | #include <linux/cache.h> | |
22 | #include <linux/delay.h> | |
23 | #include <linux/init.h> | |
24 | #include <linux/interrupt.h> | |
631330f5 | 25 | #include <linux/smp.h> |
1da177e4 LT |
26 | #include <linux/spinlock.h> |
27 | #include <linux/threads.h> | |
d9d54177 | 28 | #include <linux/export.h> |
1da177e4 LT |
29 | #include <linux/time.h> |
30 | #include <linux/timex.h> | |
589ee628 | 31 | #include <linux/sched/mm.h> |
1da177e4 | 32 | #include <linux/cpumask.h> |
1e35aaba | 33 | #include <linux/cpu.h> |
4e950f6f | 34 | #include <linux/err.h> |
8f99a162 | 35 | #include <linux/ftrace.h> |
fbde2d7d QY |
36 | #include <linux/irqdomain.h> |
37 | #include <linux/of.h> | |
38 | #include <linux/of_irq.h> | |
1da177e4 | 39 | |
60063497 | 40 | #include <linux/atomic.h> |
1da177e4 LT |
41 | #include <asm/cpu.h> |
42 | #include <asm/processor.h> | |
bdc92d74 | 43 | #include <asm/idle.h> |
39b8d525 | 44 | #include <asm/r4k-timer.h> |
fbde2d7d | 45 | #include <asm/mips-cpc.h> |
1da177e4 | 46 | #include <asm/mmu_context.h> |
7bcf7717 | 47 | #include <asm/time.h> |
b81947c6 | 48 | #include <asm/setup.h> |
e060f6ed | 49 | #include <asm/maar.h> |
1da177e4 | 50 | |
1da177e4 | 51 | int __cpu_number_map[NR_CPUS]; /* Map physical to logical */ |
2dc2ae34 DD |
52 | EXPORT_SYMBOL(__cpu_number_map); |
53 | ||
1da177e4 | 54 | int __cpu_logical_map[NR_CPUS]; /* Map logical to physical */ |
2dc2ae34 | 55 | EXPORT_SYMBOL(__cpu_logical_map); |
1da177e4 | 56 | |
0ab7aefc RB |
57 | /* Number of TCs (or siblings in Intel speak) per CPU core */ |
58 | int smp_num_siblings = 1; | |
59 | EXPORT_SYMBOL(smp_num_siblings); | |
60 | ||
61 | /* representing the TCs (or siblings in Intel speak) of each logical CPU */ | |
62 | cpumask_t cpu_sibling_map[NR_CPUS] __read_mostly; | |
63 | EXPORT_SYMBOL(cpu_sibling_map); | |
64 | ||
bda4584c HC |
65 | /* representing the core map of multi-core chips of each logical CPU */ |
66 | cpumask_t cpu_core_map[NR_CPUS] __read_mostly; | |
67 | EXPORT_SYMBOL(cpu_core_map); | |
68 | ||
a00eeede MR |
69 | static DECLARE_COMPLETION(cpu_running); |
70 | ||
cccf34e9 MC |
71 | /* |
72 | * A logcal cpu mask containing only one VPE per core to | |
73 | * reduce the number of IPIs on large MT systems. | |
74 | */ | |
640511ae | 75 | cpumask_t cpu_foreign_map[NR_CPUS] __read_mostly; |
cccf34e9 MC |
76 | EXPORT_SYMBOL(cpu_foreign_map); |
77 | ||
0ab7aefc RB |
78 | /* representing cpus for which sibling maps can be computed */ |
79 | static cpumask_t cpu_sibling_setup_map; | |
80 | ||
bda4584c HC |
81 | /* representing cpus for which core maps can be computed */ |
82 | static cpumask_t cpu_core_setup_map; | |
83 | ||
76306f42 PB |
84 | cpumask_t cpu_coherent_mask; |
85 | ||
fbde2d7d QY |
86 | #ifdef CONFIG_GENERIC_IRQ_IPI |
87 | static struct irq_desc *call_desc; | |
88 | static struct irq_desc *sched_desc; | |
89 | #endif | |
90 | ||
0ab7aefc RB |
91 | static inline void set_cpu_sibling_map(int cpu) |
92 | { | |
93 | int i; | |
94 | ||
8dd92891 | 95 | cpumask_set_cpu(cpu, &cpu_sibling_setup_map); |
0ab7aefc RB |
96 | |
97 | if (smp_num_siblings > 1) { | |
8dd92891 | 98 | for_each_cpu(i, &cpu_sibling_setup_map) { |
bda4584c HC |
99 | if (cpu_data[cpu].package == cpu_data[i].package && |
100 | cpu_data[cpu].core == cpu_data[i].core) { | |
8dd92891 RR |
101 | cpumask_set_cpu(i, &cpu_sibling_map[cpu]); |
102 | cpumask_set_cpu(cpu, &cpu_sibling_map[i]); | |
0ab7aefc RB |
103 | } |
104 | } | |
105 | } else | |
8dd92891 | 106 | cpumask_set_cpu(cpu, &cpu_sibling_map[cpu]); |
0ab7aefc RB |
107 | } |
108 | ||
bda4584c HC |
109 | static inline void set_cpu_core_map(int cpu) |
110 | { | |
111 | int i; | |
112 | ||
8dd92891 | 113 | cpumask_set_cpu(cpu, &cpu_core_setup_map); |
bda4584c | 114 | |
8dd92891 | 115 | for_each_cpu(i, &cpu_core_setup_map) { |
bda4584c | 116 | if (cpu_data[cpu].package == cpu_data[i].package) { |
8dd92891 RR |
117 | cpumask_set_cpu(i, &cpu_core_map[cpu]); |
118 | cpumask_set_cpu(cpu, &cpu_core_map[i]); | |
bda4584c HC |
119 | } |
120 | } | |
121 | } | |
122 | ||
cccf34e9 MC |
123 | /* |
124 | * Calculate a new cpu_foreign_map mask whenever a | |
125 | * new cpu appears or disappears. | |
126 | */ | |
826e99be | 127 | void calculate_cpu_foreign_map(void) |
cccf34e9 MC |
128 | { |
129 | int i, k, core_present; | |
130 | cpumask_t temp_foreign_map; | |
131 | ||
132 | /* Re-calculate the mask */ | |
d825c06b | 133 | cpumask_clear(&temp_foreign_map); |
cccf34e9 MC |
134 | for_each_online_cpu(i) { |
135 | core_present = 0; | |
136 | for_each_cpu(k, &temp_foreign_map) | |
137 | if (cpu_data[i].package == cpu_data[k].package && | |
138 | cpu_data[i].core == cpu_data[k].core) | |
139 | core_present = 1; | |
140 | if (!core_present) | |
141 | cpumask_set_cpu(i, &temp_foreign_map); | |
142 | } | |
143 | ||
640511ae JH |
144 | for_each_online_cpu(i) |
145 | cpumask_andnot(&cpu_foreign_map[i], | |
146 | &temp_foreign_map, &cpu_sibling_map[i]); | |
cccf34e9 MC |
147 | } |
148 | ||
87353d8a | 149 | struct plat_smp_ops *mp_ops; |
82d45de6 | 150 | EXPORT_SYMBOL(mp_ops); |
87353d8a | 151 | |
078a55fc | 152 | void register_smp_ops(struct plat_smp_ops *ops) |
87353d8a | 153 | { |
83738e30 TS |
154 | if (mp_ops) |
155 | printk(KERN_WARNING "Overriding previously set SMP ops\n"); | |
87353d8a RB |
156 | |
157 | mp_ops = ops; | |
158 | } | |
159 | ||
fbde2d7d QY |
160 | #ifdef CONFIG_GENERIC_IRQ_IPI |
161 | void mips_smp_send_ipi_single(int cpu, unsigned int action) | |
162 | { | |
163 | mips_smp_send_ipi_mask(cpumask_of(cpu), action); | |
164 | } | |
165 | ||
166 | void mips_smp_send_ipi_mask(const struct cpumask *mask, unsigned int action) | |
167 | { | |
168 | unsigned long flags; | |
169 | unsigned int core; | |
170 | int cpu; | |
171 | ||
172 | local_irq_save(flags); | |
173 | ||
174 | switch (action) { | |
175 | case SMP_CALL_FUNCTION: | |
176 | __ipi_send_mask(call_desc, mask); | |
177 | break; | |
178 | ||
179 | case SMP_RESCHEDULE_YOURSELF: | |
180 | __ipi_send_mask(sched_desc, mask); | |
181 | break; | |
182 | ||
183 | default: | |
184 | BUG(); | |
185 | } | |
186 | ||
187 | if (mips_cpc_present()) { | |
188 | for_each_cpu(cpu, mask) { | |
189 | core = cpu_data[cpu].core; | |
190 | ||
191 | if (core == current_cpu_data.core) | |
192 | continue; | |
193 | ||
194 | while (!cpumask_test_cpu(cpu, &cpu_coherent_mask)) { | |
4b640136 | 195 | mips_cm_lock_other(core, 0); |
fbde2d7d QY |
196 | mips_cpc_lock_other(core); |
197 | write_cpc_co_cmd(CPC_Cx_CMD_PWRUP); | |
198 | mips_cpc_unlock_other(); | |
4b640136 | 199 | mips_cm_unlock_other(); |
fbde2d7d QY |
200 | } |
201 | } | |
202 | } | |
203 | ||
204 | local_irq_restore(flags); | |
205 | } | |
206 | ||
207 | ||
208 | static irqreturn_t ipi_resched_interrupt(int irq, void *dev_id) | |
209 | { | |
210 | scheduler_ipi(); | |
211 | ||
212 | return IRQ_HANDLED; | |
213 | } | |
214 | ||
215 | static irqreturn_t ipi_call_interrupt(int irq, void *dev_id) | |
216 | { | |
217 | generic_smp_call_function_interrupt(); | |
218 | ||
219 | return IRQ_HANDLED; | |
220 | } | |
221 | ||
222 | static struct irqaction irq_resched = { | |
223 | .handler = ipi_resched_interrupt, | |
224 | .flags = IRQF_PERCPU, | |
225 | .name = "IPI resched" | |
226 | }; | |
227 | ||
228 | static struct irqaction irq_call = { | |
229 | .handler = ipi_call_interrupt, | |
230 | .flags = IRQF_PERCPU, | |
231 | .name = "IPI call" | |
232 | }; | |
233 | ||
7688c539 | 234 | static void smp_ipi_init_one(unsigned int virq, |
fbde2d7d QY |
235 | struct irqaction *action) |
236 | { | |
237 | int ret; | |
238 | ||
239 | irq_set_handler(virq, handle_percpu_irq); | |
240 | ret = setup_irq(virq, action); | |
241 | BUG_ON(ret); | |
242 | } | |
243 | ||
7688c539 MR |
244 | static unsigned int call_virq, sched_virq; |
245 | ||
246 | int mips_smp_ipi_allocate(const struct cpumask *mask) | |
fbde2d7d | 247 | { |
7688c539 | 248 | int virq; |
fbde2d7d QY |
249 | struct irq_domain *ipidomain; |
250 | struct device_node *node; | |
251 | ||
252 | node = of_irq_find_parent(of_root); | |
253 | ipidomain = irq_find_matching_host(node, DOMAIN_BUS_IPI); | |
254 | ||
255 | /* | |
256 | * Some platforms have half DT setup. So if we found irq node but | |
257 | * didn't find an ipidomain, try to search for one that is not in the | |
258 | * DT. | |
259 | */ | |
260 | if (node && !ipidomain) | |
261 | ipidomain = irq_find_matching_host(NULL, DOMAIN_BUS_IPI); | |
262 | ||
578bffc8 PB |
263 | /* |
264 | * There are systems which only use IPI domains some of the time, | |
265 | * depending upon configuration we don't know until runtime. An | |
266 | * example is Malta where we may compile in support for GIC & the | |
267 | * MT ASE, but run on a system which has multiple VPEs in a single | |
268 | * core and doesn't include a GIC. Until all IPI implementations | |
269 | * have been converted to use IPI domains the best we can do here | |
270 | * is to return & hope some other code sets up the IPIs. | |
271 | */ | |
272 | if (!ipidomain) | |
273 | return 0; | |
fbde2d7d | 274 | |
7688c539 MR |
275 | virq = irq_reserve_ipi(ipidomain, mask); |
276 | BUG_ON(!virq); | |
277 | if (!call_virq) | |
278 | call_virq = virq; | |
fbde2d7d | 279 | |
7688c539 MR |
280 | virq = irq_reserve_ipi(ipidomain, mask); |
281 | BUG_ON(!virq); | |
282 | if (!sched_virq) | |
283 | sched_virq = virq; | |
fbde2d7d QY |
284 | |
285 | if (irq_domain_is_ipi_per_cpu(ipidomain)) { | |
286 | int cpu; | |
287 | ||
7688c539 | 288 | for_each_cpu(cpu, mask) { |
fbde2d7d QY |
289 | smp_ipi_init_one(call_virq + cpu, &irq_call); |
290 | smp_ipi_init_one(sched_virq + cpu, &irq_resched); | |
291 | } | |
292 | } else { | |
293 | smp_ipi_init_one(call_virq, &irq_call); | |
294 | smp_ipi_init_one(sched_virq, &irq_resched); | |
295 | } | |
296 | ||
7688c539 MR |
297 | return 0; |
298 | } | |
299 | ||
300 | int mips_smp_ipi_free(const struct cpumask *mask) | |
301 | { | |
302 | struct irq_domain *ipidomain; | |
303 | struct device_node *node; | |
304 | ||
305 | node = of_irq_find_parent(of_root); | |
306 | ipidomain = irq_find_matching_host(node, DOMAIN_BUS_IPI); | |
307 | ||
308 | /* | |
309 | * Some platforms have half DT setup. So if we found irq node but | |
310 | * didn't find an ipidomain, try to search for one that is not in the | |
311 | * DT. | |
312 | */ | |
313 | if (node && !ipidomain) | |
314 | ipidomain = irq_find_matching_host(NULL, DOMAIN_BUS_IPI); | |
315 | ||
316 | BUG_ON(!ipidomain); | |
317 | ||
318 | if (irq_domain_is_ipi_per_cpu(ipidomain)) { | |
319 | int cpu; | |
320 | ||
321 | for_each_cpu(cpu, mask) { | |
322 | remove_irq(call_virq + cpu, &irq_call); | |
323 | remove_irq(sched_virq + cpu, &irq_resched); | |
324 | } | |
325 | } | |
326 | irq_destroy_ipi(call_virq, mask); | |
327 | irq_destroy_ipi(sched_virq, mask); | |
328 | return 0; | |
329 | } | |
330 | ||
331 | ||
332 | static int __init mips_smp_ipi_init(void) | |
333 | { | |
334 | mips_smp_ipi_allocate(cpu_possible_mask); | |
335 | ||
fbde2d7d QY |
336 | call_desc = irq_to_desc(call_virq); |
337 | sched_desc = irq_to_desc(sched_virq); | |
338 | ||
339 | return 0; | |
340 | } | |
341 | early_initcall(mips_smp_ipi_init); | |
342 | #endif | |
343 | ||
1da177e4 LT |
344 | /* |
345 | * First C code run on the secondary CPUs after being started up by | |
346 | * the master. | |
347 | */ | |
078a55fc | 348 | asmlinkage void start_secondary(void) |
1da177e4 | 349 | { |
5bfb5d69 | 350 | unsigned int cpu; |
1da177e4 LT |
351 | |
352 | cpu_probe(); | |
6650df3c | 353 | per_cpu_trap_init(false); |
7bcf7717 | 354 | mips_clockevent_init(); |
87353d8a | 355 | mp_ops->init_secondary(); |
c7754e75 | 356 | cpu_report(); |
e060f6ed | 357 | maar_init(); |
1da177e4 LT |
358 | |
359 | /* | |
360 | * XXX parity protection should be folded in here when it's converted | |
361 | * to an option instead of something based on .cputype | |
362 | */ | |
363 | ||
364 | calibrate_delay(); | |
5bfb5d69 NP |
365 | preempt_disable(); |
366 | cpu = smp_processor_id(); | |
1da177e4 LT |
367 | cpu_data[cpu].udelay_val = loops_per_jiffy; |
368 | ||
8dd92891 | 369 | cpumask_set_cpu(cpu, &cpu_coherent_mask); |
e545a614 MS |
370 | notify_cpu_starting(cpu); |
371 | ||
a00eeede | 372 | complete(&cpu_running); |
8f46cca1 MR |
373 | synchronise_count_slave(cpu); |
374 | ||
b9a09a06 YZ |
375 | set_cpu_online(cpu, true); |
376 | ||
0ab7aefc | 377 | set_cpu_sibling_map(cpu); |
bda4584c | 378 | set_cpu_core_map(cpu); |
1da177e4 | 379 | |
cccf34e9 MC |
380 | calculate_cpu_foreign_map(); |
381 | ||
b789ad63 YZ |
382 | /* |
383 | * irq will be enabled in ->smp_finish(), enabling it too early | |
384 | * is dangerous. | |
385 | */ | |
386 | WARN_ON_ONCE(!irqs_disabled()); | |
5309bdac YZ |
387 | mp_ops->smp_finish(); |
388 | ||
fc6d73d6 | 389 | cpu_startup_entry(CPUHP_AP_ONLINE_IDLE); |
1da177e4 LT |
390 | } |
391 | ||
1da177e4 LT |
392 | static void stop_this_cpu(void *dummy) |
393 | { | |
394 | /* | |
92696316 | 395 | * Remove this CPU: |
1da177e4 | 396 | */ |
cccf34e9 | 397 | |
0b5f9c00 | 398 | set_cpu_online(smp_processor_id(), false); |
cccf34e9 | 399 | calculate_cpu_foreign_map(); |
ea925a72 AB |
400 | local_irq_disable(); |
401 | while (1); | |
1da177e4 LT |
402 | } |
403 | ||
404 | void smp_send_stop(void) | |
405 | { | |
8691e5a8 | 406 | smp_call_function(stop_this_cpu, NULL, 0); |
1da177e4 LT |
407 | } |
408 | ||
409 | void __init smp_cpus_done(unsigned int max_cpus) | |
410 | { | |
1da177e4 LT |
411 | } |
412 | ||
413 | /* called from main before smp_init() */ | |
414 | void __init smp_prepare_cpus(unsigned int max_cpus) | |
415 | { | |
1da177e4 LT |
416 | init_new_context(current, &init_mm); |
417 | current_thread_info()->cpu = 0; | |
87353d8a | 418 | mp_ops->prepare_cpus(max_cpus); |
0ab7aefc | 419 | set_cpu_sibling_map(0); |
bda4584c | 420 | set_cpu_core_map(0); |
cccf34e9 | 421 | calculate_cpu_foreign_map(); |
320e6aba | 422 | #ifndef CONFIG_HOTPLUG_CPU |
0b5f9c00 | 423 | init_cpu_present(cpu_possible_mask); |
320e6aba | 424 | #endif |
76306f42 | 425 | cpumask_copy(&cpu_coherent_mask, cpu_possible_mask); |
1da177e4 LT |
426 | } |
427 | ||
428 | /* preload SMP state for boot cpu */ | |
28eb0e46 | 429 | void smp_prepare_boot_cpu(void) |
1da177e4 | 430 | { |
4037ac6e RR |
431 | set_cpu_possible(0, true); |
432 | set_cpu_online(0, true); | |
1da177e4 LT |
433 | } |
434 | ||
078a55fc | 435 | int __cpu_up(unsigned int cpu, struct task_struct *tidle) |
1da177e4 | 436 | { |
360014a3 | 437 | mp_ops->boot_secondary(cpu, tidle); |
1da177e4 | 438 | |
b727a602 | 439 | /* |
a00eeede MR |
440 | * We must check for timeout here, as the CPU will not be marked |
441 | * online until the counters are synchronised. | |
b727a602 | 442 | */ |
a00eeede MR |
443 | if (!wait_for_completion_timeout(&cpu_running, |
444 | msecs_to_jiffies(1000))) { | |
445 | pr_crit("CPU%u: failed to start\n", cpu); | |
446 | return -EIO; | |
cafb45b2 | 447 | } |
1da177e4 | 448 | |
cf9bfe55 | 449 | synchronise_count_master(cpu); |
1da177e4 LT |
450 | return 0; |
451 | } | |
452 | ||
1da177e4 LT |
453 | /* Not really SMP stuff ... */ |
454 | int setup_profiling_timer(unsigned int multiplier) | |
455 | { | |
456 | return 0; | |
457 | } | |
458 | ||
459 | static void flush_tlb_all_ipi(void *info) | |
460 | { | |
461 | local_flush_tlb_all(); | |
462 | } | |
463 | ||
464 | void flush_tlb_all(void) | |
465 | { | |
15c8b6c1 | 466 | on_each_cpu(flush_tlb_all_ipi, NULL, 1); |
1da177e4 LT |
467 | } |
468 | ||
469 | static void flush_tlb_mm_ipi(void *mm) | |
470 | { | |
471 | local_flush_tlb_mm((struct mm_struct *)mm); | |
472 | } | |
473 | ||
25969354 RB |
474 | /* |
475 | * Special Variant of smp_call_function for use by TLB functions: | |
476 | * | |
477 | * o No return value | |
478 | * o collapses to normal function call on UP kernels | |
479 | * o collapses to normal function call on systems with a single shared | |
480 | * primary cache. | |
25969354 RB |
481 | */ |
482 | static inline void smp_on_other_tlbs(void (*func) (void *info), void *info) | |
483 | { | |
8691e5a8 | 484 | smp_call_function(func, info, 1); |
25969354 RB |
485 | } |
486 | ||
487 | static inline void smp_on_each_tlb(void (*func) (void *info), void *info) | |
488 | { | |
489 | preempt_disable(); | |
490 | ||
491 | smp_on_other_tlbs(func, info); | |
492 | func(info); | |
493 | ||
494 | preempt_enable(); | |
495 | } | |
496 | ||
1da177e4 LT |
497 | /* |
498 | * The following tlb flush calls are invoked when old translations are | |
499 | * being torn down, or pte attributes are changing. For single threaded | |
500 | * address spaces, a new context is obtained on the current cpu, and tlb | |
501 | * context on other cpus are invalidated to force a new context allocation | |
502 | * at switch_mm time, should the mm ever be used on other cpus. For | |
503 | * multithreaded address spaces, intercpu interrupts have to be sent. | |
504 | * Another case where intercpu interrupts are required is when the target | |
505 | * mm might be active on another cpu (eg debuggers doing the flushes on | |
506 | * behalf of debugees, kswapd stealing pages from another process etc). | |
507 | * Kanoj 07/00. | |
508 | */ | |
509 | ||
510 | void flush_tlb_mm(struct mm_struct *mm) | |
511 | { | |
512 | preempt_disable(); | |
513 | ||
514 | if ((atomic_read(&mm->mm_users) != 1) || (current->mm != mm)) { | |
c50cade9 | 515 | smp_on_other_tlbs(flush_tlb_mm_ipi, mm); |
1da177e4 | 516 | } else { |
b5eb5511 RB |
517 | unsigned int cpu; |
518 | ||
0b5f9c00 RR |
519 | for_each_online_cpu(cpu) { |
520 | if (cpu != smp_processor_id() && cpu_context(cpu, mm)) | |
b5eb5511 | 521 | cpu_context(cpu, mm) = 0; |
0b5f9c00 | 522 | } |
1da177e4 LT |
523 | } |
524 | local_flush_tlb_mm(mm); | |
525 | ||
526 | preempt_enable(); | |
527 | } | |
528 | ||
529 | struct flush_tlb_data { | |
530 | struct vm_area_struct *vma; | |
531 | unsigned long addr1; | |
532 | unsigned long addr2; | |
533 | }; | |
534 | ||
535 | static void flush_tlb_range_ipi(void *info) | |
536 | { | |
c50cade9 | 537 | struct flush_tlb_data *fd = info; |
1da177e4 LT |
538 | |
539 | local_flush_tlb_range(fd->vma, fd->addr1, fd->addr2); | |
540 | } | |
541 | ||
542 | void flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end) | |
543 | { | |
544 | struct mm_struct *mm = vma->vm_mm; | |
545 | ||
546 | preempt_disable(); | |
547 | if ((atomic_read(&mm->mm_users) != 1) || (current->mm != mm)) { | |
89a8a5a6 RB |
548 | struct flush_tlb_data fd = { |
549 | .vma = vma, | |
550 | .addr1 = start, | |
551 | .addr2 = end, | |
552 | }; | |
1da177e4 | 553 | |
c50cade9 | 554 | smp_on_other_tlbs(flush_tlb_range_ipi, &fd); |
1da177e4 | 555 | } else { |
b5eb5511 | 556 | unsigned int cpu; |
a05c3920 | 557 | int exec = vma->vm_flags & VM_EXEC; |
b5eb5511 | 558 | |
0b5f9c00 | 559 | for_each_online_cpu(cpu) { |
a05c3920 JH |
560 | /* |
561 | * flush_cache_range() will only fully flush icache if | |
562 | * the VMA is executable, otherwise we must invalidate | |
563 | * ASID without it appearing to has_valid_asid() as if | |
564 | * mm has been completely unused by that CPU. | |
565 | */ | |
0b5f9c00 | 566 | if (cpu != smp_processor_id() && cpu_context(cpu, mm)) |
a05c3920 | 567 | cpu_context(cpu, mm) = !exec; |
0b5f9c00 | 568 | } |
1da177e4 LT |
569 | } |
570 | local_flush_tlb_range(vma, start, end); | |
571 | preempt_enable(); | |
572 | } | |
573 | ||
574 | static void flush_tlb_kernel_range_ipi(void *info) | |
575 | { | |
c50cade9 | 576 | struct flush_tlb_data *fd = info; |
1da177e4 LT |
577 | |
578 | local_flush_tlb_kernel_range(fd->addr1, fd->addr2); | |
579 | } | |
580 | ||
581 | void flush_tlb_kernel_range(unsigned long start, unsigned long end) | |
582 | { | |
89a8a5a6 RB |
583 | struct flush_tlb_data fd = { |
584 | .addr1 = start, | |
585 | .addr2 = end, | |
586 | }; | |
1da177e4 | 587 | |
15c8b6c1 | 588 | on_each_cpu(flush_tlb_kernel_range_ipi, &fd, 1); |
1da177e4 LT |
589 | } |
590 | ||
591 | static void flush_tlb_page_ipi(void *info) | |
592 | { | |
c50cade9 | 593 | struct flush_tlb_data *fd = info; |
1da177e4 LT |
594 | |
595 | local_flush_tlb_page(fd->vma, fd->addr1); | |
596 | } | |
597 | ||
598 | void flush_tlb_page(struct vm_area_struct *vma, unsigned long page) | |
599 | { | |
600 | preempt_disable(); | |
601 | if ((atomic_read(&vma->vm_mm->mm_users) != 1) || (current->mm != vma->vm_mm)) { | |
89a8a5a6 RB |
602 | struct flush_tlb_data fd = { |
603 | .vma = vma, | |
604 | .addr1 = page, | |
605 | }; | |
1da177e4 | 606 | |
c50cade9 | 607 | smp_on_other_tlbs(flush_tlb_page_ipi, &fd); |
1da177e4 | 608 | } else { |
b5eb5511 RB |
609 | unsigned int cpu; |
610 | ||
0b5f9c00 | 611 | for_each_online_cpu(cpu) { |
a05c3920 JH |
612 | /* |
613 | * flush_cache_page() only does partial flushes, so | |
614 | * invalidate ASID without it appearing to | |
615 | * has_valid_asid() as if mm has been completely unused | |
616 | * by that CPU. | |
617 | */ | |
0b5f9c00 | 618 | if (cpu != smp_processor_id() && cpu_context(cpu, vma->vm_mm)) |
a05c3920 | 619 | cpu_context(cpu, vma->vm_mm) = 1; |
0b5f9c00 | 620 | } |
1da177e4 LT |
621 | } |
622 | local_flush_tlb_page(vma, page); | |
623 | preempt_enable(); | |
624 | } | |
625 | ||
626 | static void flush_tlb_one_ipi(void *info) | |
627 | { | |
628 | unsigned long vaddr = (unsigned long) info; | |
629 | ||
630 | local_flush_tlb_one(vaddr); | |
631 | } | |
632 | ||
633 | void flush_tlb_one(unsigned long vaddr) | |
634 | { | |
25969354 | 635 | smp_on_each_tlb(flush_tlb_one_ipi, (void *) vaddr); |
1da177e4 LT |
636 | } |
637 | ||
638 | EXPORT_SYMBOL(flush_tlb_page); | |
639 | EXPORT_SYMBOL(flush_tlb_one); | |
7aa1c8f4 | 640 | |
cc7964af PB |
641 | #ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST |
642 | ||
643 | static DEFINE_PER_CPU(atomic_t, tick_broadcast_count); | |
644 | static DEFINE_PER_CPU(struct call_single_data, tick_broadcast_csd); | |
645 | ||
646 | void tick_broadcast(const struct cpumask *mask) | |
647 | { | |
648 | atomic_t *count; | |
649 | struct call_single_data *csd; | |
650 | int cpu; | |
651 | ||
652 | for_each_cpu(cpu, mask) { | |
653 | count = &per_cpu(tick_broadcast_count, cpu); | |
654 | csd = &per_cpu(tick_broadcast_csd, cpu); | |
655 | ||
656 | if (atomic_inc_return(count) == 1) | |
657 | smp_call_function_single_async(cpu, csd); | |
658 | } | |
659 | } | |
660 | ||
661 | static void tick_broadcast_callee(void *info) | |
662 | { | |
663 | int cpu = smp_processor_id(); | |
664 | tick_receive_broadcast(); | |
665 | atomic_set(&per_cpu(tick_broadcast_count, cpu), 0); | |
666 | } | |
667 | ||
668 | static int __init tick_broadcast_init(void) | |
669 | { | |
670 | struct call_single_data *csd; | |
671 | int cpu; | |
672 | ||
673 | for (cpu = 0; cpu < NR_CPUS; cpu++) { | |
674 | csd = &per_cpu(tick_broadcast_csd, cpu); | |
675 | csd->func = tick_broadcast_callee; | |
676 | } | |
677 | ||
678 | return 0; | |
679 | } | |
680 | early_initcall(tick_broadcast_init); | |
681 | ||
682 | #endif /* CONFIG_GENERIC_CLOCKEVENTS_BROADCAST */ |