[mirror_ubuntu-artful-kernel.git] / arch / mips / kernel / smp.c

/*
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
 *
 * Copyright (C) 2000, 2001 Kanoj Sarcar
 * Copyright (C) 2000, 2001 Ralf Baechle
 * Copyright (C) 2000, 2001 Silicon Graphics, Inc.
 * Copyright (C) 2000, 2001, 2003 Broadcom Corporation
 */
#include <linux/cache.h>
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/smp.h>
#include <linux/spinlock.h>
#include <linux/threads.h>
#include <linux/export.h>
#include <linux/time.h>
#include <linux/timex.h>
#include <linux/sched/mm.h>
#include <linux/cpumask.h>
#include <linux/cpu.h>
#include <linux/err.h>
#include <linux/ftrace.h>
#include <linux/irqdomain.h>
#include <linux/of.h>
#include <linux/of_irq.h>

#include <linux/atomic.h>
#include <asm/cpu.h>
#include <asm/processor.h>
#include <asm/idle.h>
#include <asm/r4k-timer.h>
#include <asm/mips-cpc.h>
#include <asm/mmu_context.h>
#include <asm/time.h>
#include <asm/setup.h>
#include <asm/maar.h>

int __cpu_number_map[NR_CPUS];		/* Map physical to logical */
EXPORT_SYMBOL(__cpu_number_map);

int __cpu_logical_map[NR_CPUS];		/* Map logical to physical */
EXPORT_SYMBOL(__cpu_logical_map);

/* Number of TCs (or siblings in Intel speak) per CPU core */
int smp_num_siblings = 1;
EXPORT_SYMBOL(smp_num_siblings);

/* representing the TCs (or siblings in Intel speak) of each logical CPU */
cpumask_t cpu_sibling_map[NR_CPUS] __read_mostly;
EXPORT_SYMBOL(cpu_sibling_map);

/* representing the core map of multi-core chips of each logical CPU */
cpumask_t cpu_core_map[NR_CPUS] __read_mostly;
EXPORT_SYMBOL(cpu_core_map);

static DECLARE_COMPLETION(cpu_running);

/*
 * A logcal cpu mask containing only one VPE per core to
 * reduce the number of IPIs on large MT systems.
 */
cpumask_t cpu_foreign_map[NR_CPUS] __read_mostly;
EXPORT_SYMBOL(cpu_foreign_map);

/* representing cpus for which sibling maps can be computed */
static cpumask_t cpu_sibling_setup_map;

/* representing cpus for which core maps can be computed */
static cpumask_t cpu_core_setup_map;

cpumask_t cpu_coherent_mask;

#ifdef CONFIG_GENERIC_IRQ_IPI
static struct irq_desc *call_desc;
static struct irq_desc *sched_desc;
#endif

static inline void set_cpu_sibling_map(int cpu)
{
	int i;

	cpumask_set_cpu(cpu, &cpu_sibling_setup_map);

	if (smp_num_siblings > 1) {
		for_each_cpu(i, &cpu_sibling_setup_map) {
			if (cpu_data[cpu].package == cpu_data[i].package &&
				    cpu_data[cpu].core == cpu_data[i].core) {
				cpumask_set_cpu(i, &cpu_sibling_map[cpu]);
				cpumask_set_cpu(cpu, &cpu_sibling_map[i]);
			}
		}
	} else
		cpumask_set_cpu(cpu, &cpu_sibling_map[cpu]);
}

static inline void set_cpu_core_map(int cpu)
{
	int i;

	cpumask_set_cpu(cpu, &cpu_core_setup_map);

	for_each_cpu(i, &cpu_core_setup_map) {
		if (cpu_data[cpu].package == cpu_data[i].package) {
			cpumask_set_cpu(i, &cpu_core_map[cpu]);
			cpumask_set_cpu(cpu, &cpu_core_map[i]);
		}
	}
}

/*
 * Calculate a new cpu_foreign_map mask whenever a
 * new cpu appears or disappears.
 */
void calculate_cpu_foreign_map(void)
{
	int i, k, core_present;
	cpumask_t temp_foreign_map;

	/* Re-calculate the mask */
	cpumask_clear(&temp_foreign_map);
	for_each_online_cpu(i) {
		core_present = 0;
		for_each_cpu(k, &temp_foreign_map)
			if (cpu_data[i].package == cpu_data[k].package &&
			    cpu_data[i].core == cpu_data[k].core)
				core_present = 1;
		if (!core_present)
			cpumask_set_cpu(i, &temp_foreign_map);
	}

	for_each_online_cpu(i)
		cpumask_andnot(&cpu_foreign_map[i],
			       &temp_foreign_map, &cpu_sibling_map[i]);
}

struct plat_smp_ops *mp_ops;
EXPORT_SYMBOL(mp_ops);

void register_smp_ops(struct plat_smp_ops *ops)
{
	if (mp_ops)
		printk(KERN_WARNING "Overriding previously set SMP ops\n");

	mp_ops = ops;
}

#ifdef CONFIG_GENERIC_IRQ_IPI
void mips_smp_send_ipi_single(int cpu, unsigned int action)
{
	mips_smp_send_ipi_mask(cpumask_of(cpu), action);
}

void mips_smp_send_ipi_mask(const struct cpumask *mask, unsigned int action)
{
	unsigned long flags;
	unsigned int core;
	int cpu;

	local_irq_save(flags);

	switch (action) {
	case SMP_CALL_FUNCTION:
		__ipi_send_mask(call_desc, mask);
		break;

	case SMP_RESCHEDULE_YOURSELF:
		__ipi_send_mask(sched_desc, mask);
		break;

	default:
		BUG();
	}

	if (mips_cpc_present()) {
		for_each_cpu(cpu, mask) {
			core = cpu_data[cpu].core;

			if (core == current_cpu_data.core)
				continue;

			while (!cpumask_test_cpu(cpu, &cpu_coherent_mask)) {
				mips_cm_lock_other(core, 0);
				mips_cpc_lock_other(core);
				write_cpc_co_cmd(CPC_Cx_CMD_PWRUP);
				mips_cpc_unlock_other();
				mips_cm_unlock_other();
			}
		}
	}

	local_irq_restore(flags);
}


static irqreturn_t ipi_resched_interrupt(int irq, void *dev_id)
{
	scheduler_ipi();

	return IRQ_HANDLED;
}

static irqreturn_t ipi_call_interrupt(int irq, void *dev_id)
{
	generic_smp_call_function_interrupt();

	return IRQ_HANDLED;
}

static struct irqaction irq_resched = {
	.handler	= ipi_resched_interrupt,
	.flags		= IRQF_PERCPU,
	.name		= "IPI resched"
};

static struct irqaction irq_call = {
	.handler	= ipi_call_interrupt,
	.flags		= IRQF_PERCPU,
	.name		= "IPI call"
};

static void smp_ipi_init_one(unsigned int virq,
				    struct irqaction *action)
{
	int ret;

	irq_set_handler(virq, handle_percpu_irq);
	ret = setup_irq(virq, action);
	BUG_ON(ret);
}

static unsigned int call_virq, sched_virq;

int mips_smp_ipi_allocate(const struct cpumask *mask)
{
	int virq;
	struct irq_domain *ipidomain;
	struct device_node *node;

	node = of_irq_find_parent(of_root);
	ipidomain = irq_find_matching_host(node, DOMAIN_BUS_IPI);

	/*
	 * Some platforms have half DT setup. So if we found irq node but
	 * didn't find an ipidomain, try to search for one that is not in the
	 * DT.
	 */
	if (node && !ipidomain)
		ipidomain = irq_find_matching_host(NULL, DOMAIN_BUS_IPI);

	/*
	 * There are systems which use IPI IRQ domains, but only have one
	 * registered when some runtime condition is met. For example a Malta
	 * kernel may include support for GIC & CPU interrupt controller IPI
	 * IRQ domains, but if run on a system with no GIC & no MT ASE then
	 * neither will be supported or registered.
	 *
	 * We only have a problem if we're actually using multiple CPUs so fail
	 * loudly if that is the case. Otherwise simply return, skipping IPI
	 * setup, if we're running with only a single CPU.
	 */
	if (!ipidomain) {
		BUG_ON(num_present_cpus() > 1);
		return 0;
	}

	virq = irq_reserve_ipi(ipidomain, mask);
	BUG_ON(!virq);
	if (!call_virq)
		call_virq = virq;

	virq = irq_reserve_ipi(ipidomain, mask);
	BUG_ON(!virq);
	if (!sched_virq)
		sched_virq = virq;

	if (irq_domain_is_ipi_per_cpu(ipidomain)) {
		int cpu;

		for_each_cpu(cpu, mask) {
			smp_ipi_init_one(call_virq + cpu, &irq_call);
			smp_ipi_init_one(sched_virq + cpu, &irq_resched);
		}
	} else {
		smp_ipi_init_one(call_virq, &irq_call);
		smp_ipi_init_one(sched_virq, &irq_resched);
	}

	return 0;
}

int mips_smp_ipi_free(const struct cpumask *mask)
{
	struct irq_domain *ipidomain;
	struct device_node *node;

	node = of_irq_find_parent(of_root);
	ipidomain = irq_find_matching_host(node, DOMAIN_BUS_IPI);

	/*
	 * Some platforms have half DT setup. So if we found irq node but
	 * didn't find an ipidomain, try to search for one that is not in the
	 * DT.
	 */
	if (node && !ipidomain)
		ipidomain = irq_find_matching_host(NULL, DOMAIN_BUS_IPI);

	BUG_ON(!ipidomain);

	if (irq_domain_is_ipi_per_cpu(ipidomain)) {
		int cpu;

		for_each_cpu(cpu, mask) {
			remove_irq(call_virq + cpu, &irq_call);
			remove_irq(sched_virq + cpu, &irq_resched);
		}
	}
	irq_destroy_ipi(call_virq, mask);
	irq_destroy_ipi(sched_virq, mask);
	return 0;
}


static int __init mips_smp_ipi_init(void)
{
	if (num_possible_cpus() == 1)
		return 0;

	mips_smp_ipi_allocate(cpu_possible_mask);

	call_desc = irq_to_desc(call_virq);
	sched_desc = irq_to_desc(sched_virq);

	return 0;
}
early_initcall(mips_smp_ipi_init);
#endif

/*
 * First C code run on the secondary CPUs after being started up by
 * the master.
 */
asmlinkage void start_secondary(void)
{
	unsigned int cpu;

	cpu_probe();
	per_cpu_trap_init(false);
	mips_clockevent_init();
	mp_ops->init_secondary();
	cpu_report();
	maar_init();

	/*
	 * XXX parity protection should be folded in here when it's converted
	 * to an option instead of something based on .cputype
	 */

	calibrate_delay();
	preempt_disable();
	cpu = smp_processor_id();
	cpu_data[cpu].udelay_val = loops_per_jiffy;

	cpumask_set_cpu(cpu, &cpu_coherent_mask);
	notify_cpu_starting(cpu);

	set_cpu_online(cpu, true);

	set_cpu_sibling_map(cpu);
	set_cpu_core_map(cpu);

	calculate_cpu_foreign_map();

	complete(&cpu_running);
	synchronise_count_slave(cpu);

	/*
	 * irq will be enabled in ->smp_finish(), enabling it too early
	 * is dangerous.
	 */
	WARN_ON_ONCE(!irqs_disabled());
	mp_ops->smp_finish();

	cpu_startup_entry(CPUHP_AP_ONLINE_IDLE);
}

static void stop_this_cpu(void *dummy)
{
	/*
	 * Remove this CPU:
	 */

	set_cpu_online(smp_processor_id(), false);
	calculate_cpu_foreign_map();
	local_irq_disable();
	while (1);
}

void smp_send_stop(void)
{
	smp_call_function(stop_this_cpu, NULL, 0);
}

void __init smp_cpus_done(unsigned int max_cpus)
{
}

/* called from main before smp_init() */
void __init smp_prepare_cpus(unsigned int max_cpus)
{
	init_new_context(current, &init_mm);
	current_thread_info()->cpu = 0;
	mp_ops->prepare_cpus(max_cpus);
	set_cpu_sibling_map(0);
	set_cpu_core_map(0);
	calculate_cpu_foreign_map();
#ifndef CONFIG_HOTPLUG_CPU
	init_cpu_present(cpu_possible_mask);
#endif
	cpumask_copy(&cpu_coherent_mask, cpu_possible_mask);
}

/* preload SMP state for boot cpu */
void smp_prepare_boot_cpu(void)
{
	set_cpu_possible(0, true);
	set_cpu_online(0, true);
}

int __cpu_up(unsigned int cpu, struct task_struct *tidle)
{
	mp_ops->boot_secondary(cpu, tidle);

	/*
	 * We must check for timeout here, as the CPU will not be marked
	 * online until the counters are synchronised.
	 */
	if (!wait_for_completion_timeout(&cpu_running,
					 msecs_to_jiffies(1000))) {
		pr_crit("CPU%u: failed to start\n", cpu);
		return -EIO;
	}

	synchronise_count_master(cpu);
	return 0;
}

/* Not really SMP stuff ... */
int setup_profiling_timer(unsigned int multiplier)
{
	return 0;
}

static void flush_tlb_all_ipi(void *info)
{
	local_flush_tlb_all();
}

void flush_tlb_all(void)
{
	on_each_cpu(flush_tlb_all_ipi, NULL, 1);
}

static void flush_tlb_mm_ipi(void *mm)
{
	local_flush_tlb_mm((struct mm_struct *)mm);
}

/*
 * Special Variant of smp_call_function for use by TLB functions:
 *
 *  o No return value
 *  o collapses to normal function call on UP kernels
 *  o collapses to normal function call on systems with a single shared
 *    primary cache.
 */
static inline void smp_on_other_tlbs(void (*func) (void *info), void *info)
{
	smp_call_function(func, info, 1);
}

static inline void smp_on_each_tlb(void (*func) (void *info), void *info)
{
	preempt_disable();

	smp_on_other_tlbs(func, info);
	func(info);

	preempt_enable();
}

/*
 * The following tlb flush calls are invoked when old translations are
 * being torn down, or pte attributes are changing. For single threaded
 * address spaces, a new context is obtained on the current cpu, and tlb
 * context on other cpus are invalidated to force a new context allocation
 * at switch_mm time, should the mm ever be used on other cpus. For
 * multithreaded address spaces, intercpu interrupts have to be sent.
 * Another case where intercpu interrupts are required is when the target
 * mm might be active on another cpu (eg debuggers doing the flushes on
 * behalf of debugees, kswapd stealing pages from another process etc).
 * Kanoj 07/00.
 */

void flush_tlb_mm(struct mm_struct *mm)
{
	preempt_disable();

	if ((atomic_read(&mm->mm_users) != 1) || (current->mm != mm)) {
		smp_on_other_tlbs(flush_tlb_mm_ipi, mm);
	} else {
		unsigned int cpu;

		for_each_online_cpu(cpu) {
			if (cpu != smp_processor_id() && cpu_context(cpu, mm))
				cpu_context(cpu, mm) = 0;
		}
	}
	local_flush_tlb_mm(mm);

	preempt_enable();
}

struct flush_tlb_data {
	struct vm_area_struct *vma;
	unsigned long addr1;
	unsigned long addr2;
};

static void flush_tlb_range_ipi(void *info)
{
	struct flush_tlb_data *fd = info;

	local_flush_tlb_range(fd->vma, fd->addr1, fd->addr2);
}

void flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)
{
	struct mm_struct *mm = vma->vm_mm;

	preempt_disable();
	if ((atomic_read(&mm->mm_users) != 1) || (current->mm != mm)) {
		struct flush_tlb_data fd = {
			.vma = vma,
			.addr1 = start,
			.addr2 = end,
		};

		smp_on_other_tlbs(flush_tlb_range_ipi, &fd);
	} else {
		unsigned int cpu;
		int exec = vma->vm_flags & VM_EXEC;

		for_each_online_cpu(cpu) {
			/*
			 * flush_cache_range() will only fully flush icache if
			 * the VMA is executable, otherwise we must invalidate
			 * ASID without it appearing to has_valid_asid() as if
			 * mm has been completely unused by that CPU.
			 */
			if (cpu != smp_processor_id() && cpu_context(cpu, mm))
				cpu_context(cpu, mm) = !exec;
		}
	}
	local_flush_tlb_range(vma, start, end);
	preempt_enable();
}

static void flush_tlb_kernel_range_ipi(void *info)
{
	struct flush_tlb_data *fd = info;

	local_flush_tlb_kernel_range(fd->addr1, fd->addr2);
}

void flush_tlb_kernel_range(unsigned long start, unsigned long end)
{
	struct flush_tlb_data fd = {
		.addr1 = start,
		.addr2 = end,
	};

	on_each_cpu(flush_tlb_kernel_range_ipi, &fd, 1);
}

static void flush_tlb_page_ipi(void *info)
{
	struct flush_tlb_data *fd = info;

	local_flush_tlb_page(fd->vma, fd->addr1);
}

void flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
{
	preempt_disable();
	if ((atomic_read(&vma->vm_mm->mm_users) != 1) || (current->mm != vma->vm_mm)) {
		struct flush_tlb_data fd = {
			.vma = vma,
			.addr1 = page,
		};

		smp_on_other_tlbs(flush_tlb_page_ipi, &fd);
	} else {
		unsigned int cpu;

		for_each_online_cpu(cpu) {
			/*
			 * flush_cache_page() only does partial flushes, so
			 * invalidate ASID without it appearing to
			 * has_valid_asid() as if mm has been completely unused
			 * by that CPU.
			 */
			if (cpu != smp_processor_id() && cpu_context(cpu, vma->vm_mm))
				cpu_context(cpu, vma->vm_mm) = 1;
		}
	}
	local_flush_tlb_page(vma, page);
	preempt_enable();
}

static void flush_tlb_one_ipi(void *info)
{
	unsigned long vaddr = (unsigned long) info;

	local_flush_tlb_one(vaddr);
}

void flush_tlb_one(unsigned long vaddr)
{
	smp_on_each_tlb(flush_tlb_one_ipi, (void *) vaddr);
}

EXPORT_SYMBOL(flush_tlb_page);
EXPORT_SYMBOL(flush_tlb_one);

#ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST

static DEFINE_PER_CPU(atomic_t, tick_broadcast_count);
static DEFINE_PER_CPU(struct call_single_data, tick_broadcast_csd);

void tick_broadcast(const struct cpumask *mask)
{
	atomic_t *count;
	struct call_single_data *csd;
	int cpu;

	for_each_cpu(cpu, mask) {
		count = &per_cpu(tick_broadcast_count, cpu);
		csd = &per_cpu(tick_broadcast_csd, cpu);

		if (atomic_inc_return(count) == 1)
			smp_call_function_single_async(cpu, csd);
	}
}

static void tick_broadcast_callee(void *info)
{
	int cpu = smp_processor_id();
	tick_receive_broadcast();
	atomic_set(&per_cpu(tick_broadcast_count, cpu), 0);
}

static int __init tick_broadcast_init(void)
{
	struct call_single_data *csd;
	int cpu;

	for (cpu = 0; cpu < NR_CPUS; cpu++) {
		csd = &per_cpu(tick_broadcast_csd, cpu);
		csd->func = tick_broadcast_callee;
	}

	return 0;
}
early_initcall(tick_broadcast_init);

#endif /* CONFIG_GENERIC_CLOCKEVENTS_BROADCAST */
Commit	Line	Data
1da177e4 LT	1	/*
	2	* This program is free software; you can redistribute it and/or
	3	* modify it under the terms of the GNU General Public License
	4	* as published by the Free Software Foundation; either version 2
	5	* of the License, or (at your option) any later version.
	6	*
	7	* This program is distributed in the hope that it will be useful,
	8	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	9	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	10	* GNU General Public License for more details.
	11	*
	12	* You should have received a copy of the GNU General Public License
	13	* along with this program; if not, write to the Free Software
	14	* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
	15	*
	16	* Copyright (C) 2000, 2001 Kanoj Sarcar
	17	* Copyright (C) 2000, 2001 Ralf Baechle
	18	* Copyright (C) 2000, 2001 Silicon Graphics, Inc.
	19	* Copyright (C) 2000, 2001, 2003 Broadcom Corporation
	20	*/
	21	#include <linux/cache.h>
	22	#include <linux/delay.h>
	23	#include <linux/init.h>
	24	#include <linux/interrupt.h>
631330f5	25	#include <linux/smp.h>
1da177e4 LT	26	#include <linux/spinlock.h>
1da177e4 LT	27	#include <linux/threads.h>
d9d54177	28	#include <linux/export.h>
1da177e4 LT	29	#include <linux/time.h>
1da177e4 LT	30	#include <linux/timex.h>
589ee628	31	#include <linux/sched/mm.h>
1da177e4	32	#include <linux/cpumask.h>
1e35aaba	33	#include <linux/cpu.h>
4e950f6f	34	#include <linux/err.h>
8f99a162	35	#include <linux/ftrace.h>
fbde2d7d QY	36	#include <linux/irqdomain.h>
	37	#include <linux/of.h>
	38	#include <linux/of_irq.h>
1da177e4	39
60063497	40	#include <linux/atomic.h>
1da177e4 LT	41	#include <asm/cpu.h>
1da177e4 LT	42	#include <asm/processor.h>
bdc92d74	43	#include <asm/idle.h>
39b8d525	44	#include <asm/r4k-timer.h>
fbde2d7d	45	#include <asm/mips-cpc.h>
1da177e4	46	#include <asm/mmu_context.h>
7bcf7717	47	#include <asm/time.h>
b81947c6	48	#include <asm/setup.h>
e060f6ed	49	#include <asm/maar.h>
1da177e4	50
1da177e4	51	int __cpu_number_map[NR_CPUS]; /* Map physical to logical */
2dc2ae34 DD	52	EXPORT_SYMBOL(__cpu_number_map);
2dc2ae34 DD	53
1da177e4	54	int __cpu_logical_map[NR_CPUS]; /* Map logical to physical */
2dc2ae34	55	EXPORT_SYMBOL(__cpu_logical_map);
1da177e4	56
0ab7aefc RB	57	/* Number of TCs (or siblings in Intel speak) per CPU core */
	58	int smp_num_siblings = 1;
	59	EXPORT_SYMBOL(smp_num_siblings);
	60
	61	/* representing the TCs (or siblings in Intel speak) of each logical CPU */
	62	cpumask_t cpu_sibling_map[NR_CPUS] __read_mostly;
	63	EXPORT_SYMBOL(cpu_sibling_map);
	64
bda4584c HC	65	/* representing the core map of multi-core chips of each logical CPU */
	66	cpumask_t cpu_core_map[NR_CPUS] __read_mostly;
	67	EXPORT_SYMBOL(cpu_core_map);
	68
a00eeede MR	69	static DECLARE_COMPLETION(cpu_running);
a00eeede MR	70
cccf34e9 MC	71	/*
	72	* A logcal cpu mask containing only one VPE per core to
	73	* reduce the number of IPIs on large MT systems.
	74	*/
640511ae	75	cpumask_t cpu_foreign_map[NR_CPUS] __read_mostly;
cccf34e9 MC	76	EXPORT_SYMBOL(cpu_foreign_map);
cccf34e9 MC	77
0ab7aefc RB	78	/* representing cpus for which sibling maps can be computed */
	79	static cpumask_t cpu_sibling_setup_map;
	80
bda4584c HC	81	/* representing cpus for which core maps can be computed */
	82	static cpumask_t cpu_core_setup_map;
	83
76306f42 PB	84	cpumask_t cpu_coherent_mask;
76306f42 PB	85
fbde2d7d QY	86	#ifdef CONFIG_GENERIC_IRQ_IPI
	87	static struct irq_desc *call_desc;
	88	static struct irq_desc *sched_desc;
	89	#endif
	90
0ab7aefc RB	91	static inline void set_cpu_sibling_map(int cpu)
	92	{
	93	int i;
	94
8dd92891	95	cpumask_set_cpu(cpu, &cpu_sibling_setup_map);
0ab7aefc RB	96
0ab7aefc RB	97	if (smp_num_siblings > 1) {
8dd92891	98	for_each_cpu(i, &cpu_sibling_setup_map) {
bda4584c HC	99	if (cpu_data[cpu].package == cpu_data[i].package &&
bda4584c HC	100	cpu_data[cpu].core == cpu_data[i].core) {
8dd92891 RR	101	cpumask_set_cpu(i, &cpu_sibling_map[cpu]);
8dd92891 RR	102	cpumask_set_cpu(cpu, &cpu_sibling_map[i]);
0ab7aefc RB	103	}
	104	}
	105	} else
8dd92891	106	cpumask_set_cpu(cpu, &cpu_sibling_map[cpu]);
0ab7aefc RB	107	}
0ab7aefc RB	108
bda4584c HC	109	static inline void set_cpu_core_map(int cpu)
	110	{
	111	int i;
	112
8dd92891	113	cpumask_set_cpu(cpu, &cpu_core_setup_map);
bda4584c	114
8dd92891	115	for_each_cpu(i, &cpu_core_setup_map) {
bda4584c	116	if (cpu_data[cpu].package == cpu_data[i].package) {
8dd92891 RR	117	cpumask_set_cpu(i, &cpu_core_map[cpu]);
8dd92891 RR	118	cpumask_set_cpu(cpu, &cpu_core_map[i]);
bda4584c HC	119	}
	120	}
	121	}
	122
cccf34e9 MC	123	/*
	124	* Calculate a new cpu_foreign_map mask whenever a
	125	* new cpu appears or disappears.
	126	*/
826e99be	127	void calculate_cpu_foreign_map(void)
cccf34e9 MC	128	{
	129	int i, k, core_present;
	130	cpumask_t temp_foreign_map;
	131
	132	/* Re-calculate the mask */
d825c06b	133	cpumask_clear(&temp_foreign_map);
cccf34e9 MC	134	for_each_online_cpu(i) {
	135	core_present = 0;
	136	for_each_cpu(k, &temp_foreign_map)
	137	if (cpu_data[i].package == cpu_data[k].package &&
	138	cpu_data[i].core == cpu_data[k].core)
	139	core_present = 1;
	140	if (!core_present)
	141	cpumask_set_cpu(i, &temp_foreign_map);
	142	}
	143
640511ae JH	144	for_each_online_cpu(i)
	145	cpumask_andnot(&cpu_foreign_map[i],
	146	&temp_foreign_map, &cpu_sibling_map[i]);
cccf34e9 MC	147	}
cccf34e9 MC	148
87353d8a	149	struct plat_smp_ops *mp_ops;
82d45de6	150	EXPORT_SYMBOL(mp_ops);
87353d8a	151
078a55fc	152	void register_smp_ops(struct plat_smp_ops *ops)
87353d8a	153	{
83738e30 TS	154	if (mp_ops)
83738e30 TS	155	printk(KERN_WARNING "Overriding previously set SMP ops\n");
87353d8a RB	156
	157	mp_ops = ops;
	158	}
	159
fbde2d7d QY	160	#ifdef CONFIG_GENERIC_IRQ_IPI
	161	void mips_smp_send_ipi_single(int cpu, unsigned int action)
	162	{
	163	mips_smp_send_ipi_mask(cpumask_of(cpu), action);
	164	}
	165
	166	void mips_smp_send_ipi_mask(const struct cpumask *mask, unsigned int action)
	167	{
	168	unsigned long flags;
	169	unsigned int core;
	170	int cpu;
	171
	172	local_irq_save(flags);
	173
	174	switch (action) {
	175	case SMP_CALL_FUNCTION:
	176	__ipi_send_mask(call_desc, mask);
	177	break;
	178
	179	case SMP_RESCHEDULE_YOURSELF:
	180	__ipi_send_mask(sched_desc, mask);
	181	break;
	182
	183	default:
	184	BUG();
	185	}
	186
	187	if (mips_cpc_present()) {
	188	for_each_cpu(cpu, mask) {
	189	core = cpu_data[cpu].core;
	190
	191	if (core == current_cpu_data.core)
	192	continue;
	193
	194	while (!cpumask_test_cpu(cpu, &cpu_coherent_mask)) {
4b640136	195	mips_cm_lock_other(core, 0);
fbde2d7d QY	196	mips_cpc_lock_other(core);
	197	write_cpc_co_cmd(CPC_Cx_CMD_PWRUP);
	198	mips_cpc_unlock_other();
4b640136	199	mips_cm_unlock_other();
fbde2d7d QY	200	}
	201	}
	202	}
	203
	204	local_irq_restore(flags);
	205	}
	206
	207
	208	static irqreturn_t ipi_resched_interrupt(int irq, void *dev_id)
	209	{
	210	scheduler_ipi();
	211
	212	return IRQ_HANDLED;
	213	}
	214
	215	static irqreturn_t ipi_call_interrupt(int irq, void *dev_id)
	216	{
	217	generic_smp_call_function_interrupt();
	218
	219	return IRQ_HANDLED;
	220	}
	221
	222	static struct irqaction irq_resched = {
	223	.handler = ipi_resched_interrupt,
	224	.flags = IRQF_PERCPU,
	225	.name = "IPI resched"
	226	};
	227
	228	static struct irqaction irq_call = {
	229	.handler = ipi_call_interrupt,
	230	.flags = IRQF_PERCPU,
	231	.name = "IPI call"
	232	};
	233
7688c539	234	static void smp_ipi_init_one(unsigned int virq,
fbde2d7d QY	235	struct irqaction *action)
	236	{
	237	int ret;
	238
	239	irq_set_handler(virq, handle_percpu_irq);
	240	ret = setup_irq(virq, action);
	241	BUG_ON(ret);
	242	}
	243
7688c539 MR	244	static unsigned int call_virq, sched_virq;
	245
	246	int mips_smp_ipi_allocate(const struct cpumask *mask)
fbde2d7d	247	{
7688c539	248	int virq;
fbde2d7d QY	249	struct irq_domain *ipidomain;
	250	struct device_node *node;
	251
	252	node = of_irq_find_parent(of_root);
	253	ipidomain = irq_find_matching_host(node, DOMAIN_BUS_IPI);
	254
	255	/*
	256	* Some platforms have half DT setup. So if we found irq node but
	257	* didn't find an ipidomain, try to search for one that is not in the
	258	* DT.
	259	*/
	260	if (node && !ipidomain)
	261	ipidomain = irq_find_matching_host(NULL, DOMAIN_BUS_IPI);
	262
578bffc8	263	/*
e6488982 PB	264	* There are systems which use IPI IRQ domains, but only have one
	265	* registered when some runtime condition is met. For example a Malta
	266	* kernel may include support for GIC & CPU interrupt controller IPI
	267	* IRQ domains, but if run on a system with no GIC & no MT ASE then
	268	* neither will be supported or registered.
	269	*
	270	* We only have a problem if we're actually using multiple CPUs so fail
	271	* loudly if that is the case. Otherwise simply return, skipping IPI
	272	* setup, if we're running with only a single CPU.
578bffc8	273	*/
e6488982 PB	274	if (!ipidomain) {
e6488982 PB	275	BUG_ON(num_present_cpus() > 1);
578bffc8	276	return 0;
e6488982	277	}
fbde2d7d	278
7688c539 MR	279	virq = irq_reserve_ipi(ipidomain, mask);
	280	BUG_ON(!virq);
	281	if (!call_virq)
	282	call_virq = virq;
fbde2d7d	283
7688c539 MR	284	virq = irq_reserve_ipi(ipidomain, mask);
	285	BUG_ON(!virq);
	286	if (!sched_virq)
	287	sched_virq = virq;
fbde2d7d QY	288
	289	if (irq_domain_is_ipi_per_cpu(ipidomain)) {
	290	int cpu;
	291
7688c539	292	for_each_cpu(cpu, mask) {
fbde2d7d QY	293	smp_ipi_init_one(call_virq + cpu, &irq_call);
	294	smp_ipi_init_one(sched_virq + cpu, &irq_resched);
	295	}
	296	} else {
	297	smp_ipi_init_one(call_virq, &irq_call);
	298	smp_ipi_init_one(sched_virq, &irq_resched);
	299	}
	300
7688c539 MR	301	return 0;
	302	}
	303
	304	int mips_smp_ipi_free(const struct cpumask *mask)
	305	{
	306	struct irq_domain *ipidomain;
	307	struct device_node *node;
	308
	309	node = of_irq_find_parent(of_root);
	310	ipidomain = irq_find_matching_host(node, DOMAIN_BUS_IPI);
	311
	312	/*
	313	* Some platforms have half DT setup. So if we found irq node but
	314	* didn't find an ipidomain, try to search for one that is not in the
	315	* DT.
	316	*/
	317	if (node && !ipidomain)
	318	ipidomain = irq_find_matching_host(NULL, DOMAIN_BUS_IPI);
	319
	320	BUG_ON(!ipidomain);
	321
	322	if (irq_domain_is_ipi_per_cpu(ipidomain)) {
	323	int cpu;
	324
	325	for_each_cpu(cpu, mask) {
	326	remove_irq(call_virq + cpu, &irq_call);
	327	remove_irq(sched_virq + cpu, &irq_resched);
	328	}
	329	}
	330	irq_destroy_ipi(call_virq, mask);
	331	irq_destroy_ipi(sched_virq, mask);
	332	return 0;
	333	}
	334
	335
	336	static int __init mips_smp_ipi_init(void)
	337	{
9b03d8ab PB	338	if (num_possible_cpus() == 1)
	339	return 0;
	340
7688c539 MR	341	mips_smp_ipi_allocate(cpu_possible_mask);
7688c539 MR	342
fbde2d7d QY	343	call_desc = irq_to_desc(call_virq);
	344	sched_desc = irq_to_desc(sched_virq);
	345
	346	return 0;
	347	}
	348	early_initcall(mips_smp_ipi_init);
	349	#endif
	350
1da177e4 LT	351	/*
	352	* First C code run on the secondary CPUs after being started up by
	353	* the master.
	354	*/
078a55fc	355	asmlinkage void start_secondary(void)
1da177e4	356	{
5bfb5d69	357	unsigned int cpu;
1da177e4 LT	358
1da177e4 LT	359	cpu_probe();
6650df3c	360	per_cpu_trap_init(false);
7bcf7717	361	mips_clockevent_init();
87353d8a	362	mp_ops->init_secondary();
c7754e75	363	cpu_report();
e060f6ed	364	maar_init();
1da177e4 LT	365
	366	/*
	367	* XXX parity protection should be folded in here when it's converted
	368	* to an option instead of something based on .cputype
	369	*/
	370
	371	calibrate_delay();
5bfb5d69 NP	372	preempt_disable();
5bfb5d69 NP	373	cpu = smp_processor_id();
1da177e4 LT	374	cpu_data[cpu].udelay_val = loops_per_jiffy;
1da177e4 LT	375
8dd92891	376	cpumask_set_cpu(cpu, &cpu_coherent_mask);
e545a614 MS	377	notify_cpu_starting(cpu);
e545a614 MS	378
b9a09a06 YZ	379	set_cpu_online(cpu, true);
b9a09a06 YZ	380
0ab7aefc	381	set_cpu_sibling_map(cpu);
bda4584c	382	set_cpu_core_map(cpu);
1da177e4	383
cccf34e9 MC	384	calculate_cpu_foreign_map();
cccf34e9 MC	385
6f542ebe MGP	386	complete(&cpu_running);
	387	synchronise_count_slave(cpu);
	388
b789ad63 YZ	389	/*
	390	* irq will be enabled in ->smp_finish(), enabling it too early
	391	* is dangerous.
	392	*/
	393	WARN_ON_ONCE(!irqs_disabled());
5309bdac YZ	394	mp_ops->smp_finish();
5309bdac YZ	395
fc6d73d6	396	cpu_startup_entry(CPUHP_AP_ONLINE_IDLE);
1da177e4 LT	397	}
1da177e4 LT	398
1da177e4 LT	399	static void stop_this_cpu(void *dummy)
	400	{
	401	/*
92696316	402	* Remove this CPU:
1da177e4	403	*/
cccf34e9	404
0b5f9c00	405	set_cpu_online(smp_processor_id(), false);
cccf34e9	406	calculate_cpu_foreign_map();
ea925a72 AB	407	local_irq_disable();
ea925a72 AB	408	while (1);
1da177e4 LT	409	}
	410
	411	void smp_send_stop(void)
	412	{
8691e5a8	413	smp_call_function(stop_this_cpu, NULL, 0);
1da177e4 LT	414	}
	415
	416	void __init smp_cpus_done(unsigned int max_cpus)
	417	{
1da177e4 LT	418	}
	419
	420	/* called from main before smp_init() */
	421	void __init smp_prepare_cpus(unsigned int max_cpus)
	422	{
1da177e4 LT	423	init_new_context(current, &init_mm);
1da177e4 LT	424	current_thread_info()->cpu = 0;
87353d8a	425	mp_ops->prepare_cpus(max_cpus);
0ab7aefc	426	set_cpu_sibling_map(0);
bda4584c	427	set_cpu_core_map(0);
cccf34e9	428	calculate_cpu_foreign_map();
320e6aba	429	#ifndef CONFIG_HOTPLUG_CPU
0b5f9c00	430	init_cpu_present(cpu_possible_mask);
320e6aba	431	#endif
76306f42	432	cpumask_copy(&cpu_coherent_mask, cpu_possible_mask);
1da177e4 LT	433	}
	434
	435	/* preload SMP state for boot cpu */
28eb0e46	436	void smp_prepare_boot_cpu(void)
1da177e4	437	{
4037ac6e RR	438	set_cpu_possible(0, true);
4037ac6e RR	439	set_cpu_online(0, true);
1da177e4 LT	440	}
1da177e4 LT	441
078a55fc	442	int __cpu_up(unsigned int cpu, struct task_struct *tidle)
1da177e4	443	{
360014a3	444	mp_ops->boot_secondary(cpu, tidle);
1da177e4	445
b727a602	446	/*
a00eeede MR	447	* We must check for timeout here, as the CPU will not be marked
a00eeede MR	448	* online until the counters are synchronised.
b727a602	449	*/
a00eeede MR	450	if (!wait_for_completion_timeout(&cpu_running,
	451	msecs_to_jiffies(1000))) {
	452	pr_crit("CPU%u: failed to start\n", cpu);
	453	return -EIO;
cafb45b2	454	}
1da177e4	455
cf9bfe55	456	synchronise_count_master(cpu);
1da177e4 LT	457	return 0;
	458	}
	459
1da177e4 LT	460	/* Not really SMP stuff ... */
	461	int setup_profiling_timer(unsigned int multiplier)
	462	{
	463	return 0;
	464	}
	465
	466	static void flush_tlb_all_ipi(void *info)
	467	{
	468	local_flush_tlb_all();
	469	}
	470
	471	void flush_tlb_all(void)
	472	{
15c8b6c1	473	on_each_cpu(flush_tlb_all_ipi, NULL, 1);
1da177e4 LT	474	}
	475
	476	static void flush_tlb_mm_ipi(void *mm)
	477	{
	478	local_flush_tlb_mm((struct mm_struct *)mm);
	479	}
	480
25969354 RB	481	/*
	482	* Special Variant of smp_call_function for use by TLB functions:
	483	*
	484	* o No return value
	485	* o collapses to normal function call on UP kernels
	486	* o collapses to normal function call on systems with a single shared
	487	* primary cache.
25969354 RB	488	*/
	489	static inline void smp_on_other_tlbs(void (func) (void info), void *info)
	490	{
8691e5a8	491	smp_call_function(func, info, 1);
25969354 RB	492	}
	493
	494	static inline void smp_on_each_tlb(void (func) (void info), void *info)
	495	{
	496	preempt_disable();
	497
	498	smp_on_other_tlbs(func, info);
	499	func(info);
	500
	501	preempt_enable();
	502	}
	503
1da177e4 LT	504	/*
	505	* The following tlb flush calls are invoked when old translations are
	506	* being torn down, or pte attributes are changing. For single threaded
	507	* address spaces, a new context is obtained on the current cpu, and tlb
	508	* context on other cpus are invalidated to force a new context allocation
	509	* at switch_mm time, should the mm ever be used on other cpus. For
	510	* multithreaded address spaces, intercpu interrupts have to be sent.
	511	* Another case where intercpu interrupts are required is when the target
	512	* mm might be active on another cpu (eg debuggers doing the flushes on
	513	* behalf of debugees, kswapd stealing pages from another process etc).
	514	* Kanoj 07/00.
	515	*/
	516
	517	void flush_tlb_mm(struct mm_struct *mm)
	518	{
	519	preempt_disable();
	520
	521	if ((atomic_read(&mm->mm_users) != 1) \|\| (current->mm != mm)) {
c50cade9	522	smp_on_other_tlbs(flush_tlb_mm_ipi, mm);
1da177e4	523	} else {
b5eb5511 RB	524	unsigned int cpu;
b5eb5511 RB	525
0b5f9c00 RR	526	for_each_online_cpu(cpu) {
0b5f9c00 RR	527	if (cpu != smp_processor_id() && cpu_context(cpu, mm))
b5eb5511	528	cpu_context(cpu, mm) = 0;
0b5f9c00	529	}
1da177e4 LT	530	}
	531	local_flush_tlb_mm(mm);
	532
	533	preempt_enable();
	534	}
	535
	536	struct flush_tlb_data {
	537	struct vm_area_struct *vma;
	538	unsigned long addr1;
	539	unsigned long addr2;
	540	};
	541
	542	static void flush_tlb_range_ipi(void *info)
	543	{
c50cade9	544	struct flush_tlb_data *fd = info;
1da177e4 LT	545
	546	local_flush_tlb_range(fd->vma, fd->addr1, fd->addr2);
	547	}
	548
	549	void flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)
	550	{
	551	struct mm_struct *mm = vma->vm_mm;
	552
	553	preempt_disable();
	554	if ((atomic_read(&mm->mm_users) != 1) \|\| (current->mm != mm)) {
89a8a5a6 RB	555	struct flush_tlb_data fd = {
	556	.vma = vma,
	557	.addr1 = start,
	558	.addr2 = end,
	559	};
1da177e4	560
c50cade9	561	smp_on_other_tlbs(flush_tlb_range_ipi, &fd);
1da177e4	562	} else {
b5eb5511	563	unsigned int cpu;
a05c3920	564	int exec = vma->vm_flags & VM_EXEC;
b5eb5511	565
0b5f9c00	566	for_each_online_cpu(cpu) {
a05c3920 JH	567	/*
	568	* flush_cache_range() will only fully flush icache if
	569	* the VMA is executable, otherwise we must invalidate
	570	* ASID without it appearing to has_valid_asid() as if
	571	* mm has been completely unused by that CPU.
	572	*/
0b5f9c00	573	if (cpu != smp_processor_id() && cpu_context(cpu, mm))
a05c3920	574	cpu_context(cpu, mm) = !exec;
0b5f9c00	575	}
1da177e4 LT	576	}
	577	local_flush_tlb_range(vma, start, end);
	578	preempt_enable();
	579	}
	580
	581	static void flush_tlb_kernel_range_ipi(void *info)
	582	{
c50cade9	583	struct flush_tlb_data *fd = info;
1da177e4 LT	584
	585	local_flush_tlb_kernel_range(fd->addr1, fd->addr2);
	586	}
	587
	588	void flush_tlb_kernel_range(unsigned long start, unsigned long end)
	589	{
89a8a5a6 RB	590	struct flush_tlb_data fd = {
	591	.addr1 = start,
	592	.addr2 = end,
	593	};
1da177e4	594
15c8b6c1	595	on_each_cpu(flush_tlb_kernel_range_ipi, &fd, 1);
1da177e4 LT	596	}
	597
	598	static void flush_tlb_page_ipi(void *info)
	599	{
c50cade9	600	struct flush_tlb_data *fd = info;
1da177e4 LT	601
	602	local_flush_tlb_page(fd->vma, fd->addr1);
	603	}
	604
	605	void flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
	606	{
	607	preempt_disable();
	608	if ((atomic_read(&vma->vm_mm->mm_users) != 1) \|\| (current->mm != vma->vm_mm)) {
89a8a5a6 RB	609	struct flush_tlb_data fd = {
	610	.vma = vma,
	611	.addr1 = page,
	612	};
1da177e4	613
c50cade9	614	smp_on_other_tlbs(flush_tlb_page_ipi, &fd);
1da177e4	615	} else {
b5eb5511 RB	616	unsigned int cpu;
b5eb5511 RB	617
0b5f9c00	618	for_each_online_cpu(cpu) {
a05c3920 JH	619	/*
	620	* flush_cache_page() only does partial flushes, so
	621	* invalidate ASID without it appearing to
	622	* has_valid_asid() as if mm has been completely unused
	623	* by that CPU.
	624	*/
0b5f9c00	625	if (cpu != smp_processor_id() && cpu_context(cpu, vma->vm_mm))
a05c3920	626	cpu_context(cpu, vma->vm_mm) = 1;
0b5f9c00	627	}
1da177e4 LT	628	}
	629	local_flush_tlb_page(vma, page);
	630	preempt_enable();
	631	}
	632
	633	static void flush_tlb_one_ipi(void *info)
	634	{
	635	unsigned long vaddr = (unsigned long) info;
	636
	637	local_flush_tlb_one(vaddr);
	638	}
	639
	640	void flush_tlb_one(unsigned long vaddr)
	641	{
25969354	642	smp_on_each_tlb(flush_tlb_one_ipi, (void *) vaddr);
1da177e4 LT	643	}
	644
	645	EXPORT_SYMBOL(flush_tlb_page);
	646	EXPORT_SYMBOL(flush_tlb_one);
7aa1c8f4	647
cc7964af PB	648	#ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST
	649
	650	static DEFINE_PER_CPU(atomic_t, tick_broadcast_count);
	651	static DEFINE_PER_CPU(struct call_single_data, tick_broadcast_csd);
	652
	653	void tick_broadcast(const struct cpumask *mask)
	654	{
	655	atomic_t *count;
	656	struct call_single_data *csd;
	657	int cpu;
	658
	659	for_each_cpu(cpu, mask) {
	660	count = &per_cpu(tick_broadcast_count, cpu);
	661	csd = &per_cpu(tick_broadcast_csd, cpu);
	662
	663	if (atomic_inc_return(count) == 1)
	664	smp_call_function_single_async(cpu, csd);
	665	}
	666	}
	667
	668	static void tick_broadcast_callee(void *info)
	669	{
	670	int cpu = smp_processor_id();
	671	tick_receive_broadcast();
	672	atomic_set(&per_cpu(tick_broadcast_count, cpu), 0);
	673	}
	674
	675	static int __init tick_broadcast_init(void)
	676	{
	677	struct call_single_data *csd;
	678	int cpu;
	679
	680	for (cpu = 0; cpu < NR_CPUS; cpu++) {
	681	csd = &per_cpu(tick_broadcast_csd, cpu);
	682	csd->func = tick_broadcast_callee;
	683	}
	684
	685	return 0;
	686	}
	687	early_initcall(tick_broadcast_init);
	688
	689	#endif /* CONFIG_GENERIC_CLOCKEVENTS_BROADCAST */