[mirror_ubuntu-artful-kernel.git] / arch / mips / kernel / sync-r4k.c

/*
 * Count register synchronisation.
 *
 * All CPUs will have their count registers synchronised to the CPU0 next time
 * value. This can cause a small timewarp for CPU0. All other CPU's should
 * not have done anything significant (but they may have had interrupts
 * enabled briefly - prom_smp_finish() should not be responsible for enabling
 * interrupts...)
 */

#include <linux/kernel.h>
#include <linux/irqflags.h>
#include <linux/cpumask.h>

#include <asm/r4k-timer.h>
#include <linux/atomic.h>
#include <asm/barrier.h>
#include <asm/mipsregs.h>

static unsigned int initcount = 0;
static atomic_t count_count_start = ATOMIC_INIT(0);
static atomic_t count_count_stop = ATOMIC_INIT(0);

#define COUNTON 100
#define NR_LOOPS 3

void synchronise_count_master(int cpu)
{
	int i;
	unsigned long flags;

	pr_info("Synchronize counters for CPU %u: ", cpu);

	local_irq_save(flags);

	/*
	 * We loop a few times to get a primed instruction cache,
	 * then the last pass is more or less synchronised and
	 * the master and slaves each set their cycle counters to a known
	 * value all at once. This reduces the chance of having random offsets
	 * between the processors, and guarantees that the maximum
	 * delay between the cycle counters is never bigger than
	 * the latency of information-passing (cachelines) between
	 * two CPUs.
	 */

	for (i = 0; i < NR_LOOPS; i++) {
		/* slaves loop on '!= 2' */
		while (atomic_read(&count_count_start) != 1)
			mb();
		atomic_set(&count_count_stop, 0);
		smp_wmb();

		/* Let the slave writes its count register */
		atomic_inc(&count_count_start);

		/* Count will be initialised to current timer */
		if (i == 1)
			initcount = read_c0_count();

		/*
		 * Everyone initialises count in the last loop:
		 */
		if (i == NR_LOOPS-1)
			write_c0_count(initcount);

		/*
		 * Wait for slave to leave the synchronization point:
		 */
		while (atomic_read(&count_count_stop) != 1)
			mb();
		atomic_set(&count_count_start, 0);
		smp_wmb();
		atomic_inc(&count_count_stop);
	}
	/* Arrange for an interrupt in a short while */
	write_c0_compare(read_c0_count() + COUNTON);

	local_irq_restore(flags);

	/*
	 * i386 code reported the skew here, but the
	 * count registers were almost certainly out of sync
	 * so no point in alarming people
	 */
	pr_cont("done.\n");
}

void synchronise_count_slave(int cpu)
{
	int i;

	/*
	 * Not every cpu is online at the time this gets called,
	 * so we first wait for the master to say everyone is ready
	 */

	for (i = 0; i < NR_LOOPS; i++) {
		atomic_inc(&count_count_start);
		while (atomic_read(&count_count_start) != 2)
			mb();

		/*
		 * Everyone initialises count in the last loop:
		 */
		if (i == NR_LOOPS-1)
			write_c0_count(initcount);

		atomic_inc(&count_count_stop);
		while (atomic_read(&count_count_stop) != 2)
			mb();
	}
	/* Arrange for an interrupt in a short while */
	write_c0_compare(read_c0_count() + COUNTON);
}
#undef NR_LOOPS
Commit	Line	Data
39b8d525 RB	1	/*
	2	* Count register synchronisation.
	3	*
eb9b5141	4	* All CPUs will have their count registers synchronised to the CPU0 next time
39b8d525 RB	5	* value. This can cause a small timewarp for CPU0. All other CPU's should
	6	* not have done anything significant (but they may have had interrupts
	7	* enabled briefly - prom_smp_finish() should not be responsible for enabling
	8	* interrupts...)
39b8d525 RB	9	*/
	10
	11	#include <linux/kernel.h>
39b8d525	12	#include <linux/irqflags.h>
eb9b5141	13	#include <linux/cpumask.h>
39b8d525	14
eb9b5141	15	#include <asm/r4k-timer.h>
60063497	16	#include <linux/atomic.h>
39b8d525	17	#include <asm/barrier.h>
39b8d525 RB	18	#include <asm/mipsregs.h>
39b8d525 RB	19
db0dbd57	20	static unsigned int initcount = 0;
078a55fc PG	21	static atomic_t count_count_start = ATOMIC_INIT(0);
078a55fc PG	22	static atomic_t count_count_stop = ATOMIC_INIT(0);
39b8d525	23
70342287	24	#define COUNTON 100
db0dbd57	25	#define NR_LOOPS 3
39b8d525	26
078a55fc	27	void synchronise_count_master(int cpu)
39b8d525 RB	28	{
	29	int i;
	30	unsigned long flags;
39b8d525	31
4fb69afa	32	pr_info("Synchronize counters for CPU %u: ", cpu);
39b8d525 RB	33
	34	local_irq_save(flags);
	35
39b8d525 RB	36	/*
	37	* We loop a few times to get a primed instruction cache,
	38	* then the last pass is more or less synchronised and
	39	* the master and slaves each set their cycle counters to a known
	40	* value all at once. This reduces the chance of having random offsets
	41	* between the processors, and guarantees that the maximum
	42	* delay between the cycle counters is never bigger than
	43	* the latency of information-passing (cachelines) between
	44	* two CPUs.
	45	*/
	46
39b8d525	47	for (i = 0; i < NR_LOOPS; i++) {
cf9bfe55 J	48	/* slaves loop on '!= 2' */
cf9bfe55 J	49	while (atomic_read(&count_count_start) != 1)
39b8d525 RB	50	mb();
	51	atomic_set(&count_count_stop, 0);
	52	smp_wmb();
	53
db0dbd57	54	/* Let the slave writes its count register */
39b8d525 RB	55	atomic_inc(&count_count_start);
39b8d525 RB	56
db0dbd57 HC	57	/* Count will be initialised to current timer */
	58	if (i == 1)
	59	initcount = read_c0_count();
	60
39b8d525 RB	61	/*
	62	* Everyone initialises count in the last loop:
	63	*/
	64	if (i == NR_LOOPS-1)
	65	write_c0_count(initcount);
	66
	67	/*
db0dbd57	68	* Wait for slave to leave the synchronization point:
39b8d525	69	*/
cf9bfe55	70	while (atomic_read(&count_count_stop) != 1)
39b8d525 RB	71	mb();
	72	atomic_set(&count_count_start, 0);
	73	smp_wmb();
	74	atomic_inc(&count_count_stop);
	75	}
	76	/* Arrange for an interrupt in a short while */
	77	write_c0_compare(read_c0_count() + COUNTON);
	78
	79	local_irq_restore(flags);
	80
	81	/*
	82	* i386 code reported the skew here, but the
	83	* count registers were almost certainly out of sync
	84	* so no point in alarming people
	85	*/
4fb69afa	86	pr_cont("done.\n");
39b8d525 RB	87	}
39b8d525 RB	88
078a55fc	89	void synchronise_count_slave(int cpu)
39b8d525 RB	90	{
39b8d525 RB	91	int i;
39b8d525	92
39b8d525 RB	93	/*
	94	* Not every cpu is online at the time this gets called,
	95	* so we first wait for the master to say everyone is ready
	96	*/
	97
39b8d525 RB	98	for (i = 0; i < NR_LOOPS; i++) {
39b8d525 RB	99	atomic_inc(&count_count_start);
cf9bfe55	100	while (atomic_read(&count_count_start) != 2)
39b8d525 RB	101	mb();
	102
	103	/*
	104	* Everyone initialises count in the last loop:
	105	*/
	106	if (i == NR_LOOPS-1)
	107	write_c0_count(initcount);
	108
	109	atomic_inc(&count_count_stop);
cf9bfe55	110	while (atomic_read(&count_count_stop) != 2)
39b8d525 RB	111	mb();
	112	}
	113	/* Arrange for an interrupt in a short while */
	114	write_c0_compare(read_c0_count() + COUNTON);
39b8d525 RB	115	}
39b8d525 RB	116	#undef NR_LOOPS