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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public | |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
36ccf1c0 | 6 | * Copyright (C) 1994 - 1999, 2000, 01, 06 Ralf Baechle |
1da177e4 LT |
7 | * Copyright (C) 1995, 1996 Paul M. Antoine |
8 | * Copyright (C) 1998 Ulf Carlsson | |
9 | * Copyright (C) 1999 Silicon Graphics, Inc. | |
10 | * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com | |
11 | * Copyright (C) 2000, 01 MIPS Technologies, Inc. | |
60b0d655 | 12 | * Copyright (C) 2002, 2003, 2004, 2005, 2007 Maciej W. Rozycki |
1da177e4 | 13 | */ |
8e8a52ed | 14 | #include <linux/bug.h> |
60b0d655 | 15 | #include <linux/compiler.h> |
1da177e4 | 16 | #include <linux/init.h> |
8742cd23 | 17 | #include <linux/kernel.h> |
f9ded569 | 18 | #include <linux/module.h> |
1da177e4 | 19 | #include <linux/mm.h> |
1da177e4 LT |
20 | #include <linux/sched.h> |
21 | #include <linux/smp.h> | |
1da177e4 LT |
22 | #include <linux/spinlock.h> |
23 | #include <linux/kallsyms.h> | |
e01402b1 | 24 | #include <linux/bootmem.h> |
d4fd1989 | 25 | #include <linux/interrupt.h> |
39b8d525 | 26 | #include <linux/ptrace.h> |
88547001 JW |
27 | #include <linux/kgdb.h> |
28 | #include <linux/kdebug.h> | |
c1bf207d | 29 | #include <linux/kprobes.h> |
69f3a7de | 30 | #include <linux/notifier.h> |
5dd11d5d | 31 | #include <linux/kdb.h> |
ca4d3e67 | 32 | #include <linux/irq.h> |
7f788d2d | 33 | #include <linux/perf_event.h> |
1da177e4 LT |
34 | |
35 | #include <asm/bootinfo.h> | |
36 | #include <asm/branch.h> | |
37 | #include <asm/break.h> | |
69f3a7de | 38 | #include <asm/cop2.h> |
1da177e4 | 39 | #include <asm/cpu.h> |
e50c0a8f | 40 | #include <asm/dsp.h> |
1da177e4 | 41 | #include <asm/fpu.h> |
ba3049ed | 42 | #include <asm/fpu_emulator.h> |
340ee4b9 RB |
43 | #include <asm/mipsregs.h> |
44 | #include <asm/mipsmtregs.h> | |
1da177e4 LT |
45 | #include <asm/module.h> |
46 | #include <asm/pgtable.h> | |
47 | #include <asm/ptrace.h> | |
48 | #include <asm/sections.h> | |
1da177e4 LT |
49 | #include <asm/tlbdebug.h> |
50 | #include <asm/traps.h> | |
51 | #include <asm/uaccess.h> | |
b67b2b70 | 52 | #include <asm/watch.h> |
1da177e4 | 53 | #include <asm/mmu_context.h> |
1da177e4 | 54 | #include <asm/types.h> |
1df0f0ff | 55 | #include <asm/stacktrace.h> |
92bbe1b9 | 56 | #include <asm/uasm.h> |
1da177e4 | 57 | |
c65a5480 AN |
58 | extern void check_wait(void); |
59 | extern asmlinkage void r4k_wait(void); | |
60 | extern asmlinkage void rollback_handle_int(void); | |
e4ac58af | 61 | extern asmlinkage void handle_int(void); |
1da177e4 LT |
62 | extern asmlinkage void handle_tlbm(void); |
63 | extern asmlinkage void handle_tlbl(void); | |
64 | extern asmlinkage void handle_tlbs(void); | |
65 | extern asmlinkage void handle_adel(void); | |
66 | extern asmlinkage void handle_ades(void); | |
67 | extern asmlinkage void handle_ibe(void); | |
68 | extern asmlinkage void handle_dbe(void); | |
69 | extern asmlinkage void handle_sys(void); | |
70 | extern asmlinkage void handle_bp(void); | |
71 | extern asmlinkage void handle_ri(void); | |
5b10496b AN |
72 | extern asmlinkage void handle_ri_rdhwr_vivt(void); |
73 | extern asmlinkage void handle_ri_rdhwr(void); | |
1da177e4 LT |
74 | extern asmlinkage void handle_cpu(void); |
75 | extern asmlinkage void handle_ov(void); | |
76 | extern asmlinkage void handle_tr(void); | |
77 | extern asmlinkage void handle_fpe(void); | |
78 | extern asmlinkage void handle_mdmx(void); | |
79 | extern asmlinkage void handle_watch(void); | |
340ee4b9 | 80 | extern asmlinkage void handle_mt(void); |
e50c0a8f | 81 | extern asmlinkage void handle_dsp(void); |
1da177e4 LT |
82 | extern asmlinkage void handle_mcheck(void); |
83 | extern asmlinkage void handle_reserved(void); | |
84 | ||
12616ed2 | 85 | extern int fpu_emulator_cop1Handler(struct pt_regs *xcp, |
515b029d DD |
86 | struct mips_fpu_struct *ctx, int has_fpu, |
87 | void *__user *fault_addr); | |
1da177e4 LT |
88 | |
89 | void (*board_be_init)(void); | |
90 | int (*board_be_handler)(struct pt_regs *regs, int is_fixup); | |
e01402b1 RB |
91 | void (*board_nmi_handler_setup)(void); |
92 | void (*board_ejtag_handler_setup)(void); | |
93 | void (*board_bind_eic_interrupt)(int irq, int regset); | |
6fb97eff | 94 | void (*board_ebase_setup)(void); |
fcbf1dfd | 95 | void __cpuinitdata(*board_cache_error_setup)(void); |
1da177e4 | 96 | |
4d157d5e | 97 | static void show_raw_backtrace(unsigned long reg29) |
e889d78f | 98 | { |
39b8d525 | 99 | unsigned long *sp = (unsigned long *)(reg29 & ~3); |
e889d78f AN |
100 | unsigned long addr; |
101 | ||
102 | printk("Call Trace:"); | |
103 | #ifdef CONFIG_KALLSYMS | |
104 | printk("\n"); | |
105 | #endif | |
10220c88 TB |
106 | while (!kstack_end(sp)) { |
107 | unsigned long __user *p = | |
108 | (unsigned long __user *)(unsigned long)sp++; | |
109 | if (__get_user(addr, p)) { | |
110 | printk(" (Bad stack address)"); | |
111 | break; | |
39b8d525 | 112 | } |
10220c88 TB |
113 | if (__kernel_text_address(addr)) |
114 | print_ip_sym(addr); | |
e889d78f | 115 | } |
10220c88 | 116 | printk("\n"); |
e889d78f AN |
117 | } |
118 | ||
f66686f7 | 119 | #ifdef CONFIG_KALLSYMS |
1df0f0ff | 120 | int raw_show_trace; |
f66686f7 AN |
121 | static int __init set_raw_show_trace(char *str) |
122 | { | |
123 | raw_show_trace = 1; | |
124 | return 1; | |
125 | } | |
126 | __setup("raw_show_trace", set_raw_show_trace); | |
1df0f0ff | 127 | #endif |
4d157d5e | 128 | |
eae23f2c | 129 | static void show_backtrace(struct task_struct *task, const struct pt_regs *regs) |
f66686f7 | 130 | { |
4d157d5e FBH |
131 | unsigned long sp = regs->regs[29]; |
132 | unsigned long ra = regs->regs[31]; | |
f66686f7 | 133 | unsigned long pc = regs->cp0_epc; |
f66686f7 | 134 | |
e909be82 VW |
135 | if (!task) |
136 | task = current; | |
137 | ||
f66686f7 | 138 | if (raw_show_trace || !__kernel_text_address(pc)) { |
87151ae3 | 139 | show_raw_backtrace(sp); |
f66686f7 AN |
140 | return; |
141 | } | |
142 | printk("Call Trace:\n"); | |
4d157d5e | 143 | do { |
87151ae3 | 144 | print_ip_sym(pc); |
1924600c | 145 | pc = unwind_stack(task, &sp, pc, &ra); |
4d157d5e | 146 | } while (pc); |
f66686f7 AN |
147 | printk("\n"); |
148 | } | |
f66686f7 | 149 | |
1da177e4 LT |
150 | /* |
151 | * This routine abuses get_user()/put_user() to reference pointers | |
152 | * with at least a bit of error checking ... | |
153 | */ | |
eae23f2c RB |
154 | static void show_stacktrace(struct task_struct *task, |
155 | const struct pt_regs *regs) | |
1da177e4 LT |
156 | { |
157 | const int field = 2 * sizeof(unsigned long); | |
158 | long stackdata; | |
159 | int i; | |
5e0373b8 | 160 | unsigned long __user *sp = (unsigned long __user *)regs->regs[29]; |
1da177e4 LT |
161 | |
162 | printk("Stack :"); | |
163 | i = 0; | |
164 | while ((unsigned long) sp & (PAGE_SIZE - 1)) { | |
165 | if (i && ((i % (64 / field)) == 0)) | |
166 | printk("\n "); | |
167 | if (i > 39) { | |
168 | printk(" ..."); | |
169 | break; | |
170 | } | |
171 | ||
172 | if (__get_user(stackdata, sp++)) { | |
173 | printk(" (Bad stack address)"); | |
174 | break; | |
175 | } | |
176 | ||
177 | printk(" %0*lx", field, stackdata); | |
178 | i++; | |
179 | } | |
180 | printk("\n"); | |
87151ae3 | 181 | show_backtrace(task, regs); |
f66686f7 AN |
182 | } |
183 | ||
f66686f7 AN |
184 | void show_stack(struct task_struct *task, unsigned long *sp) |
185 | { | |
186 | struct pt_regs regs; | |
187 | if (sp) { | |
188 | regs.regs[29] = (unsigned long)sp; | |
189 | regs.regs[31] = 0; | |
190 | regs.cp0_epc = 0; | |
191 | } else { | |
192 | if (task && task != current) { | |
193 | regs.regs[29] = task->thread.reg29; | |
194 | regs.regs[31] = 0; | |
195 | regs.cp0_epc = task->thread.reg31; | |
5dd11d5d JW |
196 | #ifdef CONFIG_KGDB_KDB |
197 | } else if (atomic_read(&kgdb_active) != -1 && | |
198 | kdb_current_regs) { | |
199 | memcpy(®s, kdb_current_regs, sizeof(regs)); | |
200 | #endif /* CONFIG_KGDB_KDB */ | |
f66686f7 AN |
201 | } else { |
202 | prepare_frametrace(®s); | |
203 | } | |
204 | } | |
205 | show_stacktrace(task, ®s); | |
1da177e4 LT |
206 | } |
207 | ||
208 | /* | |
209 | * The architecture-independent dump_stack generator | |
210 | */ | |
211 | void dump_stack(void) | |
212 | { | |
1666a6fc | 213 | struct pt_regs regs; |
1da177e4 | 214 | |
1666a6fc FBH |
215 | prepare_frametrace(®s); |
216 | show_backtrace(current, ®s); | |
1da177e4 LT |
217 | } |
218 | ||
219 | EXPORT_SYMBOL(dump_stack); | |
220 | ||
e1bb8289 | 221 | static void show_code(unsigned int __user *pc) |
1da177e4 LT |
222 | { |
223 | long i; | |
39b8d525 | 224 | unsigned short __user *pc16 = NULL; |
1da177e4 LT |
225 | |
226 | printk("\nCode:"); | |
227 | ||
39b8d525 RB |
228 | if ((unsigned long)pc & 1) |
229 | pc16 = (unsigned short __user *)((unsigned long)pc & ~1); | |
1da177e4 LT |
230 | for(i = -3 ; i < 6 ; i++) { |
231 | unsigned int insn; | |
39b8d525 | 232 | if (pc16 ? __get_user(insn, pc16 + i) : __get_user(insn, pc + i)) { |
1da177e4 LT |
233 | printk(" (Bad address in epc)\n"); |
234 | break; | |
235 | } | |
39b8d525 | 236 | printk("%c%0*x%c", (i?' ':'<'), pc16 ? 4 : 8, insn, (i?' ':'>')); |
1da177e4 LT |
237 | } |
238 | } | |
239 | ||
eae23f2c | 240 | static void __show_regs(const struct pt_regs *regs) |
1da177e4 LT |
241 | { |
242 | const int field = 2 * sizeof(unsigned long); | |
243 | unsigned int cause = regs->cp0_cause; | |
244 | int i; | |
245 | ||
246 | printk("Cpu %d\n", smp_processor_id()); | |
247 | ||
248 | /* | |
249 | * Saved main processor registers | |
250 | */ | |
251 | for (i = 0; i < 32; ) { | |
252 | if ((i % 4) == 0) | |
253 | printk("$%2d :", i); | |
254 | if (i == 0) | |
255 | printk(" %0*lx", field, 0UL); | |
256 | else if (i == 26 || i == 27) | |
257 | printk(" %*s", field, ""); | |
258 | else | |
259 | printk(" %0*lx", field, regs->regs[i]); | |
260 | ||
261 | i++; | |
262 | if ((i % 4) == 0) | |
263 | printk("\n"); | |
264 | } | |
265 | ||
9693a853 FBH |
266 | #ifdef CONFIG_CPU_HAS_SMARTMIPS |
267 | printk("Acx : %0*lx\n", field, regs->acx); | |
268 | #endif | |
1da177e4 LT |
269 | printk("Hi : %0*lx\n", field, regs->hi); |
270 | printk("Lo : %0*lx\n", field, regs->lo); | |
271 | ||
272 | /* | |
273 | * Saved cp0 registers | |
274 | */ | |
b012cffe RB |
275 | printk("epc : %0*lx %pS\n", field, regs->cp0_epc, |
276 | (void *) regs->cp0_epc); | |
1da177e4 | 277 | printk(" %s\n", print_tainted()); |
b012cffe RB |
278 | printk("ra : %0*lx %pS\n", field, regs->regs[31], |
279 | (void *) regs->regs[31]); | |
1da177e4 LT |
280 | |
281 | printk("Status: %08x ", (uint32_t) regs->cp0_status); | |
282 | ||
3b2396d9 MR |
283 | if (current_cpu_data.isa_level == MIPS_CPU_ISA_I) { |
284 | if (regs->cp0_status & ST0_KUO) | |
285 | printk("KUo "); | |
286 | if (regs->cp0_status & ST0_IEO) | |
287 | printk("IEo "); | |
288 | if (regs->cp0_status & ST0_KUP) | |
289 | printk("KUp "); | |
290 | if (regs->cp0_status & ST0_IEP) | |
291 | printk("IEp "); | |
292 | if (regs->cp0_status & ST0_KUC) | |
293 | printk("KUc "); | |
294 | if (regs->cp0_status & ST0_IEC) | |
295 | printk("IEc "); | |
296 | } else { | |
297 | if (regs->cp0_status & ST0_KX) | |
298 | printk("KX "); | |
299 | if (regs->cp0_status & ST0_SX) | |
300 | printk("SX "); | |
301 | if (regs->cp0_status & ST0_UX) | |
302 | printk("UX "); | |
303 | switch (regs->cp0_status & ST0_KSU) { | |
304 | case KSU_USER: | |
305 | printk("USER "); | |
306 | break; | |
307 | case KSU_SUPERVISOR: | |
308 | printk("SUPERVISOR "); | |
309 | break; | |
310 | case KSU_KERNEL: | |
311 | printk("KERNEL "); | |
312 | break; | |
313 | default: | |
314 | printk("BAD_MODE "); | |
315 | break; | |
316 | } | |
317 | if (regs->cp0_status & ST0_ERL) | |
318 | printk("ERL "); | |
319 | if (regs->cp0_status & ST0_EXL) | |
320 | printk("EXL "); | |
321 | if (regs->cp0_status & ST0_IE) | |
322 | printk("IE "); | |
1da177e4 | 323 | } |
1da177e4 LT |
324 | printk("\n"); |
325 | ||
326 | printk("Cause : %08x\n", cause); | |
327 | ||
328 | cause = (cause & CAUSEF_EXCCODE) >> CAUSEB_EXCCODE; | |
329 | if (1 <= cause && cause <= 5) | |
330 | printk("BadVA : %0*lx\n", field, regs->cp0_badvaddr); | |
331 | ||
9966db25 RB |
332 | printk("PrId : %08x (%s)\n", read_c0_prid(), |
333 | cpu_name_string()); | |
1da177e4 LT |
334 | } |
335 | ||
eae23f2c RB |
336 | /* |
337 | * FIXME: really the generic show_regs should take a const pointer argument. | |
338 | */ | |
339 | void show_regs(struct pt_regs *regs) | |
340 | { | |
341 | __show_regs((struct pt_regs *)regs); | |
342 | } | |
343 | ||
c1bf207d | 344 | void show_registers(struct pt_regs *regs) |
1da177e4 | 345 | { |
39b8d525 RB |
346 | const int field = 2 * sizeof(unsigned long); |
347 | ||
eae23f2c | 348 | __show_regs(regs); |
1da177e4 | 349 | print_modules(); |
39b8d525 RB |
350 | printk("Process %s (pid: %d, threadinfo=%p, task=%p, tls=%0*lx)\n", |
351 | current->comm, current->pid, current_thread_info(), current, | |
352 | field, current_thread_info()->tp_value); | |
353 | if (cpu_has_userlocal) { | |
354 | unsigned long tls; | |
355 | ||
356 | tls = read_c0_userlocal(); | |
357 | if (tls != current_thread_info()->tp_value) | |
358 | printk("*HwTLS: %0*lx\n", field, tls); | |
359 | } | |
360 | ||
f66686f7 | 361 | show_stacktrace(current, regs); |
e1bb8289 | 362 | show_code((unsigned int __user *) regs->cp0_epc); |
1da177e4 LT |
363 | printk("\n"); |
364 | } | |
365 | ||
70dc6f04 DD |
366 | static int regs_to_trapnr(struct pt_regs *regs) |
367 | { | |
368 | return (regs->cp0_cause >> 2) & 0x1f; | |
369 | } | |
370 | ||
4d85f6af | 371 | static DEFINE_RAW_SPINLOCK(die_lock); |
1da177e4 | 372 | |
70dc6f04 | 373 | void __noreturn die(const char *str, struct pt_regs *regs) |
1da177e4 LT |
374 | { |
375 | static int die_counter; | |
ce384d83 | 376 | int sig = SIGSEGV; |
41c594ab | 377 | #ifdef CONFIG_MIPS_MT_SMTC |
8742cd23 | 378 | unsigned long dvpret; |
41c594ab | 379 | #endif /* CONFIG_MIPS_MT_SMTC */ |
1da177e4 | 380 | |
8742cd23 NL |
381 | oops_enter(); |
382 | ||
10423c91 RB |
383 | if (notify_die(DIE_OOPS, str, regs, 0, regs_to_trapnr(regs), SIGSEGV) == NOTIFY_STOP) |
384 | sig = 0; | |
5dd11d5d | 385 | |
1da177e4 | 386 | console_verbose(); |
4d85f6af | 387 | raw_spin_lock_irq(&die_lock); |
8742cd23 NL |
388 | #ifdef CONFIG_MIPS_MT_SMTC |
389 | dvpret = dvpe(); | |
390 | #endif /* CONFIG_MIPS_MT_SMTC */ | |
41c594ab RB |
391 | bust_spinlocks(1); |
392 | #ifdef CONFIG_MIPS_MT_SMTC | |
393 | mips_mt_regdump(dvpret); | |
394 | #endif /* CONFIG_MIPS_MT_SMTC */ | |
ce384d83 | 395 | |
178086c8 | 396 | printk("%s[#%d]:\n", str, ++die_counter); |
1da177e4 | 397 | show_registers(regs); |
bcdcd8e7 | 398 | add_taint(TAINT_DIE); |
4d85f6af | 399 | raw_spin_unlock_irq(&die_lock); |
d4fd1989 | 400 | |
8742cd23 NL |
401 | oops_exit(); |
402 | ||
d4fd1989 MB |
403 | if (in_interrupt()) |
404 | panic("Fatal exception in interrupt"); | |
405 | ||
406 | if (panic_on_oops) { | |
ab75dc02 | 407 | printk(KERN_EMERG "Fatal exception: panic in 5 seconds"); |
d4fd1989 MB |
408 | ssleep(5); |
409 | panic("Fatal exception"); | |
410 | } | |
411 | ||
ce384d83 | 412 | do_exit(sig); |
1da177e4 LT |
413 | } |
414 | ||
0510617b TB |
415 | extern struct exception_table_entry __start___dbe_table[]; |
416 | extern struct exception_table_entry __stop___dbe_table[]; | |
1da177e4 | 417 | |
b6dcec9b RB |
418 | __asm__( |
419 | " .section __dbe_table, \"a\"\n" | |
420 | " .previous \n"); | |
1da177e4 LT |
421 | |
422 | /* Given an address, look for it in the exception tables. */ | |
423 | static const struct exception_table_entry *search_dbe_tables(unsigned long addr) | |
424 | { | |
425 | const struct exception_table_entry *e; | |
426 | ||
427 | e = search_extable(__start___dbe_table, __stop___dbe_table - 1, addr); | |
428 | if (!e) | |
429 | e = search_module_dbetables(addr); | |
430 | return e; | |
431 | } | |
432 | ||
433 | asmlinkage void do_be(struct pt_regs *regs) | |
434 | { | |
435 | const int field = 2 * sizeof(unsigned long); | |
436 | const struct exception_table_entry *fixup = NULL; | |
437 | int data = regs->cp0_cause & 4; | |
438 | int action = MIPS_BE_FATAL; | |
439 | ||
440 | /* XXX For now. Fixme, this searches the wrong table ... */ | |
441 | if (data && !user_mode(regs)) | |
442 | fixup = search_dbe_tables(exception_epc(regs)); | |
443 | ||
444 | if (fixup) | |
445 | action = MIPS_BE_FIXUP; | |
446 | ||
447 | if (board_be_handler) | |
28fc582c | 448 | action = board_be_handler(regs, fixup != NULL); |
1da177e4 LT |
449 | |
450 | switch (action) { | |
451 | case MIPS_BE_DISCARD: | |
452 | return; | |
453 | case MIPS_BE_FIXUP: | |
454 | if (fixup) { | |
455 | regs->cp0_epc = fixup->nextinsn; | |
456 | return; | |
457 | } | |
458 | break; | |
459 | default: | |
460 | break; | |
461 | } | |
462 | ||
463 | /* | |
464 | * Assume it would be too dangerous to continue ... | |
465 | */ | |
466 | printk(KERN_ALERT "%s bus error, epc == %0*lx, ra == %0*lx\n", | |
467 | data ? "Data" : "Instruction", | |
468 | field, regs->cp0_epc, field, regs->regs[31]); | |
70dc6f04 | 469 | if (notify_die(DIE_OOPS, "bus error", regs, 0, regs_to_trapnr(regs), SIGBUS) |
88547001 JW |
470 | == NOTIFY_STOP) |
471 | return; | |
472 | ||
1da177e4 LT |
473 | die_if_kernel("Oops", regs); |
474 | force_sig(SIGBUS, current); | |
475 | } | |
476 | ||
1da177e4 | 477 | /* |
60b0d655 | 478 | * ll/sc, rdhwr, sync emulation |
1da177e4 LT |
479 | */ |
480 | ||
481 | #define OPCODE 0xfc000000 | |
482 | #define BASE 0x03e00000 | |
483 | #define RT 0x001f0000 | |
484 | #define OFFSET 0x0000ffff | |
485 | #define LL 0xc0000000 | |
486 | #define SC 0xe0000000 | |
60b0d655 | 487 | #define SPEC0 0x00000000 |
3c37026d RB |
488 | #define SPEC3 0x7c000000 |
489 | #define RD 0x0000f800 | |
490 | #define FUNC 0x0000003f | |
60b0d655 | 491 | #define SYNC 0x0000000f |
3c37026d | 492 | #define RDHWR 0x0000003b |
1da177e4 LT |
493 | |
494 | /* | |
495 | * The ll_bit is cleared by r*_switch.S | |
496 | */ | |
497 | ||
f1e39a4a RB |
498 | unsigned int ll_bit; |
499 | struct task_struct *ll_task; | |
1da177e4 | 500 | |
60b0d655 | 501 | static inline int simulate_ll(struct pt_regs *regs, unsigned int opcode) |
1da177e4 | 502 | { |
fe00f943 | 503 | unsigned long value, __user *vaddr; |
1da177e4 | 504 | long offset; |
1da177e4 LT |
505 | |
506 | /* | |
507 | * analyse the ll instruction that just caused a ri exception | |
508 | * and put the referenced address to addr. | |
509 | */ | |
510 | ||
511 | /* sign extend offset */ | |
512 | offset = opcode & OFFSET; | |
513 | offset <<= 16; | |
514 | offset >>= 16; | |
515 | ||
fe00f943 RB |
516 | vaddr = (unsigned long __user *) |
517 | ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset); | |
1da177e4 | 518 | |
60b0d655 MR |
519 | if ((unsigned long)vaddr & 3) |
520 | return SIGBUS; | |
521 | if (get_user(value, vaddr)) | |
522 | return SIGSEGV; | |
1da177e4 LT |
523 | |
524 | preempt_disable(); | |
525 | ||
526 | if (ll_task == NULL || ll_task == current) { | |
527 | ll_bit = 1; | |
528 | } else { | |
529 | ll_bit = 0; | |
530 | } | |
531 | ll_task = current; | |
532 | ||
533 | preempt_enable(); | |
534 | ||
535 | regs->regs[(opcode & RT) >> 16] = value; | |
536 | ||
60b0d655 | 537 | return 0; |
1da177e4 LT |
538 | } |
539 | ||
60b0d655 | 540 | static inline int simulate_sc(struct pt_regs *regs, unsigned int opcode) |
1da177e4 | 541 | { |
fe00f943 RB |
542 | unsigned long __user *vaddr; |
543 | unsigned long reg; | |
1da177e4 | 544 | long offset; |
1da177e4 LT |
545 | |
546 | /* | |
547 | * analyse the sc instruction that just caused a ri exception | |
548 | * and put the referenced address to addr. | |
549 | */ | |
550 | ||
551 | /* sign extend offset */ | |
552 | offset = opcode & OFFSET; | |
553 | offset <<= 16; | |
554 | offset >>= 16; | |
555 | ||
fe00f943 RB |
556 | vaddr = (unsigned long __user *) |
557 | ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset); | |
1da177e4 LT |
558 | reg = (opcode & RT) >> 16; |
559 | ||
60b0d655 MR |
560 | if ((unsigned long)vaddr & 3) |
561 | return SIGBUS; | |
1da177e4 LT |
562 | |
563 | preempt_disable(); | |
564 | ||
565 | if (ll_bit == 0 || ll_task != current) { | |
566 | regs->regs[reg] = 0; | |
567 | preempt_enable(); | |
60b0d655 | 568 | return 0; |
1da177e4 LT |
569 | } |
570 | ||
571 | preempt_enable(); | |
572 | ||
60b0d655 MR |
573 | if (put_user(regs->regs[reg], vaddr)) |
574 | return SIGSEGV; | |
1da177e4 LT |
575 | |
576 | regs->regs[reg] = 1; | |
577 | ||
60b0d655 | 578 | return 0; |
1da177e4 LT |
579 | } |
580 | ||
581 | /* | |
582 | * ll uses the opcode of lwc0 and sc uses the opcode of swc0. That is both | |
583 | * opcodes are supposed to result in coprocessor unusable exceptions if | |
584 | * executed on ll/sc-less processors. That's the theory. In practice a | |
585 | * few processors such as NEC's VR4100 throw reserved instruction exceptions | |
586 | * instead, so we're doing the emulation thing in both exception handlers. | |
587 | */ | |
60b0d655 | 588 | static int simulate_llsc(struct pt_regs *regs, unsigned int opcode) |
1da177e4 | 589 | { |
7f788d2d DCZ |
590 | if ((opcode & OPCODE) == LL) { |
591 | perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, | |
a8b0ca17 | 592 | 1, regs, 0); |
60b0d655 | 593 | return simulate_ll(regs, opcode); |
7f788d2d DCZ |
594 | } |
595 | if ((opcode & OPCODE) == SC) { | |
596 | perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, | |
a8b0ca17 | 597 | 1, regs, 0); |
60b0d655 | 598 | return simulate_sc(regs, opcode); |
7f788d2d | 599 | } |
1da177e4 | 600 | |
60b0d655 | 601 | return -1; /* Must be something else ... */ |
1da177e4 LT |
602 | } |
603 | ||
3c37026d RB |
604 | /* |
605 | * Simulate trapping 'rdhwr' instructions to provide user accessible | |
1f5826bd | 606 | * registers not implemented in hardware. |
3c37026d | 607 | */ |
60b0d655 | 608 | static int simulate_rdhwr(struct pt_regs *regs, unsigned int opcode) |
3c37026d | 609 | { |
dc8f6029 | 610 | struct thread_info *ti = task_thread_info(current); |
3c37026d RB |
611 | |
612 | if ((opcode & OPCODE) == SPEC3 && (opcode & FUNC) == RDHWR) { | |
613 | int rd = (opcode & RD) >> 11; | |
614 | int rt = (opcode & RT) >> 16; | |
7f788d2d | 615 | perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, |
a8b0ca17 | 616 | 1, regs, 0); |
3c37026d | 617 | switch (rd) { |
1f5826bd CD |
618 | case 0: /* CPU number */ |
619 | regs->regs[rt] = smp_processor_id(); | |
620 | return 0; | |
621 | case 1: /* SYNCI length */ | |
622 | regs->regs[rt] = min(current_cpu_data.dcache.linesz, | |
623 | current_cpu_data.icache.linesz); | |
624 | return 0; | |
625 | case 2: /* Read count register */ | |
626 | regs->regs[rt] = read_c0_count(); | |
627 | return 0; | |
628 | case 3: /* Count register resolution */ | |
629 | switch (current_cpu_data.cputype) { | |
630 | case CPU_20KC: | |
631 | case CPU_25KF: | |
632 | regs->regs[rt] = 1; | |
633 | break; | |
3c37026d | 634 | default: |
1f5826bd CD |
635 | regs->regs[rt] = 2; |
636 | } | |
637 | return 0; | |
638 | case 29: | |
639 | regs->regs[rt] = ti->tp_value; | |
640 | return 0; | |
641 | default: | |
642 | return -1; | |
3c37026d RB |
643 | } |
644 | } | |
645 | ||
56ebd51b | 646 | /* Not ours. */ |
60b0d655 MR |
647 | return -1; |
648 | } | |
e5679882 | 649 | |
60b0d655 MR |
650 | static int simulate_sync(struct pt_regs *regs, unsigned int opcode) |
651 | { | |
7f788d2d DCZ |
652 | if ((opcode & OPCODE) == SPEC0 && (opcode & FUNC) == SYNC) { |
653 | perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, | |
a8b0ca17 | 654 | 1, regs, 0); |
60b0d655 | 655 | return 0; |
7f788d2d | 656 | } |
60b0d655 MR |
657 | |
658 | return -1; /* Must be something else ... */ | |
3c37026d RB |
659 | } |
660 | ||
1da177e4 LT |
661 | asmlinkage void do_ov(struct pt_regs *regs) |
662 | { | |
663 | siginfo_t info; | |
664 | ||
36ccf1c0 RB |
665 | die_if_kernel("Integer overflow", regs); |
666 | ||
1da177e4 LT |
667 | info.si_code = FPE_INTOVF; |
668 | info.si_signo = SIGFPE; | |
669 | info.si_errno = 0; | |
fe00f943 | 670 | info.si_addr = (void __user *) regs->cp0_epc; |
1da177e4 LT |
671 | force_sig_info(SIGFPE, &info, current); |
672 | } | |
673 | ||
515b029d DD |
674 | static int process_fpemu_return(int sig, void __user *fault_addr) |
675 | { | |
676 | if (sig == SIGSEGV || sig == SIGBUS) { | |
677 | struct siginfo si = {0}; | |
678 | si.si_addr = fault_addr; | |
679 | si.si_signo = sig; | |
680 | if (sig == SIGSEGV) { | |
681 | if (find_vma(current->mm, (unsigned long)fault_addr)) | |
682 | si.si_code = SEGV_ACCERR; | |
683 | else | |
684 | si.si_code = SEGV_MAPERR; | |
685 | } else { | |
686 | si.si_code = BUS_ADRERR; | |
687 | } | |
688 | force_sig_info(sig, &si, current); | |
689 | return 1; | |
690 | } else if (sig) { | |
691 | force_sig(sig, current); | |
692 | return 1; | |
693 | } else { | |
694 | return 0; | |
695 | } | |
696 | } | |
697 | ||
1da177e4 LT |
698 | /* |
699 | * XXX Delayed fp exceptions when doing a lazy ctx switch XXX | |
700 | */ | |
701 | asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31) | |
702 | { | |
515b029d | 703 | siginfo_t info = {0}; |
948a34cf | 704 | |
70dc6f04 | 705 | if (notify_die(DIE_FP, "FP exception", regs, 0, regs_to_trapnr(regs), SIGFPE) |
88547001 JW |
706 | == NOTIFY_STOP) |
707 | return; | |
57725f9e CD |
708 | die_if_kernel("FP exception in kernel code", regs); |
709 | ||
1da177e4 LT |
710 | if (fcr31 & FPU_CSR_UNI_X) { |
711 | int sig; | |
515b029d | 712 | void __user *fault_addr = NULL; |
1da177e4 | 713 | |
1da177e4 | 714 | /* |
a3dddd56 | 715 | * Unimplemented operation exception. If we've got the full |
1da177e4 LT |
716 | * software emulator on-board, let's use it... |
717 | * | |
718 | * Force FPU to dump state into task/thread context. We're | |
719 | * moving a lot of data here for what is probably a single | |
720 | * instruction, but the alternative is to pre-decode the FP | |
721 | * register operands before invoking the emulator, which seems | |
722 | * a bit extreme for what should be an infrequent event. | |
723 | */ | |
cd21dfcf | 724 | /* Ensure 'resume' not overwrite saved fp context again. */ |
53dc8028 | 725 | lose_fpu(1); |
1da177e4 LT |
726 | |
727 | /* Run the emulator */ | |
515b029d DD |
728 | sig = fpu_emulator_cop1Handler(regs, ¤t->thread.fpu, 1, |
729 | &fault_addr); | |
1da177e4 LT |
730 | |
731 | /* | |
732 | * We can't allow the emulated instruction to leave any of | |
733 | * the cause bit set in $fcr31. | |
734 | */ | |
eae89076 | 735 | current->thread.fpu.fcr31 &= ~FPU_CSR_ALL_X; |
1da177e4 LT |
736 | |
737 | /* Restore the hardware register state */ | |
53dc8028 | 738 | own_fpu(1); /* Using the FPU again. */ |
1da177e4 LT |
739 | |
740 | /* If something went wrong, signal */ | |
515b029d | 741 | process_fpemu_return(sig, fault_addr); |
1da177e4 LT |
742 | |
743 | return; | |
948a34cf TS |
744 | } else if (fcr31 & FPU_CSR_INV_X) |
745 | info.si_code = FPE_FLTINV; | |
746 | else if (fcr31 & FPU_CSR_DIV_X) | |
747 | info.si_code = FPE_FLTDIV; | |
748 | else if (fcr31 & FPU_CSR_OVF_X) | |
749 | info.si_code = FPE_FLTOVF; | |
750 | else if (fcr31 & FPU_CSR_UDF_X) | |
751 | info.si_code = FPE_FLTUND; | |
752 | else if (fcr31 & FPU_CSR_INE_X) | |
753 | info.si_code = FPE_FLTRES; | |
754 | else | |
755 | info.si_code = __SI_FAULT; | |
756 | info.si_signo = SIGFPE; | |
757 | info.si_errno = 0; | |
758 | info.si_addr = (void __user *) regs->cp0_epc; | |
759 | force_sig_info(SIGFPE, &info, current); | |
1da177e4 LT |
760 | } |
761 | ||
df270051 RB |
762 | static void do_trap_or_bp(struct pt_regs *regs, unsigned int code, |
763 | const char *str) | |
1da177e4 | 764 | { |
1da177e4 | 765 | siginfo_t info; |
df270051 | 766 | char b[40]; |
1da177e4 | 767 | |
5dd11d5d | 768 | #ifdef CONFIG_KGDB_LOW_LEVEL_TRAP |
70dc6f04 | 769 | if (kgdb_ll_trap(DIE_TRAP, str, regs, code, regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP) |
5dd11d5d JW |
770 | return; |
771 | #endif /* CONFIG_KGDB_LOW_LEVEL_TRAP */ | |
772 | ||
70dc6f04 | 773 | if (notify_die(DIE_TRAP, str, regs, code, regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP) |
88547001 JW |
774 | return; |
775 | ||
1da177e4 | 776 | /* |
df270051 RB |
777 | * A short test says that IRIX 5.3 sends SIGTRAP for all trap |
778 | * insns, even for trap and break codes that indicate arithmetic | |
779 | * failures. Weird ... | |
1da177e4 LT |
780 | * But should we continue the brokenness??? --macro |
781 | */ | |
df270051 RB |
782 | switch (code) { |
783 | case BRK_OVERFLOW: | |
784 | case BRK_DIVZERO: | |
785 | scnprintf(b, sizeof(b), "%s instruction in kernel code", str); | |
786 | die_if_kernel(b, regs); | |
787 | if (code == BRK_DIVZERO) | |
1da177e4 LT |
788 | info.si_code = FPE_INTDIV; |
789 | else | |
790 | info.si_code = FPE_INTOVF; | |
791 | info.si_signo = SIGFPE; | |
792 | info.si_errno = 0; | |
fe00f943 | 793 | info.si_addr = (void __user *) regs->cp0_epc; |
1da177e4 LT |
794 | force_sig_info(SIGFPE, &info, current); |
795 | break; | |
63dc68a8 | 796 | case BRK_BUG: |
df270051 RB |
797 | die_if_kernel("Kernel bug detected", regs); |
798 | force_sig(SIGTRAP, current); | |
63dc68a8 | 799 | break; |
ba3049ed RB |
800 | case BRK_MEMU: |
801 | /* | |
802 | * Address errors may be deliberately induced by the FPU | |
803 | * emulator to retake control of the CPU after executing the | |
804 | * instruction in the delay slot of an emulated branch. | |
805 | * | |
806 | * Terminate if exception was recognized as a delay slot return | |
807 | * otherwise handle as normal. | |
808 | */ | |
809 | if (do_dsemulret(regs)) | |
810 | return; | |
811 | ||
812 | die_if_kernel("Math emu break/trap", regs); | |
813 | force_sig(SIGTRAP, current); | |
814 | break; | |
1da177e4 | 815 | default: |
df270051 RB |
816 | scnprintf(b, sizeof(b), "%s instruction in kernel code", str); |
817 | die_if_kernel(b, regs); | |
1da177e4 LT |
818 | force_sig(SIGTRAP, current); |
819 | } | |
df270051 RB |
820 | } |
821 | ||
822 | asmlinkage void do_bp(struct pt_regs *regs) | |
823 | { | |
824 | unsigned int opcode, bcode; | |
825 | ||
826 | if (__get_user(opcode, (unsigned int __user *) exception_epc(regs))) | |
827 | goto out_sigsegv; | |
828 | ||
829 | /* | |
830 | * There is the ancient bug in the MIPS assemblers that the break | |
831 | * code starts left to bit 16 instead to bit 6 in the opcode. | |
832 | * Gas is bug-compatible, but not always, grrr... | |
833 | * We handle both cases with a simple heuristics. --macro | |
834 | */ | |
835 | bcode = ((opcode >> 6) & ((1 << 20) - 1)); | |
836 | if (bcode >= (1 << 10)) | |
837 | bcode >>= 10; | |
838 | ||
c1bf207d DD |
839 | /* |
840 | * notify the kprobe handlers, if instruction is likely to | |
841 | * pertain to them. | |
842 | */ | |
843 | switch (bcode) { | |
844 | case BRK_KPROBE_BP: | |
70dc6f04 | 845 | if (notify_die(DIE_BREAK, "debug", regs, bcode, regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP) |
c1bf207d DD |
846 | return; |
847 | else | |
848 | break; | |
849 | case BRK_KPROBE_SSTEPBP: | |
70dc6f04 | 850 | if (notify_die(DIE_SSTEPBP, "single_step", regs, bcode, regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP) |
c1bf207d DD |
851 | return; |
852 | else | |
853 | break; | |
854 | default: | |
855 | break; | |
856 | } | |
857 | ||
df270051 | 858 | do_trap_or_bp(regs, bcode, "Break"); |
90fccb13 | 859 | return; |
e5679882 RB |
860 | |
861 | out_sigsegv: | |
862 | force_sig(SIGSEGV, current); | |
1da177e4 LT |
863 | } |
864 | ||
865 | asmlinkage void do_tr(struct pt_regs *regs) | |
866 | { | |
867 | unsigned int opcode, tcode = 0; | |
1da177e4 | 868 | |
ba755f8e | 869 | if (__get_user(opcode, (unsigned int __user *) exception_epc(regs))) |
e5679882 | 870 | goto out_sigsegv; |
1da177e4 LT |
871 | |
872 | /* Immediate versions don't provide a code. */ | |
873 | if (!(opcode & OPCODE)) | |
874 | tcode = ((opcode >> 6) & ((1 << 10) - 1)); | |
875 | ||
df270051 | 876 | do_trap_or_bp(regs, tcode, "Trap"); |
90fccb13 | 877 | return; |
e5679882 RB |
878 | |
879 | out_sigsegv: | |
880 | force_sig(SIGSEGV, current); | |
1da177e4 LT |
881 | } |
882 | ||
883 | asmlinkage void do_ri(struct pt_regs *regs) | |
884 | { | |
60b0d655 MR |
885 | unsigned int __user *epc = (unsigned int __user *)exception_epc(regs); |
886 | unsigned long old_epc = regs->cp0_epc; | |
887 | unsigned int opcode = 0; | |
888 | int status = -1; | |
1da177e4 | 889 | |
70dc6f04 | 890 | if (notify_die(DIE_RI, "RI Fault", regs, 0, regs_to_trapnr(regs), SIGILL) |
88547001 JW |
891 | == NOTIFY_STOP) |
892 | return; | |
893 | ||
60b0d655 | 894 | die_if_kernel("Reserved instruction in kernel code", regs); |
1da177e4 | 895 | |
60b0d655 | 896 | if (unlikely(compute_return_epc(regs) < 0)) |
3c37026d RB |
897 | return; |
898 | ||
60b0d655 MR |
899 | if (unlikely(get_user(opcode, epc) < 0)) |
900 | status = SIGSEGV; | |
901 | ||
902 | if (!cpu_has_llsc && status < 0) | |
903 | status = simulate_llsc(regs, opcode); | |
904 | ||
905 | if (status < 0) | |
906 | status = simulate_rdhwr(regs, opcode); | |
907 | ||
908 | if (status < 0) | |
909 | status = simulate_sync(regs, opcode); | |
910 | ||
911 | if (status < 0) | |
912 | status = SIGILL; | |
913 | ||
914 | if (unlikely(status > 0)) { | |
915 | regs->cp0_epc = old_epc; /* Undo skip-over. */ | |
916 | force_sig(status, current); | |
917 | } | |
1da177e4 LT |
918 | } |
919 | ||
d223a861 RB |
920 | /* |
921 | * MIPS MT processors may have fewer FPU contexts than CPU threads. If we've | |
922 | * emulated more than some threshold number of instructions, force migration to | |
923 | * a "CPU" that has FP support. | |
924 | */ | |
925 | static void mt_ase_fp_affinity(void) | |
926 | { | |
927 | #ifdef CONFIG_MIPS_MT_FPAFF | |
928 | if (mt_fpemul_threshold > 0 && | |
929 | ((current->thread.emulated_fp++ > mt_fpemul_threshold))) { | |
930 | /* | |
931 | * If there's no FPU present, or if the application has already | |
932 | * restricted the allowed set to exclude any CPUs with FPUs, | |
933 | * we'll skip the procedure. | |
934 | */ | |
935 | if (cpus_intersects(current->cpus_allowed, mt_fpu_cpumask)) { | |
936 | cpumask_t tmask; | |
937 | ||
9cc12363 KK |
938 | current->thread.user_cpus_allowed |
939 | = current->cpus_allowed; | |
940 | cpus_and(tmask, current->cpus_allowed, | |
941 | mt_fpu_cpumask); | |
ed1bbdef | 942 | set_cpus_allowed_ptr(current, &tmask); |
293c5bd1 | 943 | set_thread_flag(TIF_FPUBOUND); |
d223a861 RB |
944 | } |
945 | } | |
946 | #endif /* CONFIG_MIPS_MT_FPAFF */ | |
947 | } | |
948 | ||
69f3a7de RB |
949 | /* |
950 | * No lock; only written during early bootup by CPU 0. | |
951 | */ | |
952 | static RAW_NOTIFIER_HEAD(cu2_chain); | |
953 | ||
954 | int __ref register_cu2_notifier(struct notifier_block *nb) | |
955 | { | |
956 | return raw_notifier_chain_register(&cu2_chain, nb); | |
957 | } | |
958 | ||
959 | int cu2_notifier_call_chain(unsigned long val, void *v) | |
960 | { | |
961 | return raw_notifier_call_chain(&cu2_chain, val, v); | |
962 | } | |
963 | ||
964 | static int default_cu2_call(struct notifier_block *nfb, unsigned long action, | |
965 | void *data) | |
966 | { | |
967 | struct pt_regs *regs = data; | |
968 | ||
969 | switch (action) { | |
970 | default: | |
971 | die_if_kernel("Unhandled kernel unaligned access or invalid " | |
972 | "instruction", regs); | |
973 | /* Fall through */ | |
974 | ||
975 | case CU2_EXCEPTION: | |
976 | force_sig(SIGILL, current); | |
977 | } | |
978 | ||
979 | return NOTIFY_OK; | |
980 | } | |
981 | ||
1da177e4 LT |
982 | asmlinkage void do_cpu(struct pt_regs *regs) |
983 | { | |
60b0d655 MR |
984 | unsigned int __user *epc; |
985 | unsigned long old_epc; | |
986 | unsigned int opcode; | |
1da177e4 | 987 | unsigned int cpid; |
60b0d655 | 988 | int status; |
f9bb4cf3 | 989 | unsigned long __maybe_unused flags; |
1da177e4 | 990 | |
5323180d AN |
991 | die_if_kernel("do_cpu invoked from kernel context!", regs); |
992 | ||
1da177e4 LT |
993 | cpid = (regs->cp0_cause >> CAUSEB_CE) & 3; |
994 | ||
995 | switch (cpid) { | |
996 | case 0: | |
60b0d655 MR |
997 | epc = (unsigned int __user *)exception_epc(regs); |
998 | old_epc = regs->cp0_epc; | |
999 | opcode = 0; | |
1000 | status = -1; | |
1da177e4 | 1001 | |
60b0d655 | 1002 | if (unlikely(compute_return_epc(regs) < 0)) |
1da177e4 | 1003 | return; |
3c37026d | 1004 | |
60b0d655 MR |
1005 | if (unlikely(get_user(opcode, epc) < 0)) |
1006 | status = SIGSEGV; | |
1007 | ||
1008 | if (!cpu_has_llsc && status < 0) | |
1009 | status = simulate_llsc(regs, opcode); | |
1010 | ||
1011 | if (status < 0) | |
1012 | status = simulate_rdhwr(regs, opcode); | |
1013 | ||
1014 | if (status < 0) | |
1015 | status = SIGILL; | |
1016 | ||
1017 | if (unlikely(status > 0)) { | |
1018 | regs->cp0_epc = old_epc; /* Undo skip-over. */ | |
1019 | force_sig(status, current); | |
1020 | } | |
1021 | ||
1022 | return; | |
1da177e4 LT |
1023 | |
1024 | case 1: | |
53dc8028 AN |
1025 | if (used_math()) /* Using the FPU again. */ |
1026 | own_fpu(1); | |
1027 | else { /* First time FPU user. */ | |
1da177e4 LT |
1028 | init_fpu(); |
1029 | set_used_math(); | |
1030 | } | |
1031 | ||
5323180d | 1032 | if (!raw_cpu_has_fpu) { |
e04582b7 | 1033 | int sig; |
515b029d | 1034 | void __user *fault_addr = NULL; |
e04582b7 | 1035 | sig = fpu_emulator_cop1Handler(regs, |
515b029d DD |
1036 | ¤t->thread.fpu, |
1037 | 0, &fault_addr); | |
1038 | if (!process_fpemu_return(sig, fault_addr)) | |
d223a861 | 1039 | mt_ase_fp_affinity(); |
1da177e4 LT |
1040 | } |
1041 | ||
1da177e4 LT |
1042 | return; |
1043 | ||
1044 | case 2: | |
69f3a7de | 1045 | raw_notifier_call_chain(&cu2_chain, CU2_EXCEPTION, regs); |
55dc9d51 | 1046 | return; |
69f3a7de | 1047 | |
1da177e4 LT |
1048 | case 3: |
1049 | break; | |
1050 | } | |
1051 | ||
1052 | force_sig(SIGILL, current); | |
1053 | } | |
1054 | ||
1055 | asmlinkage void do_mdmx(struct pt_regs *regs) | |
1056 | { | |
1057 | force_sig(SIGILL, current); | |
1058 | } | |
1059 | ||
8bc6d05b DD |
1060 | /* |
1061 | * Called with interrupts disabled. | |
1062 | */ | |
1da177e4 LT |
1063 | asmlinkage void do_watch(struct pt_regs *regs) |
1064 | { | |
b67b2b70 DD |
1065 | u32 cause; |
1066 | ||
1da177e4 | 1067 | /* |
b67b2b70 DD |
1068 | * Clear WP (bit 22) bit of cause register so we don't loop |
1069 | * forever. | |
1da177e4 | 1070 | */ |
b67b2b70 DD |
1071 | cause = read_c0_cause(); |
1072 | cause &= ~(1 << 22); | |
1073 | write_c0_cause(cause); | |
1074 | ||
1075 | /* | |
1076 | * If the current thread has the watch registers loaded, save | |
1077 | * their values and send SIGTRAP. Otherwise another thread | |
1078 | * left the registers set, clear them and continue. | |
1079 | */ | |
1080 | if (test_tsk_thread_flag(current, TIF_LOAD_WATCH)) { | |
1081 | mips_read_watch_registers(); | |
8bc6d05b | 1082 | local_irq_enable(); |
b67b2b70 | 1083 | force_sig(SIGTRAP, current); |
8bc6d05b | 1084 | } else { |
b67b2b70 | 1085 | mips_clear_watch_registers(); |
8bc6d05b DD |
1086 | local_irq_enable(); |
1087 | } | |
1da177e4 LT |
1088 | } |
1089 | ||
1090 | asmlinkage void do_mcheck(struct pt_regs *regs) | |
1091 | { | |
cac4bcbc RB |
1092 | const int field = 2 * sizeof(unsigned long); |
1093 | int multi_match = regs->cp0_status & ST0_TS; | |
1094 | ||
1da177e4 | 1095 | show_regs(regs); |
cac4bcbc RB |
1096 | |
1097 | if (multi_match) { | |
1098 | printk("Index : %0x\n", read_c0_index()); | |
1099 | printk("Pagemask: %0x\n", read_c0_pagemask()); | |
1100 | printk("EntryHi : %0*lx\n", field, read_c0_entryhi()); | |
1101 | printk("EntryLo0: %0*lx\n", field, read_c0_entrylo0()); | |
1102 | printk("EntryLo1: %0*lx\n", field, read_c0_entrylo1()); | |
1103 | printk("\n"); | |
1104 | dump_tlb_all(); | |
1105 | } | |
1106 | ||
e1bb8289 | 1107 | show_code((unsigned int __user *) regs->cp0_epc); |
cac4bcbc | 1108 | |
1da177e4 LT |
1109 | /* |
1110 | * Some chips may have other causes of machine check (e.g. SB1 | |
1111 | * graduation timer) | |
1112 | */ | |
1113 | panic("Caught Machine Check exception - %scaused by multiple " | |
1114 | "matching entries in the TLB.", | |
cac4bcbc | 1115 | (multi_match) ? "" : "not "); |
1da177e4 LT |
1116 | } |
1117 | ||
340ee4b9 RB |
1118 | asmlinkage void do_mt(struct pt_regs *regs) |
1119 | { | |
41c594ab RB |
1120 | int subcode; |
1121 | ||
41c594ab RB |
1122 | subcode = (read_vpe_c0_vpecontrol() & VPECONTROL_EXCPT) |
1123 | >> VPECONTROL_EXCPT_SHIFT; | |
1124 | switch (subcode) { | |
1125 | case 0: | |
e35a5e35 | 1126 | printk(KERN_DEBUG "Thread Underflow\n"); |
41c594ab RB |
1127 | break; |
1128 | case 1: | |
e35a5e35 | 1129 | printk(KERN_DEBUG "Thread Overflow\n"); |
41c594ab RB |
1130 | break; |
1131 | case 2: | |
e35a5e35 | 1132 | printk(KERN_DEBUG "Invalid YIELD Qualifier\n"); |
41c594ab RB |
1133 | break; |
1134 | case 3: | |
e35a5e35 | 1135 | printk(KERN_DEBUG "Gating Storage Exception\n"); |
41c594ab RB |
1136 | break; |
1137 | case 4: | |
e35a5e35 | 1138 | printk(KERN_DEBUG "YIELD Scheduler Exception\n"); |
41c594ab RB |
1139 | break; |
1140 | case 5: | |
f232c7e8 | 1141 | printk(KERN_DEBUG "Gating Storage Scheduler Exception\n"); |
41c594ab RB |
1142 | break; |
1143 | default: | |
e35a5e35 | 1144 | printk(KERN_DEBUG "*** UNKNOWN THREAD EXCEPTION %d ***\n", |
41c594ab RB |
1145 | subcode); |
1146 | break; | |
1147 | } | |
340ee4b9 RB |
1148 | die_if_kernel("MIPS MT Thread exception in kernel", regs); |
1149 | ||
1150 | force_sig(SIGILL, current); | |
1151 | } | |
1152 | ||
1153 | ||
e50c0a8f RB |
1154 | asmlinkage void do_dsp(struct pt_regs *regs) |
1155 | { | |
1156 | if (cpu_has_dsp) | |
ab75dc02 | 1157 | panic("Unexpected DSP exception"); |
e50c0a8f RB |
1158 | |
1159 | force_sig(SIGILL, current); | |
1160 | } | |
1161 | ||
1da177e4 LT |
1162 | asmlinkage void do_reserved(struct pt_regs *regs) |
1163 | { | |
1164 | /* | |
1165 | * Game over - no way to handle this if it ever occurs. Most probably | |
1166 | * caused by a new unknown cpu type or after another deadly | |
1167 | * hard/software error. | |
1168 | */ | |
1169 | show_regs(regs); | |
1170 | panic("Caught reserved exception %ld - should not happen.", | |
1171 | (regs->cp0_cause & 0x7f) >> 2); | |
1172 | } | |
1173 | ||
39b8d525 RB |
1174 | static int __initdata l1parity = 1; |
1175 | static int __init nol1parity(char *s) | |
1176 | { | |
1177 | l1parity = 0; | |
1178 | return 1; | |
1179 | } | |
1180 | __setup("nol1par", nol1parity); | |
1181 | static int __initdata l2parity = 1; | |
1182 | static int __init nol2parity(char *s) | |
1183 | { | |
1184 | l2parity = 0; | |
1185 | return 1; | |
1186 | } | |
1187 | __setup("nol2par", nol2parity); | |
1188 | ||
1da177e4 LT |
1189 | /* |
1190 | * Some MIPS CPUs can enable/disable for cache parity detection, but do | |
1191 | * it different ways. | |
1192 | */ | |
1193 | static inline void parity_protection_init(void) | |
1194 | { | |
10cc3529 | 1195 | switch (current_cpu_type()) { |
1da177e4 | 1196 | case CPU_24K: |
98a41de9 | 1197 | case CPU_34K: |
39b8d525 RB |
1198 | case CPU_74K: |
1199 | case CPU_1004K: | |
1200 | { | |
1201 | #define ERRCTL_PE 0x80000000 | |
1202 | #define ERRCTL_L2P 0x00800000 | |
1203 | unsigned long errctl; | |
1204 | unsigned int l1parity_present, l2parity_present; | |
1205 | ||
1206 | errctl = read_c0_ecc(); | |
1207 | errctl &= ~(ERRCTL_PE|ERRCTL_L2P); | |
1208 | ||
1209 | /* probe L1 parity support */ | |
1210 | write_c0_ecc(errctl | ERRCTL_PE); | |
1211 | back_to_back_c0_hazard(); | |
1212 | l1parity_present = (read_c0_ecc() & ERRCTL_PE); | |
1213 | ||
1214 | /* probe L2 parity support */ | |
1215 | write_c0_ecc(errctl|ERRCTL_L2P); | |
1216 | back_to_back_c0_hazard(); | |
1217 | l2parity_present = (read_c0_ecc() & ERRCTL_L2P); | |
1218 | ||
1219 | if (l1parity_present && l2parity_present) { | |
1220 | if (l1parity) | |
1221 | errctl |= ERRCTL_PE; | |
1222 | if (l1parity ^ l2parity) | |
1223 | errctl |= ERRCTL_L2P; | |
1224 | } else if (l1parity_present) { | |
1225 | if (l1parity) | |
1226 | errctl |= ERRCTL_PE; | |
1227 | } else if (l2parity_present) { | |
1228 | if (l2parity) | |
1229 | errctl |= ERRCTL_L2P; | |
1230 | } else { | |
1231 | /* No parity available */ | |
1232 | } | |
1233 | ||
1234 | printk(KERN_INFO "Writing ErrCtl register=%08lx\n", errctl); | |
1235 | ||
1236 | write_c0_ecc(errctl); | |
1237 | back_to_back_c0_hazard(); | |
1238 | errctl = read_c0_ecc(); | |
1239 | printk(KERN_INFO "Readback ErrCtl register=%08lx\n", errctl); | |
1240 | ||
1241 | if (l1parity_present) | |
1242 | printk(KERN_INFO "Cache parity protection %sabled\n", | |
1243 | (errctl & ERRCTL_PE) ? "en" : "dis"); | |
1244 | ||
1245 | if (l2parity_present) { | |
1246 | if (l1parity_present && l1parity) | |
1247 | errctl ^= ERRCTL_L2P; | |
1248 | printk(KERN_INFO "L2 cache parity protection %sabled\n", | |
1249 | (errctl & ERRCTL_L2P) ? "en" : "dis"); | |
1250 | } | |
1251 | } | |
1252 | break; | |
1253 | ||
1da177e4 | 1254 | case CPU_5KC: |
78d4803f | 1255 | case CPU_5KE: |
2fa36399 | 1256 | case CPU_LOONGSON1: |
14f18b7f RB |
1257 | write_c0_ecc(0x80000000); |
1258 | back_to_back_c0_hazard(); | |
1259 | /* Set the PE bit (bit 31) in the c0_errctl register. */ | |
1260 | printk(KERN_INFO "Cache parity protection %sabled\n", | |
1261 | (read_c0_ecc() & 0x80000000) ? "en" : "dis"); | |
1da177e4 LT |
1262 | break; |
1263 | case CPU_20KC: | |
1264 | case CPU_25KF: | |
1265 | /* Clear the DE bit (bit 16) in the c0_status register. */ | |
1266 | printk(KERN_INFO "Enable cache parity protection for " | |
1267 | "MIPS 20KC/25KF CPUs.\n"); | |
1268 | clear_c0_status(ST0_DE); | |
1269 | break; | |
1270 | default: | |
1271 | break; | |
1272 | } | |
1273 | } | |
1274 | ||
1275 | asmlinkage void cache_parity_error(void) | |
1276 | { | |
1277 | const int field = 2 * sizeof(unsigned long); | |
1278 | unsigned int reg_val; | |
1279 | ||
1280 | /* For the moment, report the problem and hang. */ | |
1281 | printk("Cache error exception:\n"); | |
1282 | printk("cp0_errorepc == %0*lx\n", field, read_c0_errorepc()); | |
1283 | reg_val = read_c0_cacheerr(); | |
1284 | printk("c0_cacheerr == %08x\n", reg_val); | |
1285 | ||
1286 | printk("Decoded c0_cacheerr: %s cache fault in %s reference.\n", | |
1287 | reg_val & (1<<30) ? "secondary" : "primary", | |
1288 | reg_val & (1<<31) ? "data" : "insn"); | |
1289 | printk("Error bits: %s%s%s%s%s%s%s\n", | |
1290 | reg_val & (1<<29) ? "ED " : "", | |
1291 | reg_val & (1<<28) ? "ET " : "", | |
1292 | reg_val & (1<<26) ? "EE " : "", | |
1293 | reg_val & (1<<25) ? "EB " : "", | |
1294 | reg_val & (1<<24) ? "EI " : "", | |
1295 | reg_val & (1<<23) ? "E1 " : "", | |
1296 | reg_val & (1<<22) ? "E0 " : ""); | |
1297 | printk("IDX: 0x%08x\n", reg_val & ((1<<22)-1)); | |
1298 | ||
ec917c2c | 1299 | #if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64) |
1da177e4 LT |
1300 | if (reg_val & (1<<22)) |
1301 | printk("DErrAddr0: 0x%0*lx\n", field, read_c0_derraddr0()); | |
1302 | ||
1303 | if (reg_val & (1<<23)) | |
1304 | printk("DErrAddr1: 0x%0*lx\n", field, read_c0_derraddr1()); | |
1305 | #endif | |
1306 | ||
1307 | panic("Can't handle the cache error!"); | |
1308 | } | |
1309 | ||
1310 | /* | |
1311 | * SDBBP EJTAG debug exception handler. | |
1312 | * We skip the instruction and return to the next instruction. | |
1313 | */ | |
1314 | void ejtag_exception_handler(struct pt_regs *regs) | |
1315 | { | |
1316 | const int field = 2 * sizeof(unsigned long); | |
1317 | unsigned long depc, old_epc; | |
1318 | unsigned int debug; | |
1319 | ||
70ae6126 | 1320 | printk(KERN_DEBUG "SDBBP EJTAG debug exception - not handled yet, just ignored!\n"); |
1da177e4 LT |
1321 | depc = read_c0_depc(); |
1322 | debug = read_c0_debug(); | |
70ae6126 | 1323 | printk(KERN_DEBUG "c0_depc = %0*lx, DEBUG = %08x\n", field, depc, debug); |
1da177e4 LT |
1324 | if (debug & 0x80000000) { |
1325 | /* | |
1326 | * In branch delay slot. | |
1327 | * We cheat a little bit here and use EPC to calculate the | |
1328 | * debug return address (DEPC). EPC is restored after the | |
1329 | * calculation. | |
1330 | */ | |
1331 | old_epc = regs->cp0_epc; | |
1332 | regs->cp0_epc = depc; | |
1333 | __compute_return_epc(regs); | |
1334 | depc = regs->cp0_epc; | |
1335 | regs->cp0_epc = old_epc; | |
1336 | } else | |
1337 | depc += 4; | |
1338 | write_c0_depc(depc); | |
1339 | ||
1340 | #if 0 | |
70ae6126 | 1341 | printk(KERN_DEBUG "\n\n----- Enable EJTAG single stepping ----\n\n"); |
1da177e4 LT |
1342 | write_c0_debug(debug | 0x100); |
1343 | #endif | |
1344 | } | |
1345 | ||
1346 | /* | |
1347 | * NMI exception handler. | |
34bd92e2 | 1348 | * No lock; only written during early bootup by CPU 0. |
1da177e4 | 1349 | */ |
34bd92e2 KC |
1350 | static RAW_NOTIFIER_HEAD(nmi_chain); |
1351 | ||
1352 | int register_nmi_notifier(struct notifier_block *nb) | |
1353 | { | |
1354 | return raw_notifier_chain_register(&nmi_chain, nb); | |
1355 | } | |
1356 | ||
ff2d8b19 | 1357 | void __noreturn nmi_exception_handler(struct pt_regs *regs) |
1da177e4 | 1358 | { |
34bd92e2 | 1359 | raw_notifier_call_chain(&nmi_chain, 0, regs); |
41c594ab | 1360 | bust_spinlocks(1); |
1da177e4 LT |
1361 | printk("NMI taken!!!!\n"); |
1362 | die("NMI", regs); | |
1da177e4 LT |
1363 | } |
1364 | ||
e01402b1 RB |
1365 | #define VECTORSPACING 0x100 /* for EI/VI mode */ |
1366 | ||
1367 | unsigned long ebase; | |
1da177e4 | 1368 | unsigned long exception_handlers[32]; |
e01402b1 | 1369 | unsigned long vi_handlers[64]; |
1da177e4 | 1370 | |
2d1b6e95 | 1371 | void __init *set_except_vector(int n, void *addr) |
1da177e4 LT |
1372 | { |
1373 | unsigned long handler = (unsigned long) addr; | |
1374 | unsigned long old_handler = exception_handlers[n]; | |
1375 | ||
1376 | exception_handlers[n] = handler; | |
1377 | if (n == 0 && cpu_has_divec) { | |
92bbe1b9 FF |
1378 | unsigned long jump_mask = ~((1 << 28) - 1); |
1379 | u32 *buf = (u32 *)(ebase + 0x200); | |
1380 | unsigned int k0 = 26; | |
1381 | if ((handler & jump_mask) == ((ebase + 0x200) & jump_mask)) { | |
1382 | uasm_i_j(&buf, handler & ~jump_mask); | |
1383 | uasm_i_nop(&buf); | |
1384 | } else { | |
1385 | UASM_i_LA(&buf, k0, handler); | |
1386 | uasm_i_jr(&buf, k0); | |
1387 | uasm_i_nop(&buf); | |
1388 | } | |
1389 | local_flush_icache_range(ebase + 0x200, (unsigned long)buf); | |
e01402b1 RB |
1390 | } |
1391 | return (void *)old_handler; | |
1392 | } | |
1393 | ||
6ba07e59 AN |
1394 | static asmlinkage void do_default_vi(void) |
1395 | { | |
1396 | show_regs(get_irq_regs()); | |
1397 | panic("Caught unexpected vectored interrupt."); | |
1398 | } | |
1399 | ||
ef300e42 | 1400 | static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs) |
e01402b1 RB |
1401 | { |
1402 | unsigned long handler; | |
1403 | unsigned long old_handler = vi_handlers[n]; | |
f6771dbb | 1404 | int srssets = current_cpu_data.srsets; |
e01402b1 RB |
1405 | u32 *w; |
1406 | unsigned char *b; | |
1407 | ||
b72b7092 | 1408 | BUG_ON(!cpu_has_veic && !cpu_has_vint); |
e01402b1 RB |
1409 | |
1410 | if (addr == NULL) { | |
1411 | handler = (unsigned long) do_default_vi; | |
1412 | srs = 0; | |
41c594ab | 1413 | } else |
e01402b1 RB |
1414 | handler = (unsigned long) addr; |
1415 | vi_handlers[n] = (unsigned long) addr; | |
1416 | ||
1417 | b = (unsigned char *)(ebase + 0x200 + n*VECTORSPACING); | |
1418 | ||
f6771dbb | 1419 | if (srs >= srssets) |
e01402b1 RB |
1420 | panic("Shadow register set %d not supported", srs); |
1421 | ||
1422 | if (cpu_has_veic) { | |
1423 | if (board_bind_eic_interrupt) | |
49a89efb | 1424 | board_bind_eic_interrupt(n, srs); |
41c594ab | 1425 | } else if (cpu_has_vint) { |
e01402b1 | 1426 | /* SRSMap is only defined if shadow sets are implemented */ |
f6771dbb | 1427 | if (srssets > 1) |
49a89efb | 1428 | change_c0_srsmap(0xf << n*4, srs << n*4); |
e01402b1 RB |
1429 | } |
1430 | ||
1431 | if (srs == 0) { | |
1432 | /* | |
1433 | * If no shadow set is selected then use the default handler | |
1434 | * that does normal register saving and a standard interrupt exit | |
1435 | */ | |
1436 | ||
1437 | extern char except_vec_vi, except_vec_vi_lui; | |
1438 | extern char except_vec_vi_ori, except_vec_vi_end; | |
c65a5480 AN |
1439 | extern char rollback_except_vec_vi; |
1440 | char *vec_start = (cpu_wait == r4k_wait) ? | |
1441 | &rollback_except_vec_vi : &except_vec_vi; | |
41c594ab RB |
1442 | #ifdef CONFIG_MIPS_MT_SMTC |
1443 | /* | |
1444 | * We need to provide the SMTC vectored interrupt handler | |
1445 | * not only with the address of the handler, but with the | |
1446 | * Status.IM bit to be masked before going there. | |
1447 | */ | |
1448 | extern char except_vec_vi_mori; | |
c65a5480 | 1449 | const int mori_offset = &except_vec_vi_mori - vec_start; |
41c594ab | 1450 | #endif /* CONFIG_MIPS_MT_SMTC */ |
c65a5480 AN |
1451 | const int handler_len = &except_vec_vi_end - vec_start; |
1452 | const int lui_offset = &except_vec_vi_lui - vec_start; | |
1453 | const int ori_offset = &except_vec_vi_ori - vec_start; | |
e01402b1 RB |
1454 | |
1455 | if (handler_len > VECTORSPACING) { | |
1456 | /* | |
1457 | * Sigh... panicing won't help as the console | |
1458 | * is probably not configured :( | |
1459 | */ | |
49a89efb | 1460 | panic("VECTORSPACING too small"); |
e01402b1 RB |
1461 | } |
1462 | ||
c65a5480 | 1463 | memcpy(b, vec_start, handler_len); |
41c594ab | 1464 | #ifdef CONFIG_MIPS_MT_SMTC |
8e8a52ed RB |
1465 | BUG_ON(n > 7); /* Vector index %d exceeds SMTC maximum. */ |
1466 | ||
41c594ab RB |
1467 | w = (u32 *)(b + mori_offset); |
1468 | *w = (*w & 0xffff0000) | (0x100 << n); | |
1469 | #endif /* CONFIG_MIPS_MT_SMTC */ | |
e01402b1 RB |
1470 | w = (u32 *)(b + lui_offset); |
1471 | *w = (*w & 0xffff0000) | (((u32)handler >> 16) & 0xffff); | |
1472 | w = (u32 *)(b + ori_offset); | |
1473 | *w = (*w & 0xffff0000) | ((u32)handler & 0xffff); | |
e0cee3ee TB |
1474 | local_flush_icache_range((unsigned long)b, |
1475 | (unsigned long)(b+handler_len)); | |
e01402b1 RB |
1476 | } |
1477 | else { | |
1478 | /* | |
1479 | * In other cases jump directly to the interrupt handler | |
1480 | * | |
1481 | * It is the handlers responsibility to save registers if required | |
1482 | * (eg hi/lo) and return from the exception using "eret" | |
1483 | */ | |
1484 | w = (u32 *)b; | |
1485 | *w++ = 0x08000000 | (((u32)handler >> 2) & 0x03fffff); /* j handler */ | |
1486 | *w = 0; | |
e0cee3ee TB |
1487 | local_flush_icache_range((unsigned long)b, |
1488 | (unsigned long)(b+8)); | |
1da177e4 | 1489 | } |
e01402b1 | 1490 | |
1da177e4 LT |
1491 | return (void *)old_handler; |
1492 | } | |
1493 | ||
ef300e42 | 1494 | void *set_vi_handler(int n, vi_handler_t addr) |
e01402b1 | 1495 | { |
ff3eab2a | 1496 | return set_vi_srs_handler(n, addr, 0); |
e01402b1 | 1497 | } |
f41ae0b2 | 1498 | |
1da177e4 | 1499 | extern void tlb_init(void); |
1d40cfcd | 1500 | extern void flush_tlb_handlers(void); |
1da177e4 | 1501 | |
42f77542 RB |
1502 | /* |
1503 | * Timer interrupt | |
1504 | */ | |
1505 | int cp0_compare_irq; | |
68b6352c | 1506 | EXPORT_SYMBOL_GPL(cp0_compare_irq); |
010c108d | 1507 | int cp0_compare_irq_shift; |
42f77542 RB |
1508 | |
1509 | /* | |
1510 | * Performance counter IRQ or -1 if shared with timer | |
1511 | */ | |
1512 | int cp0_perfcount_irq; | |
1513 | EXPORT_SYMBOL_GPL(cp0_perfcount_irq); | |
1514 | ||
bdc94eb4 CD |
1515 | static int __cpuinitdata noulri; |
1516 | ||
1517 | static int __init ulri_disable(char *s) | |
1518 | { | |
1519 | pr_info("Disabling ulri\n"); | |
1520 | noulri = 1; | |
1521 | ||
1522 | return 1; | |
1523 | } | |
1524 | __setup("noulri", ulri_disable); | |
1525 | ||
6650df3c | 1526 | void __cpuinit per_cpu_trap_init(bool is_boot_cpu) |
1da177e4 LT |
1527 | { |
1528 | unsigned int cpu = smp_processor_id(); | |
1529 | unsigned int status_set = ST0_CU0; | |
18d693b3 | 1530 | unsigned int hwrena = cpu_hwrena_impl_bits; |
41c594ab RB |
1531 | #ifdef CONFIG_MIPS_MT_SMTC |
1532 | int secondaryTC = 0; | |
1533 | int bootTC = (cpu == 0); | |
1534 | ||
1535 | /* | |
1536 | * Only do per_cpu_trap_init() for first TC of Each VPE. | |
1537 | * Note that this hack assumes that the SMTC init code | |
1538 | * assigns TCs consecutively and in ascending order. | |
1539 | */ | |
1540 | ||
1541 | if (((read_c0_tcbind() & TCBIND_CURTC) != 0) && | |
1542 | ((read_c0_tcbind() & TCBIND_CURVPE) == cpu_data[cpu - 1].vpe_id)) | |
1543 | secondaryTC = 1; | |
1544 | #endif /* CONFIG_MIPS_MT_SMTC */ | |
1da177e4 LT |
1545 | |
1546 | /* | |
1547 | * Disable coprocessors and select 32-bit or 64-bit addressing | |
1548 | * and the 16/32 or 32/32 FPR register model. Reset the BEV | |
1549 | * flag that some firmware may have left set and the TS bit (for | |
1550 | * IP27). Set XX for ISA IV code to work. | |
1551 | */ | |
875d43e7 | 1552 | #ifdef CONFIG_64BIT |
1da177e4 LT |
1553 | status_set |= ST0_FR|ST0_KX|ST0_SX|ST0_UX; |
1554 | #endif | |
1555 | if (current_cpu_data.isa_level == MIPS_CPU_ISA_IV) | |
1556 | status_set |= ST0_XX; | |
bbaf238b CD |
1557 | if (cpu_has_dsp) |
1558 | status_set |= ST0_MX; | |
1559 | ||
b38c7399 | 1560 | change_c0_status(ST0_CU|ST0_MX|ST0_RE|ST0_FR|ST0_BEV|ST0_TS|ST0_KX|ST0_SX|ST0_UX, |
1da177e4 LT |
1561 | status_set); |
1562 | ||
18d693b3 KC |
1563 | if (cpu_has_mips_r2) |
1564 | hwrena |= 0x0000000f; | |
a3692020 | 1565 | |
18d693b3 KC |
1566 | if (!noulri && cpu_has_userlocal) |
1567 | hwrena |= (1 << 29); | |
a3692020 | 1568 | |
18d693b3 KC |
1569 | if (hwrena) |
1570 | write_c0_hwrena(hwrena); | |
e01402b1 | 1571 | |
41c594ab RB |
1572 | #ifdef CONFIG_MIPS_MT_SMTC |
1573 | if (!secondaryTC) { | |
1574 | #endif /* CONFIG_MIPS_MT_SMTC */ | |
1575 | ||
e01402b1 | 1576 | if (cpu_has_veic || cpu_has_vint) { |
9fb4c2b9 | 1577 | unsigned long sr = set_c0_status(ST0_BEV); |
49a89efb | 1578 | write_c0_ebase(ebase); |
9fb4c2b9 | 1579 | write_c0_status(sr); |
e01402b1 | 1580 | /* Setting vector spacing enables EI/VI mode */ |
49a89efb | 1581 | change_c0_intctl(0x3e0, VECTORSPACING); |
e01402b1 | 1582 | } |
d03d0a57 RB |
1583 | if (cpu_has_divec) { |
1584 | if (cpu_has_mipsmt) { | |
1585 | unsigned int vpflags = dvpe(); | |
1586 | set_c0_cause(CAUSEF_IV); | |
1587 | evpe(vpflags); | |
1588 | } else | |
1589 | set_c0_cause(CAUSEF_IV); | |
1590 | } | |
3b1d4ed5 RB |
1591 | |
1592 | /* | |
1593 | * Before R2 both interrupt numbers were fixed to 7, so on R2 only: | |
1594 | * | |
1595 | * o read IntCtl.IPTI to determine the timer interrupt | |
1596 | * o read IntCtl.IPPCI to determine the performance counter interrupt | |
1597 | */ | |
1598 | if (cpu_has_mips_r2) { | |
010c108d DV |
1599 | cp0_compare_irq_shift = CAUSEB_TI - CAUSEB_IP; |
1600 | cp0_compare_irq = (read_c0_intctl() >> INTCTLB_IPTI) & 7; | |
1601 | cp0_perfcount_irq = (read_c0_intctl() >> INTCTLB_IPPCI) & 7; | |
c3e838a2 | 1602 | if (cp0_perfcount_irq == cp0_compare_irq) |
3b1d4ed5 | 1603 | cp0_perfcount_irq = -1; |
c3e838a2 CD |
1604 | } else { |
1605 | cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ; | |
c6a4ebb9 | 1606 | cp0_compare_irq_shift = CP0_LEGACY_PERFCNT_IRQ; |
c3e838a2 | 1607 | cp0_perfcount_irq = -1; |
3b1d4ed5 RB |
1608 | } |
1609 | ||
41c594ab RB |
1610 | #ifdef CONFIG_MIPS_MT_SMTC |
1611 | } | |
1612 | #endif /* CONFIG_MIPS_MT_SMTC */ | |
1da177e4 | 1613 | |
5c200197 MR |
1614 | if (!cpu_data[cpu].asid_cache) |
1615 | cpu_data[cpu].asid_cache = ASID_FIRST_VERSION; | |
1da177e4 LT |
1616 | |
1617 | atomic_inc(&init_mm.mm_count); | |
1618 | current->active_mm = &init_mm; | |
1619 | BUG_ON(current->mm); | |
1620 | enter_lazy_tlb(&init_mm, current); | |
1621 | ||
41c594ab RB |
1622 | #ifdef CONFIG_MIPS_MT_SMTC |
1623 | if (bootTC) { | |
1624 | #endif /* CONFIG_MIPS_MT_SMTC */ | |
6650df3c DD |
1625 | /* Boot CPU's cache setup in setup_arch(). */ |
1626 | if (!is_boot_cpu) | |
1627 | cpu_cache_init(); | |
41c594ab RB |
1628 | tlb_init(); |
1629 | #ifdef CONFIG_MIPS_MT_SMTC | |
6a05888d RB |
1630 | } else if (!secondaryTC) { |
1631 | /* | |
1632 | * First TC in non-boot VPE must do subset of tlb_init() | |
1633 | * for MMU countrol registers. | |
1634 | */ | |
1635 | write_c0_pagemask(PM_DEFAULT_MASK); | |
1636 | write_c0_wired(0); | |
41c594ab RB |
1637 | } |
1638 | #endif /* CONFIG_MIPS_MT_SMTC */ | |
3d8bfdd0 | 1639 | TLBMISS_HANDLER_SETUP(); |
1da177e4 LT |
1640 | } |
1641 | ||
e01402b1 | 1642 | /* Install CPU exception handler */ |
e3dc81f2 | 1643 | void __cpuinit set_handler(unsigned long offset, void *addr, unsigned long size) |
e01402b1 RB |
1644 | { |
1645 | memcpy((void *)(ebase + offset), addr, size); | |
e0cee3ee | 1646 | local_flush_icache_range(ebase + offset, ebase + offset + size); |
e01402b1 RB |
1647 | } |
1648 | ||
234fcd14 | 1649 | static char panic_null_cerr[] __cpuinitdata = |
641e97f3 RB |
1650 | "Trying to set NULL cache error exception handler"; |
1651 | ||
42fe7ee3 RB |
1652 | /* |
1653 | * Install uncached CPU exception handler. | |
1654 | * This is suitable only for the cache error exception which is the only | |
1655 | * exception handler that is being run uncached. | |
1656 | */ | |
234fcd14 RB |
1657 | void __cpuinit set_uncached_handler(unsigned long offset, void *addr, |
1658 | unsigned long size) | |
e01402b1 | 1659 | { |
4f81b01a | 1660 | unsigned long uncached_ebase = CKSEG1ADDR(ebase); |
e01402b1 | 1661 | |
641e97f3 RB |
1662 | if (!addr) |
1663 | panic(panic_null_cerr); | |
1664 | ||
e01402b1 RB |
1665 | memcpy((void *)(uncached_ebase + offset), addr, size); |
1666 | } | |
1667 | ||
5b10496b AN |
1668 | static int __initdata rdhwr_noopt; |
1669 | static int __init set_rdhwr_noopt(char *str) | |
1670 | { | |
1671 | rdhwr_noopt = 1; | |
1672 | return 1; | |
1673 | } | |
1674 | ||
1675 | __setup("rdhwr_noopt", set_rdhwr_noopt); | |
1676 | ||
1da177e4 LT |
1677 | void __init trap_init(void) |
1678 | { | |
1679 | extern char except_vec3_generic, except_vec3_r4000; | |
1da177e4 LT |
1680 | extern char except_vec4; |
1681 | unsigned long i; | |
c65a5480 AN |
1682 | int rollback; |
1683 | ||
1684 | check_wait(); | |
1685 | rollback = (cpu_wait == r4k_wait); | |
1da177e4 | 1686 | |
88547001 JW |
1687 | #if defined(CONFIG_KGDB) |
1688 | if (kgdb_early_setup) | |
1689 | return; /* Already done */ | |
1690 | #endif | |
1691 | ||
9fb4c2b9 CD |
1692 | if (cpu_has_veic || cpu_has_vint) { |
1693 | unsigned long size = 0x200 + VECTORSPACING*64; | |
1694 | ebase = (unsigned long) | |
1695 | __alloc_bootmem(size, 1 << fls(size), 0); | |
1696 | } else { | |
f6be75d0 | 1697 | ebase = CKSEG0; |
566f74f6 DD |
1698 | if (cpu_has_mips_r2) |
1699 | ebase += (read_c0_ebase() & 0x3ffff000); | |
1700 | } | |
e01402b1 | 1701 | |
6fb97eff KC |
1702 | if (board_ebase_setup) |
1703 | board_ebase_setup(); | |
6650df3c | 1704 | per_cpu_trap_init(true); |
1da177e4 LT |
1705 | |
1706 | /* | |
1707 | * Copy the generic exception handlers to their final destination. | |
1708 | * This will be overriden later as suitable for a particular | |
1709 | * configuration. | |
1710 | */ | |
e01402b1 | 1711 | set_handler(0x180, &except_vec3_generic, 0x80); |
1da177e4 LT |
1712 | |
1713 | /* | |
1714 | * Setup default vectors | |
1715 | */ | |
1716 | for (i = 0; i <= 31; i++) | |
1717 | set_except_vector(i, handle_reserved); | |
1718 | ||
1719 | /* | |
1720 | * Copy the EJTAG debug exception vector handler code to it's final | |
1721 | * destination. | |
1722 | */ | |
e01402b1 | 1723 | if (cpu_has_ejtag && board_ejtag_handler_setup) |
49a89efb | 1724 | board_ejtag_handler_setup(); |
1da177e4 LT |
1725 | |
1726 | /* | |
1727 | * Only some CPUs have the watch exceptions. | |
1728 | */ | |
1729 | if (cpu_has_watch) | |
1730 | set_except_vector(23, handle_watch); | |
1731 | ||
1732 | /* | |
e01402b1 | 1733 | * Initialise interrupt handlers |
1da177e4 | 1734 | */ |
e01402b1 RB |
1735 | if (cpu_has_veic || cpu_has_vint) { |
1736 | int nvec = cpu_has_veic ? 64 : 8; | |
1737 | for (i = 0; i < nvec; i++) | |
ff3eab2a | 1738 | set_vi_handler(i, NULL); |
e01402b1 RB |
1739 | } |
1740 | else if (cpu_has_divec) | |
1741 | set_handler(0x200, &except_vec4, 0x8); | |
1da177e4 LT |
1742 | |
1743 | /* | |
1744 | * Some CPUs can enable/disable for cache parity detection, but does | |
1745 | * it different ways. | |
1746 | */ | |
1747 | parity_protection_init(); | |
1748 | ||
1749 | /* | |
1750 | * The Data Bus Errors / Instruction Bus Errors are signaled | |
1751 | * by external hardware. Therefore these two exceptions | |
1752 | * may have board specific handlers. | |
1753 | */ | |
1754 | if (board_be_init) | |
1755 | board_be_init(); | |
1756 | ||
c65a5480 | 1757 | set_except_vector(0, rollback ? rollback_handle_int : handle_int); |
1da177e4 LT |
1758 | set_except_vector(1, handle_tlbm); |
1759 | set_except_vector(2, handle_tlbl); | |
1760 | set_except_vector(3, handle_tlbs); | |
1761 | ||
1762 | set_except_vector(4, handle_adel); | |
1763 | set_except_vector(5, handle_ades); | |
1764 | ||
1765 | set_except_vector(6, handle_ibe); | |
1766 | set_except_vector(7, handle_dbe); | |
1767 | ||
1768 | set_except_vector(8, handle_sys); | |
1769 | set_except_vector(9, handle_bp); | |
5b10496b AN |
1770 | set_except_vector(10, rdhwr_noopt ? handle_ri : |
1771 | (cpu_has_vtag_icache ? | |
1772 | handle_ri_rdhwr_vivt : handle_ri_rdhwr)); | |
1da177e4 LT |
1773 | set_except_vector(11, handle_cpu); |
1774 | set_except_vector(12, handle_ov); | |
1775 | set_except_vector(13, handle_tr); | |
1da177e4 | 1776 | |
10cc3529 RB |
1777 | if (current_cpu_type() == CPU_R6000 || |
1778 | current_cpu_type() == CPU_R6000A) { | |
1da177e4 LT |
1779 | /* |
1780 | * The R6000 is the only R-series CPU that features a machine | |
1781 | * check exception (similar to the R4000 cache error) and | |
1782 | * unaligned ldc1/sdc1 exception. The handlers have not been | |
1783 | * written yet. Well, anyway there is no R6000 machine on the | |
1784 | * current list of targets for Linux/MIPS. | |
1785 | * (Duh, crap, there is someone with a triple R6k machine) | |
1786 | */ | |
1787 | //set_except_vector(14, handle_mc); | |
1788 | //set_except_vector(15, handle_ndc); | |
1789 | } | |
1790 | ||
e01402b1 RB |
1791 | |
1792 | if (board_nmi_handler_setup) | |
1793 | board_nmi_handler_setup(); | |
1794 | ||
e50c0a8f RB |
1795 | if (cpu_has_fpu && !cpu_has_nofpuex) |
1796 | set_except_vector(15, handle_fpe); | |
1797 | ||
1798 | set_except_vector(22, handle_mdmx); | |
1799 | ||
1800 | if (cpu_has_mcheck) | |
1801 | set_except_vector(24, handle_mcheck); | |
1802 | ||
340ee4b9 RB |
1803 | if (cpu_has_mipsmt) |
1804 | set_except_vector(25, handle_mt); | |
1805 | ||
acaec427 | 1806 | set_except_vector(26, handle_dsp); |
e50c0a8f | 1807 | |
fcbf1dfd DD |
1808 | if (board_cache_error_setup) |
1809 | board_cache_error_setup(); | |
1810 | ||
e50c0a8f RB |
1811 | if (cpu_has_vce) |
1812 | /* Special exception: R4[04]00 uses also the divec space. */ | |
566f74f6 | 1813 | memcpy((void *)(ebase + 0x180), &except_vec3_r4000, 0x100); |
e50c0a8f | 1814 | else if (cpu_has_4kex) |
566f74f6 | 1815 | memcpy((void *)(ebase + 0x180), &except_vec3_generic, 0x80); |
e50c0a8f | 1816 | else |
566f74f6 | 1817 | memcpy((void *)(ebase + 0x080), &except_vec3_generic, 0x80); |
e50c0a8f | 1818 | |
e0cee3ee | 1819 | local_flush_icache_range(ebase, ebase + 0x400); |
1d40cfcd | 1820 | flush_tlb_handlers(); |
0510617b TB |
1821 | |
1822 | sort_extable(__start___dbe_table, __stop___dbe_table); | |
69f3a7de | 1823 | |
4483b159 | 1824 | cu2_notifier(default_cu2_call, 0x80000000); /* Run last */ |
1da177e4 | 1825 | } |