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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public | |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
36ccf1c0 | 6 | * Copyright (C) 1994 - 1999, 2000, 01, 06 Ralf Baechle |
1da177e4 LT |
7 | * Copyright (C) 1995, 1996 Paul M. Antoine |
8 | * Copyright (C) 1998 Ulf Carlsson | |
9 | * Copyright (C) 1999 Silicon Graphics, Inc. | |
10 | * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com | |
11 | * Copyright (C) 2000, 01 MIPS Technologies, Inc. | |
60b0d655 | 12 | * Copyright (C) 2002, 2003, 2004, 2005, 2007 Maciej W. Rozycki |
1da177e4 | 13 | */ |
8e8a52ed | 14 | #include <linux/bug.h> |
60b0d655 | 15 | #include <linux/compiler.h> |
1da177e4 LT |
16 | #include <linux/init.h> |
17 | #include <linux/mm.h> | |
18 | #include <linux/module.h> | |
19 | #include <linux/sched.h> | |
20 | #include <linux/smp.h> | |
1da177e4 LT |
21 | #include <linux/spinlock.h> |
22 | #include <linux/kallsyms.h> | |
e01402b1 | 23 | #include <linux/bootmem.h> |
d4fd1989 | 24 | #include <linux/interrupt.h> |
39b8d525 | 25 | #include <linux/ptrace.h> |
88547001 JW |
26 | #include <linux/kgdb.h> |
27 | #include <linux/kdebug.h> | |
1da177e4 LT |
28 | |
29 | #include <asm/bootinfo.h> | |
30 | #include <asm/branch.h> | |
31 | #include <asm/break.h> | |
32 | #include <asm/cpu.h> | |
e50c0a8f | 33 | #include <asm/dsp.h> |
1da177e4 | 34 | #include <asm/fpu.h> |
340ee4b9 RB |
35 | #include <asm/mipsregs.h> |
36 | #include <asm/mipsmtregs.h> | |
1da177e4 LT |
37 | #include <asm/module.h> |
38 | #include <asm/pgtable.h> | |
39 | #include <asm/ptrace.h> | |
40 | #include <asm/sections.h> | |
41 | #include <asm/system.h> | |
42 | #include <asm/tlbdebug.h> | |
43 | #include <asm/traps.h> | |
44 | #include <asm/uaccess.h> | |
45 | #include <asm/mmu_context.h> | |
1da177e4 | 46 | #include <asm/types.h> |
1df0f0ff | 47 | #include <asm/stacktrace.h> |
1da177e4 | 48 | |
c65a5480 AN |
49 | extern void check_wait(void); |
50 | extern asmlinkage void r4k_wait(void); | |
51 | extern asmlinkage void rollback_handle_int(void); | |
e4ac58af | 52 | extern asmlinkage void handle_int(void); |
1da177e4 LT |
53 | extern asmlinkage void handle_tlbm(void); |
54 | extern asmlinkage void handle_tlbl(void); | |
55 | extern asmlinkage void handle_tlbs(void); | |
56 | extern asmlinkage void handle_adel(void); | |
57 | extern asmlinkage void handle_ades(void); | |
58 | extern asmlinkage void handle_ibe(void); | |
59 | extern asmlinkage void handle_dbe(void); | |
60 | extern asmlinkage void handle_sys(void); | |
61 | extern asmlinkage void handle_bp(void); | |
62 | extern asmlinkage void handle_ri(void); | |
5b10496b AN |
63 | extern asmlinkage void handle_ri_rdhwr_vivt(void); |
64 | extern asmlinkage void handle_ri_rdhwr(void); | |
1da177e4 LT |
65 | extern asmlinkage void handle_cpu(void); |
66 | extern asmlinkage void handle_ov(void); | |
67 | extern asmlinkage void handle_tr(void); | |
68 | extern asmlinkage void handle_fpe(void); | |
69 | extern asmlinkage void handle_mdmx(void); | |
70 | extern asmlinkage void handle_watch(void); | |
340ee4b9 | 71 | extern asmlinkage void handle_mt(void); |
e50c0a8f | 72 | extern asmlinkage void handle_dsp(void); |
1da177e4 LT |
73 | extern asmlinkage void handle_mcheck(void); |
74 | extern asmlinkage void handle_reserved(void); | |
75 | ||
12616ed2 | 76 | extern int fpu_emulator_cop1Handler(struct pt_regs *xcp, |
e04582b7 | 77 | struct mips_fpu_struct *ctx, int has_fpu); |
1da177e4 LT |
78 | |
79 | void (*board_be_init)(void); | |
80 | int (*board_be_handler)(struct pt_regs *regs, int is_fixup); | |
e01402b1 RB |
81 | void (*board_nmi_handler_setup)(void); |
82 | void (*board_ejtag_handler_setup)(void); | |
83 | void (*board_bind_eic_interrupt)(int irq, int regset); | |
1da177e4 | 84 | |
1da177e4 | 85 | |
4d157d5e | 86 | static void show_raw_backtrace(unsigned long reg29) |
e889d78f | 87 | { |
39b8d525 | 88 | unsigned long *sp = (unsigned long *)(reg29 & ~3); |
e889d78f AN |
89 | unsigned long addr; |
90 | ||
91 | printk("Call Trace:"); | |
92 | #ifdef CONFIG_KALLSYMS | |
93 | printk("\n"); | |
94 | #endif | |
10220c88 TB |
95 | while (!kstack_end(sp)) { |
96 | unsigned long __user *p = | |
97 | (unsigned long __user *)(unsigned long)sp++; | |
98 | if (__get_user(addr, p)) { | |
99 | printk(" (Bad stack address)"); | |
100 | break; | |
39b8d525 | 101 | } |
10220c88 TB |
102 | if (__kernel_text_address(addr)) |
103 | print_ip_sym(addr); | |
e889d78f | 104 | } |
10220c88 | 105 | printk("\n"); |
e889d78f AN |
106 | } |
107 | ||
f66686f7 | 108 | #ifdef CONFIG_KALLSYMS |
1df0f0ff | 109 | int raw_show_trace; |
f66686f7 AN |
110 | static int __init set_raw_show_trace(char *str) |
111 | { | |
112 | raw_show_trace = 1; | |
113 | return 1; | |
114 | } | |
115 | __setup("raw_show_trace", set_raw_show_trace); | |
1df0f0ff | 116 | #endif |
4d157d5e | 117 | |
eae23f2c | 118 | static void show_backtrace(struct task_struct *task, const struct pt_regs *regs) |
f66686f7 | 119 | { |
4d157d5e FBH |
120 | unsigned long sp = regs->regs[29]; |
121 | unsigned long ra = regs->regs[31]; | |
f66686f7 | 122 | unsigned long pc = regs->cp0_epc; |
f66686f7 AN |
123 | |
124 | if (raw_show_trace || !__kernel_text_address(pc)) { | |
87151ae3 | 125 | show_raw_backtrace(sp); |
f66686f7 AN |
126 | return; |
127 | } | |
128 | printk("Call Trace:\n"); | |
4d157d5e | 129 | do { |
87151ae3 | 130 | print_ip_sym(pc); |
1924600c | 131 | pc = unwind_stack(task, &sp, pc, &ra); |
4d157d5e | 132 | } while (pc); |
f66686f7 AN |
133 | printk("\n"); |
134 | } | |
f66686f7 | 135 | |
1da177e4 LT |
136 | /* |
137 | * This routine abuses get_user()/put_user() to reference pointers | |
138 | * with at least a bit of error checking ... | |
139 | */ | |
eae23f2c RB |
140 | static void show_stacktrace(struct task_struct *task, |
141 | const struct pt_regs *regs) | |
1da177e4 LT |
142 | { |
143 | const int field = 2 * sizeof(unsigned long); | |
144 | long stackdata; | |
145 | int i; | |
5e0373b8 | 146 | unsigned long __user *sp = (unsigned long __user *)regs->regs[29]; |
1da177e4 LT |
147 | |
148 | printk("Stack :"); | |
149 | i = 0; | |
150 | while ((unsigned long) sp & (PAGE_SIZE - 1)) { | |
151 | if (i && ((i % (64 / field)) == 0)) | |
152 | printk("\n "); | |
153 | if (i > 39) { | |
154 | printk(" ..."); | |
155 | break; | |
156 | } | |
157 | ||
158 | if (__get_user(stackdata, sp++)) { | |
159 | printk(" (Bad stack address)"); | |
160 | break; | |
161 | } | |
162 | ||
163 | printk(" %0*lx", field, stackdata); | |
164 | i++; | |
165 | } | |
166 | printk("\n"); | |
87151ae3 | 167 | show_backtrace(task, regs); |
f66686f7 AN |
168 | } |
169 | ||
f66686f7 AN |
170 | void show_stack(struct task_struct *task, unsigned long *sp) |
171 | { | |
172 | struct pt_regs regs; | |
173 | if (sp) { | |
174 | regs.regs[29] = (unsigned long)sp; | |
175 | regs.regs[31] = 0; | |
176 | regs.cp0_epc = 0; | |
177 | } else { | |
178 | if (task && task != current) { | |
179 | regs.regs[29] = task->thread.reg29; | |
180 | regs.regs[31] = 0; | |
181 | regs.cp0_epc = task->thread.reg31; | |
182 | } else { | |
183 | prepare_frametrace(®s); | |
184 | } | |
185 | } | |
186 | show_stacktrace(task, ®s); | |
1da177e4 LT |
187 | } |
188 | ||
189 | /* | |
190 | * The architecture-independent dump_stack generator | |
191 | */ | |
192 | void dump_stack(void) | |
193 | { | |
1666a6fc | 194 | struct pt_regs regs; |
1da177e4 | 195 | |
1666a6fc FBH |
196 | prepare_frametrace(®s); |
197 | show_backtrace(current, ®s); | |
1da177e4 LT |
198 | } |
199 | ||
200 | EXPORT_SYMBOL(dump_stack); | |
201 | ||
e1bb8289 | 202 | static void show_code(unsigned int __user *pc) |
1da177e4 LT |
203 | { |
204 | long i; | |
39b8d525 | 205 | unsigned short __user *pc16 = NULL; |
1da177e4 LT |
206 | |
207 | printk("\nCode:"); | |
208 | ||
39b8d525 RB |
209 | if ((unsigned long)pc & 1) |
210 | pc16 = (unsigned short __user *)((unsigned long)pc & ~1); | |
1da177e4 LT |
211 | for(i = -3 ; i < 6 ; i++) { |
212 | unsigned int insn; | |
39b8d525 | 213 | if (pc16 ? __get_user(insn, pc16 + i) : __get_user(insn, pc + i)) { |
1da177e4 LT |
214 | printk(" (Bad address in epc)\n"); |
215 | break; | |
216 | } | |
39b8d525 | 217 | printk("%c%0*x%c", (i?' ':'<'), pc16 ? 4 : 8, insn, (i?' ':'>')); |
1da177e4 LT |
218 | } |
219 | } | |
220 | ||
eae23f2c | 221 | static void __show_regs(const struct pt_regs *regs) |
1da177e4 LT |
222 | { |
223 | const int field = 2 * sizeof(unsigned long); | |
224 | unsigned int cause = regs->cp0_cause; | |
225 | int i; | |
226 | ||
227 | printk("Cpu %d\n", smp_processor_id()); | |
228 | ||
229 | /* | |
230 | * Saved main processor registers | |
231 | */ | |
232 | for (i = 0; i < 32; ) { | |
233 | if ((i % 4) == 0) | |
234 | printk("$%2d :", i); | |
235 | if (i == 0) | |
236 | printk(" %0*lx", field, 0UL); | |
237 | else if (i == 26 || i == 27) | |
238 | printk(" %*s", field, ""); | |
239 | else | |
240 | printk(" %0*lx", field, regs->regs[i]); | |
241 | ||
242 | i++; | |
243 | if ((i % 4) == 0) | |
244 | printk("\n"); | |
245 | } | |
246 | ||
9693a853 FBH |
247 | #ifdef CONFIG_CPU_HAS_SMARTMIPS |
248 | printk("Acx : %0*lx\n", field, regs->acx); | |
249 | #endif | |
1da177e4 LT |
250 | printk("Hi : %0*lx\n", field, regs->hi); |
251 | printk("Lo : %0*lx\n", field, regs->lo); | |
252 | ||
253 | /* | |
254 | * Saved cp0 registers | |
255 | */ | |
b012cffe RB |
256 | printk("epc : %0*lx %pS\n", field, regs->cp0_epc, |
257 | (void *) regs->cp0_epc); | |
1da177e4 | 258 | printk(" %s\n", print_tainted()); |
b012cffe RB |
259 | printk("ra : %0*lx %pS\n", field, regs->regs[31], |
260 | (void *) regs->regs[31]); | |
1da177e4 LT |
261 | |
262 | printk("Status: %08x ", (uint32_t) regs->cp0_status); | |
263 | ||
3b2396d9 MR |
264 | if (current_cpu_data.isa_level == MIPS_CPU_ISA_I) { |
265 | if (regs->cp0_status & ST0_KUO) | |
266 | printk("KUo "); | |
267 | if (regs->cp0_status & ST0_IEO) | |
268 | printk("IEo "); | |
269 | if (regs->cp0_status & ST0_KUP) | |
270 | printk("KUp "); | |
271 | if (regs->cp0_status & ST0_IEP) | |
272 | printk("IEp "); | |
273 | if (regs->cp0_status & ST0_KUC) | |
274 | printk("KUc "); | |
275 | if (regs->cp0_status & ST0_IEC) | |
276 | printk("IEc "); | |
277 | } else { | |
278 | if (regs->cp0_status & ST0_KX) | |
279 | printk("KX "); | |
280 | if (regs->cp0_status & ST0_SX) | |
281 | printk("SX "); | |
282 | if (regs->cp0_status & ST0_UX) | |
283 | printk("UX "); | |
284 | switch (regs->cp0_status & ST0_KSU) { | |
285 | case KSU_USER: | |
286 | printk("USER "); | |
287 | break; | |
288 | case KSU_SUPERVISOR: | |
289 | printk("SUPERVISOR "); | |
290 | break; | |
291 | case KSU_KERNEL: | |
292 | printk("KERNEL "); | |
293 | break; | |
294 | default: | |
295 | printk("BAD_MODE "); | |
296 | break; | |
297 | } | |
298 | if (regs->cp0_status & ST0_ERL) | |
299 | printk("ERL "); | |
300 | if (regs->cp0_status & ST0_EXL) | |
301 | printk("EXL "); | |
302 | if (regs->cp0_status & ST0_IE) | |
303 | printk("IE "); | |
1da177e4 | 304 | } |
1da177e4 LT |
305 | printk("\n"); |
306 | ||
307 | printk("Cause : %08x\n", cause); | |
308 | ||
309 | cause = (cause & CAUSEF_EXCCODE) >> CAUSEB_EXCCODE; | |
310 | if (1 <= cause && cause <= 5) | |
311 | printk("BadVA : %0*lx\n", field, regs->cp0_badvaddr); | |
312 | ||
9966db25 RB |
313 | printk("PrId : %08x (%s)\n", read_c0_prid(), |
314 | cpu_name_string()); | |
1da177e4 LT |
315 | } |
316 | ||
eae23f2c RB |
317 | /* |
318 | * FIXME: really the generic show_regs should take a const pointer argument. | |
319 | */ | |
320 | void show_regs(struct pt_regs *regs) | |
321 | { | |
322 | __show_regs((struct pt_regs *)regs); | |
323 | } | |
324 | ||
325 | void show_registers(const struct pt_regs *regs) | |
1da177e4 | 326 | { |
39b8d525 RB |
327 | const int field = 2 * sizeof(unsigned long); |
328 | ||
eae23f2c | 329 | __show_regs(regs); |
1da177e4 | 330 | print_modules(); |
39b8d525 RB |
331 | printk("Process %s (pid: %d, threadinfo=%p, task=%p, tls=%0*lx)\n", |
332 | current->comm, current->pid, current_thread_info(), current, | |
333 | field, current_thread_info()->tp_value); | |
334 | if (cpu_has_userlocal) { | |
335 | unsigned long tls; | |
336 | ||
337 | tls = read_c0_userlocal(); | |
338 | if (tls != current_thread_info()->tp_value) | |
339 | printk("*HwTLS: %0*lx\n", field, tls); | |
340 | } | |
341 | ||
f66686f7 | 342 | show_stacktrace(current, regs); |
e1bb8289 | 343 | show_code((unsigned int __user *) regs->cp0_epc); |
1da177e4 LT |
344 | printk("\n"); |
345 | } | |
346 | ||
347 | static DEFINE_SPINLOCK(die_lock); | |
348 | ||
eae23f2c | 349 | void __noreturn die(const char * str, const struct pt_regs * regs) |
1da177e4 LT |
350 | { |
351 | static int die_counter; | |
41c594ab RB |
352 | #ifdef CONFIG_MIPS_MT_SMTC |
353 | unsigned long dvpret = dvpe(); | |
354 | #endif /* CONFIG_MIPS_MT_SMTC */ | |
1da177e4 LT |
355 | |
356 | console_verbose(); | |
357 | spin_lock_irq(&die_lock); | |
41c594ab RB |
358 | bust_spinlocks(1); |
359 | #ifdef CONFIG_MIPS_MT_SMTC | |
360 | mips_mt_regdump(dvpret); | |
361 | #endif /* CONFIG_MIPS_MT_SMTC */ | |
178086c8 | 362 | printk("%s[#%d]:\n", str, ++die_counter); |
1da177e4 | 363 | show_registers(regs); |
bcdcd8e7 | 364 | add_taint(TAINT_DIE); |
1da177e4 | 365 | spin_unlock_irq(&die_lock); |
d4fd1989 MB |
366 | |
367 | if (in_interrupt()) | |
368 | panic("Fatal exception in interrupt"); | |
369 | ||
370 | if (panic_on_oops) { | |
371 | printk(KERN_EMERG "Fatal exception: panic in 5 seconds\n"); | |
372 | ssleep(5); | |
373 | panic("Fatal exception"); | |
374 | } | |
375 | ||
1da177e4 LT |
376 | do_exit(SIGSEGV); |
377 | } | |
378 | ||
0510617b TB |
379 | extern struct exception_table_entry __start___dbe_table[]; |
380 | extern struct exception_table_entry __stop___dbe_table[]; | |
1da177e4 | 381 | |
b6dcec9b RB |
382 | __asm__( |
383 | " .section __dbe_table, \"a\"\n" | |
384 | " .previous \n"); | |
1da177e4 LT |
385 | |
386 | /* Given an address, look for it in the exception tables. */ | |
387 | static const struct exception_table_entry *search_dbe_tables(unsigned long addr) | |
388 | { | |
389 | const struct exception_table_entry *e; | |
390 | ||
391 | e = search_extable(__start___dbe_table, __stop___dbe_table - 1, addr); | |
392 | if (!e) | |
393 | e = search_module_dbetables(addr); | |
394 | return e; | |
395 | } | |
396 | ||
397 | asmlinkage void do_be(struct pt_regs *regs) | |
398 | { | |
399 | const int field = 2 * sizeof(unsigned long); | |
400 | const struct exception_table_entry *fixup = NULL; | |
401 | int data = regs->cp0_cause & 4; | |
402 | int action = MIPS_BE_FATAL; | |
403 | ||
404 | /* XXX For now. Fixme, this searches the wrong table ... */ | |
405 | if (data && !user_mode(regs)) | |
406 | fixup = search_dbe_tables(exception_epc(regs)); | |
407 | ||
408 | if (fixup) | |
409 | action = MIPS_BE_FIXUP; | |
410 | ||
411 | if (board_be_handler) | |
28fc582c | 412 | action = board_be_handler(regs, fixup != NULL); |
1da177e4 LT |
413 | |
414 | switch (action) { | |
415 | case MIPS_BE_DISCARD: | |
416 | return; | |
417 | case MIPS_BE_FIXUP: | |
418 | if (fixup) { | |
419 | regs->cp0_epc = fixup->nextinsn; | |
420 | return; | |
421 | } | |
422 | break; | |
423 | default: | |
424 | break; | |
425 | } | |
426 | ||
427 | /* | |
428 | * Assume it would be too dangerous to continue ... | |
429 | */ | |
430 | printk(KERN_ALERT "%s bus error, epc == %0*lx, ra == %0*lx\n", | |
431 | data ? "Data" : "Instruction", | |
432 | field, regs->cp0_epc, field, regs->regs[31]); | |
88547001 JW |
433 | if (notify_die(DIE_OOPS, "bus error", regs, SIGBUS, 0, 0) |
434 | == NOTIFY_STOP) | |
435 | return; | |
436 | ||
1da177e4 LT |
437 | die_if_kernel("Oops", regs); |
438 | force_sig(SIGBUS, current); | |
439 | } | |
440 | ||
1da177e4 | 441 | /* |
60b0d655 | 442 | * ll/sc, rdhwr, sync emulation |
1da177e4 LT |
443 | */ |
444 | ||
445 | #define OPCODE 0xfc000000 | |
446 | #define BASE 0x03e00000 | |
447 | #define RT 0x001f0000 | |
448 | #define OFFSET 0x0000ffff | |
449 | #define LL 0xc0000000 | |
450 | #define SC 0xe0000000 | |
60b0d655 | 451 | #define SPEC0 0x00000000 |
3c37026d RB |
452 | #define SPEC3 0x7c000000 |
453 | #define RD 0x0000f800 | |
454 | #define FUNC 0x0000003f | |
60b0d655 | 455 | #define SYNC 0x0000000f |
3c37026d | 456 | #define RDHWR 0x0000003b |
1da177e4 LT |
457 | |
458 | /* | |
459 | * The ll_bit is cleared by r*_switch.S | |
460 | */ | |
461 | ||
462 | unsigned long ll_bit; | |
463 | ||
464 | static struct task_struct *ll_task = NULL; | |
465 | ||
60b0d655 | 466 | static inline int simulate_ll(struct pt_regs *regs, unsigned int opcode) |
1da177e4 | 467 | { |
fe00f943 | 468 | unsigned long value, __user *vaddr; |
1da177e4 | 469 | long offset; |
1da177e4 LT |
470 | |
471 | /* | |
472 | * analyse the ll instruction that just caused a ri exception | |
473 | * and put the referenced address to addr. | |
474 | */ | |
475 | ||
476 | /* sign extend offset */ | |
477 | offset = opcode & OFFSET; | |
478 | offset <<= 16; | |
479 | offset >>= 16; | |
480 | ||
fe00f943 RB |
481 | vaddr = (unsigned long __user *) |
482 | ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset); | |
1da177e4 | 483 | |
60b0d655 MR |
484 | if ((unsigned long)vaddr & 3) |
485 | return SIGBUS; | |
486 | if (get_user(value, vaddr)) | |
487 | return SIGSEGV; | |
1da177e4 LT |
488 | |
489 | preempt_disable(); | |
490 | ||
491 | if (ll_task == NULL || ll_task == current) { | |
492 | ll_bit = 1; | |
493 | } else { | |
494 | ll_bit = 0; | |
495 | } | |
496 | ll_task = current; | |
497 | ||
498 | preempt_enable(); | |
499 | ||
500 | regs->regs[(opcode & RT) >> 16] = value; | |
501 | ||
60b0d655 | 502 | return 0; |
1da177e4 LT |
503 | } |
504 | ||
60b0d655 | 505 | static inline int simulate_sc(struct pt_regs *regs, unsigned int opcode) |
1da177e4 | 506 | { |
fe00f943 RB |
507 | unsigned long __user *vaddr; |
508 | unsigned long reg; | |
1da177e4 | 509 | long offset; |
1da177e4 LT |
510 | |
511 | /* | |
512 | * analyse the sc instruction that just caused a ri exception | |
513 | * and put the referenced address to addr. | |
514 | */ | |
515 | ||
516 | /* sign extend offset */ | |
517 | offset = opcode & OFFSET; | |
518 | offset <<= 16; | |
519 | offset >>= 16; | |
520 | ||
fe00f943 RB |
521 | vaddr = (unsigned long __user *) |
522 | ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset); | |
1da177e4 LT |
523 | reg = (opcode & RT) >> 16; |
524 | ||
60b0d655 MR |
525 | if ((unsigned long)vaddr & 3) |
526 | return SIGBUS; | |
1da177e4 LT |
527 | |
528 | preempt_disable(); | |
529 | ||
530 | if (ll_bit == 0 || ll_task != current) { | |
531 | regs->regs[reg] = 0; | |
532 | preempt_enable(); | |
60b0d655 | 533 | return 0; |
1da177e4 LT |
534 | } |
535 | ||
536 | preempt_enable(); | |
537 | ||
60b0d655 MR |
538 | if (put_user(regs->regs[reg], vaddr)) |
539 | return SIGSEGV; | |
1da177e4 LT |
540 | |
541 | regs->regs[reg] = 1; | |
542 | ||
60b0d655 | 543 | return 0; |
1da177e4 LT |
544 | } |
545 | ||
546 | /* | |
547 | * ll uses the opcode of lwc0 and sc uses the opcode of swc0. That is both | |
548 | * opcodes are supposed to result in coprocessor unusable exceptions if | |
549 | * executed on ll/sc-less processors. That's the theory. In practice a | |
550 | * few processors such as NEC's VR4100 throw reserved instruction exceptions | |
551 | * instead, so we're doing the emulation thing in both exception handlers. | |
552 | */ | |
60b0d655 | 553 | static int simulate_llsc(struct pt_regs *regs, unsigned int opcode) |
1da177e4 | 554 | { |
60b0d655 MR |
555 | if ((opcode & OPCODE) == LL) |
556 | return simulate_ll(regs, opcode); | |
557 | if ((opcode & OPCODE) == SC) | |
558 | return simulate_sc(regs, opcode); | |
1da177e4 | 559 | |
60b0d655 | 560 | return -1; /* Must be something else ... */ |
1da177e4 LT |
561 | } |
562 | ||
3c37026d RB |
563 | /* |
564 | * Simulate trapping 'rdhwr' instructions to provide user accessible | |
1f5826bd | 565 | * registers not implemented in hardware. |
3c37026d | 566 | */ |
60b0d655 | 567 | static int simulate_rdhwr(struct pt_regs *regs, unsigned int opcode) |
3c37026d | 568 | { |
dc8f6029 | 569 | struct thread_info *ti = task_thread_info(current); |
3c37026d RB |
570 | |
571 | if ((opcode & OPCODE) == SPEC3 && (opcode & FUNC) == RDHWR) { | |
572 | int rd = (opcode & RD) >> 11; | |
573 | int rt = (opcode & RT) >> 16; | |
574 | switch (rd) { | |
1f5826bd CD |
575 | case 0: /* CPU number */ |
576 | regs->regs[rt] = smp_processor_id(); | |
577 | return 0; | |
578 | case 1: /* SYNCI length */ | |
579 | regs->regs[rt] = min(current_cpu_data.dcache.linesz, | |
580 | current_cpu_data.icache.linesz); | |
581 | return 0; | |
582 | case 2: /* Read count register */ | |
583 | regs->regs[rt] = read_c0_count(); | |
584 | return 0; | |
585 | case 3: /* Count register resolution */ | |
586 | switch (current_cpu_data.cputype) { | |
587 | case CPU_20KC: | |
588 | case CPU_25KF: | |
589 | regs->regs[rt] = 1; | |
590 | break; | |
3c37026d | 591 | default: |
1f5826bd CD |
592 | regs->regs[rt] = 2; |
593 | } | |
594 | return 0; | |
595 | case 29: | |
596 | regs->regs[rt] = ti->tp_value; | |
597 | return 0; | |
598 | default: | |
599 | return -1; | |
3c37026d RB |
600 | } |
601 | } | |
602 | ||
56ebd51b | 603 | /* Not ours. */ |
60b0d655 MR |
604 | return -1; |
605 | } | |
e5679882 | 606 | |
60b0d655 MR |
607 | static int simulate_sync(struct pt_regs *regs, unsigned int opcode) |
608 | { | |
609 | if ((opcode & OPCODE) == SPEC0 && (opcode & FUNC) == SYNC) | |
610 | return 0; | |
611 | ||
612 | return -1; /* Must be something else ... */ | |
3c37026d RB |
613 | } |
614 | ||
1da177e4 LT |
615 | asmlinkage void do_ov(struct pt_regs *regs) |
616 | { | |
617 | siginfo_t info; | |
618 | ||
36ccf1c0 RB |
619 | die_if_kernel("Integer overflow", regs); |
620 | ||
1da177e4 LT |
621 | info.si_code = FPE_INTOVF; |
622 | info.si_signo = SIGFPE; | |
623 | info.si_errno = 0; | |
fe00f943 | 624 | info.si_addr = (void __user *) regs->cp0_epc; |
1da177e4 LT |
625 | force_sig_info(SIGFPE, &info, current); |
626 | } | |
627 | ||
628 | /* | |
629 | * XXX Delayed fp exceptions when doing a lazy ctx switch XXX | |
630 | */ | |
631 | asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31) | |
632 | { | |
948a34cf TS |
633 | siginfo_t info; |
634 | ||
88547001 JW |
635 | if (notify_die(DIE_FP, "FP exception", regs, SIGFPE, 0, 0) |
636 | == NOTIFY_STOP) | |
637 | return; | |
57725f9e CD |
638 | die_if_kernel("FP exception in kernel code", regs); |
639 | ||
1da177e4 LT |
640 | if (fcr31 & FPU_CSR_UNI_X) { |
641 | int sig; | |
642 | ||
1da177e4 | 643 | /* |
a3dddd56 | 644 | * Unimplemented operation exception. If we've got the full |
1da177e4 LT |
645 | * software emulator on-board, let's use it... |
646 | * | |
647 | * Force FPU to dump state into task/thread context. We're | |
648 | * moving a lot of data here for what is probably a single | |
649 | * instruction, but the alternative is to pre-decode the FP | |
650 | * register operands before invoking the emulator, which seems | |
651 | * a bit extreme for what should be an infrequent event. | |
652 | */ | |
cd21dfcf | 653 | /* Ensure 'resume' not overwrite saved fp context again. */ |
53dc8028 | 654 | lose_fpu(1); |
1da177e4 LT |
655 | |
656 | /* Run the emulator */ | |
49a89efb | 657 | sig = fpu_emulator_cop1Handler(regs, ¤t->thread.fpu, 1); |
1da177e4 LT |
658 | |
659 | /* | |
660 | * We can't allow the emulated instruction to leave any of | |
661 | * the cause bit set in $fcr31. | |
662 | */ | |
eae89076 | 663 | current->thread.fpu.fcr31 &= ~FPU_CSR_ALL_X; |
1da177e4 LT |
664 | |
665 | /* Restore the hardware register state */ | |
53dc8028 | 666 | own_fpu(1); /* Using the FPU again. */ |
1da177e4 LT |
667 | |
668 | /* If something went wrong, signal */ | |
669 | if (sig) | |
670 | force_sig(sig, current); | |
671 | ||
672 | return; | |
948a34cf TS |
673 | } else if (fcr31 & FPU_CSR_INV_X) |
674 | info.si_code = FPE_FLTINV; | |
675 | else if (fcr31 & FPU_CSR_DIV_X) | |
676 | info.si_code = FPE_FLTDIV; | |
677 | else if (fcr31 & FPU_CSR_OVF_X) | |
678 | info.si_code = FPE_FLTOVF; | |
679 | else if (fcr31 & FPU_CSR_UDF_X) | |
680 | info.si_code = FPE_FLTUND; | |
681 | else if (fcr31 & FPU_CSR_INE_X) | |
682 | info.si_code = FPE_FLTRES; | |
683 | else | |
684 | info.si_code = __SI_FAULT; | |
685 | info.si_signo = SIGFPE; | |
686 | info.si_errno = 0; | |
687 | info.si_addr = (void __user *) regs->cp0_epc; | |
688 | force_sig_info(SIGFPE, &info, current); | |
1da177e4 LT |
689 | } |
690 | ||
df270051 RB |
691 | static void do_trap_or_bp(struct pt_regs *regs, unsigned int code, |
692 | const char *str) | |
1da177e4 | 693 | { |
1da177e4 | 694 | siginfo_t info; |
df270051 | 695 | char b[40]; |
1da177e4 | 696 | |
88547001 JW |
697 | if (notify_die(DIE_TRAP, str, regs, code, 0, 0) == NOTIFY_STOP) |
698 | return; | |
699 | ||
1da177e4 | 700 | /* |
df270051 RB |
701 | * A short test says that IRIX 5.3 sends SIGTRAP for all trap |
702 | * insns, even for trap and break codes that indicate arithmetic | |
703 | * failures. Weird ... | |
1da177e4 LT |
704 | * But should we continue the brokenness??? --macro |
705 | */ | |
df270051 RB |
706 | switch (code) { |
707 | case BRK_OVERFLOW: | |
708 | case BRK_DIVZERO: | |
709 | scnprintf(b, sizeof(b), "%s instruction in kernel code", str); | |
710 | die_if_kernel(b, regs); | |
711 | if (code == BRK_DIVZERO) | |
1da177e4 LT |
712 | info.si_code = FPE_INTDIV; |
713 | else | |
714 | info.si_code = FPE_INTOVF; | |
715 | info.si_signo = SIGFPE; | |
716 | info.si_errno = 0; | |
fe00f943 | 717 | info.si_addr = (void __user *) regs->cp0_epc; |
1da177e4 LT |
718 | force_sig_info(SIGFPE, &info, current); |
719 | break; | |
63dc68a8 | 720 | case BRK_BUG: |
df270051 RB |
721 | die_if_kernel("Kernel bug detected", regs); |
722 | force_sig(SIGTRAP, current); | |
63dc68a8 | 723 | break; |
1da177e4 | 724 | default: |
df270051 RB |
725 | scnprintf(b, sizeof(b), "%s instruction in kernel code", str); |
726 | die_if_kernel(b, regs); | |
1da177e4 LT |
727 | force_sig(SIGTRAP, current); |
728 | } | |
df270051 RB |
729 | } |
730 | ||
731 | asmlinkage void do_bp(struct pt_regs *regs) | |
732 | { | |
733 | unsigned int opcode, bcode; | |
734 | ||
735 | if (__get_user(opcode, (unsigned int __user *) exception_epc(regs))) | |
736 | goto out_sigsegv; | |
737 | ||
738 | /* | |
739 | * There is the ancient bug in the MIPS assemblers that the break | |
740 | * code starts left to bit 16 instead to bit 6 in the opcode. | |
741 | * Gas is bug-compatible, but not always, grrr... | |
742 | * We handle both cases with a simple heuristics. --macro | |
743 | */ | |
744 | bcode = ((opcode >> 6) & ((1 << 20) - 1)); | |
745 | if (bcode >= (1 << 10)) | |
746 | bcode >>= 10; | |
747 | ||
748 | do_trap_or_bp(regs, bcode, "Break"); | |
90fccb13 | 749 | return; |
e5679882 RB |
750 | |
751 | out_sigsegv: | |
752 | force_sig(SIGSEGV, current); | |
1da177e4 LT |
753 | } |
754 | ||
755 | asmlinkage void do_tr(struct pt_regs *regs) | |
756 | { | |
757 | unsigned int opcode, tcode = 0; | |
1da177e4 | 758 | |
ba755f8e | 759 | if (__get_user(opcode, (unsigned int __user *) exception_epc(regs))) |
e5679882 | 760 | goto out_sigsegv; |
1da177e4 LT |
761 | |
762 | /* Immediate versions don't provide a code. */ | |
763 | if (!(opcode & OPCODE)) | |
764 | tcode = ((opcode >> 6) & ((1 << 10) - 1)); | |
765 | ||
df270051 | 766 | do_trap_or_bp(regs, tcode, "Trap"); |
90fccb13 | 767 | return; |
e5679882 RB |
768 | |
769 | out_sigsegv: | |
770 | force_sig(SIGSEGV, current); | |
1da177e4 LT |
771 | } |
772 | ||
773 | asmlinkage void do_ri(struct pt_regs *regs) | |
774 | { | |
60b0d655 MR |
775 | unsigned int __user *epc = (unsigned int __user *)exception_epc(regs); |
776 | unsigned long old_epc = regs->cp0_epc; | |
777 | unsigned int opcode = 0; | |
778 | int status = -1; | |
1da177e4 | 779 | |
88547001 JW |
780 | if (notify_die(DIE_RI, "RI Fault", regs, SIGSEGV, 0, 0) |
781 | == NOTIFY_STOP) | |
782 | return; | |
783 | ||
60b0d655 | 784 | die_if_kernel("Reserved instruction in kernel code", regs); |
1da177e4 | 785 | |
60b0d655 | 786 | if (unlikely(compute_return_epc(regs) < 0)) |
3c37026d RB |
787 | return; |
788 | ||
60b0d655 MR |
789 | if (unlikely(get_user(opcode, epc) < 0)) |
790 | status = SIGSEGV; | |
791 | ||
792 | if (!cpu_has_llsc && status < 0) | |
793 | status = simulate_llsc(regs, opcode); | |
794 | ||
795 | if (status < 0) | |
796 | status = simulate_rdhwr(regs, opcode); | |
797 | ||
798 | if (status < 0) | |
799 | status = simulate_sync(regs, opcode); | |
800 | ||
801 | if (status < 0) | |
802 | status = SIGILL; | |
803 | ||
804 | if (unlikely(status > 0)) { | |
805 | regs->cp0_epc = old_epc; /* Undo skip-over. */ | |
806 | force_sig(status, current); | |
807 | } | |
1da177e4 LT |
808 | } |
809 | ||
d223a861 RB |
810 | /* |
811 | * MIPS MT processors may have fewer FPU contexts than CPU threads. If we've | |
812 | * emulated more than some threshold number of instructions, force migration to | |
813 | * a "CPU" that has FP support. | |
814 | */ | |
815 | static void mt_ase_fp_affinity(void) | |
816 | { | |
817 | #ifdef CONFIG_MIPS_MT_FPAFF | |
818 | if (mt_fpemul_threshold > 0 && | |
819 | ((current->thread.emulated_fp++ > mt_fpemul_threshold))) { | |
820 | /* | |
821 | * If there's no FPU present, or if the application has already | |
822 | * restricted the allowed set to exclude any CPUs with FPUs, | |
823 | * we'll skip the procedure. | |
824 | */ | |
825 | if (cpus_intersects(current->cpus_allowed, mt_fpu_cpumask)) { | |
826 | cpumask_t tmask; | |
827 | ||
828 | cpus_and(tmask, current->thread.user_cpus_allowed, | |
829 | mt_fpu_cpumask); | |
830 | set_cpus_allowed(current, tmask); | |
293c5bd1 | 831 | set_thread_flag(TIF_FPUBOUND); |
d223a861 RB |
832 | } |
833 | } | |
834 | #endif /* CONFIG_MIPS_MT_FPAFF */ | |
835 | } | |
836 | ||
1da177e4 LT |
837 | asmlinkage void do_cpu(struct pt_regs *regs) |
838 | { | |
60b0d655 MR |
839 | unsigned int __user *epc; |
840 | unsigned long old_epc; | |
841 | unsigned int opcode; | |
1da177e4 | 842 | unsigned int cpid; |
60b0d655 | 843 | int status; |
1da177e4 | 844 | |
5323180d AN |
845 | die_if_kernel("do_cpu invoked from kernel context!", regs); |
846 | ||
1da177e4 LT |
847 | cpid = (regs->cp0_cause >> CAUSEB_CE) & 3; |
848 | ||
849 | switch (cpid) { | |
850 | case 0: | |
60b0d655 MR |
851 | epc = (unsigned int __user *)exception_epc(regs); |
852 | old_epc = regs->cp0_epc; | |
853 | opcode = 0; | |
854 | status = -1; | |
1da177e4 | 855 | |
60b0d655 | 856 | if (unlikely(compute_return_epc(regs) < 0)) |
1da177e4 | 857 | return; |
3c37026d | 858 | |
60b0d655 MR |
859 | if (unlikely(get_user(opcode, epc) < 0)) |
860 | status = SIGSEGV; | |
861 | ||
862 | if (!cpu_has_llsc && status < 0) | |
863 | status = simulate_llsc(regs, opcode); | |
864 | ||
865 | if (status < 0) | |
866 | status = simulate_rdhwr(regs, opcode); | |
867 | ||
868 | if (status < 0) | |
869 | status = SIGILL; | |
870 | ||
871 | if (unlikely(status > 0)) { | |
872 | regs->cp0_epc = old_epc; /* Undo skip-over. */ | |
873 | force_sig(status, current); | |
874 | } | |
875 | ||
876 | return; | |
1da177e4 LT |
877 | |
878 | case 1: | |
53dc8028 AN |
879 | if (used_math()) /* Using the FPU again. */ |
880 | own_fpu(1); | |
881 | else { /* First time FPU user. */ | |
1da177e4 LT |
882 | init_fpu(); |
883 | set_used_math(); | |
884 | } | |
885 | ||
5323180d | 886 | if (!raw_cpu_has_fpu) { |
e04582b7 | 887 | int sig; |
e04582b7 AN |
888 | sig = fpu_emulator_cop1Handler(regs, |
889 | ¤t->thread.fpu, 0); | |
1da177e4 LT |
890 | if (sig) |
891 | force_sig(sig, current); | |
d223a861 RB |
892 | else |
893 | mt_ase_fp_affinity(); | |
1da177e4 LT |
894 | } |
895 | ||
1da177e4 LT |
896 | return; |
897 | ||
898 | case 2: | |
899 | case 3: | |
900 | break; | |
901 | } | |
902 | ||
903 | force_sig(SIGILL, current); | |
904 | } | |
905 | ||
906 | asmlinkage void do_mdmx(struct pt_regs *regs) | |
907 | { | |
908 | force_sig(SIGILL, current); | |
909 | } | |
910 | ||
911 | asmlinkage void do_watch(struct pt_regs *regs) | |
912 | { | |
913 | /* | |
914 | * We use the watch exception where available to detect stack | |
915 | * overflows. | |
916 | */ | |
917 | dump_tlb_all(); | |
918 | show_regs(regs); | |
919 | panic("Caught WATCH exception - probably caused by stack overflow."); | |
920 | } | |
921 | ||
922 | asmlinkage void do_mcheck(struct pt_regs *regs) | |
923 | { | |
cac4bcbc RB |
924 | const int field = 2 * sizeof(unsigned long); |
925 | int multi_match = regs->cp0_status & ST0_TS; | |
926 | ||
1da177e4 | 927 | show_regs(regs); |
cac4bcbc RB |
928 | |
929 | if (multi_match) { | |
930 | printk("Index : %0x\n", read_c0_index()); | |
931 | printk("Pagemask: %0x\n", read_c0_pagemask()); | |
932 | printk("EntryHi : %0*lx\n", field, read_c0_entryhi()); | |
933 | printk("EntryLo0: %0*lx\n", field, read_c0_entrylo0()); | |
934 | printk("EntryLo1: %0*lx\n", field, read_c0_entrylo1()); | |
935 | printk("\n"); | |
936 | dump_tlb_all(); | |
937 | } | |
938 | ||
e1bb8289 | 939 | show_code((unsigned int __user *) regs->cp0_epc); |
cac4bcbc | 940 | |
1da177e4 LT |
941 | /* |
942 | * Some chips may have other causes of machine check (e.g. SB1 | |
943 | * graduation timer) | |
944 | */ | |
945 | panic("Caught Machine Check exception - %scaused by multiple " | |
946 | "matching entries in the TLB.", | |
cac4bcbc | 947 | (multi_match) ? "" : "not "); |
1da177e4 LT |
948 | } |
949 | ||
340ee4b9 RB |
950 | asmlinkage void do_mt(struct pt_regs *regs) |
951 | { | |
41c594ab RB |
952 | int subcode; |
953 | ||
41c594ab RB |
954 | subcode = (read_vpe_c0_vpecontrol() & VPECONTROL_EXCPT) |
955 | >> VPECONTROL_EXCPT_SHIFT; | |
956 | switch (subcode) { | |
957 | case 0: | |
e35a5e35 | 958 | printk(KERN_DEBUG "Thread Underflow\n"); |
41c594ab RB |
959 | break; |
960 | case 1: | |
e35a5e35 | 961 | printk(KERN_DEBUG "Thread Overflow\n"); |
41c594ab RB |
962 | break; |
963 | case 2: | |
e35a5e35 | 964 | printk(KERN_DEBUG "Invalid YIELD Qualifier\n"); |
41c594ab RB |
965 | break; |
966 | case 3: | |
e35a5e35 | 967 | printk(KERN_DEBUG "Gating Storage Exception\n"); |
41c594ab RB |
968 | break; |
969 | case 4: | |
e35a5e35 | 970 | printk(KERN_DEBUG "YIELD Scheduler Exception\n"); |
41c594ab RB |
971 | break; |
972 | case 5: | |
e35a5e35 | 973 | printk(KERN_DEBUG "Gating Storage Schedulier Exception\n"); |
41c594ab RB |
974 | break; |
975 | default: | |
e35a5e35 | 976 | printk(KERN_DEBUG "*** UNKNOWN THREAD EXCEPTION %d ***\n", |
41c594ab RB |
977 | subcode); |
978 | break; | |
979 | } | |
340ee4b9 RB |
980 | die_if_kernel("MIPS MT Thread exception in kernel", regs); |
981 | ||
982 | force_sig(SIGILL, current); | |
983 | } | |
984 | ||
985 | ||
e50c0a8f RB |
986 | asmlinkage void do_dsp(struct pt_regs *regs) |
987 | { | |
988 | if (cpu_has_dsp) | |
989 | panic("Unexpected DSP exception\n"); | |
990 | ||
991 | force_sig(SIGILL, current); | |
992 | } | |
993 | ||
1da177e4 LT |
994 | asmlinkage void do_reserved(struct pt_regs *regs) |
995 | { | |
996 | /* | |
997 | * Game over - no way to handle this if it ever occurs. Most probably | |
998 | * caused by a new unknown cpu type or after another deadly | |
999 | * hard/software error. | |
1000 | */ | |
1001 | show_regs(regs); | |
1002 | panic("Caught reserved exception %ld - should not happen.", | |
1003 | (regs->cp0_cause & 0x7f) >> 2); | |
1004 | } | |
1005 | ||
39b8d525 RB |
1006 | static int __initdata l1parity = 1; |
1007 | static int __init nol1parity(char *s) | |
1008 | { | |
1009 | l1parity = 0; | |
1010 | return 1; | |
1011 | } | |
1012 | __setup("nol1par", nol1parity); | |
1013 | static int __initdata l2parity = 1; | |
1014 | static int __init nol2parity(char *s) | |
1015 | { | |
1016 | l2parity = 0; | |
1017 | return 1; | |
1018 | } | |
1019 | __setup("nol2par", nol2parity); | |
1020 | ||
1da177e4 LT |
1021 | /* |
1022 | * Some MIPS CPUs can enable/disable for cache parity detection, but do | |
1023 | * it different ways. | |
1024 | */ | |
1025 | static inline void parity_protection_init(void) | |
1026 | { | |
10cc3529 | 1027 | switch (current_cpu_type()) { |
1da177e4 | 1028 | case CPU_24K: |
98a41de9 | 1029 | case CPU_34K: |
39b8d525 RB |
1030 | case CPU_74K: |
1031 | case CPU_1004K: | |
1032 | { | |
1033 | #define ERRCTL_PE 0x80000000 | |
1034 | #define ERRCTL_L2P 0x00800000 | |
1035 | unsigned long errctl; | |
1036 | unsigned int l1parity_present, l2parity_present; | |
1037 | ||
1038 | errctl = read_c0_ecc(); | |
1039 | errctl &= ~(ERRCTL_PE|ERRCTL_L2P); | |
1040 | ||
1041 | /* probe L1 parity support */ | |
1042 | write_c0_ecc(errctl | ERRCTL_PE); | |
1043 | back_to_back_c0_hazard(); | |
1044 | l1parity_present = (read_c0_ecc() & ERRCTL_PE); | |
1045 | ||
1046 | /* probe L2 parity support */ | |
1047 | write_c0_ecc(errctl|ERRCTL_L2P); | |
1048 | back_to_back_c0_hazard(); | |
1049 | l2parity_present = (read_c0_ecc() & ERRCTL_L2P); | |
1050 | ||
1051 | if (l1parity_present && l2parity_present) { | |
1052 | if (l1parity) | |
1053 | errctl |= ERRCTL_PE; | |
1054 | if (l1parity ^ l2parity) | |
1055 | errctl |= ERRCTL_L2P; | |
1056 | } else if (l1parity_present) { | |
1057 | if (l1parity) | |
1058 | errctl |= ERRCTL_PE; | |
1059 | } else if (l2parity_present) { | |
1060 | if (l2parity) | |
1061 | errctl |= ERRCTL_L2P; | |
1062 | } else { | |
1063 | /* No parity available */ | |
1064 | } | |
1065 | ||
1066 | printk(KERN_INFO "Writing ErrCtl register=%08lx\n", errctl); | |
1067 | ||
1068 | write_c0_ecc(errctl); | |
1069 | back_to_back_c0_hazard(); | |
1070 | errctl = read_c0_ecc(); | |
1071 | printk(KERN_INFO "Readback ErrCtl register=%08lx\n", errctl); | |
1072 | ||
1073 | if (l1parity_present) | |
1074 | printk(KERN_INFO "Cache parity protection %sabled\n", | |
1075 | (errctl & ERRCTL_PE) ? "en" : "dis"); | |
1076 | ||
1077 | if (l2parity_present) { | |
1078 | if (l1parity_present && l1parity) | |
1079 | errctl ^= ERRCTL_L2P; | |
1080 | printk(KERN_INFO "L2 cache parity protection %sabled\n", | |
1081 | (errctl & ERRCTL_L2P) ? "en" : "dis"); | |
1082 | } | |
1083 | } | |
1084 | break; | |
1085 | ||
1da177e4 | 1086 | case CPU_5KC: |
14f18b7f RB |
1087 | write_c0_ecc(0x80000000); |
1088 | back_to_back_c0_hazard(); | |
1089 | /* Set the PE bit (bit 31) in the c0_errctl register. */ | |
1090 | printk(KERN_INFO "Cache parity protection %sabled\n", | |
1091 | (read_c0_ecc() & 0x80000000) ? "en" : "dis"); | |
1da177e4 LT |
1092 | break; |
1093 | case CPU_20KC: | |
1094 | case CPU_25KF: | |
1095 | /* Clear the DE bit (bit 16) in the c0_status register. */ | |
1096 | printk(KERN_INFO "Enable cache parity protection for " | |
1097 | "MIPS 20KC/25KF CPUs.\n"); | |
1098 | clear_c0_status(ST0_DE); | |
1099 | break; | |
1100 | default: | |
1101 | break; | |
1102 | } | |
1103 | } | |
1104 | ||
1105 | asmlinkage void cache_parity_error(void) | |
1106 | { | |
1107 | const int field = 2 * sizeof(unsigned long); | |
1108 | unsigned int reg_val; | |
1109 | ||
1110 | /* For the moment, report the problem and hang. */ | |
1111 | printk("Cache error exception:\n"); | |
1112 | printk("cp0_errorepc == %0*lx\n", field, read_c0_errorepc()); | |
1113 | reg_val = read_c0_cacheerr(); | |
1114 | printk("c0_cacheerr == %08x\n", reg_val); | |
1115 | ||
1116 | printk("Decoded c0_cacheerr: %s cache fault in %s reference.\n", | |
1117 | reg_val & (1<<30) ? "secondary" : "primary", | |
1118 | reg_val & (1<<31) ? "data" : "insn"); | |
1119 | printk("Error bits: %s%s%s%s%s%s%s\n", | |
1120 | reg_val & (1<<29) ? "ED " : "", | |
1121 | reg_val & (1<<28) ? "ET " : "", | |
1122 | reg_val & (1<<26) ? "EE " : "", | |
1123 | reg_val & (1<<25) ? "EB " : "", | |
1124 | reg_val & (1<<24) ? "EI " : "", | |
1125 | reg_val & (1<<23) ? "E1 " : "", | |
1126 | reg_val & (1<<22) ? "E0 " : ""); | |
1127 | printk("IDX: 0x%08x\n", reg_val & ((1<<22)-1)); | |
1128 | ||
ec917c2c | 1129 | #if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64) |
1da177e4 LT |
1130 | if (reg_val & (1<<22)) |
1131 | printk("DErrAddr0: 0x%0*lx\n", field, read_c0_derraddr0()); | |
1132 | ||
1133 | if (reg_val & (1<<23)) | |
1134 | printk("DErrAddr1: 0x%0*lx\n", field, read_c0_derraddr1()); | |
1135 | #endif | |
1136 | ||
1137 | panic("Can't handle the cache error!"); | |
1138 | } | |
1139 | ||
1140 | /* | |
1141 | * SDBBP EJTAG debug exception handler. | |
1142 | * We skip the instruction and return to the next instruction. | |
1143 | */ | |
1144 | void ejtag_exception_handler(struct pt_regs *regs) | |
1145 | { | |
1146 | const int field = 2 * sizeof(unsigned long); | |
1147 | unsigned long depc, old_epc; | |
1148 | unsigned int debug; | |
1149 | ||
70ae6126 | 1150 | printk(KERN_DEBUG "SDBBP EJTAG debug exception - not handled yet, just ignored!\n"); |
1da177e4 LT |
1151 | depc = read_c0_depc(); |
1152 | debug = read_c0_debug(); | |
70ae6126 | 1153 | printk(KERN_DEBUG "c0_depc = %0*lx, DEBUG = %08x\n", field, depc, debug); |
1da177e4 LT |
1154 | if (debug & 0x80000000) { |
1155 | /* | |
1156 | * In branch delay slot. | |
1157 | * We cheat a little bit here and use EPC to calculate the | |
1158 | * debug return address (DEPC). EPC is restored after the | |
1159 | * calculation. | |
1160 | */ | |
1161 | old_epc = regs->cp0_epc; | |
1162 | regs->cp0_epc = depc; | |
1163 | __compute_return_epc(regs); | |
1164 | depc = regs->cp0_epc; | |
1165 | regs->cp0_epc = old_epc; | |
1166 | } else | |
1167 | depc += 4; | |
1168 | write_c0_depc(depc); | |
1169 | ||
1170 | #if 0 | |
70ae6126 | 1171 | printk(KERN_DEBUG "\n\n----- Enable EJTAG single stepping ----\n\n"); |
1da177e4 LT |
1172 | write_c0_debug(debug | 0x100); |
1173 | #endif | |
1174 | } | |
1175 | ||
1176 | /* | |
1177 | * NMI exception handler. | |
1178 | */ | |
34412c72 | 1179 | NORET_TYPE void ATTRIB_NORET nmi_exception_handler(struct pt_regs *regs) |
1da177e4 | 1180 | { |
41c594ab | 1181 | bust_spinlocks(1); |
1da177e4 LT |
1182 | printk("NMI taken!!!!\n"); |
1183 | die("NMI", regs); | |
1da177e4 LT |
1184 | } |
1185 | ||
e01402b1 RB |
1186 | #define VECTORSPACING 0x100 /* for EI/VI mode */ |
1187 | ||
1188 | unsigned long ebase; | |
1da177e4 | 1189 | unsigned long exception_handlers[32]; |
e01402b1 | 1190 | unsigned long vi_handlers[64]; |
1da177e4 LT |
1191 | |
1192 | /* | |
1193 | * As a side effect of the way this is implemented we're limited | |
1194 | * to interrupt handlers in the address range from | |
1195 | * KSEG0 <= x < KSEG0 + 256mb on the Nevada. Oh well ... | |
1196 | */ | |
1197 | void *set_except_vector(int n, void *addr) | |
1198 | { | |
1199 | unsigned long handler = (unsigned long) addr; | |
1200 | unsigned long old_handler = exception_handlers[n]; | |
1201 | ||
1202 | exception_handlers[n] = handler; | |
1203 | if (n == 0 && cpu_has_divec) { | |
ec70f65e RB |
1204 | *(u32 *)(ebase + 0x200) = 0x08000000 | |
1205 | (0x03ffffff & (handler >> 2)); | |
e0cee3ee | 1206 | local_flush_icache_range(ebase + 0x200, ebase + 0x204); |
e01402b1 RB |
1207 | } |
1208 | return (void *)old_handler; | |
1209 | } | |
1210 | ||
6ba07e59 AN |
1211 | static asmlinkage void do_default_vi(void) |
1212 | { | |
1213 | show_regs(get_irq_regs()); | |
1214 | panic("Caught unexpected vectored interrupt."); | |
1215 | } | |
1216 | ||
ef300e42 | 1217 | static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs) |
e01402b1 RB |
1218 | { |
1219 | unsigned long handler; | |
1220 | unsigned long old_handler = vi_handlers[n]; | |
f6771dbb | 1221 | int srssets = current_cpu_data.srsets; |
e01402b1 RB |
1222 | u32 *w; |
1223 | unsigned char *b; | |
1224 | ||
1225 | if (!cpu_has_veic && !cpu_has_vint) | |
1226 | BUG(); | |
1227 | ||
1228 | if (addr == NULL) { | |
1229 | handler = (unsigned long) do_default_vi; | |
1230 | srs = 0; | |
41c594ab | 1231 | } else |
e01402b1 RB |
1232 | handler = (unsigned long) addr; |
1233 | vi_handlers[n] = (unsigned long) addr; | |
1234 | ||
1235 | b = (unsigned char *)(ebase + 0x200 + n*VECTORSPACING); | |
1236 | ||
f6771dbb | 1237 | if (srs >= srssets) |
e01402b1 RB |
1238 | panic("Shadow register set %d not supported", srs); |
1239 | ||
1240 | if (cpu_has_veic) { | |
1241 | if (board_bind_eic_interrupt) | |
49a89efb | 1242 | board_bind_eic_interrupt(n, srs); |
41c594ab | 1243 | } else if (cpu_has_vint) { |
e01402b1 | 1244 | /* SRSMap is only defined if shadow sets are implemented */ |
f6771dbb | 1245 | if (srssets > 1) |
49a89efb | 1246 | change_c0_srsmap(0xf << n*4, srs << n*4); |
e01402b1 RB |
1247 | } |
1248 | ||
1249 | if (srs == 0) { | |
1250 | /* | |
1251 | * If no shadow set is selected then use the default handler | |
1252 | * that does normal register saving and a standard interrupt exit | |
1253 | */ | |
1254 | ||
1255 | extern char except_vec_vi, except_vec_vi_lui; | |
1256 | extern char except_vec_vi_ori, except_vec_vi_end; | |
c65a5480 AN |
1257 | extern char rollback_except_vec_vi; |
1258 | char *vec_start = (cpu_wait == r4k_wait) ? | |
1259 | &rollback_except_vec_vi : &except_vec_vi; | |
41c594ab RB |
1260 | #ifdef CONFIG_MIPS_MT_SMTC |
1261 | /* | |
1262 | * We need to provide the SMTC vectored interrupt handler | |
1263 | * not only with the address of the handler, but with the | |
1264 | * Status.IM bit to be masked before going there. | |
1265 | */ | |
1266 | extern char except_vec_vi_mori; | |
c65a5480 | 1267 | const int mori_offset = &except_vec_vi_mori - vec_start; |
41c594ab | 1268 | #endif /* CONFIG_MIPS_MT_SMTC */ |
c65a5480 AN |
1269 | const int handler_len = &except_vec_vi_end - vec_start; |
1270 | const int lui_offset = &except_vec_vi_lui - vec_start; | |
1271 | const int ori_offset = &except_vec_vi_ori - vec_start; | |
e01402b1 RB |
1272 | |
1273 | if (handler_len > VECTORSPACING) { | |
1274 | /* | |
1275 | * Sigh... panicing won't help as the console | |
1276 | * is probably not configured :( | |
1277 | */ | |
49a89efb | 1278 | panic("VECTORSPACING too small"); |
e01402b1 RB |
1279 | } |
1280 | ||
c65a5480 | 1281 | memcpy(b, vec_start, handler_len); |
41c594ab | 1282 | #ifdef CONFIG_MIPS_MT_SMTC |
8e8a52ed RB |
1283 | BUG_ON(n > 7); /* Vector index %d exceeds SMTC maximum. */ |
1284 | ||
41c594ab RB |
1285 | w = (u32 *)(b + mori_offset); |
1286 | *w = (*w & 0xffff0000) | (0x100 << n); | |
1287 | #endif /* CONFIG_MIPS_MT_SMTC */ | |
e01402b1 RB |
1288 | w = (u32 *)(b + lui_offset); |
1289 | *w = (*w & 0xffff0000) | (((u32)handler >> 16) & 0xffff); | |
1290 | w = (u32 *)(b + ori_offset); | |
1291 | *w = (*w & 0xffff0000) | ((u32)handler & 0xffff); | |
e0cee3ee TB |
1292 | local_flush_icache_range((unsigned long)b, |
1293 | (unsigned long)(b+handler_len)); | |
e01402b1 RB |
1294 | } |
1295 | else { | |
1296 | /* | |
1297 | * In other cases jump directly to the interrupt handler | |
1298 | * | |
1299 | * It is the handlers responsibility to save registers if required | |
1300 | * (eg hi/lo) and return from the exception using "eret" | |
1301 | */ | |
1302 | w = (u32 *)b; | |
1303 | *w++ = 0x08000000 | (((u32)handler >> 2) & 0x03fffff); /* j handler */ | |
1304 | *w = 0; | |
e0cee3ee TB |
1305 | local_flush_icache_range((unsigned long)b, |
1306 | (unsigned long)(b+8)); | |
1da177e4 | 1307 | } |
e01402b1 | 1308 | |
1da177e4 LT |
1309 | return (void *)old_handler; |
1310 | } | |
1311 | ||
ef300e42 | 1312 | void *set_vi_handler(int n, vi_handler_t addr) |
e01402b1 | 1313 | { |
ff3eab2a | 1314 | return set_vi_srs_handler(n, addr, 0); |
e01402b1 | 1315 | } |
f41ae0b2 | 1316 | |
1da177e4 LT |
1317 | /* |
1318 | * This is used by native signal handling | |
1319 | */ | |
53dc8028 AN |
1320 | asmlinkage int (*save_fp_context)(struct sigcontext __user *sc); |
1321 | asmlinkage int (*restore_fp_context)(struct sigcontext __user *sc); | |
1da177e4 | 1322 | |
53dc8028 AN |
1323 | extern asmlinkage int _save_fp_context(struct sigcontext __user *sc); |
1324 | extern asmlinkage int _restore_fp_context(struct sigcontext __user *sc); | |
1da177e4 | 1325 | |
53dc8028 AN |
1326 | extern asmlinkage int fpu_emulator_save_context(struct sigcontext __user *sc); |
1327 | extern asmlinkage int fpu_emulator_restore_context(struct sigcontext __user *sc); | |
1da177e4 | 1328 | |
41c594ab | 1329 | #ifdef CONFIG_SMP |
53dc8028 | 1330 | static int smp_save_fp_context(struct sigcontext __user *sc) |
41c594ab | 1331 | { |
53dc8028 | 1332 | return raw_cpu_has_fpu |
41c594ab RB |
1333 | ? _save_fp_context(sc) |
1334 | : fpu_emulator_save_context(sc); | |
1335 | } | |
1336 | ||
53dc8028 | 1337 | static int smp_restore_fp_context(struct sigcontext __user *sc) |
41c594ab | 1338 | { |
53dc8028 | 1339 | return raw_cpu_has_fpu |
41c594ab RB |
1340 | ? _restore_fp_context(sc) |
1341 | : fpu_emulator_restore_context(sc); | |
1342 | } | |
1343 | #endif | |
1344 | ||
1da177e4 LT |
1345 | static inline void signal_init(void) |
1346 | { | |
41c594ab RB |
1347 | #ifdef CONFIG_SMP |
1348 | /* For now just do the cpu_has_fpu check when the functions are invoked */ | |
1349 | save_fp_context = smp_save_fp_context; | |
1350 | restore_fp_context = smp_restore_fp_context; | |
1351 | #else | |
1da177e4 LT |
1352 | if (cpu_has_fpu) { |
1353 | save_fp_context = _save_fp_context; | |
1354 | restore_fp_context = _restore_fp_context; | |
1355 | } else { | |
1356 | save_fp_context = fpu_emulator_save_context; | |
1357 | restore_fp_context = fpu_emulator_restore_context; | |
1358 | } | |
41c594ab | 1359 | #endif |
1da177e4 LT |
1360 | } |
1361 | ||
1362 | #ifdef CONFIG_MIPS32_COMPAT | |
1363 | ||
1364 | /* | |
1365 | * This is used by 32-bit signal stuff on the 64-bit kernel | |
1366 | */ | |
53dc8028 AN |
1367 | asmlinkage int (*save_fp_context32)(struct sigcontext32 __user *sc); |
1368 | asmlinkage int (*restore_fp_context32)(struct sigcontext32 __user *sc); | |
1da177e4 | 1369 | |
53dc8028 AN |
1370 | extern asmlinkage int _save_fp_context32(struct sigcontext32 __user *sc); |
1371 | extern asmlinkage int _restore_fp_context32(struct sigcontext32 __user *sc); | |
1da177e4 | 1372 | |
53dc8028 AN |
1373 | extern asmlinkage int fpu_emulator_save_context32(struct sigcontext32 __user *sc); |
1374 | extern asmlinkage int fpu_emulator_restore_context32(struct sigcontext32 __user *sc); | |
1da177e4 LT |
1375 | |
1376 | static inline void signal32_init(void) | |
1377 | { | |
1378 | if (cpu_has_fpu) { | |
1379 | save_fp_context32 = _save_fp_context32; | |
1380 | restore_fp_context32 = _restore_fp_context32; | |
1381 | } else { | |
1382 | save_fp_context32 = fpu_emulator_save_context32; | |
1383 | restore_fp_context32 = fpu_emulator_restore_context32; | |
1384 | } | |
1385 | } | |
1386 | #endif | |
1387 | ||
1388 | extern void cpu_cache_init(void); | |
1389 | extern void tlb_init(void); | |
1d40cfcd | 1390 | extern void flush_tlb_handlers(void); |
1da177e4 | 1391 | |
42f77542 RB |
1392 | /* |
1393 | * Timer interrupt | |
1394 | */ | |
1395 | int cp0_compare_irq; | |
1396 | ||
1397 | /* | |
1398 | * Performance counter IRQ or -1 if shared with timer | |
1399 | */ | |
1400 | int cp0_perfcount_irq; | |
1401 | EXPORT_SYMBOL_GPL(cp0_perfcount_irq); | |
1402 | ||
bdc94eb4 CD |
1403 | static int __cpuinitdata noulri; |
1404 | ||
1405 | static int __init ulri_disable(char *s) | |
1406 | { | |
1407 | pr_info("Disabling ulri\n"); | |
1408 | noulri = 1; | |
1409 | ||
1410 | return 1; | |
1411 | } | |
1412 | __setup("noulri", ulri_disable); | |
1413 | ||
234fcd14 | 1414 | void __cpuinit per_cpu_trap_init(void) |
1da177e4 LT |
1415 | { |
1416 | unsigned int cpu = smp_processor_id(); | |
1417 | unsigned int status_set = ST0_CU0; | |
41c594ab RB |
1418 | #ifdef CONFIG_MIPS_MT_SMTC |
1419 | int secondaryTC = 0; | |
1420 | int bootTC = (cpu == 0); | |
1421 | ||
1422 | /* | |
1423 | * Only do per_cpu_trap_init() for first TC of Each VPE. | |
1424 | * Note that this hack assumes that the SMTC init code | |
1425 | * assigns TCs consecutively and in ascending order. | |
1426 | */ | |
1427 | ||
1428 | if (((read_c0_tcbind() & TCBIND_CURTC) != 0) && | |
1429 | ((read_c0_tcbind() & TCBIND_CURVPE) == cpu_data[cpu - 1].vpe_id)) | |
1430 | secondaryTC = 1; | |
1431 | #endif /* CONFIG_MIPS_MT_SMTC */ | |
1da177e4 LT |
1432 | |
1433 | /* | |
1434 | * Disable coprocessors and select 32-bit or 64-bit addressing | |
1435 | * and the 16/32 or 32/32 FPR register model. Reset the BEV | |
1436 | * flag that some firmware may have left set and the TS bit (for | |
1437 | * IP27). Set XX for ISA IV code to work. | |
1438 | */ | |
875d43e7 | 1439 | #ifdef CONFIG_64BIT |
1da177e4 LT |
1440 | status_set |= ST0_FR|ST0_KX|ST0_SX|ST0_UX; |
1441 | #endif | |
1442 | if (current_cpu_data.isa_level == MIPS_CPU_ISA_IV) | |
1443 | status_set |= ST0_XX; | |
bbaf238b CD |
1444 | if (cpu_has_dsp) |
1445 | status_set |= ST0_MX; | |
1446 | ||
b38c7399 | 1447 | change_c0_status(ST0_CU|ST0_MX|ST0_RE|ST0_FR|ST0_BEV|ST0_TS|ST0_KX|ST0_SX|ST0_UX, |
1da177e4 LT |
1448 | status_set); |
1449 | ||
a3692020 RB |
1450 | if (cpu_has_mips_r2) { |
1451 | unsigned int enable = 0x0000000f; | |
1452 | ||
bdc94eb4 | 1453 | if (!noulri && cpu_has_userlocal) |
a3692020 RB |
1454 | enable |= (1 << 29); |
1455 | ||
1456 | write_c0_hwrena(enable); | |
1457 | } | |
e01402b1 | 1458 | |
41c594ab RB |
1459 | #ifdef CONFIG_MIPS_MT_SMTC |
1460 | if (!secondaryTC) { | |
1461 | #endif /* CONFIG_MIPS_MT_SMTC */ | |
1462 | ||
e01402b1 | 1463 | if (cpu_has_veic || cpu_has_vint) { |
49a89efb | 1464 | write_c0_ebase(ebase); |
e01402b1 | 1465 | /* Setting vector spacing enables EI/VI mode */ |
49a89efb | 1466 | change_c0_intctl(0x3e0, VECTORSPACING); |
e01402b1 | 1467 | } |
d03d0a57 RB |
1468 | if (cpu_has_divec) { |
1469 | if (cpu_has_mipsmt) { | |
1470 | unsigned int vpflags = dvpe(); | |
1471 | set_c0_cause(CAUSEF_IV); | |
1472 | evpe(vpflags); | |
1473 | } else | |
1474 | set_c0_cause(CAUSEF_IV); | |
1475 | } | |
3b1d4ed5 RB |
1476 | |
1477 | /* | |
1478 | * Before R2 both interrupt numbers were fixed to 7, so on R2 only: | |
1479 | * | |
1480 | * o read IntCtl.IPTI to determine the timer interrupt | |
1481 | * o read IntCtl.IPPCI to determine the performance counter interrupt | |
1482 | */ | |
1483 | if (cpu_has_mips_r2) { | |
49a89efb RB |
1484 | cp0_compare_irq = (read_c0_intctl() >> 29) & 7; |
1485 | cp0_perfcount_irq = (read_c0_intctl() >> 26) & 7; | |
c3e838a2 | 1486 | if (cp0_perfcount_irq == cp0_compare_irq) |
3b1d4ed5 | 1487 | cp0_perfcount_irq = -1; |
c3e838a2 CD |
1488 | } else { |
1489 | cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ; | |
1490 | cp0_perfcount_irq = -1; | |
3b1d4ed5 RB |
1491 | } |
1492 | ||
41c594ab RB |
1493 | #ifdef CONFIG_MIPS_MT_SMTC |
1494 | } | |
1495 | #endif /* CONFIG_MIPS_MT_SMTC */ | |
1da177e4 LT |
1496 | |
1497 | cpu_data[cpu].asid_cache = ASID_FIRST_VERSION; | |
1498 | TLBMISS_HANDLER_SETUP(); | |
1499 | ||
1500 | atomic_inc(&init_mm.mm_count); | |
1501 | current->active_mm = &init_mm; | |
1502 | BUG_ON(current->mm); | |
1503 | enter_lazy_tlb(&init_mm, current); | |
1504 | ||
41c594ab RB |
1505 | #ifdef CONFIG_MIPS_MT_SMTC |
1506 | if (bootTC) { | |
1507 | #endif /* CONFIG_MIPS_MT_SMTC */ | |
1508 | cpu_cache_init(); | |
1509 | tlb_init(); | |
1510 | #ifdef CONFIG_MIPS_MT_SMTC | |
6a05888d RB |
1511 | } else if (!secondaryTC) { |
1512 | /* | |
1513 | * First TC in non-boot VPE must do subset of tlb_init() | |
1514 | * for MMU countrol registers. | |
1515 | */ | |
1516 | write_c0_pagemask(PM_DEFAULT_MASK); | |
1517 | write_c0_wired(0); | |
41c594ab RB |
1518 | } |
1519 | #endif /* CONFIG_MIPS_MT_SMTC */ | |
1da177e4 LT |
1520 | } |
1521 | ||
e01402b1 | 1522 | /* Install CPU exception handler */ |
49a89efb | 1523 | void __init set_handler(unsigned long offset, void *addr, unsigned long size) |
e01402b1 RB |
1524 | { |
1525 | memcpy((void *)(ebase + offset), addr, size); | |
e0cee3ee | 1526 | local_flush_icache_range(ebase + offset, ebase + offset + size); |
e01402b1 RB |
1527 | } |
1528 | ||
234fcd14 | 1529 | static char panic_null_cerr[] __cpuinitdata = |
641e97f3 RB |
1530 | "Trying to set NULL cache error exception handler"; |
1531 | ||
e01402b1 | 1532 | /* Install uncached CPU exception handler */ |
234fcd14 RB |
1533 | void __cpuinit set_uncached_handler(unsigned long offset, void *addr, |
1534 | unsigned long size) | |
e01402b1 RB |
1535 | { |
1536 | #ifdef CONFIG_32BIT | |
1537 | unsigned long uncached_ebase = KSEG1ADDR(ebase); | |
1538 | #endif | |
1539 | #ifdef CONFIG_64BIT | |
1540 | unsigned long uncached_ebase = TO_UNCAC(ebase); | |
1541 | #endif | |
1542 | ||
641e97f3 RB |
1543 | if (!addr) |
1544 | panic(panic_null_cerr); | |
1545 | ||
e01402b1 RB |
1546 | memcpy((void *)(uncached_ebase + offset), addr, size); |
1547 | } | |
1548 | ||
5b10496b AN |
1549 | static int __initdata rdhwr_noopt; |
1550 | static int __init set_rdhwr_noopt(char *str) | |
1551 | { | |
1552 | rdhwr_noopt = 1; | |
1553 | return 1; | |
1554 | } | |
1555 | ||
1556 | __setup("rdhwr_noopt", set_rdhwr_noopt); | |
1557 | ||
1da177e4 LT |
1558 | void __init trap_init(void) |
1559 | { | |
1560 | extern char except_vec3_generic, except_vec3_r4000; | |
1da177e4 LT |
1561 | extern char except_vec4; |
1562 | unsigned long i; | |
c65a5480 AN |
1563 | int rollback; |
1564 | ||
1565 | check_wait(); | |
1566 | rollback = (cpu_wait == r4k_wait); | |
1da177e4 | 1567 | |
88547001 JW |
1568 | #if defined(CONFIG_KGDB) |
1569 | if (kgdb_early_setup) | |
1570 | return; /* Already done */ | |
1571 | #endif | |
1572 | ||
e01402b1 | 1573 | if (cpu_has_veic || cpu_has_vint) |
49a89efb | 1574 | ebase = (unsigned long) alloc_bootmem_low_pages(0x200 + VECTORSPACING*64); |
e01402b1 RB |
1575 | else |
1576 | ebase = CAC_BASE; | |
1577 | ||
1da177e4 LT |
1578 | per_cpu_trap_init(); |
1579 | ||
1580 | /* | |
1581 | * Copy the generic exception handlers to their final destination. | |
1582 | * This will be overriden later as suitable for a particular | |
1583 | * configuration. | |
1584 | */ | |
e01402b1 | 1585 | set_handler(0x180, &except_vec3_generic, 0x80); |
1da177e4 LT |
1586 | |
1587 | /* | |
1588 | * Setup default vectors | |
1589 | */ | |
1590 | for (i = 0; i <= 31; i++) | |
1591 | set_except_vector(i, handle_reserved); | |
1592 | ||
1593 | /* | |
1594 | * Copy the EJTAG debug exception vector handler code to it's final | |
1595 | * destination. | |
1596 | */ | |
e01402b1 | 1597 | if (cpu_has_ejtag && board_ejtag_handler_setup) |
49a89efb | 1598 | board_ejtag_handler_setup(); |
1da177e4 LT |
1599 | |
1600 | /* | |
1601 | * Only some CPUs have the watch exceptions. | |
1602 | */ | |
1603 | if (cpu_has_watch) | |
1604 | set_except_vector(23, handle_watch); | |
1605 | ||
1606 | /* | |
e01402b1 | 1607 | * Initialise interrupt handlers |
1da177e4 | 1608 | */ |
e01402b1 RB |
1609 | if (cpu_has_veic || cpu_has_vint) { |
1610 | int nvec = cpu_has_veic ? 64 : 8; | |
1611 | for (i = 0; i < nvec; i++) | |
ff3eab2a | 1612 | set_vi_handler(i, NULL); |
e01402b1 RB |
1613 | } |
1614 | else if (cpu_has_divec) | |
1615 | set_handler(0x200, &except_vec4, 0x8); | |
1da177e4 LT |
1616 | |
1617 | /* | |
1618 | * Some CPUs can enable/disable for cache parity detection, but does | |
1619 | * it different ways. | |
1620 | */ | |
1621 | parity_protection_init(); | |
1622 | ||
1623 | /* | |
1624 | * The Data Bus Errors / Instruction Bus Errors are signaled | |
1625 | * by external hardware. Therefore these two exceptions | |
1626 | * may have board specific handlers. | |
1627 | */ | |
1628 | if (board_be_init) | |
1629 | board_be_init(); | |
1630 | ||
c65a5480 | 1631 | set_except_vector(0, rollback ? rollback_handle_int : handle_int); |
1da177e4 LT |
1632 | set_except_vector(1, handle_tlbm); |
1633 | set_except_vector(2, handle_tlbl); | |
1634 | set_except_vector(3, handle_tlbs); | |
1635 | ||
1636 | set_except_vector(4, handle_adel); | |
1637 | set_except_vector(5, handle_ades); | |
1638 | ||
1639 | set_except_vector(6, handle_ibe); | |
1640 | set_except_vector(7, handle_dbe); | |
1641 | ||
1642 | set_except_vector(8, handle_sys); | |
1643 | set_except_vector(9, handle_bp); | |
5b10496b AN |
1644 | set_except_vector(10, rdhwr_noopt ? handle_ri : |
1645 | (cpu_has_vtag_icache ? | |
1646 | handle_ri_rdhwr_vivt : handle_ri_rdhwr)); | |
1da177e4 LT |
1647 | set_except_vector(11, handle_cpu); |
1648 | set_except_vector(12, handle_ov); | |
1649 | set_except_vector(13, handle_tr); | |
1da177e4 | 1650 | |
10cc3529 RB |
1651 | if (current_cpu_type() == CPU_R6000 || |
1652 | current_cpu_type() == CPU_R6000A) { | |
1da177e4 LT |
1653 | /* |
1654 | * The R6000 is the only R-series CPU that features a machine | |
1655 | * check exception (similar to the R4000 cache error) and | |
1656 | * unaligned ldc1/sdc1 exception. The handlers have not been | |
1657 | * written yet. Well, anyway there is no R6000 machine on the | |
1658 | * current list of targets for Linux/MIPS. | |
1659 | * (Duh, crap, there is someone with a triple R6k machine) | |
1660 | */ | |
1661 | //set_except_vector(14, handle_mc); | |
1662 | //set_except_vector(15, handle_ndc); | |
1663 | } | |
1664 | ||
e01402b1 RB |
1665 | |
1666 | if (board_nmi_handler_setup) | |
1667 | board_nmi_handler_setup(); | |
1668 | ||
e50c0a8f RB |
1669 | if (cpu_has_fpu && !cpu_has_nofpuex) |
1670 | set_except_vector(15, handle_fpe); | |
1671 | ||
1672 | set_except_vector(22, handle_mdmx); | |
1673 | ||
1674 | if (cpu_has_mcheck) | |
1675 | set_except_vector(24, handle_mcheck); | |
1676 | ||
340ee4b9 RB |
1677 | if (cpu_has_mipsmt) |
1678 | set_except_vector(25, handle_mt); | |
1679 | ||
acaec427 | 1680 | set_except_vector(26, handle_dsp); |
e50c0a8f RB |
1681 | |
1682 | if (cpu_has_vce) | |
1683 | /* Special exception: R4[04]00 uses also the divec space. */ | |
1684 | memcpy((void *)(CAC_BASE + 0x180), &except_vec3_r4000, 0x100); | |
1685 | else if (cpu_has_4kex) | |
1686 | memcpy((void *)(CAC_BASE + 0x180), &except_vec3_generic, 0x80); | |
1687 | else | |
1688 | memcpy((void *)(CAC_BASE + 0x080), &except_vec3_generic, 0x80); | |
1689 | ||
1da177e4 LT |
1690 | signal_init(); |
1691 | #ifdef CONFIG_MIPS32_COMPAT | |
1692 | signal32_init(); | |
1693 | #endif | |
1694 | ||
e0cee3ee | 1695 | local_flush_icache_range(ebase, ebase + 0x400); |
1d40cfcd | 1696 | flush_tlb_handlers(); |
0510617b TB |
1697 | |
1698 | sort_extable(__start___dbe_table, __stop___dbe_table); | |
1da177e4 | 1699 | } |