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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public | |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
36ccf1c0 | 6 | * Copyright (C) 1994 - 1999, 2000, 01, 06 Ralf Baechle |
1da177e4 LT |
7 | * Copyright (C) 1995, 1996 Paul M. Antoine |
8 | * Copyright (C) 1998 Ulf Carlsson | |
9 | * Copyright (C) 1999 Silicon Graphics, Inc. | |
10 | * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com | |
60b0d655 | 11 | * Copyright (C) 2002, 2003, 2004, 2005, 2007 Maciej W. Rozycki |
2a0b24f5 | 12 | * Copyright (C) 2000, 2001, 2012 MIPS Technologies, Inc. All rights reserved. |
b08a9c95 | 13 | * Copyright (C) 2014, Imagination Technologies Ltd. |
1da177e4 | 14 | */ |
8e8a52ed | 15 | #include <linux/bug.h> |
60b0d655 | 16 | #include <linux/compiler.h> |
c3fc5cd5 | 17 | #include <linux/context_tracking.h> |
ae4ce454 | 18 | #include <linux/cpu_pm.h> |
7aa1c8f4 | 19 | #include <linux/kexec.h> |
1da177e4 | 20 | #include <linux/init.h> |
8742cd23 | 21 | #include <linux/kernel.h> |
f9ded569 | 22 | #include <linux/module.h> |
1da177e4 | 23 | #include <linux/mm.h> |
1da177e4 LT |
24 | #include <linux/sched.h> |
25 | #include <linux/smp.h> | |
1da177e4 LT |
26 | #include <linux/spinlock.h> |
27 | #include <linux/kallsyms.h> | |
e01402b1 | 28 | #include <linux/bootmem.h> |
d4fd1989 | 29 | #include <linux/interrupt.h> |
39b8d525 | 30 | #include <linux/ptrace.h> |
88547001 JW |
31 | #include <linux/kgdb.h> |
32 | #include <linux/kdebug.h> | |
c1bf207d | 33 | #include <linux/kprobes.h> |
69f3a7de | 34 | #include <linux/notifier.h> |
5dd11d5d | 35 | #include <linux/kdb.h> |
ca4d3e67 | 36 | #include <linux/irq.h> |
7f788d2d | 37 | #include <linux/perf_event.h> |
1da177e4 LT |
38 | |
39 | #include <asm/bootinfo.h> | |
40 | #include <asm/branch.h> | |
41 | #include <asm/break.h> | |
69f3a7de | 42 | #include <asm/cop2.h> |
1da177e4 | 43 | #include <asm/cpu.h> |
69f24d17 | 44 | #include <asm/cpu-type.h> |
e50c0a8f | 45 | #include <asm/dsp.h> |
1da177e4 | 46 | #include <asm/fpu.h> |
ba3049ed | 47 | #include <asm/fpu_emulator.h> |
bdc92d74 | 48 | #include <asm/idle.h> |
340ee4b9 RB |
49 | #include <asm/mipsregs.h> |
50 | #include <asm/mipsmtregs.h> | |
1da177e4 | 51 | #include <asm/module.h> |
1db1af84 | 52 | #include <asm/msa.h> |
1da177e4 LT |
53 | #include <asm/pgtable.h> |
54 | #include <asm/ptrace.h> | |
55 | #include <asm/sections.h> | |
1da177e4 LT |
56 | #include <asm/tlbdebug.h> |
57 | #include <asm/traps.h> | |
58 | #include <asm/uaccess.h> | |
b67b2b70 | 59 | #include <asm/watch.h> |
1da177e4 | 60 | #include <asm/mmu_context.h> |
1da177e4 | 61 | #include <asm/types.h> |
1df0f0ff | 62 | #include <asm/stacktrace.h> |
92bbe1b9 | 63 | #include <asm/uasm.h> |
1da177e4 | 64 | |
c65a5480 | 65 | extern void check_wait(void); |
c65a5480 | 66 | extern asmlinkage void rollback_handle_int(void); |
e4ac58af | 67 | extern asmlinkage void handle_int(void); |
86a1708a RB |
68 | extern u32 handle_tlbl[]; |
69 | extern u32 handle_tlbs[]; | |
70 | extern u32 handle_tlbm[]; | |
1da177e4 LT |
71 | extern asmlinkage void handle_adel(void); |
72 | extern asmlinkage void handle_ades(void); | |
73 | extern asmlinkage void handle_ibe(void); | |
74 | extern asmlinkage void handle_dbe(void); | |
75 | extern asmlinkage void handle_sys(void); | |
76 | extern asmlinkage void handle_bp(void); | |
77 | extern asmlinkage void handle_ri(void); | |
5b10496b AN |
78 | extern asmlinkage void handle_ri_rdhwr_vivt(void); |
79 | extern asmlinkage void handle_ri_rdhwr(void); | |
1da177e4 LT |
80 | extern asmlinkage void handle_cpu(void); |
81 | extern asmlinkage void handle_ov(void); | |
82 | extern asmlinkage void handle_tr(void); | |
2bcb3fbc | 83 | extern asmlinkage void handle_msa_fpe(void); |
1da177e4 | 84 | extern asmlinkage void handle_fpe(void); |
75b5b5e0 | 85 | extern asmlinkage void handle_ftlb(void); |
1db1af84 | 86 | extern asmlinkage void handle_msa(void); |
1da177e4 LT |
87 | extern asmlinkage void handle_mdmx(void); |
88 | extern asmlinkage void handle_watch(void); | |
340ee4b9 | 89 | extern asmlinkage void handle_mt(void); |
e50c0a8f | 90 | extern asmlinkage void handle_dsp(void); |
1da177e4 LT |
91 | extern asmlinkage void handle_mcheck(void); |
92 | extern asmlinkage void handle_reserved(void); | |
5890f70f | 93 | extern void tlb_do_page_fault_0(void); |
1da177e4 | 94 | |
1da177e4 LT |
95 | void (*board_be_init)(void); |
96 | int (*board_be_handler)(struct pt_regs *regs, int is_fixup); | |
e01402b1 RB |
97 | void (*board_nmi_handler_setup)(void); |
98 | void (*board_ejtag_handler_setup)(void); | |
99 | void (*board_bind_eic_interrupt)(int irq, int regset); | |
6fb97eff | 100 | void (*board_ebase_setup)(void); |
078a55fc | 101 | void(*board_cache_error_setup)(void); |
1da177e4 | 102 | |
4d157d5e | 103 | static void show_raw_backtrace(unsigned long reg29) |
e889d78f | 104 | { |
39b8d525 | 105 | unsigned long *sp = (unsigned long *)(reg29 & ~3); |
e889d78f AN |
106 | unsigned long addr; |
107 | ||
108 | printk("Call Trace:"); | |
109 | #ifdef CONFIG_KALLSYMS | |
110 | printk("\n"); | |
111 | #endif | |
10220c88 TB |
112 | while (!kstack_end(sp)) { |
113 | unsigned long __user *p = | |
114 | (unsigned long __user *)(unsigned long)sp++; | |
115 | if (__get_user(addr, p)) { | |
116 | printk(" (Bad stack address)"); | |
117 | break; | |
39b8d525 | 118 | } |
10220c88 TB |
119 | if (__kernel_text_address(addr)) |
120 | print_ip_sym(addr); | |
e889d78f | 121 | } |
10220c88 | 122 | printk("\n"); |
e889d78f AN |
123 | } |
124 | ||
f66686f7 | 125 | #ifdef CONFIG_KALLSYMS |
1df0f0ff | 126 | int raw_show_trace; |
f66686f7 AN |
127 | static int __init set_raw_show_trace(char *str) |
128 | { | |
129 | raw_show_trace = 1; | |
130 | return 1; | |
131 | } | |
132 | __setup("raw_show_trace", set_raw_show_trace); | |
1df0f0ff | 133 | #endif |
4d157d5e | 134 | |
eae23f2c | 135 | static void show_backtrace(struct task_struct *task, const struct pt_regs *regs) |
f66686f7 | 136 | { |
4d157d5e FBH |
137 | unsigned long sp = regs->regs[29]; |
138 | unsigned long ra = regs->regs[31]; | |
f66686f7 | 139 | unsigned long pc = regs->cp0_epc; |
f66686f7 | 140 | |
e909be82 VW |
141 | if (!task) |
142 | task = current; | |
143 | ||
f66686f7 | 144 | if (raw_show_trace || !__kernel_text_address(pc)) { |
87151ae3 | 145 | show_raw_backtrace(sp); |
f66686f7 AN |
146 | return; |
147 | } | |
148 | printk("Call Trace:\n"); | |
4d157d5e | 149 | do { |
87151ae3 | 150 | print_ip_sym(pc); |
1924600c | 151 | pc = unwind_stack(task, &sp, pc, &ra); |
4d157d5e | 152 | } while (pc); |
f66686f7 AN |
153 | printk("\n"); |
154 | } | |
f66686f7 | 155 | |
1da177e4 LT |
156 | /* |
157 | * This routine abuses get_user()/put_user() to reference pointers | |
158 | * with at least a bit of error checking ... | |
159 | */ | |
eae23f2c RB |
160 | static void show_stacktrace(struct task_struct *task, |
161 | const struct pt_regs *regs) | |
1da177e4 LT |
162 | { |
163 | const int field = 2 * sizeof(unsigned long); | |
164 | long stackdata; | |
165 | int i; | |
5e0373b8 | 166 | unsigned long __user *sp = (unsigned long __user *)regs->regs[29]; |
1da177e4 LT |
167 | |
168 | printk("Stack :"); | |
169 | i = 0; | |
170 | while ((unsigned long) sp & (PAGE_SIZE - 1)) { | |
171 | if (i && ((i % (64 / field)) == 0)) | |
70342287 | 172 | printk("\n "); |
1da177e4 LT |
173 | if (i > 39) { |
174 | printk(" ..."); | |
175 | break; | |
176 | } | |
177 | ||
178 | if (__get_user(stackdata, sp++)) { | |
179 | printk(" (Bad stack address)"); | |
180 | break; | |
181 | } | |
182 | ||
183 | printk(" %0*lx", field, stackdata); | |
184 | i++; | |
185 | } | |
186 | printk("\n"); | |
87151ae3 | 187 | show_backtrace(task, regs); |
f66686f7 AN |
188 | } |
189 | ||
f66686f7 AN |
190 | void show_stack(struct task_struct *task, unsigned long *sp) |
191 | { | |
192 | struct pt_regs regs; | |
193 | if (sp) { | |
194 | regs.regs[29] = (unsigned long)sp; | |
195 | regs.regs[31] = 0; | |
196 | regs.cp0_epc = 0; | |
197 | } else { | |
198 | if (task && task != current) { | |
199 | regs.regs[29] = task->thread.reg29; | |
200 | regs.regs[31] = 0; | |
201 | regs.cp0_epc = task->thread.reg31; | |
5dd11d5d JW |
202 | #ifdef CONFIG_KGDB_KDB |
203 | } else if (atomic_read(&kgdb_active) != -1 && | |
204 | kdb_current_regs) { | |
205 | memcpy(®s, kdb_current_regs, sizeof(regs)); | |
206 | #endif /* CONFIG_KGDB_KDB */ | |
f66686f7 AN |
207 | } else { |
208 | prepare_frametrace(®s); | |
209 | } | |
210 | } | |
211 | show_stacktrace(task, ®s); | |
1da177e4 LT |
212 | } |
213 | ||
e1bb8289 | 214 | static void show_code(unsigned int __user *pc) |
1da177e4 LT |
215 | { |
216 | long i; | |
39b8d525 | 217 | unsigned short __user *pc16 = NULL; |
1da177e4 LT |
218 | |
219 | printk("\nCode:"); | |
220 | ||
39b8d525 RB |
221 | if ((unsigned long)pc & 1) |
222 | pc16 = (unsigned short __user *)((unsigned long)pc & ~1); | |
1da177e4 LT |
223 | for(i = -3 ; i < 6 ; i++) { |
224 | unsigned int insn; | |
39b8d525 | 225 | if (pc16 ? __get_user(insn, pc16 + i) : __get_user(insn, pc + i)) { |
1da177e4 LT |
226 | printk(" (Bad address in epc)\n"); |
227 | break; | |
228 | } | |
39b8d525 | 229 | printk("%c%0*x%c", (i?' ':'<'), pc16 ? 4 : 8, insn, (i?' ':'>')); |
1da177e4 LT |
230 | } |
231 | } | |
232 | ||
eae23f2c | 233 | static void __show_regs(const struct pt_regs *regs) |
1da177e4 LT |
234 | { |
235 | const int field = 2 * sizeof(unsigned long); | |
236 | unsigned int cause = regs->cp0_cause; | |
237 | int i; | |
238 | ||
a43cb95d | 239 | show_regs_print_info(KERN_DEFAULT); |
1da177e4 LT |
240 | |
241 | /* | |
242 | * Saved main processor registers | |
243 | */ | |
244 | for (i = 0; i < 32; ) { | |
245 | if ((i % 4) == 0) | |
246 | printk("$%2d :", i); | |
247 | if (i == 0) | |
248 | printk(" %0*lx", field, 0UL); | |
249 | else if (i == 26 || i == 27) | |
250 | printk(" %*s", field, ""); | |
251 | else | |
252 | printk(" %0*lx", field, regs->regs[i]); | |
253 | ||
254 | i++; | |
255 | if ((i % 4) == 0) | |
256 | printk("\n"); | |
257 | } | |
258 | ||
9693a853 FBH |
259 | #ifdef CONFIG_CPU_HAS_SMARTMIPS |
260 | printk("Acx : %0*lx\n", field, regs->acx); | |
261 | #endif | |
1da177e4 LT |
262 | printk("Hi : %0*lx\n", field, regs->hi); |
263 | printk("Lo : %0*lx\n", field, regs->lo); | |
264 | ||
265 | /* | |
266 | * Saved cp0 registers | |
267 | */ | |
b012cffe RB |
268 | printk("epc : %0*lx %pS\n", field, regs->cp0_epc, |
269 | (void *) regs->cp0_epc); | |
1da177e4 | 270 | printk(" %s\n", print_tainted()); |
b012cffe RB |
271 | printk("ra : %0*lx %pS\n", field, regs->regs[31], |
272 | (void *) regs->regs[31]); | |
1da177e4 | 273 | |
70342287 | 274 | printk("Status: %08x ", (uint32_t) regs->cp0_status); |
1da177e4 | 275 | |
1990e542 | 276 | if (cpu_has_3kex) { |
3b2396d9 MR |
277 | if (regs->cp0_status & ST0_KUO) |
278 | printk("KUo "); | |
279 | if (regs->cp0_status & ST0_IEO) | |
280 | printk("IEo "); | |
281 | if (regs->cp0_status & ST0_KUP) | |
282 | printk("KUp "); | |
283 | if (regs->cp0_status & ST0_IEP) | |
284 | printk("IEp "); | |
285 | if (regs->cp0_status & ST0_KUC) | |
286 | printk("KUc "); | |
287 | if (regs->cp0_status & ST0_IEC) | |
288 | printk("IEc "); | |
1990e542 | 289 | } else if (cpu_has_4kex) { |
3b2396d9 MR |
290 | if (regs->cp0_status & ST0_KX) |
291 | printk("KX "); | |
292 | if (regs->cp0_status & ST0_SX) | |
293 | printk("SX "); | |
294 | if (regs->cp0_status & ST0_UX) | |
295 | printk("UX "); | |
296 | switch (regs->cp0_status & ST0_KSU) { | |
297 | case KSU_USER: | |
298 | printk("USER "); | |
299 | break; | |
300 | case KSU_SUPERVISOR: | |
301 | printk("SUPERVISOR "); | |
302 | break; | |
303 | case KSU_KERNEL: | |
304 | printk("KERNEL "); | |
305 | break; | |
306 | default: | |
307 | printk("BAD_MODE "); | |
308 | break; | |
309 | } | |
310 | if (regs->cp0_status & ST0_ERL) | |
311 | printk("ERL "); | |
312 | if (regs->cp0_status & ST0_EXL) | |
313 | printk("EXL "); | |
314 | if (regs->cp0_status & ST0_IE) | |
315 | printk("IE "); | |
1da177e4 | 316 | } |
1da177e4 LT |
317 | printk("\n"); |
318 | ||
319 | printk("Cause : %08x\n", cause); | |
320 | ||
321 | cause = (cause & CAUSEF_EXCCODE) >> CAUSEB_EXCCODE; | |
322 | if (1 <= cause && cause <= 5) | |
323 | printk("BadVA : %0*lx\n", field, regs->cp0_badvaddr); | |
324 | ||
9966db25 RB |
325 | printk("PrId : %08x (%s)\n", read_c0_prid(), |
326 | cpu_name_string()); | |
1da177e4 LT |
327 | } |
328 | ||
eae23f2c RB |
329 | /* |
330 | * FIXME: really the generic show_regs should take a const pointer argument. | |
331 | */ | |
332 | void show_regs(struct pt_regs *regs) | |
333 | { | |
334 | __show_regs((struct pt_regs *)regs); | |
335 | } | |
336 | ||
c1bf207d | 337 | void show_registers(struct pt_regs *regs) |
1da177e4 | 338 | { |
39b8d525 | 339 | const int field = 2 * sizeof(unsigned long); |
83e4da1e | 340 | mm_segment_t old_fs = get_fs(); |
39b8d525 | 341 | |
eae23f2c | 342 | __show_regs(regs); |
1da177e4 | 343 | print_modules(); |
39b8d525 RB |
344 | printk("Process %s (pid: %d, threadinfo=%p, task=%p, tls=%0*lx)\n", |
345 | current->comm, current->pid, current_thread_info(), current, | |
346 | field, current_thread_info()->tp_value); | |
347 | if (cpu_has_userlocal) { | |
348 | unsigned long tls; | |
349 | ||
350 | tls = read_c0_userlocal(); | |
351 | if (tls != current_thread_info()->tp_value) | |
352 | printk("*HwTLS: %0*lx\n", field, tls); | |
353 | } | |
354 | ||
83e4da1e LY |
355 | if (!user_mode(regs)) |
356 | /* Necessary for getting the correct stack content */ | |
357 | set_fs(KERNEL_DS); | |
f66686f7 | 358 | show_stacktrace(current, regs); |
e1bb8289 | 359 | show_code((unsigned int __user *) regs->cp0_epc); |
1da177e4 | 360 | printk("\n"); |
83e4da1e | 361 | set_fs(old_fs); |
1da177e4 LT |
362 | } |
363 | ||
70dc6f04 DD |
364 | static int regs_to_trapnr(struct pt_regs *regs) |
365 | { | |
366 | return (regs->cp0_cause >> 2) & 0x1f; | |
367 | } | |
368 | ||
4d85f6af | 369 | static DEFINE_RAW_SPINLOCK(die_lock); |
1da177e4 | 370 | |
70dc6f04 | 371 | void __noreturn die(const char *str, struct pt_regs *regs) |
1da177e4 LT |
372 | { |
373 | static int die_counter; | |
ce384d83 | 374 | int sig = SIGSEGV; |
1da177e4 | 375 | |
8742cd23 NL |
376 | oops_enter(); |
377 | ||
dc73e4c1 RB |
378 | if (notify_die(DIE_OOPS, str, regs, 0, regs_to_trapnr(regs), |
379 | SIGSEGV) == NOTIFY_STOP) | |
10423c91 | 380 | sig = 0; |
5dd11d5d | 381 | |
1da177e4 | 382 | console_verbose(); |
4d85f6af | 383 | raw_spin_lock_irq(&die_lock); |
41c594ab | 384 | bust_spinlocks(1); |
ce384d83 | 385 | |
178086c8 | 386 | printk("%s[#%d]:\n", str, ++die_counter); |
1da177e4 | 387 | show_registers(regs); |
373d4d09 | 388 | add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE); |
4d85f6af | 389 | raw_spin_unlock_irq(&die_lock); |
d4fd1989 | 390 | |
8742cd23 NL |
391 | oops_exit(); |
392 | ||
d4fd1989 MB |
393 | if (in_interrupt()) |
394 | panic("Fatal exception in interrupt"); | |
395 | ||
396 | if (panic_on_oops) { | |
ab75dc02 | 397 | printk(KERN_EMERG "Fatal exception: panic in 5 seconds"); |
d4fd1989 MB |
398 | ssleep(5); |
399 | panic("Fatal exception"); | |
400 | } | |
401 | ||
7aa1c8f4 RB |
402 | if (regs && kexec_should_crash(current)) |
403 | crash_kexec(regs); | |
404 | ||
ce384d83 | 405 | do_exit(sig); |
1da177e4 LT |
406 | } |
407 | ||
0510617b TB |
408 | extern struct exception_table_entry __start___dbe_table[]; |
409 | extern struct exception_table_entry __stop___dbe_table[]; | |
1da177e4 | 410 | |
b6dcec9b RB |
411 | __asm__( |
412 | " .section __dbe_table, \"a\"\n" | |
413 | " .previous \n"); | |
1da177e4 LT |
414 | |
415 | /* Given an address, look for it in the exception tables. */ | |
416 | static const struct exception_table_entry *search_dbe_tables(unsigned long addr) | |
417 | { | |
418 | const struct exception_table_entry *e; | |
419 | ||
420 | e = search_extable(__start___dbe_table, __stop___dbe_table - 1, addr); | |
421 | if (!e) | |
422 | e = search_module_dbetables(addr); | |
423 | return e; | |
424 | } | |
425 | ||
426 | asmlinkage void do_be(struct pt_regs *regs) | |
427 | { | |
428 | const int field = 2 * sizeof(unsigned long); | |
429 | const struct exception_table_entry *fixup = NULL; | |
430 | int data = regs->cp0_cause & 4; | |
431 | int action = MIPS_BE_FATAL; | |
c3fc5cd5 | 432 | enum ctx_state prev_state; |
1da177e4 | 433 | |
c3fc5cd5 | 434 | prev_state = exception_enter(); |
70342287 | 435 | /* XXX For now. Fixme, this searches the wrong table ... */ |
1da177e4 LT |
436 | if (data && !user_mode(regs)) |
437 | fixup = search_dbe_tables(exception_epc(regs)); | |
438 | ||
439 | if (fixup) | |
440 | action = MIPS_BE_FIXUP; | |
441 | ||
442 | if (board_be_handler) | |
28fc582c | 443 | action = board_be_handler(regs, fixup != NULL); |
1da177e4 LT |
444 | |
445 | switch (action) { | |
446 | case MIPS_BE_DISCARD: | |
c3fc5cd5 | 447 | goto out; |
1da177e4 LT |
448 | case MIPS_BE_FIXUP: |
449 | if (fixup) { | |
450 | regs->cp0_epc = fixup->nextinsn; | |
c3fc5cd5 | 451 | goto out; |
1da177e4 LT |
452 | } |
453 | break; | |
454 | default: | |
455 | break; | |
456 | } | |
457 | ||
458 | /* | |
459 | * Assume it would be too dangerous to continue ... | |
460 | */ | |
461 | printk(KERN_ALERT "%s bus error, epc == %0*lx, ra == %0*lx\n", | |
462 | data ? "Data" : "Instruction", | |
463 | field, regs->cp0_epc, field, regs->regs[31]); | |
dc73e4c1 RB |
464 | if (notify_die(DIE_OOPS, "bus error", regs, 0, regs_to_trapnr(regs), |
465 | SIGBUS) == NOTIFY_STOP) | |
c3fc5cd5 | 466 | goto out; |
88547001 | 467 | |
1da177e4 LT |
468 | die_if_kernel("Oops", regs); |
469 | force_sig(SIGBUS, current); | |
c3fc5cd5 RB |
470 | |
471 | out: | |
472 | exception_exit(prev_state); | |
1da177e4 LT |
473 | } |
474 | ||
1da177e4 | 475 | /* |
60b0d655 | 476 | * ll/sc, rdhwr, sync emulation |
1da177e4 LT |
477 | */ |
478 | ||
479 | #define OPCODE 0xfc000000 | |
480 | #define BASE 0x03e00000 | |
481 | #define RT 0x001f0000 | |
482 | #define OFFSET 0x0000ffff | |
483 | #define LL 0xc0000000 | |
484 | #define SC 0xe0000000 | |
60b0d655 | 485 | #define SPEC0 0x00000000 |
3c37026d RB |
486 | #define SPEC3 0x7c000000 |
487 | #define RD 0x0000f800 | |
488 | #define FUNC 0x0000003f | |
60b0d655 | 489 | #define SYNC 0x0000000f |
3c37026d | 490 | #define RDHWR 0x0000003b |
1da177e4 | 491 | |
2a0b24f5 SH |
492 | /* microMIPS definitions */ |
493 | #define MM_POOL32A_FUNC 0xfc00ffff | |
494 | #define MM_RDHWR 0x00006b3c | |
495 | #define MM_RS 0x001f0000 | |
496 | #define MM_RT 0x03e00000 | |
497 | ||
1da177e4 LT |
498 | /* |
499 | * The ll_bit is cleared by r*_switch.S | |
500 | */ | |
501 | ||
f1e39a4a RB |
502 | unsigned int ll_bit; |
503 | struct task_struct *ll_task; | |
1da177e4 | 504 | |
60b0d655 | 505 | static inline int simulate_ll(struct pt_regs *regs, unsigned int opcode) |
1da177e4 | 506 | { |
fe00f943 | 507 | unsigned long value, __user *vaddr; |
1da177e4 | 508 | long offset; |
1da177e4 LT |
509 | |
510 | /* | |
511 | * analyse the ll instruction that just caused a ri exception | |
512 | * and put the referenced address to addr. | |
513 | */ | |
514 | ||
515 | /* sign extend offset */ | |
516 | offset = opcode & OFFSET; | |
517 | offset <<= 16; | |
518 | offset >>= 16; | |
519 | ||
fe00f943 | 520 | vaddr = (unsigned long __user *) |
b9688310 | 521 | ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset); |
1da177e4 | 522 | |
60b0d655 MR |
523 | if ((unsigned long)vaddr & 3) |
524 | return SIGBUS; | |
525 | if (get_user(value, vaddr)) | |
526 | return SIGSEGV; | |
1da177e4 LT |
527 | |
528 | preempt_disable(); | |
529 | ||
530 | if (ll_task == NULL || ll_task == current) { | |
531 | ll_bit = 1; | |
532 | } else { | |
533 | ll_bit = 0; | |
534 | } | |
535 | ll_task = current; | |
536 | ||
537 | preempt_enable(); | |
538 | ||
539 | regs->regs[(opcode & RT) >> 16] = value; | |
540 | ||
60b0d655 | 541 | return 0; |
1da177e4 LT |
542 | } |
543 | ||
60b0d655 | 544 | static inline int simulate_sc(struct pt_regs *regs, unsigned int opcode) |
1da177e4 | 545 | { |
fe00f943 RB |
546 | unsigned long __user *vaddr; |
547 | unsigned long reg; | |
1da177e4 | 548 | long offset; |
1da177e4 LT |
549 | |
550 | /* | |
551 | * analyse the sc instruction that just caused a ri exception | |
552 | * and put the referenced address to addr. | |
553 | */ | |
554 | ||
555 | /* sign extend offset */ | |
556 | offset = opcode & OFFSET; | |
557 | offset <<= 16; | |
558 | offset >>= 16; | |
559 | ||
fe00f943 | 560 | vaddr = (unsigned long __user *) |
b9688310 | 561 | ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset); |
1da177e4 LT |
562 | reg = (opcode & RT) >> 16; |
563 | ||
60b0d655 MR |
564 | if ((unsigned long)vaddr & 3) |
565 | return SIGBUS; | |
1da177e4 LT |
566 | |
567 | preempt_disable(); | |
568 | ||
569 | if (ll_bit == 0 || ll_task != current) { | |
570 | regs->regs[reg] = 0; | |
571 | preempt_enable(); | |
60b0d655 | 572 | return 0; |
1da177e4 LT |
573 | } |
574 | ||
575 | preempt_enable(); | |
576 | ||
60b0d655 MR |
577 | if (put_user(regs->regs[reg], vaddr)) |
578 | return SIGSEGV; | |
1da177e4 LT |
579 | |
580 | regs->regs[reg] = 1; | |
581 | ||
60b0d655 | 582 | return 0; |
1da177e4 LT |
583 | } |
584 | ||
585 | /* | |
586 | * ll uses the opcode of lwc0 and sc uses the opcode of swc0. That is both | |
587 | * opcodes are supposed to result in coprocessor unusable exceptions if | |
588 | * executed on ll/sc-less processors. That's the theory. In practice a | |
589 | * few processors such as NEC's VR4100 throw reserved instruction exceptions | |
590 | * instead, so we're doing the emulation thing in both exception handlers. | |
591 | */ | |
60b0d655 | 592 | static int simulate_llsc(struct pt_regs *regs, unsigned int opcode) |
1da177e4 | 593 | { |
7f788d2d DCZ |
594 | if ((opcode & OPCODE) == LL) { |
595 | perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, | |
a8b0ca17 | 596 | 1, regs, 0); |
60b0d655 | 597 | return simulate_ll(regs, opcode); |
7f788d2d DCZ |
598 | } |
599 | if ((opcode & OPCODE) == SC) { | |
600 | perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, | |
a8b0ca17 | 601 | 1, regs, 0); |
60b0d655 | 602 | return simulate_sc(regs, opcode); |
7f788d2d | 603 | } |
1da177e4 | 604 | |
60b0d655 | 605 | return -1; /* Must be something else ... */ |
1da177e4 LT |
606 | } |
607 | ||
3c37026d RB |
608 | /* |
609 | * Simulate trapping 'rdhwr' instructions to provide user accessible | |
1f5826bd | 610 | * registers not implemented in hardware. |
3c37026d | 611 | */ |
2a0b24f5 | 612 | static int simulate_rdhwr(struct pt_regs *regs, int rd, int rt) |
3c37026d | 613 | { |
dc8f6029 | 614 | struct thread_info *ti = task_thread_info(current); |
3c37026d | 615 | |
2a0b24f5 SH |
616 | perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, |
617 | 1, regs, 0); | |
618 | switch (rd) { | |
619 | case 0: /* CPU number */ | |
620 | regs->regs[rt] = smp_processor_id(); | |
621 | return 0; | |
622 | case 1: /* SYNCI length */ | |
623 | regs->regs[rt] = min(current_cpu_data.dcache.linesz, | |
624 | current_cpu_data.icache.linesz); | |
625 | return 0; | |
626 | case 2: /* Read count register */ | |
627 | regs->regs[rt] = read_c0_count(); | |
628 | return 0; | |
629 | case 3: /* Count register resolution */ | |
69f24d17 | 630 | switch (current_cpu_type()) { |
2a0b24f5 SH |
631 | case CPU_20KC: |
632 | case CPU_25KF: | |
633 | regs->regs[rt] = 1; | |
634 | break; | |
635 | default: | |
636 | regs->regs[rt] = 2; | |
637 | } | |
638 | return 0; | |
639 | case 29: | |
640 | regs->regs[rt] = ti->tp_value; | |
641 | return 0; | |
642 | default: | |
643 | return -1; | |
644 | } | |
645 | } | |
646 | ||
647 | static int simulate_rdhwr_normal(struct pt_regs *regs, unsigned int opcode) | |
648 | { | |
3c37026d RB |
649 | if ((opcode & OPCODE) == SPEC3 && (opcode & FUNC) == RDHWR) { |
650 | int rd = (opcode & RD) >> 11; | |
651 | int rt = (opcode & RT) >> 16; | |
2a0b24f5 SH |
652 | |
653 | simulate_rdhwr(regs, rd, rt); | |
654 | return 0; | |
655 | } | |
656 | ||
657 | /* Not ours. */ | |
658 | return -1; | |
659 | } | |
660 | ||
661 | static int simulate_rdhwr_mm(struct pt_regs *regs, unsigned short opcode) | |
662 | { | |
663 | if ((opcode & MM_POOL32A_FUNC) == MM_RDHWR) { | |
664 | int rd = (opcode & MM_RS) >> 16; | |
665 | int rt = (opcode & MM_RT) >> 21; | |
666 | simulate_rdhwr(regs, rd, rt); | |
667 | return 0; | |
3c37026d RB |
668 | } |
669 | ||
56ebd51b | 670 | /* Not ours. */ |
60b0d655 MR |
671 | return -1; |
672 | } | |
e5679882 | 673 | |
60b0d655 MR |
674 | static int simulate_sync(struct pt_regs *regs, unsigned int opcode) |
675 | { | |
7f788d2d DCZ |
676 | if ((opcode & OPCODE) == SPEC0 && (opcode & FUNC) == SYNC) { |
677 | perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, | |
a8b0ca17 | 678 | 1, regs, 0); |
60b0d655 | 679 | return 0; |
7f788d2d | 680 | } |
60b0d655 MR |
681 | |
682 | return -1; /* Must be something else ... */ | |
3c37026d RB |
683 | } |
684 | ||
1da177e4 LT |
685 | asmlinkage void do_ov(struct pt_regs *regs) |
686 | { | |
c3fc5cd5 | 687 | enum ctx_state prev_state; |
1da177e4 LT |
688 | siginfo_t info; |
689 | ||
c3fc5cd5 | 690 | prev_state = exception_enter(); |
36ccf1c0 RB |
691 | die_if_kernel("Integer overflow", regs); |
692 | ||
1da177e4 LT |
693 | info.si_code = FPE_INTOVF; |
694 | info.si_signo = SIGFPE; | |
695 | info.si_errno = 0; | |
fe00f943 | 696 | info.si_addr = (void __user *) regs->cp0_epc; |
1da177e4 | 697 | force_sig_info(SIGFPE, &info, current); |
c3fc5cd5 | 698 | exception_exit(prev_state); |
1da177e4 LT |
699 | } |
700 | ||
102cedc3 | 701 | int process_fpemu_return(int sig, void __user *fault_addr) |
515b029d DD |
702 | { |
703 | if (sig == SIGSEGV || sig == SIGBUS) { | |
704 | struct siginfo si = {0}; | |
705 | si.si_addr = fault_addr; | |
706 | si.si_signo = sig; | |
707 | if (sig == SIGSEGV) { | |
f7a89f1b | 708 | down_read(¤t->mm->mmap_sem); |
515b029d DD |
709 | if (find_vma(current->mm, (unsigned long)fault_addr)) |
710 | si.si_code = SEGV_ACCERR; | |
711 | else | |
712 | si.si_code = SEGV_MAPERR; | |
f7a89f1b | 713 | up_read(¤t->mm->mmap_sem); |
515b029d DD |
714 | } else { |
715 | si.si_code = BUS_ADRERR; | |
716 | } | |
717 | force_sig_info(sig, &si, current); | |
718 | return 1; | |
719 | } else if (sig) { | |
720 | force_sig(sig, current); | |
721 | return 1; | |
722 | } else { | |
723 | return 0; | |
724 | } | |
725 | } | |
726 | ||
1da177e4 LT |
727 | /* |
728 | * XXX Delayed fp exceptions when doing a lazy ctx switch XXX | |
729 | */ | |
730 | asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31) | |
731 | { | |
c3fc5cd5 | 732 | enum ctx_state prev_state; |
515b029d | 733 | siginfo_t info = {0}; |
948a34cf | 734 | |
c3fc5cd5 | 735 | prev_state = exception_enter(); |
dc73e4c1 RB |
736 | if (notify_die(DIE_FP, "FP exception", regs, 0, regs_to_trapnr(regs), |
737 | SIGFPE) == NOTIFY_STOP) | |
c3fc5cd5 | 738 | goto out; |
57725f9e CD |
739 | die_if_kernel("FP exception in kernel code", regs); |
740 | ||
1da177e4 LT |
741 | if (fcr31 & FPU_CSR_UNI_X) { |
742 | int sig; | |
515b029d | 743 | void __user *fault_addr = NULL; |
1da177e4 | 744 | |
1da177e4 | 745 | /* |
a3dddd56 | 746 | * Unimplemented operation exception. If we've got the full |
1da177e4 LT |
747 | * software emulator on-board, let's use it... |
748 | * | |
749 | * Force FPU to dump state into task/thread context. We're | |
750 | * moving a lot of data here for what is probably a single | |
751 | * instruction, but the alternative is to pre-decode the FP | |
752 | * register operands before invoking the emulator, which seems | |
753 | * a bit extreme for what should be an infrequent event. | |
754 | */ | |
cd21dfcf | 755 | /* Ensure 'resume' not overwrite saved fp context again. */ |
53dc8028 | 756 | lose_fpu(1); |
1da177e4 LT |
757 | |
758 | /* Run the emulator */ | |
515b029d DD |
759 | sig = fpu_emulator_cop1Handler(regs, ¤t->thread.fpu, 1, |
760 | &fault_addr); | |
1da177e4 LT |
761 | |
762 | /* | |
763 | * We can't allow the emulated instruction to leave any of | |
764 | * the cause bit set in $fcr31. | |
765 | */ | |
eae89076 | 766 | current->thread.fpu.fcr31 &= ~FPU_CSR_ALL_X; |
1da177e4 LT |
767 | |
768 | /* Restore the hardware register state */ | |
70342287 | 769 | own_fpu(1); /* Using the FPU again. */ |
1da177e4 LT |
770 | |
771 | /* If something went wrong, signal */ | |
515b029d | 772 | process_fpemu_return(sig, fault_addr); |
1da177e4 | 773 | |
c3fc5cd5 | 774 | goto out; |
948a34cf TS |
775 | } else if (fcr31 & FPU_CSR_INV_X) |
776 | info.si_code = FPE_FLTINV; | |
777 | else if (fcr31 & FPU_CSR_DIV_X) | |
778 | info.si_code = FPE_FLTDIV; | |
779 | else if (fcr31 & FPU_CSR_OVF_X) | |
780 | info.si_code = FPE_FLTOVF; | |
781 | else if (fcr31 & FPU_CSR_UDF_X) | |
782 | info.si_code = FPE_FLTUND; | |
783 | else if (fcr31 & FPU_CSR_INE_X) | |
784 | info.si_code = FPE_FLTRES; | |
785 | else | |
786 | info.si_code = __SI_FAULT; | |
787 | info.si_signo = SIGFPE; | |
788 | info.si_errno = 0; | |
789 | info.si_addr = (void __user *) regs->cp0_epc; | |
790 | force_sig_info(SIGFPE, &info, current); | |
c3fc5cd5 RB |
791 | |
792 | out: | |
793 | exception_exit(prev_state); | |
1da177e4 LT |
794 | } |
795 | ||
df270051 RB |
796 | static void do_trap_or_bp(struct pt_regs *regs, unsigned int code, |
797 | const char *str) | |
1da177e4 | 798 | { |
1da177e4 | 799 | siginfo_t info; |
df270051 | 800 | char b[40]; |
1da177e4 | 801 | |
5dd11d5d | 802 | #ifdef CONFIG_KGDB_LOW_LEVEL_TRAP |
70dc6f04 | 803 | if (kgdb_ll_trap(DIE_TRAP, str, regs, code, regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP) |
5dd11d5d JW |
804 | return; |
805 | #endif /* CONFIG_KGDB_LOW_LEVEL_TRAP */ | |
806 | ||
dc73e4c1 RB |
807 | if (notify_die(DIE_TRAP, str, regs, code, regs_to_trapnr(regs), |
808 | SIGTRAP) == NOTIFY_STOP) | |
88547001 JW |
809 | return; |
810 | ||
1da177e4 | 811 | /* |
df270051 RB |
812 | * A short test says that IRIX 5.3 sends SIGTRAP for all trap |
813 | * insns, even for trap and break codes that indicate arithmetic | |
814 | * failures. Weird ... | |
1da177e4 LT |
815 | * But should we continue the brokenness??? --macro |
816 | */ | |
df270051 RB |
817 | switch (code) { |
818 | case BRK_OVERFLOW: | |
819 | case BRK_DIVZERO: | |
820 | scnprintf(b, sizeof(b), "%s instruction in kernel code", str); | |
821 | die_if_kernel(b, regs); | |
822 | if (code == BRK_DIVZERO) | |
1da177e4 LT |
823 | info.si_code = FPE_INTDIV; |
824 | else | |
825 | info.si_code = FPE_INTOVF; | |
826 | info.si_signo = SIGFPE; | |
827 | info.si_errno = 0; | |
fe00f943 | 828 | info.si_addr = (void __user *) regs->cp0_epc; |
1da177e4 LT |
829 | force_sig_info(SIGFPE, &info, current); |
830 | break; | |
63dc68a8 | 831 | case BRK_BUG: |
df270051 RB |
832 | die_if_kernel("Kernel bug detected", regs); |
833 | force_sig(SIGTRAP, current); | |
63dc68a8 | 834 | break; |
ba3049ed RB |
835 | case BRK_MEMU: |
836 | /* | |
837 | * Address errors may be deliberately induced by the FPU | |
838 | * emulator to retake control of the CPU after executing the | |
839 | * instruction in the delay slot of an emulated branch. | |
840 | * | |
841 | * Terminate if exception was recognized as a delay slot return | |
842 | * otherwise handle as normal. | |
843 | */ | |
844 | if (do_dsemulret(regs)) | |
845 | return; | |
846 | ||
847 | die_if_kernel("Math emu break/trap", regs); | |
848 | force_sig(SIGTRAP, current); | |
849 | break; | |
1da177e4 | 850 | default: |
df270051 RB |
851 | scnprintf(b, sizeof(b), "%s instruction in kernel code", str); |
852 | die_if_kernel(b, regs); | |
1da177e4 LT |
853 | force_sig(SIGTRAP, current); |
854 | } | |
df270051 RB |
855 | } |
856 | ||
857 | asmlinkage void do_bp(struct pt_regs *regs) | |
858 | { | |
859 | unsigned int opcode, bcode; | |
c3fc5cd5 | 860 | enum ctx_state prev_state; |
2a0b24f5 SH |
861 | unsigned long epc; |
862 | u16 instr[2]; | |
078dde5e LY |
863 | mm_segment_t seg; |
864 | ||
865 | seg = get_fs(); | |
866 | if (!user_mode(regs)) | |
867 | set_fs(KERNEL_DS); | |
2a0b24f5 | 868 | |
c3fc5cd5 | 869 | prev_state = exception_enter(); |
2a0b24f5 SH |
870 | if (get_isa16_mode(regs->cp0_epc)) { |
871 | /* Calculate EPC. */ | |
872 | epc = exception_epc(regs); | |
873 | if (cpu_has_mmips) { | |
874 | if ((__get_user(instr[0], (u16 __user *)msk_isa16_mode(epc)) || | |
875 | (__get_user(instr[1], (u16 __user *)msk_isa16_mode(epc + 2))))) | |
876 | goto out_sigsegv; | |
b08a9c95 | 877 | opcode = (instr[0] << 16) | instr[1]; |
2a0b24f5 | 878 | } else { |
b08a9c95 MC |
879 | /* MIPS16e mode */ |
880 | if (__get_user(instr[0], | |
881 | (u16 __user *)msk_isa16_mode(epc))) | |
2a0b24f5 | 882 | goto out_sigsegv; |
b08a9c95 MC |
883 | bcode = (instr[0] >> 6) & 0x3f; |
884 | do_trap_or_bp(regs, bcode, "Break"); | |
885 | goto out; | |
2a0b24f5 SH |
886 | } |
887 | } else { | |
b08a9c95 MC |
888 | if (__get_user(opcode, |
889 | (unsigned int __user *) exception_epc(regs))) | |
2a0b24f5 SH |
890 | goto out_sigsegv; |
891 | } | |
df270051 RB |
892 | |
893 | /* | |
894 | * There is the ancient bug in the MIPS assemblers that the break | |
895 | * code starts left to bit 16 instead to bit 6 in the opcode. | |
896 | * Gas is bug-compatible, but not always, grrr... | |
897 | * We handle both cases with a simple heuristics. --macro | |
898 | */ | |
899 | bcode = ((opcode >> 6) & ((1 << 20) - 1)); | |
900 | if (bcode >= (1 << 10)) | |
901 | bcode >>= 10; | |
902 | ||
c1bf207d DD |
903 | /* |
904 | * notify the kprobe handlers, if instruction is likely to | |
905 | * pertain to them. | |
906 | */ | |
907 | switch (bcode) { | |
908 | case BRK_KPROBE_BP: | |
dc73e4c1 RB |
909 | if (notify_die(DIE_BREAK, "debug", regs, bcode, |
910 | regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP) | |
c3fc5cd5 | 911 | goto out; |
c1bf207d DD |
912 | else |
913 | break; | |
914 | case BRK_KPROBE_SSTEPBP: | |
dc73e4c1 RB |
915 | if (notify_die(DIE_SSTEPBP, "single_step", regs, bcode, |
916 | regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP) | |
c3fc5cd5 | 917 | goto out; |
c1bf207d DD |
918 | else |
919 | break; | |
920 | default: | |
921 | break; | |
922 | } | |
923 | ||
df270051 | 924 | do_trap_or_bp(regs, bcode, "Break"); |
c3fc5cd5 RB |
925 | |
926 | out: | |
078dde5e | 927 | set_fs(seg); |
c3fc5cd5 | 928 | exception_exit(prev_state); |
90fccb13 | 929 | return; |
e5679882 RB |
930 | |
931 | out_sigsegv: | |
932 | force_sig(SIGSEGV, current); | |
c3fc5cd5 | 933 | goto out; |
1da177e4 LT |
934 | } |
935 | ||
936 | asmlinkage void do_tr(struct pt_regs *regs) | |
937 | { | |
a9a6e7a0 | 938 | u32 opcode, tcode = 0; |
c3fc5cd5 | 939 | enum ctx_state prev_state; |
2a0b24f5 | 940 | u16 instr[2]; |
078dde5e | 941 | mm_segment_t seg; |
a9a6e7a0 | 942 | unsigned long epc = msk_isa16_mode(exception_epc(regs)); |
1da177e4 | 943 | |
078dde5e LY |
944 | seg = get_fs(); |
945 | if (!user_mode(regs)) | |
946 | set_fs(get_ds()); | |
947 | ||
c3fc5cd5 | 948 | prev_state = exception_enter(); |
a9a6e7a0 MR |
949 | if (get_isa16_mode(regs->cp0_epc)) { |
950 | if (__get_user(instr[0], (u16 __user *)(epc + 0)) || | |
951 | __get_user(instr[1], (u16 __user *)(epc + 2))) | |
2a0b24f5 | 952 | goto out_sigsegv; |
a9a6e7a0 MR |
953 | opcode = (instr[0] << 16) | instr[1]; |
954 | /* Immediate versions don't provide a code. */ | |
955 | if (!(opcode & OPCODE)) | |
956 | tcode = (opcode >> 12) & ((1 << 4) - 1); | |
957 | } else { | |
958 | if (__get_user(opcode, (u32 __user *)epc)) | |
959 | goto out_sigsegv; | |
960 | /* Immediate versions don't provide a code. */ | |
961 | if (!(opcode & OPCODE)) | |
962 | tcode = (opcode >> 6) & ((1 << 10) - 1); | |
2a0b24f5 | 963 | } |
1da177e4 | 964 | |
df270051 | 965 | do_trap_or_bp(regs, tcode, "Trap"); |
c3fc5cd5 RB |
966 | |
967 | out: | |
078dde5e | 968 | set_fs(seg); |
c3fc5cd5 | 969 | exception_exit(prev_state); |
90fccb13 | 970 | return; |
e5679882 RB |
971 | |
972 | out_sigsegv: | |
973 | force_sig(SIGSEGV, current); | |
c3fc5cd5 | 974 | goto out; |
1da177e4 LT |
975 | } |
976 | ||
977 | asmlinkage void do_ri(struct pt_regs *regs) | |
978 | { | |
60b0d655 MR |
979 | unsigned int __user *epc = (unsigned int __user *)exception_epc(regs); |
980 | unsigned long old_epc = regs->cp0_epc; | |
2a0b24f5 | 981 | unsigned long old31 = regs->regs[31]; |
c3fc5cd5 | 982 | enum ctx_state prev_state; |
60b0d655 MR |
983 | unsigned int opcode = 0; |
984 | int status = -1; | |
1da177e4 | 985 | |
c3fc5cd5 | 986 | prev_state = exception_enter(); |
dc73e4c1 RB |
987 | if (notify_die(DIE_RI, "RI Fault", regs, 0, regs_to_trapnr(regs), |
988 | SIGILL) == NOTIFY_STOP) | |
c3fc5cd5 | 989 | goto out; |
88547001 | 990 | |
60b0d655 | 991 | die_if_kernel("Reserved instruction in kernel code", regs); |
1da177e4 | 992 | |
60b0d655 | 993 | if (unlikely(compute_return_epc(regs) < 0)) |
c3fc5cd5 | 994 | goto out; |
3c37026d | 995 | |
2a0b24f5 SH |
996 | if (get_isa16_mode(regs->cp0_epc)) { |
997 | unsigned short mmop[2] = { 0 }; | |
60b0d655 | 998 | |
2a0b24f5 SH |
999 | if (unlikely(get_user(mmop[0], epc) < 0)) |
1000 | status = SIGSEGV; | |
1001 | if (unlikely(get_user(mmop[1], epc) < 0)) | |
1002 | status = SIGSEGV; | |
1003 | opcode = (mmop[0] << 16) | mmop[1]; | |
60b0d655 | 1004 | |
2a0b24f5 SH |
1005 | if (status < 0) |
1006 | status = simulate_rdhwr_mm(regs, opcode); | |
1007 | } else { | |
1008 | if (unlikely(get_user(opcode, epc) < 0)) | |
1009 | status = SIGSEGV; | |
60b0d655 | 1010 | |
2a0b24f5 SH |
1011 | if (!cpu_has_llsc && status < 0) |
1012 | status = simulate_llsc(regs, opcode); | |
1013 | ||
1014 | if (status < 0) | |
1015 | status = simulate_rdhwr_normal(regs, opcode); | |
1016 | ||
1017 | if (status < 0) | |
1018 | status = simulate_sync(regs, opcode); | |
1019 | } | |
60b0d655 MR |
1020 | |
1021 | if (status < 0) | |
1022 | status = SIGILL; | |
1023 | ||
1024 | if (unlikely(status > 0)) { | |
1025 | regs->cp0_epc = old_epc; /* Undo skip-over. */ | |
2a0b24f5 | 1026 | regs->regs[31] = old31; |
60b0d655 MR |
1027 | force_sig(status, current); |
1028 | } | |
c3fc5cd5 RB |
1029 | |
1030 | out: | |
1031 | exception_exit(prev_state); | |
1da177e4 LT |
1032 | } |
1033 | ||
d223a861 RB |
1034 | /* |
1035 | * MIPS MT processors may have fewer FPU contexts than CPU threads. If we've | |
1036 | * emulated more than some threshold number of instructions, force migration to | |
1037 | * a "CPU" that has FP support. | |
1038 | */ | |
1039 | static void mt_ase_fp_affinity(void) | |
1040 | { | |
1041 | #ifdef CONFIG_MIPS_MT_FPAFF | |
1042 | if (mt_fpemul_threshold > 0 && | |
1043 | ((current->thread.emulated_fp++ > mt_fpemul_threshold))) { | |
1044 | /* | |
1045 | * If there's no FPU present, or if the application has already | |
1046 | * restricted the allowed set to exclude any CPUs with FPUs, | |
1047 | * we'll skip the procedure. | |
1048 | */ | |
1049 | if (cpus_intersects(current->cpus_allowed, mt_fpu_cpumask)) { | |
1050 | cpumask_t tmask; | |
1051 | ||
9cc12363 KK |
1052 | current->thread.user_cpus_allowed |
1053 | = current->cpus_allowed; | |
1054 | cpus_and(tmask, current->cpus_allowed, | |
1055 | mt_fpu_cpumask); | |
ed1bbdef | 1056 | set_cpus_allowed_ptr(current, &tmask); |
293c5bd1 | 1057 | set_thread_flag(TIF_FPUBOUND); |
d223a861 RB |
1058 | } |
1059 | } | |
1060 | #endif /* CONFIG_MIPS_MT_FPAFF */ | |
1061 | } | |
1062 | ||
69f3a7de RB |
1063 | /* |
1064 | * No lock; only written during early bootup by CPU 0. | |
1065 | */ | |
1066 | static RAW_NOTIFIER_HEAD(cu2_chain); | |
1067 | ||
1068 | int __ref register_cu2_notifier(struct notifier_block *nb) | |
1069 | { | |
1070 | return raw_notifier_chain_register(&cu2_chain, nb); | |
1071 | } | |
1072 | ||
1073 | int cu2_notifier_call_chain(unsigned long val, void *v) | |
1074 | { | |
1075 | return raw_notifier_call_chain(&cu2_chain, val, v); | |
1076 | } | |
1077 | ||
1078 | static int default_cu2_call(struct notifier_block *nfb, unsigned long action, | |
70342287 | 1079 | void *data) |
69f3a7de RB |
1080 | { |
1081 | struct pt_regs *regs = data; | |
1082 | ||
83bee792 | 1083 | die_if_kernel("COP2: Unhandled kernel unaligned access or invalid " |
69f3a7de | 1084 | "instruction", regs); |
83bee792 | 1085 | force_sig(SIGILL, current); |
69f3a7de RB |
1086 | |
1087 | return NOTIFY_OK; | |
1088 | } | |
1089 | ||
1db1af84 PB |
1090 | static int enable_restore_fp_context(int msa) |
1091 | { | |
c9017757 | 1092 | int err, was_fpu_owner, prior_msa; |
1db1af84 PB |
1093 | |
1094 | if (!used_math()) { | |
1095 | /* First time FP context user. */ | |
1096 | err = init_fpu(); | |
c9017757 | 1097 | if (msa && !err) { |
1db1af84 | 1098 | enable_msa(); |
c9017757 | 1099 | _init_msa_upper(); |
732c0c3c PB |
1100 | set_thread_flag(TIF_USEDMSA); |
1101 | set_thread_flag(TIF_MSA_CTX_LIVE); | |
c9017757 | 1102 | } |
1db1af84 PB |
1103 | if (!err) |
1104 | set_used_math(); | |
1105 | return err; | |
1106 | } | |
1107 | ||
1108 | /* | |
1109 | * This task has formerly used the FP context. | |
1110 | * | |
1111 | * If this thread has no live MSA vector context then we can simply | |
1112 | * restore the scalar FP context. If it has live MSA vector context | |
1113 | * (that is, it has or may have used MSA since last performing a | |
1114 | * function call) then we'll need to restore the vector context. This | |
1115 | * applies even if we're currently only executing a scalar FP | |
1116 | * instruction. This is because if we were to later execute an MSA | |
1117 | * instruction then we'd either have to: | |
1118 | * | |
1119 | * - Restore the vector context & clobber any registers modified by | |
1120 | * scalar FP instructions between now & then. | |
1121 | * | |
1122 | * or | |
1123 | * | |
1124 | * - Not restore the vector context & lose the most significant bits | |
1125 | * of all vector registers. | |
1126 | * | |
1127 | * Neither of those options is acceptable. We cannot restore the least | |
1128 | * significant bits of the registers now & only restore the most | |
1129 | * significant bits later because the most significant bits of any | |
1130 | * vector registers whose aliased FP register is modified now will have | |
1131 | * been zeroed. We'd have no way to know that when restoring the vector | |
1132 | * context & thus may load an outdated value for the most significant | |
1133 | * bits of a vector register. | |
1134 | */ | |
1135 | if (!msa && !thread_msa_context_live()) | |
1136 | return own_fpu(1); | |
1137 | ||
1138 | /* | |
1139 | * This task is using or has previously used MSA. Thus we require | |
1140 | * that Status.FR == 1. | |
1141 | */ | |
1142 | was_fpu_owner = is_fpu_owner(); | |
1143 | err = own_fpu(0); | |
1144 | if (err) | |
1145 | return err; | |
1146 | ||
1147 | enable_msa(); | |
1148 | write_msa_csr(current->thread.fpu.msacsr); | |
1149 | set_thread_flag(TIF_USEDMSA); | |
1150 | ||
1151 | /* | |
1152 | * If this is the first time that the task is using MSA and it has | |
1153 | * previously used scalar FP in this time slice then we already nave | |
c9017757 PB |
1154 | * FP context which we shouldn't clobber. We do however need to clear |
1155 | * the upper 64b of each vector register so that this task has no | |
1156 | * opportunity to see data left behind by another. | |
1db1af84 | 1157 | */ |
c9017757 PB |
1158 | prior_msa = test_and_set_thread_flag(TIF_MSA_CTX_LIVE); |
1159 | if (!prior_msa && was_fpu_owner) { | |
1160 | _init_msa_upper(); | |
1db1af84 | 1161 | return 0; |
c9017757 | 1162 | } |
1db1af84 | 1163 | |
c9017757 PB |
1164 | if (!prior_msa) { |
1165 | /* | |
1166 | * Restore the least significant 64b of each vector register | |
1167 | * from the existing scalar FP context. | |
1168 | */ | |
1169 | _restore_fp(current); | |
b8340673 | 1170 | |
c9017757 PB |
1171 | /* |
1172 | * The task has not formerly used MSA, so clear the upper 64b | |
1173 | * of each vector register such that it cannot see data left | |
1174 | * behind by another task. | |
1175 | */ | |
1176 | _init_msa_upper(); | |
1177 | } else { | |
1178 | /* We need to restore the vector context. */ | |
1179 | restore_msa(current); | |
b8340673 | 1180 | |
c9017757 PB |
1181 | /* Restore the scalar FP control & status register */ |
1182 | if (!was_fpu_owner) | |
1183 | asm volatile("ctc1 %0, $31" : : "r"(current->thread.fpu.fcr31)); | |
1184 | } | |
1db1af84 PB |
1185 | return 0; |
1186 | } | |
1187 | ||
1da177e4 LT |
1188 | asmlinkage void do_cpu(struct pt_regs *regs) |
1189 | { | |
c3fc5cd5 | 1190 | enum ctx_state prev_state; |
60b0d655 | 1191 | unsigned int __user *epc; |
2a0b24f5 | 1192 | unsigned long old_epc, old31; |
60b0d655 | 1193 | unsigned int opcode; |
1da177e4 | 1194 | unsigned int cpid; |
597ce172 | 1195 | int status, err; |
f9bb4cf3 | 1196 | unsigned long __maybe_unused flags; |
1da177e4 | 1197 | |
c3fc5cd5 | 1198 | prev_state = exception_enter(); |
1da177e4 LT |
1199 | cpid = (regs->cp0_cause >> CAUSEB_CE) & 3; |
1200 | ||
83bee792 J |
1201 | if (cpid != 2) |
1202 | die_if_kernel("do_cpu invoked from kernel context!", regs); | |
1203 | ||
1da177e4 LT |
1204 | switch (cpid) { |
1205 | case 0: | |
60b0d655 MR |
1206 | epc = (unsigned int __user *)exception_epc(regs); |
1207 | old_epc = regs->cp0_epc; | |
2a0b24f5 | 1208 | old31 = regs->regs[31]; |
60b0d655 MR |
1209 | opcode = 0; |
1210 | status = -1; | |
1da177e4 | 1211 | |
60b0d655 | 1212 | if (unlikely(compute_return_epc(regs) < 0)) |
c3fc5cd5 | 1213 | goto out; |
3c37026d | 1214 | |
2a0b24f5 SH |
1215 | if (get_isa16_mode(regs->cp0_epc)) { |
1216 | unsigned short mmop[2] = { 0 }; | |
60b0d655 | 1217 | |
2a0b24f5 SH |
1218 | if (unlikely(get_user(mmop[0], epc) < 0)) |
1219 | status = SIGSEGV; | |
1220 | if (unlikely(get_user(mmop[1], epc) < 0)) | |
1221 | status = SIGSEGV; | |
1222 | opcode = (mmop[0] << 16) | mmop[1]; | |
60b0d655 | 1223 | |
2a0b24f5 SH |
1224 | if (status < 0) |
1225 | status = simulate_rdhwr_mm(regs, opcode); | |
1226 | } else { | |
1227 | if (unlikely(get_user(opcode, epc) < 0)) | |
1228 | status = SIGSEGV; | |
1229 | ||
1230 | if (!cpu_has_llsc && status < 0) | |
1231 | status = simulate_llsc(regs, opcode); | |
1232 | ||
1233 | if (status < 0) | |
1234 | status = simulate_rdhwr_normal(regs, opcode); | |
1235 | } | |
60b0d655 MR |
1236 | |
1237 | if (status < 0) | |
1238 | status = SIGILL; | |
1239 | ||
1240 | if (unlikely(status > 0)) { | |
1241 | regs->cp0_epc = old_epc; /* Undo skip-over. */ | |
2a0b24f5 | 1242 | regs->regs[31] = old31; |
60b0d655 MR |
1243 | force_sig(status, current); |
1244 | } | |
1245 | ||
c3fc5cd5 | 1246 | goto out; |
1da177e4 | 1247 | |
051ff44a MR |
1248 | case 3: |
1249 | /* | |
1250 | * Old (MIPS I and MIPS II) processors will set this code | |
1251 | * for COP1X opcode instructions that replaced the original | |
70342287 | 1252 | * COP3 space. We don't limit COP1 space instructions in |
051ff44a MR |
1253 | * the emulator according to the CPU ISA, so we want to |
1254 | * treat COP1X instructions consistently regardless of which | |
70342287 | 1255 | * code the CPU chose. Therefore we redirect this trap to |
051ff44a MR |
1256 | * the FP emulator too. |
1257 | * | |
1258 | * Then some newer FPU-less processors use this code | |
1259 | * erroneously too, so they are covered by this choice | |
1260 | * as well. | |
1261 | */ | |
1262 | if (raw_cpu_has_fpu) | |
1263 | break; | |
1264 | /* Fall through. */ | |
1265 | ||
1da177e4 | 1266 | case 1: |
1db1af84 | 1267 | err = enable_restore_fp_context(0); |
1da177e4 | 1268 | |
597ce172 | 1269 | if (!raw_cpu_has_fpu || err) { |
e04582b7 | 1270 | int sig; |
515b029d | 1271 | void __user *fault_addr = NULL; |
e04582b7 | 1272 | sig = fpu_emulator_cop1Handler(regs, |
515b029d DD |
1273 | ¤t->thread.fpu, |
1274 | 0, &fault_addr); | |
597ce172 | 1275 | if (!process_fpemu_return(sig, fault_addr) && !err) |
d223a861 | 1276 | mt_ase_fp_affinity(); |
1da177e4 LT |
1277 | } |
1278 | ||
c3fc5cd5 | 1279 | goto out; |
1da177e4 LT |
1280 | |
1281 | case 2: | |
69f3a7de | 1282 | raw_notifier_call_chain(&cu2_chain, CU2_EXCEPTION, regs); |
c3fc5cd5 | 1283 | goto out; |
1da177e4 LT |
1284 | } |
1285 | ||
1286 | force_sig(SIGILL, current); | |
c3fc5cd5 RB |
1287 | |
1288 | out: | |
1289 | exception_exit(prev_state); | |
1da177e4 LT |
1290 | } |
1291 | ||
2bcb3fbc PB |
1292 | asmlinkage void do_msa_fpe(struct pt_regs *regs) |
1293 | { | |
1294 | enum ctx_state prev_state; | |
1295 | ||
1296 | prev_state = exception_enter(); | |
1297 | die_if_kernel("do_msa_fpe invoked from kernel context!", regs); | |
1298 | force_sig(SIGFPE, current); | |
1299 | exception_exit(prev_state); | |
1300 | } | |
1301 | ||
1db1af84 PB |
1302 | asmlinkage void do_msa(struct pt_regs *regs) |
1303 | { | |
1304 | enum ctx_state prev_state; | |
1305 | int err; | |
1306 | ||
1307 | prev_state = exception_enter(); | |
1308 | ||
1309 | if (!cpu_has_msa || test_thread_flag(TIF_32BIT_FPREGS)) { | |
1310 | force_sig(SIGILL, current); | |
1311 | goto out; | |
1312 | } | |
1313 | ||
1314 | die_if_kernel("do_msa invoked from kernel context!", regs); | |
1315 | ||
1316 | err = enable_restore_fp_context(1); | |
1317 | if (err) | |
1318 | force_sig(SIGILL, current); | |
1319 | out: | |
1320 | exception_exit(prev_state); | |
1321 | } | |
1322 | ||
1da177e4 LT |
1323 | asmlinkage void do_mdmx(struct pt_regs *regs) |
1324 | { | |
c3fc5cd5 RB |
1325 | enum ctx_state prev_state; |
1326 | ||
1327 | prev_state = exception_enter(); | |
1da177e4 | 1328 | force_sig(SIGILL, current); |
c3fc5cd5 | 1329 | exception_exit(prev_state); |
1da177e4 LT |
1330 | } |
1331 | ||
8bc6d05b DD |
1332 | /* |
1333 | * Called with interrupts disabled. | |
1334 | */ | |
1da177e4 LT |
1335 | asmlinkage void do_watch(struct pt_regs *regs) |
1336 | { | |
c3fc5cd5 | 1337 | enum ctx_state prev_state; |
b67b2b70 DD |
1338 | u32 cause; |
1339 | ||
c3fc5cd5 | 1340 | prev_state = exception_enter(); |
1da177e4 | 1341 | /* |
b67b2b70 DD |
1342 | * Clear WP (bit 22) bit of cause register so we don't loop |
1343 | * forever. | |
1da177e4 | 1344 | */ |
b67b2b70 DD |
1345 | cause = read_c0_cause(); |
1346 | cause &= ~(1 << 22); | |
1347 | write_c0_cause(cause); | |
1348 | ||
1349 | /* | |
1350 | * If the current thread has the watch registers loaded, save | |
1351 | * their values and send SIGTRAP. Otherwise another thread | |
1352 | * left the registers set, clear them and continue. | |
1353 | */ | |
1354 | if (test_tsk_thread_flag(current, TIF_LOAD_WATCH)) { | |
1355 | mips_read_watch_registers(); | |
8bc6d05b | 1356 | local_irq_enable(); |
b67b2b70 | 1357 | force_sig(SIGTRAP, current); |
8bc6d05b | 1358 | } else { |
b67b2b70 | 1359 | mips_clear_watch_registers(); |
8bc6d05b DD |
1360 | local_irq_enable(); |
1361 | } | |
c3fc5cd5 | 1362 | exception_exit(prev_state); |
1da177e4 LT |
1363 | } |
1364 | ||
1365 | asmlinkage void do_mcheck(struct pt_regs *regs) | |
1366 | { | |
cac4bcbc RB |
1367 | const int field = 2 * sizeof(unsigned long); |
1368 | int multi_match = regs->cp0_status & ST0_TS; | |
c3fc5cd5 | 1369 | enum ctx_state prev_state; |
cac4bcbc | 1370 | |
c3fc5cd5 | 1371 | prev_state = exception_enter(); |
1da177e4 | 1372 | show_regs(regs); |
cac4bcbc RB |
1373 | |
1374 | if (multi_match) { | |
70342287 | 1375 | printk("Index : %0x\n", read_c0_index()); |
cac4bcbc RB |
1376 | printk("Pagemask: %0x\n", read_c0_pagemask()); |
1377 | printk("EntryHi : %0*lx\n", field, read_c0_entryhi()); | |
1378 | printk("EntryLo0: %0*lx\n", field, read_c0_entrylo0()); | |
1379 | printk("EntryLo1: %0*lx\n", field, read_c0_entrylo1()); | |
1380 | printk("\n"); | |
1381 | dump_tlb_all(); | |
1382 | } | |
1383 | ||
e1bb8289 | 1384 | show_code((unsigned int __user *) regs->cp0_epc); |
cac4bcbc | 1385 | |
1da177e4 LT |
1386 | /* |
1387 | * Some chips may have other causes of machine check (e.g. SB1 | |
1388 | * graduation timer) | |
1389 | */ | |
1390 | panic("Caught Machine Check exception - %scaused by multiple " | |
1391 | "matching entries in the TLB.", | |
cac4bcbc | 1392 | (multi_match) ? "" : "not "); |
1da177e4 LT |
1393 | } |
1394 | ||
340ee4b9 RB |
1395 | asmlinkage void do_mt(struct pt_regs *regs) |
1396 | { | |
41c594ab RB |
1397 | int subcode; |
1398 | ||
41c594ab RB |
1399 | subcode = (read_vpe_c0_vpecontrol() & VPECONTROL_EXCPT) |
1400 | >> VPECONTROL_EXCPT_SHIFT; | |
1401 | switch (subcode) { | |
1402 | case 0: | |
e35a5e35 | 1403 | printk(KERN_DEBUG "Thread Underflow\n"); |
41c594ab RB |
1404 | break; |
1405 | case 1: | |
e35a5e35 | 1406 | printk(KERN_DEBUG "Thread Overflow\n"); |
41c594ab RB |
1407 | break; |
1408 | case 2: | |
e35a5e35 | 1409 | printk(KERN_DEBUG "Invalid YIELD Qualifier\n"); |
41c594ab RB |
1410 | break; |
1411 | case 3: | |
e35a5e35 | 1412 | printk(KERN_DEBUG "Gating Storage Exception\n"); |
41c594ab RB |
1413 | break; |
1414 | case 4: | |
e35a5e35 | 1415 | printk(KERN_DEBUG "YIELD Scheduler Exception\n"); |
41c594ab RB |
1416 | break; |
1417 | case 5: | |
f232c7e8 | 1418 | printk(KERN_DEBUG "Gating Storage Scheduler Exception\n"); |
41c594ab RB |
1419 | break; |
1420 | default: | |
e35a5e35 | 1421 | printk(KERN_DEBUG "*** UNKNOWN THREAD EXCEPTION %d ***\n", |
41c594ab RB |
1422 | subcode); |
1423 | break; | |
1424 | } | |
340ee4b9 RB |
1425 | die_if_kernel("MIPS MT Thread exception in kernel", regs); |
1426 | ||
1427 | force_sig(SIGILL, current); | |
1428 | } | |
1429 | ||
1430 | ||
e50c0a8f RB |
1431 | asmlinkage void do_dsp(struct pt_regs *regs) |
1432 | { | |
1433 | if (cpu_has_dsp) | |
ab75dc02 | 1434 | panic("Unexpected DSP exception"); |
e50c0a8f RB |
1435 | |
1436 | force_sig(SIGILL, current); | |
1437 | } | |
1438 | ||
1da177e4 LT |
1439 | asmlinkage void do_reserved(struct pt_regs *regs) |
1440 | { | |
1441 | /* | |
70342287 | 1442 | * Game over - no way to handle this if it ever occurs. Most probably |
1da177e4 LT |
1443 | * caused by a new unknown cpu type or after another deadly |
1444 | * hard/software error. | |
1445 | */ | |
1446 | show_regs(regs); | |
1447 | panic("Caught reserved exception %ld - should not happen.", | |
1448 | (regs->cp0_cause & 0x7f) >> 2); | |
1449 | } | |
1450 | ||
39b8d525 RB |
1451 | static int __initdata l1parity = 1; |
1452 | static int __init nol1parity(char *s) | |
1453 | { | |
1454 | l1parity = 0; | |
1455 | return 1; | |
1456 | } | |
1457 | __setup("nol1par", nol1parity); | |
1458 | static int __initdata l2parity = 1; | |
1459 | static int __init nol2parity(char *s) | |
1460 | { | |
1461 | l2parity = 0; | |
1462 | return 1; | |
1463 | } | |
1464 | __setup("nol2par", nol2parity); | |
1465 | ||
1da177e4 LT |
1466 | /* |
1467 | * Some MIPS CPUs can enable/disable for cache parity detection, but do | |
1468 | * it different ways. | |
1469 | */ | |
1470 | static inline void parity_protection_init(void) | |
1471 | { | |
10cc3529 | 1472 | switch (current_cpu_type()) { |
1da177e4 | 1473 | case CPU_24K: |
98a41de9 | 1474 | case CPU_34K: |
39b8d525 RB |
1475 | case CPU_74K: |
1476 | case CPU_1004K: | |
442e14a2 | 1477 | case CPU_1074K: |
26ab96df | 1478 | case CPU_INTERAPTIV: |
708ac4b8 | 1479 | case CPU_PROAPTIV: |
aced4cbd | 1480 | case CPU_P5600: |
39b8d525 RB |
1481 | { |
1482 | #define ERRCTL_PE 0x80000000 | |
1483 | #define ERRCTL_L2P 0x00800000 | |
1484 | unsigned long errctl; | |
1485 | unsigned int l1parity_present, l2parity_present; | |
1486 | ||
1487 | errctl = read_c0_ecc(); | |
1488 | errctl &= ~(ERRCTL_PE|ERRCTL_L2P); | |
1489 | ||
1490 | /* probe L1 parity support */ | |
1491 | write_c0_ecc(errctl | ERRCTL_PE); | |
1492 | back_to_back_c0_hazard(); | |
1493 | l1parity_present = (read_c0_ecc() & ERRCTL_PE); | |
1494 | ||
1495 | /* probe L2 parity support */ | |
1496 | write_c0_ecc(errctl|ERRCTL_L2P); | |
1497 | back_to_back_c0_hazard(); | |
1498 | l2parity_present = (read_c0_ecc() & ERRCTL_L2P); | |
1499 | ||
1500 | if (l1parity_present && l2parity_present) { | |
1501 | if (l1parity) | |
1502 | errctl |= ERRCTL_PE; | |
1503 | if (l1parity ^ l2parity) | |
1504 | errctl |= ERRCTL_L2P; | |
1505 | } else if (l1parity_present) { | |
1506 | if (l1parity) | |
1507 | errctl |= ERRCTL_PE; | |
1508 | } else if (l2parity_present) { | |
1509 | if (l2parity) | |
1510 | errctl |= ERRCTL_L2P; | |
1511 | } else { | |
1512 | /* No parity available */ | |
1513 | } | |
1514 | ||
1515 | printk(KERN_INFO "Writing ErrCtl register=%08lx\n", errctl); | |
1516 | ||
1517 | write_c0_ecc(errctl); | |
1518 | back_to_back_c0_hazard(); | |
1519 | errctl = read_c0_ecc(); | |
1520 | printk(KERN_INFO "Readback ErrCtl register=%08lx\n", errctl); | |
1521 | ||
1522 | if (l1parity_present) | |
1523 | printk(KERN_INFO "Cache parity protection %sabled\n", | |
1524 | (errctl & ERRCTL_PE) ? "en" : "dis"); | |
1525 | ||
1526 | if (l2parity_present) { | |
1527 | if (l1parity_present && l1parity) | |
1528 | errctl ^= ERRCTL_L2P; | |
1529 | printk(KERN_INFO "L2 cache parity protection %sabled\n", | |
1530 | (errctl & ERRCTL_L2P) ? "en" : "dis"); | |
1531 | } | |
1532 | } | |
1533 | break; | |
1534 | ||
1da177e4 | 1535 | case CPU_5KC: |
78d4803f | 1536 | case CPU_5KE: |
2fa36399 | 1537 | case CPU_LOONGSON1: |
14f18b7f RB |
1538 | write_c0_ecc(0x80000000); |
1539 | back_to_back_c0_hazard(); | |
1540 | /* Set the PE bit (bit 31) in the c0_errctl register. */ | |
1541 | printk(KERN_INFO "Cache parity protection %sabled\n", | |
1542 | (read_c0_ecc() & 0x80000000) ? "en" : "dis"); | |
1da177e4 LT |
1543 | break; |
1544 | case CPU_20KC: | |
1545 | case CPU_25KF: | |
1546 | /* Clear the DE bit (bit 16) in the c0_status register. */ | |
1547 | printk(KERN_INFO "Enable cache parity protection for " | |
1548 | "MIPS 20KC/25KF CPUs.\n"); | |
1549 | clear_c0_status(ST0_DE); | |
1550 | break; | |
1551 | default: | |
1552 | break; | |
1553 | } | |
1554 | } | |
1555 | ||
1556 | asmlinkage void cache_parity_error(void) | |
1557 | { | |
1558 | const int field = 2 * sizeof(unsigned long); | |
1559 | unsigned int reg_val; | |
1560 | ||
1561 | /* For the moment, report the problem and hang. */ | |
1562 | printk("Cache error exception:\n"); | |
1563 | printk("cp0_errorepc == %0*lx\n", field, read_c0_errorepc()); | |
1564 | reg_val = read_c0_cacheerr(); | |
1565 | printk("c0_cacheerr == %08x\n", reg_val); | |
1566 | ||
1567 | printk("Decoded c0_cacheerr: %s cache fault in %s reference.\n", | |
1568 | reg_val & (1<<30) ? "secondary" : "primary", | |
1569 | reg_val & (1<<31) ? "data" : "insn"); | |
6de20451 | 1570 | if (cpu_has_mips_r2 && |
721a9205 | 1571 | ((current_cpu_data.processor_id & 0xff0000) == PRID_COMP_MIPS)) { |
6de20451 LY |
1572 | pr_err("Error bits: %s%s%s%s%s%s%s%s\n", |
1573 | reg_val & (1<<29) ? "ED " : "", | |
1574 | reg_val & (1<<28) ? "ET " : "", | |
1575 | reg_val & (1<<27) ? "ES " : "", | |
1576 | reg_val & (1<<26) ? "EE " : "", | |
1577 | reg_val & (1<<25) ? "EB " : "", | |
1578 | reg_val & (1<<24) ? "EI " : "", | |
1579 | reg_val & (1<<23) ? "E1 " : "", | |
1580 | reg_val & (1<<22) ? "E0 " : ""); | |
1581 | } else { | |
1582 | pr_err("Error bits: %s%s%s%s%s%s%s\n", | |
1583 | reg_val & (1<<29) ? "ED " : "", | |
1584 | reg_val & (1<<28) ? "ET " : "", | |
1585 | reg_val & (1<<26) ? "EE " : "", | |
1586 | reg_val & (1<<25) ? "EB " : "", | |
1587 | reg_val & (1<<24) ? "EI " : "", | |
1588 | reg_val & (1<<23) ? "E1 " : "", | |
1589 | reg_val & (1<<22) ? "E0 " : ""); | |
1590 | } | |
1da177e4 LT |
1591 | printk("IDX: 0x%08x\n", reg_val & ((1<<22)-1)); |
1592 | ||
ec917c2c | 1593 | #if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64) |
1da177e4 LT |
1594 | if (reg_val & (1<<22)) |
1595 | printk("DErrAddr0: 0x%0*lx\n", field, read_c0_derraddr0()); | |
1596 | ||
1597 | if (reg_val & (1<<23)) | |
1598 | printk("DErrAddr1: 0x%0*lx\n", field, read_c0_derraddr1()); | |
1599 | #endif | |
1600 | ||
1601 | panic("Can't handle the cache error!"); | |
1602 | } | |
1603 | ||
75b5b5e0 LY |
1604 | asmlinkage void do_ftlb(void) |
1605 | { | |
1606 | const int field = 2 * sizeof(unsigned long); | |
1607 | unsigned int reg_val; | |
1608 | ||
1609 | /* For the moment, report the problem and hang. */ | |
1610 | if (cpu_has_mips_r2 && | |
721a9205 | 1611 | ((current_cpu_data.processor_id & 0xff0000) == PRID_COMP_MIPS)) { |
75b5b5e0 LY |
1612 | pr_err("FTLB error exception, cp0_ecc=0x%08x:\n", |
1613 | read_c0_ecc()); | |
1614 | pr_err("cp0_errorepc == %0*lx\n", field, read_c0_errorepc()); | |
1615 | reg_val = read_c0_cacheerr(); | |
1616 | pr_err("c0_cacheerr == %08x\n", reg_val); | |
1617 | ||
1618 | if ((reg_val & 0xc0000000) == 0xc0000000) { | |
1619 | pr_err("Decoded c0_cacheerr: FTLB parity error\n"); | |
1620 | } else { | |
1621 | pr_err("Decoded c0_cacheerr: %s cache fault in %s reference.\n", | |
1622 | reg_val & (1<<30) ? "secondary" : "primary", | |
1623 | reg_val & (1<<31) ? "data" : "insn"); | |
1624 | } | |
1625 | } else { | |
1626 | pr_err("FTLB error exception\n"); | |
1627 | } | |
1628 | /* Just print the cacheerr bits for now */ | |
1629 | cache_parity_error(); | |
1630 | } | |
1631 | ||
1da177e4 LT |
1632 | /* |
1633 | * SDBBP EJTAG debug exception handler. | |
1634 | * We skip the instruction and return to the next instruction. | |
1635 | */ | |
1636 | void ejtag_exception_handler(struct pt_regs *regs) | |
1637 | { | |
1638 | const int field = 2 * sizeof(unsigned long); | |
2a0b24f5 | 1639 | unsigned long depc, old_epc, old_ra; |
1da177e4 LT |
1640 | unsigned int debug; |
1641 | ||
70ae6126 | 1642 | printk(KERN_DEBUG "SDBBP EJTAG debug exception - not handled yet, just ignored!\n"); |
1da177e4 LT |
1643 | depc = read_c0_depc(); |
1644 | debug = read_c0_debug(); | |
70ae6126 | 1645 | printk(KERN_DEBUG "c0_depc = %0*lx, DEBUG = %08x\n", field, depc, debug); |
1da177e4 LT |
1646 | if (debug & 0x80000000) { |
1647 | /* | |
1648 | * In branch delay slot. | |
1649 | * We cheat a little bit here and use EPC to calculate the | |
1650 | * debug return address (DEPC). EPC is restored after the | |
1651 | * calculation. | |
1652 | */ | |
1653 | old_epc = regs->cp0_epc; | |
2a0b24f5 | 1654 | old_ra = regs->regs[31]; |
1da177e4 | 1655 | regs->cp0_epc = depc; |
2a0b24f5 | 1656 | compute_return_epc(regs); |
1da177e4 LT |
1657 | depc = regs->cp0_epc; |
1658 | regs->cp0_epc = old_epc; | |
2a0b24f5 | 1659 | regs->regs[31] = old_ra; |
1da177e4 LT |
1660 | } else |
1661 | depc += 4; | |
1662 | write_c0_depc(depc); | |
1663 | ||
1664 | #if 0 | |
70ae6126 | 1665 | printk(KERN_DEBUG "\n\n----- Enable EJTAG single stepping ----\n\n"); |
1da177e4 LT |
1666 | write_c0_debug(debug | 0x100); |
1667 | #endif | |
1668 | } | |
1669 | ||
1670 | /* | |
1671 | * NMI exception handler. | |
34bd92e2 | 1672 | * No lock; only written during early bootup by CPU 0. |
1da177e4 | 1673 | */ |
34bd92e2 KC |
1674 | static RAW_NOTIFIER_HEAD(nmi_chain); |
1675 | ||
1676 | int register_nmi_notifier(struct notifier_block *nb) | |
1677 | { | |
1678 | return raw_notifier_chain_register(&nmi_chain, nb); | |
1679 | } | |
1680 | ||
ff2d8b19 | 1681 | void __noreturn nmi_exception_handler(struct pt_regs *regs) |
1da177e4 | 1682 | { |
83e4da1e LY |
1683 | char str[100]; |
1684 | ||
34bd92e2 | 1685 | raw_notifier_call_chain(&nmi_chain, 0, regs); |
41c594ab | 1686 | bust_spinlocks(1); |
83e4da1e LY |
1687 | snprintf(str, 100, "CPU%d NMI taken, CP0_EPC=%lx\n", |
1688 | smp_processor_id(), regs->cp0_epc); | |
1689 | regs->cp0_epc = read_c0_errorepc(); | |
1690 | die(str, regs); | |
1da177e4 LT |
1691 | } |
1692 | ||
e01402b1 RB |
1693 | #define VECTORSPACING 0x100 /* for EI/VI mode */ |
1694 | ||
1695 | unsigned long ebase; | |
1da177e4 | 1696 | unsigned long exception_handlers[32]; |
e01402b1 | 1697 | unsigned long vi_handlers[64]; |
1da177e4 | 1698 | |
2d1b6e95 | 1699 | void __init *set_except_vector(int n, void *addr) |
1da177e4 LT |
1700 | { |
1701 | unsigned long handler = (unsigned long) addr; | |
b22d1b6a | 1702 | unsigned long old_handler; |
1da177e4 | 1703 | |
2a0b24f5 SH |
1704 | #ifdef CONFIG_CPU_MICROMIPS |
1705 | /* | |
1706 | * Only the TLB handlers are cache aligned with an even | |
1707 | * address. All other handlers are on an odd address and | |
1708 | * require no modification. Otherwise, MIPS32 mode will | |
1709 | * be entered when handling any TLB exceptions. That | |
1710 | * would be bad...since we must stay in microMIPS mode. | |
1711 | */ | |
1712 | if (!(handler & 0x1)) | |
1713 | handler |= 1; | |
1714 | #endif | |
b22d1b6a | 1715 | old_handler = xchg(&exception_handlers[n], handler); |
1da177e4 | 1716 | |
1da177e4 | 1717 | if (n == 0 && cpu_has_divec) { |
2a0b24f5 SH |
1718 | #ifdef CONFIG_CPU_MICROMIPS |
1719 | unsigned long jump_mask = ~((1 << 27) - 1); | |
1720 | #else | |
92bbe1b9 | 1721 | unsigned long jump_mask = ~((1 << 28) - 1); |
2a0b24f5 | 1722 | #endif |
92bbe1b9 FF |
1723 | u32 *buf = (u32 *)(ebase + 0x200); |
1724 | unsigned int k0 = 26; | |
1725 | if ((handler & jump_mask) == ((ebase + 0x200) & jump_mask)) { | |
1726 | uasm_i_j(&buf, handler & ~jump_mask); | |
1727 | uasm_i_nop(&buf); | |
1728 | } else { | |
1729 | UASM_i_LA(&buf, k0, handler); | |
1730 | uasm_i_jr(&buf, k0); | |
1731 | uasm_i_nop(&buf); | |
1732 | } | |
1733 | local_flush_icache_range(ebase + 0x200, (unsigned long)buf); | |
e01402b1 RB |
1734 | } |
1735 | return (void *)old_handler; | |
1736 | } | |
1737 | ||
86a1708a | 1738 | static void do_default_vi(void) |
6ba07e59 AN |
1739 | { |
1740 | show_regs(get_irq_regs()); | |
1741 | panic("Caught unexpected vectored interrupt."); | |
1742 | } | |
1743 | ||
ef300e42 | 1744 | static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs) |
e01402b1 RB |
1745 | { |
1746 | unsigned long handler; | |
1747 | unsigned long old_handler = vi_handlers[n]; | |
f6771dbb | 1748 | int srssets = current_cpu_data.srsets; |
2a0b24f5 | 1749 | u16 *h; |
e01402b1 RB |
1750 | unsigned char *b; |
1751 | ||
b72b7092 | 1752 | BUG_ON(!cpu_has_veic && !cpu_has_vint); |
e01402b1 RB |
1753 | |
1754 | if (addr == NULL) { | |
1755 | handler = (unsigned long) do_default_vi; | |
1756 | srs = 0; | |
41c594ab | 1757 | } else |
e01402b1 | 1758 | handler = (unsigned long) addr; |
2a0b24f5 | 1759 | vi_handlers[n] = handler; |
e01402b1 RB |
1760 | |
1761 | b = (unsigned char *)(ebase + 0x200 + n*VECTORSPACING); | |
1762 | ||
f6771dbb | 1763 | if (srs >= srssets) |
e01402b1 RB |
1764 | panic("Shadow register set %d not supported", srs); |
1765 | ||
1766 | if (cpu_has_veic) { | |
1767 | if (board_bind_eic_interrupt) | |
49a89efb | 1768 | board_bind_eic_interrupt(n, srs); |
41c594ab | 1769 | } else if (cpu_has_vint) { |
e01402b1 | 1770 | /* SRSMap is only defined if shadow sets are implemented */ |
f6771dbb | 1771 | if (srssets > 1) |
49a89efb | 1772 | change_c0_srsmap(0xf << n*4, srs << n*4); |
e01402b1 RB |
1773 | } |
1774 | ||
1775 | if (srs == 0) { | |
1776 | /* | |
1777 | * If no shadow set is selected then use the default handler | |
2a0b24f5 | 1778 | * that does normal register saving and standard interrupt exit |
e01402b1 | 1779 | */ |
e01402b1 RB |
1780 | extern char except_vec_vi, except_vec_vi_lui; |
1781 | extern char except_vec_vi_ori, except_vec_vi_end; | |
c65a5480 | 1782 | extern char rollback_except_vec_vi; |
f94d9a8e | 1783 | char *vec_start = using_rollback_handler() ? |
c65a5480 | 1784 | &rollback_except_vec_vi : &except_vec_vi; |
2a0b24f5 SH |
1785 | #if defined(CONFIG_CPU_MICROMIPS) || defined(CONFIG_CPU_BIG_ENDIAN) |
1786 | const int lui_offset = &except_vec_vi_lui - vec_start + 2; | |
1787 | const int ori_offset = &except_vec_vi_ori - vec_start + 2; | |
1788 | #else | |
c65a5480 AN |
1789 | const int lui_offset = &except_vec_vi_lui - vec_start; |
1790 | const int ori_offset = &except_vec_vi_ori - vec_start; | |
2a0b24f5 SH |
1791 | #endif |
1792 | const int handler_len = &except_vec_vi_end - vec_start; | |
e01402b1 RB |
1793 | |
1794 | if (handler_len > VECTORSPACING) { | |
1795 | /* | |
1796 | * Sigh... panicing won't help as the console | |
1797 | * is probably not configured :( | |
1798 | */ | |
49a89efb | 1799 | panic("VECTORSPACING too small"); |
e01402b1 RB |
1800 | } |
1801 | ||
2a0b24f5 SH |
1802 | set_handler(((unsigned long)b - ebase), vec_start, |
1803 | #ifdef CONFIG_CPU_MICROMIPS | |
1804 | (handler_len - 1)); | |
1805 | #else | |
1806 | handler_len); | |
1807 | #endif | |
2a0b24f5 SH |
1808 | h = (u16 *)(b + lui_offset); |
1809 | *h = (handler >> 16) & 0xffff; | |
1810 | h = (u16 *)(b + ori_offset); | |
1811 | *h = (handler & 0xffff); | |
e0cee3ee TB |
1812 | local_flush_icache_range((unsigned long)b, |
1813 | (unsigned long)(b+handler_len)); | |
e01402b1 RB |
1814 | } |
1815 | else { | |
1816 | /* | |
2a0b24f5 SH |
1817 | * In other cases jump directly to the interrupt handler. It |
1818 | * is the handler's responsibility to save registers if required | |
1819 | * (eg hi/lo) and return from the exception using "eret". | |
e01402b1 | 1820 | */ |
2a0b24f5 SH |
1821 | u32 insn; |
1822 | ||
1823 | h = (u16 *)b; | |
1824 | /* j handler */ | |
1825 | #ifdef CONFIG_CPU_MICROMIPS | |
1826 | insn = 0xd4000000 | (((u32)handler & 0x07ffffff) >> 1); | |
1827 | #else | |
1828 | insn = 0x08000000 | (((u32)handler & 0x0fffffff) >> 2); | |
1829 | #endif | |
1830 | h[0] = (insn >> 16) & 0xffff; | |
1831 | h[1] = insn & 0xffff; | |
1832 | h[2] = 0; | |
1833 | h[3] = 0; | |
e0cee3ee TB |
1834 | local_flush_icache_range((unsigned long)b, |
1835 | (unsigned long)(b+8)); | |
1da177e4 | 1836 | } |
e01402b1 | 1837 | |
1da177e4 LT |
1838 | return (void *)old_handler; |
1839 | } | |
1840 | ||
ef300e42 | 1841 | void *set_vi_handler(int n, vi_handler_t addr) |
e01402b1 | 1842 | { |
ff3eab2a | 1843 | return set_vi_srs_handler(n, addr, 0); |
e01402b1 | 1844 | } |
f41ae0b2 | 1845 | |
1da177e4 LT |
1846 | extern void tlb_init(void); |
1847 | ||
42f77542 RB |
1848 | /* |
1849 | * Timer interrupt | |
1850 | */ | |
1851 | int cp0_compare_irq; | |
68b6352c | 1852 | EXPORT_SYMBOL_GPL(cp0_compare_irq); |
010c108d | 1853 | int cp0_compare_irq_shift; |
42f77542 RB |
1854 | |
1855 | /* | |
1856 | * Performance counter IRQ or -1 if shared with timer | |
1857 | */ | |
1858 | int cp0_perfcount_irq; | |
1859 | EXPORT_SYMBOL_GPL(cp0_perfcount_irq); | |
1860 | ||
078a55fc | 1861 | static int noulri; |
bdc94eb4 CD |
1862 | |
1863 | static int __init ulri_disable(char *s) | |
1864 | { | |
1865 | pr_info("Disabling ulri\n"); | |
1866 | noulri = 1; | |
1867 | ||
1868 | return 1; | |
1869 | } | |
1870 | __setup("noulri", ulri_disable); | |
1871 | ||
ae4ce454 JH |
1872 | /* configure STATUS register */ |
1873 | static void configure_status(void) | |
1da177e4 | 1874 | { |
1da177e4 LT |
1875 | /* |
1876 | * Disable coprocessors and select 32-bit or 64-bit addressing | |
1877 | * and the 16/32 or 32/32 FPR register model. Reset the BEV | |
1878 | * flag that some firmware may have left set and the TS bit (for | |
1879 | * IP27). Set XX for ISA IV code to work. | |
1880 | */ | |
ae4ce454 | 1881 | unsigned int status_set = ST0_CU0; |
875d43e7 | 1882 | #ifdef CONFIG_64BIT |
1da177e4 LT |
1883 | status_set |= ST0_FR|ST0_KX|ST0_SX|ST0_UX; |
1884 | #endif | |
adb37892 | 1885 | if (current_cpu_data.isa_level & MIPS_CPU_ISA_IV) |
1da177e4 | 1886 | status_set |= ST0_XX; |
bbaf238b CD |
1887 | if (cpu_has_dsp) |
1888 | status_set |= ST0_MX; | |
1889 | ||
b38c7399 | 1890 | change_c0_status(ST0_CU|ST0_MX|ST0_RE|ST0_FR|ST0_BEV|ST0_TS|ST0_KX|ST0_SX|ST0_UX, |
1da177e4 | 1891 | status_set); |
ae4ce454 JH |
1892 | } |
1893 | ||
1894 | /* configure HWRENA register */ | |
1895 | static void configure_hwrena(void) | |
1896 | { | |
1897 | unsigned int hwrena = cpu_hwrena_impl_bits; | |
1da177e4 | 1898 | |
18d693b3 KC |
1899 | if (cpu_has_mips_r2) |
1900 | hwrena |= 0x0000000f; | |
a3692020 | 1901 | |
18d693b3 KC |
1902 | if (!noulri && cpu_has_userlocal) |
1903 | hwrena |= (1 << 29); | |
a3692020 | 1904 | |
18d693b3 KC |
1905 | if (hwrena) |
1906 | write_c0_hwrena(hwrena); | |
ae4ce454 | 1907 | } |
e01402b1 | 1908 | |
ae4ce454 JH |
1909 | static void configure_exception_vector(void) |
1910 | { | |
e01402b1 | 1911 | if (cpu_has_veic || cpu_has_vint) { |
9fb4c2b9 | 1912 | unsigned long sr = set_c0_status(ST0_BEV); |
49a89efb | 1913 | write_c0_ebase(ebase); |
9fb4c2b9 | 1914 | write_c0_status(sr); |
e01402b1 | 1915 | /* Setting vector spacing enables EI/VI mode */ |
49a89efb | 1916 | change_c0_intctl(0x3e0, VECTORSPACING); |
e01402b1 | 1917 | } |
d03d0a57 RB |
1918 | if (cpu_has_divec) { |
1919 | if (cpu_has_mipsmt) { | |
1920 | unsigned int vpflags = dvpe(); | |
1921 | set_c0_cause(CAUSEF_IV); | |
1922 | evpe(vpflags); | |
1923 | } else | |
1924 | set_c0_cause(CAUSEF_IV); | |
1925 | } | |
ae4ce454 JH |
1926 | } |
1927 | ||
1928 | void per_cpu_trap_init(bool is_boot_cpu) | |
1929 | { | |
1930 | unsigned int cpu = smp_processor_id(); | |
ae4ce454 JH |
1931 | |
1932 | configure_status(); | |
1933 | configure_hwrena(); | |
1934 | ||
ae4ce454 | 1935 | configure_exception_vector(); |
3b1d4ed5 RB |
1936 | |
1937 | /* | |
1938 | * Before R2 both interrupt numbers were fixed to 7, so on R2 only: | |
1939 | * | |
1940 | * o read IntCtl.IPTI to determine the timer interrupt | |
1941 | * o read IntCtl.IPPCI to determine the performance counter interrupt | |
1942 | */ | |
1943 | if (cpu_has_mips_r2) { | |
010c108d DV |
1944 | cp0_compare_irq_shift = CAUSEB_TI - CAUSEB_IP; |
1945 | cp0_compare_irq = (read_c0_intctl() >> INTCTLB_IPTI) & 7; | |
1946 | cp0_perfcount_irq = (read_c0_intctl() >> INTCTLB_IPPCI) & 7; | |
c3e838a2 | 1947 | if (cp0_perfcount_irq == cp0_compare_irq) |
3b1d4ed5 | 1948 | cp0_perfcount_irq = -1; |
c3e838a2 CD |
1949 | } else { |
1950 | cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ; | |
c6a4ebb9 | 1951 | cp0_compare_irq_shift = CP0_LEGACY_PERFCNT_IRQ; |
c3e838a2 | 1952 | cp0_perfcount_irq = -1; |
3b1d4ed5 RB |
1953 | } |
1954 | ||
48c4ac97 DD |
1955 | if (!cpu_data[cpu].asid_cache) |
1956 | cpu_data[cpu].asid_cache = ASID_FIRST_VERSION; | |
1da177e4 LT |
1957 | |
1958 | atomic_inc(&init_mm.mm_count); | |
1959 | current->active_mm = &init_mm; | |
1960 | BUG_ON(current->mm); | |
1961 | enter_lazy_tlb(&init_mm, current); | |
1962 | ||
6650df3c DD |
1963 | /* Boot CPU's cache setup in setup_arch(). */ |
1964 | if (!is_boot_cpu) | |
1965 | cpu_cache_init(); | |
41c594ab | 1966 | tlb_init(); |
3d8bfdd0 | 1967 | TLBMISS_HANDLER_SETUP(); |
1da177e4 LT |
1968 | } |
1969 | ||
e01402b1 | 1970 | /* Install CPU exception handler */ |
078a55fc | 1971 | void set_handler(unsigned long offset, void *addr, unsigned long size) |
e01402b1 | 1972 | { |
2a0b24f5 SH |
1973 | #ifdef CONFIG_CPU_MICROMIPS |
1974 | memcpy((void *)(ebase + offset), ((unsigned char *)addr - 1), size); | |
1975 | #else | |
e01402b1 | 1976 | memcpy((void *)(ebase + offset), addr, size); |
2a0b24f5 | 1977 | #endif |
e0cee3ee | 1978 | local_flush_icache_range(ebase + offset, ebase + offset + size); |
e01402b1 RB |
1979 | } |
1980 | ||
078a55fc | 1981 | static char panic_null_cerr[] = |
641e97f3 RB |
1982 | "Trying to set NULL cache error exception handler"; |
1983 | ||
42fe7ee3 RB |
1984 | /* |
1985 | * Install uncached CPU exception handler. | |
1986 | * This is suitable only for the cache error exception which is the only | |
1987 | * exception handler that is being run uncached. | |
1988 | */ | |
078a55fc | 1989 | void set_uncached_handler(unsigned long offset, void *addr, |
234fcd14 | 1990 | unsigned long size) |
e01402b1 | 1991 | { |
4f81b01a | 1992 | unsigned long uncached_ebase = CKSEG1ADDR(ebase); |
e01402b1 | 1993 | |
641e97f3 RB |
1994 | if (!addr) |
1995 | panic(panic_null_cerr); | |
1996 | ||
e01402b1 RB |
1997 | memcpy((void *)(uncached_ebase + offset), addr, size); |
1998 | } | |
1999 | ||
5b10496b AN |
2000 | static int __initdata rdhwr_noopt; |
2001 | static int __init set_rdhwr_noopt(char *str) | |
2002 | { | |
2003 | rdhwr_noopt = 1; | |
2004 | return 1; | |
2005 | } | |
2006 | ||
2007 | __setup("rdhwr_noopt", set_rdhwr_noopt); | |
2008 | ||
1da177e4 LT |
2009 | void __init trap_init(void) |
2010 | { | |
2a0b24f5 | 2011 | extern char except_vec3_generic; |
1da177e4 | 2012 | extern char except_vec4; |
2a0b24f5 | 2013 | extern char except_vec3_r4000; |
1da177e4 | 2014 | unsigned long i; |
c65a5480 AN |
2015 | |
2016 | check_wait(); | |
1da177e4 | 2017 | |
88547001 JW |
2018 | #if defined(CONFIG_KGDB) |
2019 | if (kgdb_early_setup) | |
70342287 | 2020 | return; /* Already done */ |
88547001 JW |
2021 | #endif |
2022 | ||
9fb4c2b9 CD |
2023 | if (cpu_has_veic || cpu_has_vint) { |
2024 | unsigned long size = 0x200 + VECTORSPACING*64; | |
2025 | ebase = (unsigned long) | |
2026 | __alloc_bootmem(size, 1 << fls(size), 0); | |
2027 | } else { | |
9843b030 SL |
2028 | #ifdef CONFIG_KVM_GUEST |
2029 | #define KVM_GUEST_KSEG0 0x40000000 | |
2030 | ebase = KVM_GUEST_KSEG0; | |
2031 | #else | |
2032 | ebase = CKSEG0; | |
2033 | #endif | |
566f74f6 DD |
2034 | if (cpu_has_mips_r2) |
2035 | ebase += (read_c0_ebase() & 0x3ffff000); | |
2036 | } | |
e01402b1 | 2037 | |
c6213c6c SH |
2038 | if (cpu_has_mmips) { |
2039 | unsigned int config3 = read_c0_config3(); | |
2040 | ||
2041 | if (IS_ENABLED(CONFIG_CPU_MICROMIPS)) | |
2042 | write_c0_config3(config3 | MIPS_CONF3_ISA_OE); | |
2043 | else | |
2044 | write_c0_config3(config3 & ~MIPS_CONF3_ISA_OE); | |
2045 | } | |
2046 | ||
6fb97eff KC |
2047 | if (board_ebase_setup) |
2048 | board_ebase_setup(); | |
6650df3c | 2049 | per_cpu_trap_init(true); |
1da177e4 LT |
2050 | |
2051 | /* | |
2052 | * Copy the generic exception handlers to their final destination. | |
2053 | * This will be overriden later as suitable for a particular | |
2054 | * configuration. | |
2055 | */ | |
e01402b1 | 2056 | set_handler(0x180, &except_vec3_generic, 0x80); |
1da177e4 LT |
2057 | |
2058 | /* | |
2059 | * Setup default vectors | |
2060 | */ | |
2061 | for (i = 0; i <= 31; i++) | |
2062 | set_except_vector(i, handle_reserved); | |
2063 | ||
2064 | /* | |
2065 | * Copy the EJTAG debug exception vector handler code to it's final | |
2066 | * destination. | |
2067 | */ | |
e01402b1 | 2068 | if (cpu_has_ejtag && board_ejtag_handler_setup) |
49a89efb | 2069 | board_ejtag_handler_setup(); |
1da177e4 LT |
2070 | |
2071 | /* | |
2072 | * Only some CPUs have the watch exceptions. | |
2073 | */ | |
2074 | if (cpu_has_watch) | |
2075 | set_except_vector(23, handle_watch); | |
2076 | ||
2077 | /* | |
e01402b1 | 2078 | * Initialise interrupt handlers |
1da177e4 | 2079 | */ |
e01402b1 RB |
2080 | if (cpu_has_veic || cpu_has_vint) { |
2081 | int nvec = cpu_has_veic ? 64 : 8; | |
2082 | for (i = 0; i < nvec; i++) | |
ff3eab2a | 2083 | set_vi_handler(i, NULL); |
e01402b1 RB |
2084 | } |
2085 | else if (cpu_has_divec) | |
2086 | set_handler(0x200, &except_vec4, 0x8); | |
1da177e4 LT |
2087 | |
2088 | /* | |
2089 | * Some CPUs can enable/disable for cache parity detection, but does | |
2090 | * it different ways. | |
2091 | */ | |
2092 | parity_protection_init(); | |
2093 | ||
2094 | /* | |
2095 | * The Data Bus Errors / Instruction Bus Errors are signaled | |
2096 | * by external hardware. Therefore these two exceptions | |
2097 | * may have board specific handlers. | |
2098 | */ | |
2099 | if (board_be_init) | |
2100 | board_be_init(); | |
2101 | ||
f94d9a8e RB |
2102 | set_except_vector(0, using_rollback_handler() ? rollback_handle_int |
2103 | : handle_int); | |
1da177e4 LT |
2104 | set_except_vector(1, handle_tlbm); |
2105 | set_except_vector(2, handle_tlbl); | |
2106 | set_except_vector(3, handle_tlbs); | |
2107 | ||
2108 | set_except_vector(4, handle_adel); | |
2109 | set_except_vector(5, handle_ades); | |
2110 | ||
2111 | set_except_vector(6, handle_ibe); | |
2112 | set_except_vector(7, handle_dbe); | |
2113 | ||
2114 | set_except_vector(8, handle_sys); | |
2115 | set_except_vector(9, handle_bp); | |
5b10496b AN |
2116 | set_except_vector(10, rdhwr_noopt ? handle_ri : |
2117 | (cpu_has_vtag_icache ? | |
2118 | handle_ri_rdhwr_vivt : handle_ri_rdhwr)); | |
1da177e4 LT |
2119 | set_except_vector(11, handle_cpu); |
2120 | set_except_vector(12, handle_ov); | |
2121 | set_except_vector(13, handle_tr); | |
2bcb3fbc | 2122 | set_except_vector(14, handle_msa_fpe); |
1da177e4 | 2123 | |
10cc3529 RB |
2124 | if (current_cpu_type() == CPU_R6000 || |
2125 | current_cpu_type() == CPU_R6000A) { | |
1da177e4 LT |
2126 | /* |
2127 | * The R6000 is the only R-series CPU that features a machine | |
2128 | * check exception (similar to the R4000 cache error) and | |
2129 | * unaligned ldc1/sdc1 exception. The handlers have not been | |
70342287 | 2130 | * written yet. Well, anyway there is no R6000 machine on the |
1da177e4 LT |
2131 | * current list of targets for Linux/MIPS. |
2132 | * (Duh, crap, there is someone with a triple R6k machine) | |
2133 | */ | |
2134 | //set_except_vector(14, handle_mc); | |
2135 | //set_except_vector(15, handle_ndc); | |
2136 | } | |
2137 | ||
e01402b1 RB |
2138 | |
2139 | if (board_nmi_handler_setup) | |
2140 | board_nmi_handler_setup(); | |
2141 | ||
e50c0a8f RB |
2142 | if (cpu_has_fpu && !cpu_has_nofpuex) |
2143 | set_except_vector(15, handle_fpe); | |
2144 | ||
75b5b5e0 | 2145 | set_except_vector(16, handle_ftlb); |
5890f70f LY |
2146 | |
2147 | if (cpu_has_rixiex) { | |
2148 | set_except_vector(19, tlb_do_page_fault_0); | |
2149 | set_except_vector(20, tlb_do_page_fault_0); | |
2150 | } | |
2151 | ||
1db1af84 | 2152 | set_except_vector(21, handle_msa); |
e50c0a8f RB |
2153 | set_except_vector(22, handle_mdmx); |
2154 | ||
2155 | if (cpu_has_mcheck) | |
2156 | set_except_vector(24, handle_mcheck); | |
2157 | ||
340ee4b9 RB |
2158 | if (cpu_has_mipsmt) |
2159 | set_except_vector(25, handle_mt); | |
2160 | ||
acaec427 | 2161 | set_except_vector(26, handle_dsp); |
e50c0a8f | 2162 | |
fcbf1dfd DD |
2163 | if (board_cache_error_setup) |
2164 | board_cache_error_setup(); | |
2165 | ||
e50c0a8f RB |
2166 | if (cpu_has_vce) |
2167 | /* Special exception: R4[04]00 uses also the divec space. */ | |
2a0b24f5 | 2168 | set_handler(0x180, &except_vec3_r4000, 0x100); |
e50c0a8f | 2169 | else if (cpu_has_4kex) |
2a0b24f5 | 2170 | set_handler(0x180, &except_vec3_generic, 0x80); |
e50c0a8f | 2171 | else |
2a0b24f5 | 2172 | set_handler(0x080, &except_vec3_generic, 0x80); |
e50c0a8f | 2173 | |
e0cee3ee | 2174 | local_flush_icache_range(ebase, ebase + 0x400); |
0510617b TB |
2175 | |
2176 | sort_extable(__start___dbe_table, __stop___dbe_table); | |
69f3a7de | 2177 | |
4483b159 | 2178 | cu2_notifier(default_cu2_call, 0x80000000); /* Run last */ |
1da177e4 | 2179 | } |
ae4ce454 JH |
2180 | |
2181 | static int trap_pm_notifier(struct notifier_block *self, unsigned long cmd, | |
2182 | void *v) | |
2183 | { | |
2184 | switch (cmd) { | |
2185 | case CPU_PM_ENTER_FAILED: | |
2186 | case CPU_PM_EXIT: | |
2187 | configure_status(); | |
2188 | configure_hwrena(); | |
2189 | configure_exception_vector(); | |
2190 | ||
2191 | /* Restore register with CPU number for TLB handlers */ | |
2192 | TLBMISS_HANDLER_RESTORE(); | |
2193 | ||
2194 | break; | |
2195 | } | |
2196 | ||
2197 | return NOTIFY_OK; | |
2198 | } | |
2199 | ||
2200 | static struct notifier_block trap_pm_notifier_block = { | |
2201 | .notifier_call = trap_pm_notifier, | |
2202 | }; | |
2203 | ||
2204 | static int __init trap_pm_init(void) | |
2205 | { | |
2206 | return cpu_pm_register_notifier(&trap_pm_notifier_block); | |
2207 | } | |
2208 | arch_initcall(trap_pm_init); |