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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public | |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
36ccf1c0 | 6 | * Copyright (C) 1994 - 1999, 2000, 01, 06 Ralf Baechle |
1da177e4 LT |
7 | * Copyright (C) 1995, 1996 Paul M. Antoine |
8 | * Copyright (C) 1998 Ulf Carlsson | |
9 | * Copyright (C) 1999 Silicon Graphics, Inc. | |
10 | * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com | |
11 | * Copyright (C) 2000, 01 MIPS Technologies, Inc. | |
60b0d655 | 12 | * Copyright (C) 2002, 2003, 2004, 2005, 2007 Maciej W. Rozycki |
1da177e4 | 13 | */ |
8e8a52ed | 14 | #include <linux/bug.h> |
60b0d655 | 15 | #include <linux/compiler.h> |
1da177e4 LT |
16 | #include <linux/init.h> |
17 | #include <linux/mm.h> | |
18 | #include <linux/module.h> | |
19 | #include <linux/sched.h> | |
20 | #include <linux/smp.h> | |
1da177e4 LT |
21 | #include <linux/spinlock.h> |
22 | #include <linux/kallsyms.h> | |
e01402b1 | 23 | #include <linux/bootmem.h> |
d4fd1989 | 24 | #include <linux/interrupt.h> |
39b8d525 | 25 | #include <linux/ptrace.h> |
88547001 JW |
26 | #include <linux/kgdb.h> |
27 | #include <linux/kdebug.h> | |
1da177e4 LT |
28 | |
29 | #include <asm/bootinfo.h> | |
30 | #include <asm/branch.h> | |
31 | #include <asm/break.h> | |
32 | #include <asm/cpu.h> | |
e50c0a8f | 33 | #include <asm/dsp.h> |
1da177e4 | 34 | #include <asm/fpu.h> |
ba3049ed | 35 | #include <asm/fpu_emulator.h> |
340ee4b9 RB |
36 | #include <asm/mipsregs.h> |
37 | #include <asm/mipsmtregs.h> | |
1da177e4 LT |
38 | #include <asm/module.h> |
39 | #include <asm/pgtable.h> | |
40 | #include <asm/ptrace.h> | |
41 | #include <asm/sections.h> | |
42 | #include <asm/system.h> | |
43 | #include <asm/tlbdebug.h> | |
44 | #include <asm/traps.h> | |
45 | #include <asm/uaccess.h> | |
b67b2b70 | 46 | #include <asm/watch.h> |
1da177e4 | 47 | #include <asm/mmu_context.h> |
1da177e4 | 48 | #include <asm/types.h> |
1df0f0ff | 49 | #include <asm/stacktrace.h> |
f9bb4cf3 | 50 | #include <asm/irq.h> |
1da177e4 | 51 | |
c65a5480 AN |
52 | extern void check_wait(void); |
53 | extern asmlinkage void r4k_wait(void); | |
54 | extern asmlinkage void rollback_handle_int(void); | |
e4ac58af | 55 | extern asmlinkage void handle_int(void); |
1da177e4 LT |
56 | extern asmlinkage void handle_tlbm(void); |
57 | extern asmlinkage void handle_tlbl(void); | |
58 | extern asmlinkage void handle_tlbs(void); | |
59 | extern asmlinkage void handle_adel(void); | |
60 | extern asmlinkage void handle_ades(void); | |
61 | extern asmlinkage void handle_ibe(void); | |
62 | extern asmlinkage void handle_dbe(void); | |
63 | extern asmlinkage void handle_sys(void); | |
64 | extern asmlinkage void handle_bp(void); | |
65 | extern asmlinkage void handle_ri(void); | |
5b10496b AN |
66 | extern asmlinkage void handle_ri_rdhwr_vivt(void); |
67 | extern asmlinkage void handle_ri_rdhwr(void); | |
1da177e4 LT |
68 | extern asmlinkage void handle_cpu(void); |
69 | extern asmlinkage void handle_ov(void); | |
70 | extern asmlinkage void handle_tr(void); | |
71 | extern asmlinkage void handle_fpe(void); | |
72 | extern asmlinkage void handle_mdmx(void); | |
73 | extern asmlinkage void handle_watch(void); | |
340ee4b9 | 74 | extern asmlinkage void handle_mt(void); |
e50c0a8f | 75 | extern asmlinkage void handle_dsp(void); |
1da177e4 LT |
76 | extern asmlinkage void handle_mcheck(void); |
77 | extern asmlinkage void handle_reserved(void); | |
78 | ||
12616ed2 | 79 | extern int fpu_emulator_cop1Handler(struct pt_regs *xcp, |
e04582b7 | 80 | struct mips_fpu_struct *ctx, int has_fpu); |
1da177e4 | 81 | |
f9bb4cf3 DD |
82 | #ifdef CONFIG_CPU_CAVIUM_OCTEON |
83 | extern asmlinkage void octeon_cop2_restore(struct octeon_cop2_state *task); | |
84 | #endif | |
85 | ||
1da177e4 LT |
86 | void (*board_be_init)(void); |
87 | int (*board_be_handler)(struct pt_regs *regs, int is_fixup); | |
e01402b1 RB |
88 | void (*board_nmi_handler_setup)(void); |
89 | void (*board_ejtag_handler_setup)(void); | |
90 | void (*board_bind_eic_interrupt)(int irq, int regset); | |
1da177e4 | 91 | |
1da177e4 | 92 | |
4d157d5e | 93 | static void show_raw_backtrace(unsigned long reg29) |
e889d78f | 94 | { |
39b8d525 | 95 | unsigned long *sp = (unsigned long *)(reg29 & ~3); |
e889d78f AN |
96 | unsigned long addr; |
97 | ||
98 | printk("Call Trace:"); | |
99 | #ifdef CONFIG_KALLSYMS | |
100 | printk("\n"); | |
101 | #endif | |
10220c88 TB |
102 | while (!kstack_end(sp)) { |
103 | unsigned long __user *p = | |
104 | (unsigned long __user *)(unsigned long)sp++; | |
105 | if (__get_user(addr, p)) { | |
106 | printk(" (Bad stack address)"); | |
107 | break; | |
39b8d525 | 108 | } |
10220c88 TB |
109 | if (__kernel_text_address(addr)) |
110 | print_ip_sym(addr); | |
e889d78f | 111 | } |
10220c88 | 112 | printk("\n"); |
e889d78f AN |
113 | } |
114 | ||
f66686f7 | 115 | #ifdef CONFIG_KALLSYMS |
1df0f0ff | 116 | int raw_show_trace; |
f66686f7 AN |
117 | static int __init set_raw_show_trace(char *str) |
118 | { | |
119 | raw_show_trace = 1; | |
120 | return 1; | |
121 | } | |
122 | __setup("raw_show_trace", set_raw_show_trace); | |
1df0f0ff | 123 | #endif |
4d157d5e | 124 | |
eae23f2c | 125 | static void show_backtrace(struct task_struct *task, const struct pt_regs *regs) |
f66686f7 | 126 | { |
4d157d5e FBH |
127 | unsigned long sp = regs->regs[29]; |
128 | unsigned long ra = regs->regs[31]; | |
f66686f7 | 129 | unsigned long pc = regs->cp0_epc; |
f66686f7 AN |
130 | |
131 | if (raw_show_trace || !__kernel_text_address(pc)) { | |
87151ae3 | 132 | show_raw_backtrace(sp); |
f66686f7 AN |
133 | return; |
134 | } | |
135 | printk("Call Trace:\n"); | |
4d157d5e | 136 | do { |
87151ae3 | 137 | print_ip_sym(pc); |
1924600c | 138 | pc = unwind_stack(task, &sp, pc, &ra); |
4d157d5e | 139 | } while (pc); |
f66686f7 AN |
140 | printk("\n"); |
141 | } | |
f66686f7 | 142 | |
1da177e4 LT |
143 | /* |
144 | * This routine abuses get_user()/put_user() to reference pointers | |
145 | * with at least a bit of error checking ... | |
146 | */ | |
eae23f2c RB |
147 | static void show_stacktrace(struct task_struct *task, |
148 | const struct pt_regs *regs) | |
1da177e4 LT |
149 | { |
150 | const int field = 2 * sizeof(unsigned long); | |
151 | long stackdata; | |
152 | int i; | |
5e0373b8 | 153 | unsigned long __user *sp = (unsigned long __user *)regs->regs[29]; |
1da177e4 LT |
154 | |
155 | printk("Stack :"); | |
156 | i = 0; | |
157 | while ((unsigned long) sp & (PAGE_SIZE - 1)) { | |
158 | if (i && ((i % (64 / field)) == 0)) | |
159 | printk("\n "); | |
160 | if (i > 39) { | |
161 | printk(" ..."); | |
162 | break; | |
163 | } | |
164 | ||
165 | if (__get_user(stackdata, sp++)) { | |
166 | printk(" (Bad stack address)"); | |
167 | break; | |
168 | } | |
169 | ||
170 | printk(" %0*lx", field, stackdata); | |
171 | i++; | |
172 | } | |
173 | printk("\n"); | |
87151ae3 | 174 | show_backtrace(task, regs); |
f66686f7 AN |
175 | } |
176 | ||
f66686f7 AN |
177 | void show_stack(struct task_struct *task, unsigned long *sp) |
178 | { | |
179 | struct pt_regs regs; | |
180 | if (sp) { | |
181 | regs.regs[29] = (unsigned long)sp; | |
182 | regs.regs[31] = 0; | |
183 | regs.cp0_epc = 0; | |
184 | } else { | |
185 | if (task && task != current) { | |
186 | regs.regs[29] = task->thread.reg29; | |
187 | regs.regs[31] = 0; | |
188 | regs.cp0_epc = task->thread.reg31; | |
189 | } else { | |
190 | prepare_frametrace(®s); | |
191 | } | |
192 | } | |
193 | show_stacktrace(task, ®s); | |
1da177e4 LT |
194 | } |
195 | ||
196 | /* | |
197 | * The architecture-independent dump_stack generator | |
198 | */ | |
199 | void dump_stack(void) | |
200 | { | |
1666a6fc | 201 | struct pt_regs regs; |
1da177e4 | 202 | |
1666a6fc FBH |
203 | prepare_frametrace(®s); |
204 | show_backtrace(current, ®s); | |
1da177e4 LT |
205 | } |
206 | ||
207 | EXPORT_SYMBOL(dump_stack); | |
208 | ||
e1bb8289 | 209 | static void show_code(unsigned int __user *pc) |
1da177e4 LT |
210 | { |
211 | long i; | |
39b8d525 | 212 | unsigned short __user *pc16 = NULL; |
1da177e4 LT |
213 | |
214 | printk("\nCode:"); | |
215 | ||
39b8d525 RB |
216 | if ((unsigned long)pc & 1) |
217 | pc16 = (unsigned short __user *)((unsigned long)pc & ~1); | |
1da177e4 LT |
218 | for(i = -3 ; i < 6 ; i++) { |
219 | unsigned int insn; | |
39b8d525 | 220 | if (pc16 ? __get_user(insn, pc16 + i) : __get_user(insn, pc + i)) { |
1da177e4 LT |
221 | printk(" (Bad address in epc)\n"); |
222 | break; | |
223 | } | |
39b8d525 | 224 | printk("%c%0*x%c", (i?' ':'<'), pc16 ? 4 : 8, insn, (i?' ':'>')); |
1da177e4 LT |
225 | } |
226 | } | |
227 | ||
eae23f2c | 228 | static void __show_regs(const struct pt_regs *regs) |
1da177e4 LT |
229 | { |
230 | const int field = 2 * sizeof(unsigned long); | |
231 | unsigned int cause = regs->cp0_cause; | |
232 | int i; | |
233 | ||
234 | printk("Cpu %d\n", smp_processor_id()); | |
235 | ||
236 | /* | |
237 | * Saved main processor registers | |
238 | */ | |
239 | for (i = 0; i < 32; ) { | |
240 | if ((i % 4) == 0) | |
241 | printk("$%2d :", i); | |
242 | if (i == 0) | |
243 | printk(" %0*lx", field, 0UL); | |
244 | else if (i == 26 || i == 27) | |
245 | printk(" %*s", field, ""); | |
246 | else | |
247 | printk(" %0*lx", field, regs->regs[i]); | |
248 | ||
249 | i++; | |
250 | if ((i % 4) == 0) | |
251 | printk("\n"); | |
252 | } | |
253 | ||
9693a853 FBH |
254 | #ifdef CONFIG_CPU_HAS_SMARTMIPS |
255 | printk("Acx : %0*lx\n", field, regs->acx); | |
256 | #endif | |
1da177e4 LT |
257 | printk("Hi : %0*lx\n", field, regs->hi); |
258 | printk("Lo : %0*lx\n", field, regs->lo); | |
259 | ||
260 | /* | |
261 | * Saved cp0 registers | |
262 | */ | |
b012cffe RB |
263 | printk("epc : %0*lx %pS\n", field, regs->cp0_epc, |
264 | (void *) regs->cp0_epc); | |
1da177e4 | 265 | printk(" %s\n", print_tainted()); |
b012cffe RB |
266 | printk("ra : %0*lx %pS\n", field, regs->regs[31], |
267 | (void *) regs->regs[31]); | |
1da177e4 LT |
268 | |
269 | printk("Status: %08x ", (uint32_t) regs->cp0_status); | |
270 | ||
3b2396d9 MR |
271 | if (current_cpu_data.isa_level == MIPS_CPU_ISA_I) { |
272 | if (regs->cp0_status & ST0_KUO) | |
273 | printk("KUo "); | |
274 | if (regs->cp0_status & ST0_IEO) | |
275 | printk("IEo "); | |
276 | if (regs->cp0_status & ST0_KUP) | |
277 | printk("KUp "); | |
278 | if (regs->cp0_status & ST0_IEP) | |
279 | printk("IEp "); | |
280 | if (regs->cp0_status & ST0_KUC) | |
281 | printk("KUc "); | |
282 | if (regs->cp0_status & ST0_IEC) | |
283 | printk("IEc "); | |
284 | } else { | |
285 | if (regs->cp0_status & ST0_KX) | |
286 | printk("KX "); | |
287 | if (regs->cp0_status & ST0_SX) | |
288 | printk("SX "); | |
289 | if (regs->cp0_status & ST0_UX) | |
290 | printk("UX "); | |
291 | switch (regs->cp0_status & ST0_KSU) { | |
292 | case KSU_USER: | |
293 | printk("USER "); | |
294 | break; | |
295 | case KSU_SUPERVISOR: | |
296 | printk("SUPERVISOR "); | |
297 | break; | |
298 | case KSU_KERNEL: | |
299 | printk("KERNEL "); | |
300 | break; | |
301 | default: | |
302 | printk("BAD_MODE "); | |
303 | break; | |
304 | } | |
305 | if (regs->cp0_status & ST0_ERL) | |
306 | printk("ERL "); | |
307 | if (regs->cp0_status & ST0_EXL) | |
308 | printk("EXL "); | |
309 | if (regs->cp0_status & ST0_IE) | |
310 | printk("IE "); | |
1da177e4 | 311 | } |
1da177e4 LT |
312 | printk("\n"); |
313 | ||
314 | printk("Cause : %08x\n", cause); | |
315 | ||
316 | cause = (cause & CAUSEF_EXCCODE) >> CAUSEB_EXCCODE; | |
317 | if (1 <= cause && cause <= 5) | |
318 | printk("BadVA : %0*lx\n", field, regs->cp0_badvaddr); | |
319 | ||
9966db25 RB |
320 | printk("PrId : %08x (%s)\n", read_c0_prid(), |
321 | cpu_name_string()); | |
1da177e4 LT |
322 | } |
323 | ||
eae23f2c RB |
324 | /* |
325 | * FIXME: really the generic show_regs should take a const pointer argument. | |
326 | */ | |
327 | void show_regs(struct pt_regs *regs) | |
328 | { | |
329 | __show_regs((struct pt_regs *)regs); | |
330 | } | |
331 | ||
332 | void show_registers(const struct pt_regs *regs) | |
1da177e4 | 333 | { |
39b8d525 RB |
334 | const int field = 2 * sizeof(unsigned long); |
335 | ||
eae23f2c | 336 | __show_regs(regs); |
1da177e4 | 337 | print_modules(); |
39b8d525 RB |
338 | printk("Process %s (pid: %d, threadinfo=%p, task=%p, tls=%0*lx)\n", |
339 | current->comm, current->pid, current_thread_info(), current, | |
340 | field, current_thread_info()->tp_value); | |
341 | if (cpu_has_userlocal) { | |
342 | unsigned long tls; | |
343 | ||
344 | tls = read_c0_userlocal(); | |
345 | if (tls != current_thread_info()->tp_value) | |
346 | printk("*HwTLS: %0*lx\n", field, tls); | |
347 | } | |
348 | ||
f66686f7 | 349 | show_stacktrace(current, regs); |
e1bb8289 | 350 | show_code((unsigned int __user *) regs->cp0_epc); |
1da177e4 LT |
351 | printk("\n"); |
352 | } | |
353 | ||
354 | static DEFINE_SPINLOCK(die_lock); | |
355 | ||
eae23f2c | 356 | void __noreturn die(const char * str, const struct pt_regs * regs) |
1da177e4 LT |
357 | { |
358 | static int die_counter; | |
41c594ab RB |
359 | #ifdef CONFIG_MIPS_MT_SMTC |
360 | unsigned long dvpret = dvpe(); | |
361 | #endif /* CONFIG_MIPS_MT_SMTC */ | |
1da177e4 LT |
362 | |
363 | console_verbose(); | |
364 | spin_lock_irq(&die_lock); | |
41c594ab RB |
365 | bust_spinlocks(1); |
366 | #ifdef CONFIG_MIPS_MT_SMTC | |
367 | mips_mt_regdump(dvpret); | |
368 | #endif /* CONFIG_MIPS_MT_SMTC */ | |
178086c8 | 369 | printk("%s[#%d]:\n", str, ++die_counter); |
1da177e4 | 370 | show_registers(regs); |
bcdcd8e7 | 371 | add_taint(TAINT_DIE); |
1da177e4 | 372 | spin_unlock_irq(&die_lock); |
d4fd1989 MB |
373 | |
374 | if (in_interrupt()) | |
375 | panic("Fatal exception in interrupt"); | |
376 | ||
377 | if (panic_on_oops) { | |
378 | printk(KERN_EMERG "Fatal exception: panic in 5 seconds\n"); | |
379 | ssleep(5); | |
380 | panic("Fatal exception"); | |
381 | } | |
382 | ||
1da177e4 LT |
383 | do_exit(SIGSEGV); |
384 | } | |
385 | ||
0510617b TB |
386 | extern struct exception_table_entry __start___dbe_table[]; |
387 | extern struct exception_table_entry __stop___dbe_table[]; | |
1da177e4 | 388 | |
b6dcec9b RB |
389 | __asm__( |
390 | " .section __dbe_table, \"a\"\n" | |
391 | " .previous \n"); | |
1da177e4 LT |
392 | |
393 | /* Given an address, look for it in the exception tables. */ | |
394 | static const struct exception_table_entry *search_dbe_tables(unsigned long addr) | |
395 | { | |
396 | const struct exception_table_entry *e; | |
397 | ||
398 | e = search_extable(__start___dbe_table, __stop___dbe_table - 1, addr); | |
399 | if (!e) | |
400 | e = search_module_dbetables(addr); | |
401 | return e; | |
402 | } | |
403 | ||
404 | asmlinkage void do_be(struct pt_regs *regs) | |
405 | { | |
406 | const int field = 2 * sizeof(unsigned long); | |
407 | const struct exception_table_entry *fixup = NULL; | |
408 | int data = regs->cp0_cause & 4; | |
409 | int action = MIPS_BE_FATAL; | |
410 | ||
411 | /* XXX For now. Fixme, this searches the wrong table ... */ | |
412 | if (data && !user_mode(regs)) | |
413 | fixup = search_dbe_tables(exception_epc(regs)); | |
414 | ||
415 | if (fixup) | |
416 | action = MIPS_BE_FIXUP; | |
417 | ||
418 | if (board_be_handler) | |
28fc582c | 419 | action = board_be_handler(regs, fixup != NULL); |
1da177e4 LT |
420 | |
421 | switch (action) { | |
422 | case MIPS_BE_DISCARD: | |
423 | return; | |
424 | case MIPS_BE_FIXUP: | |
425 | if (fixup) { | |
426 | regs->cp0_epc = fixup->nextinsn; | |
427 | return; | |
428 | } | |
429 | break; | |
430 | default: | |
431 | break; | |
432 | } | |
433 | ||
434 | /* | |
435 | * Assume it would be too dangerous to continue ... | |
436 | */ | |
437 | printk(KERN_ALERT "%s bus error, epc == %0*lx, ra == %0*lx\n", | |
438 | data ? "Data" : "Instruction", | |
439 | field, regs->cp0_epc, field, regs->regs[31]); | |
88547001 JW |
440 | if (notify_die(DIE_OOPS, "bus error", regs, SIGBUS, 0, 0) |
441 | == NOTIFY_STOP) | |
442 | return; | |
443 | ||
1da177e4 LT |
444 | die_if_kernel("Oops", regs); |
445 | force_sig(SIGBUS, current); | |
446 | } | |
447 | ||
1da177e4 | 448 | /* |
60b0d655 | 449 | * ll/sc, rdhwr, sync emulation |
1da177e4 LT |
450 | */ |
451 | ||
452 | #define OPCODE 0xfc000000 | |
453 | #define BASE 0x03e00000 | |
454 | #define RT 0x001f0000 | |
455 | #define OFFSET 0x0000ffff | |
456 | #define LL 0xc0000000 | |
457 | #define SC 0xe0000000 | |
60b0d655 | 458 | #define SPEC0 0x00000000 |
3c37026d RB |
459 | #define SPEC3 0x7c000000 |
460 | #define RD 0x0000f800 | |
461 | #define FUNC 0x0000003f | |
60b0d655 | 462 | #define SYNC 0x0000000f |
3c37026d | 463 | #define RDHWR 0x0000003b |
1da177e4 LT |
464 | |
465 | /* | |
466 | * The ll_bit is cleared by r*_switch.S | |
467 | */ | |
468 | ||
469 | unsigned long ll_bit; | |
470 | ||
471 | static struct task_struct *ll_task = NULL; | |
472 | ||
60b0d655 | 473 | static inline int simulate_ll(struct pt_regs *regs, unsigned int opcode) |
1da177e4 | 474 | { |
fe00f943 | 475 | unsigned long value, __user *vaddr; |
1da177e4 | 476 | long offset; |
1da177e4 LT |
477 | |
478 | /* | |
479 | * analyse the ll instruction that just caused a ri exception | |
480 | * and put the referenced address to addr. | |
481 | */ | |
482 | ||
483 | /* sign extend offset */ | |
484 | offset = opcode & OFFSET; | |
485 | offset <<= 16; | |
486 | offset >>= 16; | |
487 | ||
fe00f943 RB |
488 | vaddr = (unsigned long __user *) |
489 | ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset); | |
1da177e4 | 490 | |
60b0d655 MR |
491 | if ((unsigned long)vaddr & 3) |
492 | return SIGBUS; | |
493 | if (get_user(value, vaddr)) | |
494 | return SIGSEGV; | |
1da177e4 LT |
495 | |
496 | preempt_disable(); | |
497 | ||
498 | if (ll_task == NULL || ll_task == current) { | |
499 | ll_bit = 1; | |
500 | } else { | |
501 | ll_bit = 0; | |
502 | } | |
503 | ll_task = current; | |
504 | ||
505 | preempt_enable(); | |
506 | ||
507 | regs->regs[(opcode & RT) >> 16] = value; | |
508 | ||
60b0d655 | 509 | return 0; |
1da177e4 LT |
510 | } |
511 | ||
60b0d655 | 512 | static inline int simulate_sc(struct pt_regs *regs, unsigned int opcode) |
1da177e4 | 513 | { |
fe00f943 RB |
514 | unsigned long __user *vaddr; |
515 | unsigned long reg; | |
1da177e4 | 516 | long offset; |
1da177e4 LT |
517 | |
518 | /* | |
519 | * analyse the sc instruction that just caused a ri exception | |
520 | * and put the referenced address to addr. | |
521 | */ | |
522 | ||
523 | /* sign extend offset */ | |
524 | offset = opcode & OFFSET; | |
525 | offset <<= 16; | |
526 | offset >>= 16; | |
527 | ||
fe00f943 RB |
528 | vaddr = (unsigned long __user *) |
529 | ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset); | |
1da177e4 LT |
530 | reg = (opcode & RT) >> 16; |
531 | ||
60b0d655 MR |
532 | if ((unsigned long)vaddr & 3) |
533 | return SIGBUS; | |
1da177e4 LT |
534 | |
535 | preempt_disable(); | |
536 | ||
537 | if (ll_bit == 0 || ll_task != current) { | |
538 | regs->regs[reg] = 0; | |
539 | preempt_enable(); | |
60b0d655 | 540 | return 0; |
1da177e4 LT |
541 | } |
542 | ||
543 | preempt_enable(); | |
544 | ||
60b0d655 MR |
545 | if (put_user(regs->regs[reg], vaddr)) |
546 | return SIGSEGV; | |
1da177e4 LT |
547 | |
548 | regs->regs[reg] = 1; | |
549 | ||
60b0d655 | 550 | return 0; |
1da177e4 LT |
551 | } |
552 | ||
553 | /* | |
554 | * ll uses the opcode of lwc0 and sc uses the opcode of swc0. That is both | |
555 | * opcodes are supposed to result in coprocessor unusable exceptions if | |
556 | * executed on ll/sc-less processors. That's the theory. In practice a | |
557 | * few processors such as NEC's VR4100 throw reserved instruction exceptions | |
558 | * instead, so we're doing the emulation thing in both exception handlers. | |
559 | */ | |
60b0d655 | 560 | static int simulate_llsc(struct pt_regs *regs, unsigned int opcode) |
1da177e4 | 561 | { |
60b0d655 MR |
562 | if ((opcode & OPCODE) == LL) |
563 | return simulate_ll(regs, opcode); | |
564 | if ((opcode & OPCODE) == SC) | |
565 | return simulate_sc(regs, opcode); | |
1da177e4 | 566 | |
60b0d655 | 567 | return -1; /* Must be something else ... */ |
1da177e4 LT |
568 | } |
569 | ||
3c37026d RB |
570 | /* |
571 | * Simulate trapping 'rdhwr' instructions to provide user accessible | |
1f5826bd | 572 | * registers not implemented in hardware. |
3c37026d | 573 | */ |
60b0d655 | 574 | static int simulate_rdhwr(struct pt_regs *regs, unsigned int opcode) |
3c37026d | 575 | { |
dc8f6029 | 576 | struct thread_info *ti = task_thread_info(current); |
3c37026d RB |
577 | |
578 | if ((opcode & OPCODE) == SPEC3 && (opcode & FUNC) == RDHWR) { | |
579 | int rd = (opcode & RD) >> 11; | |
580 | int rt = (opcode & RT) >> 16; | |
581 | switch (rd) { | |
1f5826bd CD |
582 | case 0: /* CPU number */ |
583 | regs->regs[rt] = smp_processor_id(); | |
584 | return 0; | |
585 | case 1: /* SYNCI length */ | |
586 | regs->regs[rt] = min(current_cpu_data.dcache.linesz, | |
587 | current_cpu_data.icache.linesz); | |
588 | return 0; | |
589 | case 2: /* Read count register */ | |
590 | regs->regs[rt] = read_c0_count(); | |
591 | return 0; | |
592 | case 3: /* Count register resolution */ | |
593 | switch (current_cpu_data.cputype) { | |
594 | case CPU_20KC: | |
595 | case CPU_25KF: | |
596 | regs->regs[rt] = 1; | |
597 | break; | |
3c37026d | 598 | default: |
1f5826bd CD |
599 | regs->regs[rt] = 2; |
600 | } | |
601 | return 0; | |
602 | case 29: | |
603 | regs->regs[rt] = ti->tp_value; | |
604 | return 0; | |
605 | default: | |
606 | return -1; | |
3c37026d RB |
607 | } |
608 | } | |
609 | ||
56ebd51b | 610 | /* Not ours. */ |
60b0d655 MR |
611 | return -1; |
612 | } | |
e5679882 | 613 | |
60b0d655 MR |
614 | static int simulate_sync(struct pt_regs *regs, unsigned int opcode) |
615 | { | |
616 | if ((opcode & OPCODE) == SPEC0 && (opcode & FUNC) == SYNC) | |
617 | return 0; | |
618 | ||
619 | return -1; /* Must be something else ... */ | |
3c37026d RB |
620 | } |
621 | ||
1da177e4 LT |
622 | asmlinkage void do_ov(struct pt_regs *regs) |
623 | { | |
624 | siginfo_t info; | |
625 | ||
36ccf1c0 RB |
626 | die_if_kernel("Integer overflow", regs); |
627 | ||
1da177e4 LT |
628 | info.si_code = FPE_INTOVF; |
629 | info.si_signo = SIGFPE; | |
630 | info.si_errno = 0; | |
fe00f943 | 631 | info.si_addr = (void __user *) regs->cp0_epc; |
1da177e4 LT |
632 | force_sig_info(SIGFPE, &info, current); |
633 | } | |
634 | ||
635 | /* | |
636 | * XXX Delayed fp exceptions when doing a lazy ctx switch XXX | |
637 | */ | |
638 | asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31) | |
639 | { | |
948a34cf TS |
640 | siginfo_t info; |
641 | ||
88547001 JW |
642 | if (notify_die(DIE_FP, "FP exception", regs, SIGFPE, 0, 0) |
643 | == NOTIFY_STOP) | |
644 | return; | |
57725f9e CD |
645 | die_if_kernel("FP exception in kernel code", regs); |
646 | ||
1da177e4 LT |
647 | if (fcr31 & FPU_CSR_UNI_X) { |
648 | int sig; | |
649 | ||
1da177e4 | 650 | /* |
a3dddd56 | 651 | * Unimplemented operation exception. If we've got the full |
1da177e4 LT |
652 | * software emulator on-board, let's use it... |
653 | * | |
654 | * Force FPU to dump state into task/thread context. We're | |
655 | * moving a lot of data here for what is probably a single | |
656 | * instruction, but the alternative is to pre-decode the FP | |
657 | * register operands before invoking the emulator, which seems | |
658 | * a bit extreme for what should be an infrequent event. | |
659 | */ | |
cd21dfcf | 660 | /* Ensure 'resume' not overwrite saved fp context again. */ |
53dc8028 | 661 | lose_fpu(1); |
1da177e4 LT |
662 | |
663 | /* Run the emulator */ | |
49a89efb | 664 | sig = fpu_emulator_cop1Handler(regs, ¤t->thread.fpu, 1); |
1da177e4 LT |
665 | |
666 | /* | |
667 | * We can't allow the emulated instruction to leave any of | |
668 | * the cause bit set in $fcr31. | |
669 | */ | |
eae89076 | 670 | current->thread.fpu.fcr31 &= ~FPU_CSR_ALL_X; |
1da177e4 LT |
671 | |
672 | /* Restore the hardware register state */ | |
53dc8028 | 673 | own_fpu(1); /* Using the FPU again. */ |
1da177e4 LT |
674 | |
675 | /* If something went wrong, signal */ | |
676 | if (sig) | |
677 | force_sig(sig, current); | |
678 | ||
679 | return; | |
948a34cf TS |
680 | } else if (fcr31 & FPU_CSR_INV_X) |
681 | info.si_code = FPE_FLTINV; | |
682 | else if (fcr31 & FPU_CSR_DIV_X) | |
683 | info.si_code = FPE_FLTDIV; | |
684 | else if (fcr31 & FPU_CSR_OVF_X) | |
685 | info.si_code = FPE_FLTOVF; | |
686 | else if (fcr31 & FPU_CSR_UDF_X) | |
687 | info.si_code = FPE_FLTUND; | |
688 | else if (fcr31 & FPU_CSR_INE_X) | |
689 | info.si_code = FPE_FLTRES; | |
690 | else | |
691 | info.si_code = __SI_FAULT; | |
692 | info.si_signo = SIGFPE; | |
693 | info.si_errno = 0; | |
694 | info.si_addr = (void __user *) regs->cp0_epc; | |
695 | force_sig_info(SIGFPE, &info, current); | |
1da177e4 LT |
696 | } |
697 | ||
df270051 RB |
698 | static void do_trap_or_bp(struct pt_regs *regs, unsigned int code, |
699 | const char *str) | |
1da177e4 | 700 | { |
1da177e4 | 701 | siginfo_t info; |
df270051 | 702 | char b[40]; |
1da177e4 | 703 | |
88547001 JW |
704 | if (notify_die(DIE_TRAP, str, regs, code, 0, 0) == NOTIFY_STOP) |
705 | return; | |
706 | ||
1da177e4 | 707 | /* |
df270051 RB |
708 | * A short test says that IRIX 5.3 sends SIGTRAP for all trap |
709 | * insns, even for trap and break codes that indicate arithmetic | |
710 | * failures. Weird ... | |
1da177e4 LT |
711 | * But should we continue the brokenness??? --macro |
712 | */ | |
df270051 RB |
713 | switch (code) { |
714 | case BRK_OVERFLOW: | |
715 | case BRK_DIVZERO: | |
716 | scnprintf(b, sizeof(b), "%s instruction in kernel code", str); | |
717 | die_if_kernel(b, regs); | |
718 | if (code == BRK_DIVZERO) | |
1da177e4 LT |
719 | info.si_code = FPE_INTDIV; |
720 | else | |
721 | info.si_code = FPE_INTOVF; | |
722 | info.si_signo = SIGFPE; | |
723 | info.si_errno = 0; | |
fe00f943 | 724 | info.si_addr = (void __user *) regs->cp0_epc; |
1da177e4 LT |
725 | force_sig_info(SIGFPE, &info, current); |
726 | break; | |
63dc68a8 | 727 | case BRK_BUG: |
df270051 RB |
728 | die_if_kernel("Kernel bug detected", regs); |
729 | force_sig(SIGTRAP, current); | |
63dc68a8 | 730 | break; |
ba3049ed RB |
731 | case BRK_MEMU: |
732 | /* | |
733 | * Address errors may be deliberately induced by the FPU | |
734 | * emulator to retake control of the CPU after executing the | |
735 | * instruction in the delay slot of an emulated branch. | |
736 | * | |
737 | * Terminate if exception was recognized as a delay slot return | |
738 | * otherwise handle as normal. | |
739 | */ | |
740 | if (do_dsemulret(regs)) | |
741 | return; | |
742 | ||
743 | die_if_kernel("Math emu break/trap", regs); | |
744 | force_sig(SIGTRAP, current); | |
745 | break; | |
1da177e4 | 746 | default: |
df270051 RB |
747 | scnprintf(b, sizeof(b), "%s instruction in kernel code", str); |
748 | die_if_kernel(b, regs); | |
1da177e4 LT |
749 | force_sig(SIGTRAP, current); |
750 | } | |
df270051 RB |
751 | } |
752 | ||
753 | asmlinkage void do_bp(struct pt_regs *regs) | |
754 | { | |
755 | unsigned int opcode, bcode; | |
756 | ||
757 | if (__get_user(opcode, (unsigned int __user *) exception_epc(regs))) | |
758 | goto out_sigsegv; | |
759 | ||
760 | /* | |
761 | * There is the ancient bug in the MIPS assemblers that the break | |
762 | * code starts left to bit 16 instead to bit 6 in the opcode. | |
763 | * Gas is bug-compatible, but not always, grrr... | |
764 | * We handle both cases with a simple heuristics. --macro | |
765 | */ | |
766 | bcode = ((opcode >> 6) & ((1 << 20) - 1)); | |
767 | if (bcode >= (1 << 10)) | |
768 | bcode >>= 10; | |
769 | ||
770 | do_trap_or_bp(regs, bcode, "Break"); | |
90fccb13 | 771 | return; |
e5679882 RB |
772 | |
773 | out_sigsegv: | |
774 | force_sig(SIGSEGV, current); | |
1da177e4 LT |
775 | } |
776 | ||
777 | asmlinkage void do_tr(struct pt_regs *regs) | |
778 | { | |
779 | unsigned int opcode, tcode = 0; | |
1da177e4 | 780 | |
ba755f8e | 781 | if (__get_user(opcode, (unsigned int __user *) exception_epc(regs))) |
e5679882 | 782 | goto out_sigsegv; |
1da177e4 LT |
783 | |
784 | /* Immediate versions don't provide a code. */ | |
785 | if (!(opcode & OPCODE)) | |
786 | tcode = ((opcode >> 6) & ((1 << 10) - 1)); | |
787 | ||
df270051 | 788 | do_trap_or_bp(regs, tcode, "Trap"); |
90fccb13 | 789 | return; |
e5679882 RB |
790 | |
791 | out_sigsegv: | |
792 | force_sig(SIGSEGV, current); | |
1da177e4 LT |
793 | } |
794 | ||
795 | asmlinkage void do_ri(struct pt_regs *regs) | |
796 | { | |
60b0d655 MR |
797 | unsigned int __user *epc = (unsigned int __user *)exception_epc(regs); |
798 | unsigned long old_epc = regs->cp0_epc; | |
799 | unsigned int opcode = 0; | |
800 | int status = -1; | |
1da177e4 | 801 | |
88547001 JW |
802 | if (notify_die(DIE_RI, "RI Fault", regs, SIGSEGV, 0, 0) |
803 | == NOTIFY_STOP) | |
804 | return; | |
805 | ||
60b0d655 | 806 | die_if_kernel("Reserved instruction in kernel code", regs); |
1da177e4 | 807 | |
60b0d655 | 808 | if (unlikely(compute_return_epc(regs) < 0)) |
3c37026d RB |
809 | return; |
810 | ||
60b0d655 MR |
811 | if (unlikely(get_user(opcode, epc) < 0)) |
812 | status = SIGSEGV; | |
813 | ||
814 | if (!cpu_has_llsc && status < 0) | |
815 | status = simulate_llsc(regs, opcode); | |
816 | ||
817 | if (status < 0) | |
818 | status = simulate_rdhwr(regs, opcode); | |
819 | ||
820 | if (status < 0) | |
821 | status = simulate_sync(regs, opcode); | |
822 | ||
823 | if (status < 0) | |
824 | status = SIGILL; | |
825 | ||
826 | if (unlikely(status > 0)) { | |
827 | regs->cp0_epc = old_epc; /* Undo skip-over. */ | |
828 | force_sig(status, current); | |
829 | } | |
1da177e4 LT |
830 | } |
831 | ||
d223a861 RB |
832 | /* |
833 | * MIPS MT processors may have fewer FPU contexts than CPU threads. If we've | |
834 | * emulated more than some threshold number of instructions, force migration to | |
835 | * a "CPU" that has FP support. | |
836 | */ | |
837 | static void mt_ase_fp_affinity(void) | |
838 | { | |
839 | #ifdef CONFIG_MIPS_MT_FPAFF | |
840 | if (mt_fpemul_threshold > 0 && | |
841 | ((current->thread.emulated_fp++ > mt_fpemul_threshold))) { | |
842 | /* | |
843 | * If there's no FPU present, or if the application has already | |
844 | * restricted the allowed set to exclude any CPUs with FPUs, | |
845 | * we'll skip the procedure. | |
846 | */ | |
847 | if (cpus_intersects(current->cpus_allowed, mt_fpu_cpumask)) { | |
848 | cpumask_t tmask; | |
849 | ||
9cc12363 KK |
850 | current->thread.user_cpus_allowed |
851 | = current->cpus_allowed; | |
852 | cpus_and(tmask, current->cpus_allowed, | |
853 | mt_fpu_cpumask); | |
d223a861 | 854 | set_cpus_allowed(current, tmask); |
293c5bd1 | 855 | set_thread_flag(TIF_FPUBOUND); |
d223a861 RB |
856 | } |
857 | } | |
858 | #endif /* CONFIG_MIPS_MT_FPAFF */ | |
859 | } | |
860 | ||
1da177e4 LT |
861 | asmlinkage void do_cpu(struct pt_regs *regs) |
862 | { | |
60b0d655 MR |
863 | unsigned int __user *epc; |
864 | unsigned long old_epc; | |
865 | unsigned int opcode; | |
1da177e4 | 866 | unsigned int cpid; |
60b0d655 | 867 | int status; |
f9bb4cf3 | 868 | unsigned long __maybe_unused flags; |
1da177e4 | 869 | |
5323180d AN |
870 | die_if_kernel("do_cpu invoked from kernel context!", regs); |
871 | ||
1da177e4 LT |
872 | cpid = (regs->cp0_cause >> CAUSEB_CE) & 3; |
873 | ||
874 | switch (cpid) { | |
875 | case 0: | |
60b0d655 MR |
876 | epc = (unsigned int __user *)exception_epc(regs); |
877 | old_epc = regs->cp0_epc; | |
878 | opcode = 0; | |
879 | status = -1; | |
1da177e4 | 880 | |
60b0d655 | 881 | if (unlikely(compute_return_epc(regs) < 0)) |
1da177e4 | 882 | return; |
3c37026d | 883 | |
60b0d655 MR |
884 | if (unlikely(get_user(opcode, epc) < 0)) |
885 | status = SIGSEGV; | |
886 | ||
887 | if (!cpu_has_llsc && status < 0) | |
888 | status = simulate_llsc(regs, opcode); | |
889 | ||
890 | if (status < 0) | |
891 | status = simulate_rdhwr(regs, opcode); | |
892 | ||
893 | if (status < 0) | |
894 | status = SIGILL; | |
895 | ||
896 | if (unlikely(status > 0)) { | |
897 | regs->cp0_epc = old_epc; /* Undo skip-over. */ | |
898 | force_sig(status, current); | |
899 | } | |
900 | ||
901 | return; | |
1da177e4 LT |
902 | |
903 | case 1: | |
53dc8028 AN |
904 | if (used_math()) /* Using the FPU again. */ |
905 | own_fpu(1); | |
906 | else { /* First time FPU user. */ | |
1da177e4 LT |
907 | init_fpu(); |
908 | set_used_math(); | |
909 | } | |
910 | ||
5323180d | 911 | if (!raw_cpu_has_fpu) { |
e04582b7 | 912 | int sig; |
e04582b7 AN |
913 | sig = fpu_emulator_cop1Handler(regs, |
914 | ¤t->thread.fpu, 0); | |
1da177e4 LT |
915 | if (sig) |
916 | force_sig(sig, current); | |
d223a861 RB |
917 | else |
918 | mt_ase_fp_affinity(); | |
1da177e4 LT |
919 | } |
920 | ||
1da177e4 LT |
921 | return; |
922 | ||
923 | case 2: | |
f9bb4cf3 DD |
924 | #ifdef CONFIG_CPU_CAVIUM_OCTEON |
925 | prefetch(¤t->thread.cp2); | |
926 | local_irq_save(flags); | |
927 | KSTK_STATUS(current) |= ST0_CU2; | |
928 | status = read_c0_status(); | |
929 | write_c0_status(status | ST0_CU2); | |
930 | octeon_cop2_restore(&(current->thread.cp2)); | |
931 | write_c0_status(status & ~ST0_CU2); | |
932 | local_irq_restore(flags); | |
933 | return; | |
934 | #endif | |
1da177e4 LT |
935 | case 3: |
936 | break; | |
937 | } | |
938 | ||
939 | force_sig(SIGILL, current); | |
940 | } | |
941 | ||
942 | asmlinkage void do_mdmx(struct pt_regs *regs) | |
943 | { | |
944 | force_sig(SIGILL, current); | |
945 | } | |
946 | ||
8bc6d05b DD |
947 | /* |
948 | * Called with interrupts disabled. | |
949 | */ | |
1da177e4 LT |
950 | asmlinkage void do_watch(struct pt_regs *regs) |
951 | { | |
b67b2b70 DD |
952 | u32 cause; |
953 | ||
1da177e4 | 954 | /* |
b67b2b70 DD |
955 | * Clear WP (bit 22) bit of cause register so we don't loop |
956 | * forever. | |
1da177e4 | 957 | */ |
b67b2b70 DD |
958 | cause = read_c0_cause(); |
959 | cause &= ~(1 << 22); | |
960 | write_c0_cause(cause); | |
961 | ||
962 | /* | |
963 | * If the current thread has the watch registers loaded, save | |
964 | * their values and send SIGTRAP. Otherwise another thread | |
965 | * left the registers set, clear them and continue. | |
966 | */ | |
967 | if (test_tsk_thread_flag(current, TIF_LOAD_WATCH)) { | |
968 | mips_read_watch_registers(); | |
8bc6d05b | 969 | local_irq_enable(); |
b67b2b70 | 970 | force_sig(SIGTRAP, current); |
8bc6d05b | 971 | } else { |
b67b2b70 | 972 | mips_clear_watch_registers(); |
8bc6d05b DD |
973 | local_irq_enable(); |
974 | } | |
1da177e4 LT |
975 | } |
976 | ||
977 | asmlinkage void do_mcheck(struct pt_regs *regs) | |
978 | { | |
cac4bcbc RB |
979 | const int field = 2 * sizeof(unsigned long); |
980 | int multi_match = regs->cp0_status & ST0_TS; | |
981 | ||
1da177e4 | 982 | show_regs(regs); |
cac4bcbc RB |
983 | |
984 | if (multi_match) { | |
985 | printk("Index : %0x\n", read_c0_index()); | |
986 | printk("Pagemask: %0x\n", read_c0_pagemask()); | |
987 | printk("EntryHi : %0*lx\n", field, read_c0_entryhi()); | |
988 | printk("EntryLo0: %0*lx\n", field, read_c0_entrylo0()); | |
989 | printk("EntryLo1: %0*lx\n", field, read_c0_entrylo1()); | |
990 | printk("\n"); | |
991 | dump_tlb_all(); | |
992 | } | |
993 | ||
e1bb8289 | 994 | show_code((unsigned int __user *) regs->cp0_epc); |
cac4bcbc | 995 | |
1da177e4 LT |
996 | /* |
997 | * Some chips may have other causes of machine check (e.g. SB1 | |
998 | * graduation timer) | |
999 | */ | |
1000 | panic("Caught Machine Check exception - %scaused by multiple " | |
1001 | "matching entries in the TLB.", | |
cac4bcbc | 1002 | (multi_match) ? "" : "not "); |
1da177e4 LT |
1003 | } |
1004 | ||
340ee4b9 RB |
1005 | asmlinkage void do_mt(struct pt_regs *regs) |
1006 | { | |
41c594ab RB |
1007 | int subcode; |
1008 | ||
41c594ab RB |
1009 | subcode = (read_vpe_c0_vpecontrol() & VPECONTROL_EXCPT) |
1010 | >> VPECONTROL_EXCPT_SHIFT; | |
1011 | switch (subcode) { | |
1012 | case 0: | |
e35a5e35 | 1013 | printk(KERN_DEBUG "Thread Underflow\n"); |
41c594ab RB |
1014 | break; |
1015 | case 1: | |
e35a5e35 | 1016 | printk(KERN_DEBUG "Thread Overflow\n"); |
41c594ab RB |
1017 | break; |
1018 | case 2: | |
e35a5e35 | 1019 | printk(KERN_DEBUG "Invalid YIELD Qualifier\n"); |
41c594ab RB |
1020 | break; |
1021 | case 3: | |
e35a5e35 | 1022 | printk(KERN_DEBUG "Gating Storage Exception\n"); |
41c594ab RB |
1023 | break; |
1024 | case 4: | |
e35a5e35 | 1025 | printk(KERN_DEBUG "YIELD Scheduler Exception\n"); |
41c594ab RB |
1026 | break; |
1027 | case 5: | |
e35a5e35 | 1028 | printk(KERN_DEBUG "Gating Storage Schedulier Exception\n"); |
41c594ab RB |
1029 | break; |
1030 | default: | |
e35a5e35 | 1031 | printk(KERN_DEBUG "*** UNKNOWN THREAD EXCEPTION %d ***\n", |
41c594ab RB |
1032 | subcode); |
1033 | break; | |
1034 | } | |
340ee4b9 RB |
1035 | die_if_kernel("MIPS MT Thread exception in kernel", regs); |
1036 | ||
1037 | force_sig(SIGILL, current); | |
1038 | } | |
1039 | ||
1040 | ||
e50c0a8f RB |
1041 | asmlinkage void do_dsp(struct pt_regs *regs) |
1042 | { | |
1043 | if (cpu_has_dsp) | |
1044 | panic("Unexpected DSP exception\n"); | |
1045 | ||
1046 | force_sig(SIGILL, current); | |
1047 | } | |
1048 | ||
1da177e4 LT |
1049 | asmlinkage void do_reserved(struct pt_regs *regs) |
1050 | { | |
1051 | /* | |
1052 | * Game over - no way to handle this if it ever occurs. Most probably | |
1053 | * caused by a new unknown cpu type or after another deadly | |
1054 | * hard/software error. | |
1055 | */ | |
1056 | show_regs(regs); | |
1057 | panic("Caught reserved exception %ld - should not happen.", | |
1058 | (regs->cp0_cause & 0x7f) >> 2); | |
1059 | } | |
1060 | ||
39b8d525 RB |
1061 | static int __initdata l1parity = 1; |
1062 | static int __init nol1parity(char *s) | |
1063 | { | |
1064 | l1parity = 0; | |
1065 | return 1; | |
1066 | } | |
1067 | __setup("nol1par", nol1parity); | |
1068 | static int __initdata l2parity = 1; | |
1069 | static int __init nol2parity(char *s) | |
1070 | { | |
1071 | l2parity = 0; | |
1072 | return 1; | |
1073 | } | |
1074 | __setup("nol2par", nol2parity); | |
1075 | ||
1da177e4 LT |
1076 | /* |
1077 | * Some MIPS CPUs can enable/disable for cache parity detection, but do | |
1078 | * it different ways. | |
1079 | */ | |
1080 | static inline void parity_protection_init(void) | |
1081 | { | |
10cc3529 | 1082 | switch (current_cpu_type()) { |
1da177e4 | 1083 | case CPU_24K: |
98a41de9 | 1084 | case CPU_34K: |
39b8d525 RB |
1085 | case CPU_74K: |
1086 | case CPU_1004K: | |
1087 | { | |
1088 | #define ERRCTL_PE 0x80000000 | |
1089 | #define ERRCTL_L2P 0x00800000 | |
1090 | unsigned long errctl; | |
1091 | unsigned int l1parity_present, l2parity_present; | |
1092 | ||
1093 | errctl = read_c0_ecc(); | |
1094 | errctl &= ~(ERRCTL_PE|ERRCTL_L2P); | |
1095 | ||
1096 | /* probe L1 parity support */ | |
1097 | write_c0_ecc(errctl | ERRCTL_PE); | |
1098 | back_to_back_c0_hazard(); | |
1099 | l1parity_present = (read_c0_ecc() & ERRCTL_PE); | |
1100 | ||
1101 | /* probe L2 parity support */ | |
1102 | write_c0_ecc(errctl|ERRCTL_L2P); | |
1103 | back_to_back_c0_hazard(); | |
1104 | l2parity_present = (read_c0_ecc() & ERRCTL_L2P); | |
1105 | ||
1106 | if (l1parity_present && l2parity_present) { | |
1107 | if (l1parity) | |
1108 | errctl |= ERRCTL_PE; | |
1109 | if (l1parity ^ l2parity) | |
1110 | errctl |= ERRCTL_L2P; | |
1111 | } else if (l1parity_present) { | |
1112 | if (l1parity) | |
1113 | errctl |= ERRCTL_PE; | |
1114 | } else if (l2parity_present) { | |
1115 | if (l2parity) | |
1116 | errctl |= ERRCTL_L2P; | |
1117 | } else { | |
1118 | /* No parity available */ | |
1119 | } | |
1120 | ||
1121 | printk(KERN_INFO "Writing ErrCtl register=%08lx\n", errctl); | |
1122 | ||
1123 | write_c0_ecc(errctl); | |
1124 | back_to_back_c0_hazard(); | |
1125 | errctl = read_c0_ecc(); | |
1126 | printk(KERN_INFO "Readback ErrCtl register=%08lx\n", errctl); | |
1127 | ||
1128 | if (l1parity_present) | |
1129 | printk(KERN_INFO "Cache parity protection %sabled\n", | |
1130 | (errctl & ERRCTL_PE) ? "en" : "dis"); | |
1131 | ||
1132 | if (l2parity_present) { | |
1133 | if (l1parity_present && l1parity) | |
1134 | errctl ^= ERRCTL_L2P; | |
1135 | printk(KERN_INFO "L2 cache parity protection %sabled\n", | |
1136 | (errctl & ERRCTL_L2P) ? "en" : "dis"); | |
1137 | } | |
1138 | } | |
1139 | break; | |
1140 | ||
1da177e4 | 1141 | case CPU_5KC: |
14f18b7f RB |
1142 | write_c0_ecc(0x80000000); |
1143 | back_to_back_c0_hazard(); | |
1144 | /* Set the PE bit (bit 31) in the c0_errctl register. */ | |
1145 | printk(KERN_INFO "Cache parity protection %sabled\n", | |
1146 | (read_c0_ecc() & 0x80000000) ? "en" : "dis"); | |
1da177e4 LT |
1147 | break; |
1148 | case CPU_20KC: | |
1149 | case CPU_25KF: | |
1150 | /* Clear the DE bit (bit 16) in the c0_status register. */ | |
1151 | printk(KERN_INFO "Enable cache parity protection for " | |
1152 | "MIPS 20KC/25KF CPUs.\n"); | |
1153 | clear_c0_status(ST0_DE); | |
1154 | break; | |
1155 | default: | |
1156 | break; | |
1157 | } | |
1158 | } | |
1159 | ||
1160 | asmlinkage void cache_parity_error(void) | |
1161 | { | |
1162 | const int field = 2 * sizeof(unsigned long); | |
1163 | unsigned int reg_val; | |
1164 | ||
1165 | /* For the moment, report the problem and hang. */ | |
1166 | printk("Cache error exception:\n"); | |
1167 | printk("cp0_errorepc == %0*lx\n", field, read_c0_errorepc()); | |
1168 | reg_val = read_c0_cacheerr(); | |
1169 | printk("c0_cacheerr == %08x\n", reg_val); | |
1170 | ||
1171 | printk("Decoded c0_cacheerr: %s cache fault in %s reference.\n", | |
1172 | reg_val & (1<<30) ? "secondary" : "primary", | |
1173 | reg_val & (1<<31) ? "data" : "insn"); | |
1174 | printk("Error bits: %s%s%s%s%s%s%s\n", | |
1175 | reg_val & (1<<29) ? "ED " : "", | |
1176 | reg_val & (1<<28) ? "ET " : "", | |
1177 | reg_val & (1<<26) ? "EE " : "", | |
1178 | reg_val & (1<<25) ? "EB " : "", | |
1179 | reg_val & (1<<24) ? "EI " : "", | |
1180 | reg_val & (1<<23) ? "E1 " : "", | |
1181 | reg_val & (1<<22) ? "E0 " : ""); | |
1182 | printk("IDX: 0x%08x\n", reg_val & ((1<<22)-1)); | |
1183 | ||
ec917c2c | 1184 | #if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64) |
1da177e4 LT |
1185 | if (reg_val & (1<<22)) |
1186 | printk("DErrAddr0: 0x%0*lx\n", field, read_c0_derraddr0()); | |
1187 | ||
1188 | if (reg_val & (1<<23)) | |
1189 | printk("DErrAddr1: 0x%0*lx\n", field, read_c0_derraddr1()); | |
1190 | #endif | |
1191 | ||
1192 | panic("Can't handle the cache error!"); | |
1193 | } | |
1194 | ||
1195 | /* | |
1196 | * SDBBP EJTAG debug exception handler. | |
1197 | * We skip the instruction and return to the next instruction. | |
1198 | */ | |
1199 | void ejtag_exception_handler(struct pt_regs *regs) | |
1200 | { | |
1201 | const int field = 2 * sizeof(unsigned long); | |
1202 | unsigned long depc, old_epc; | |
1203 | unsigned int debug; | |
1204 | ||
70ae6126 | 1205 | printk(KERN_DEBUG "SDBBP EJTAG debug exception - not handled yet, just ignored!\n"); |
1da177e4 LT |
1206 | depc = read_c0_depc(); |
1207 | debug = read_c0_debug(); | |
70ae6126 | 1208 | printk(KERN_DEBUG "c0_depc = %0*lx, DEBUG = %08x\n", field, depc, debug); |
1da177e4 LT |
1209 | if (debug & 0x80000000) { |
1210 | /* | |
1211 | * In branch delay slot. | |
1212 | * We cheat a little bit here and use EPC to calculate the | |
1213 | * debug return address (DEPC). EPC is restored after the | |
1214 | * calculation. | |
1215 | */ | |
1216 | old_epc = regs->cp0_epc; | |
1217 | regs->cp0_epc = depc; | |
1218 | __compute_return_epc(regs); | |
1219 | depc = regs->cp0_epc; | |
1220 | regs->cp0_epc = old_epc; | |
1221 | } else | |
1222 | depc += 4; | |
1223 | write_c0_depc(depc); | |
1224 | ||
1225 | #if 0 | |
70ae6126 | 1226 | printk(KERN_DEBUG "\n\n----- Enable EJTAG single stepping ----\n\n"); |
1da177e4 LT |
1227 | write_c0_debug(debug | 0x100); |
1228 | #endif | |
1229 | } | |
1230 | ||
1231 | /* | |
1232 | * NMI exception handler. | |
1233 | */ | |
34412c72 | 1234 | NORET_TYPE void ATTRIB_NORET nmi_exception_handler(struct pt_regs *regs) |
1da177e4 | 1235 | { |
41c594ab | 1236 | bust_spinlocks(1); |
1da177e4 LT |
1237 | printk("NMI taken!!!!\n"); |
1238 | die("NMI", regs); | |
1da177e4 LT |
1239 | } |
1240 | ||
e01402b1 RB |
1241 | #define VECTORSPACING 0x100 /* for EI/VI mode */ |
1242 | ||
1243 | unsigned long ebase; | |
1da177e4 | 1244 | unsigned long exception_handlers[32]; |
e01402b1 | 1245 | unsigned long vi_handlers[64]; |
1da177e4 LT |
1246 | |
1247 | /* | |
1248 | * As a side effect of the way this is implemented we're limited | |
1249 | * to interrupt handlers in the address range from | |
1250 | * KSEG0 <= x < KSEG0 + 256mb on the Nevada. Oh well ... | |
1251 | */ | |
1252 | void *set_except_vector(int n, void *addr) | |
1253 | { | |
1254 | unsigned long handler = (unsigned long) addr; | |
1255 | unsigned long old_handler = exception_handlers[n]; | |
1256 | ||
1257 | exception_handlers[n] = handler; | |
1258 | if (n == 0 && cpu_has_divec) { | |
ec70f65e RB |
1259 | *(u32 *)(ebase + 0x200) = 0x08000000 | |
1260 | (0x03ffffff & (handler >> 2)); | |
e0cee3ee | 1261 | local_flush_icache_range(ebase + 0x200, ebase + 0x204); |
e01402b1 RB |
1262 | } |
1263 | return (void *)old_handler; | |
1264 | } | |
1265 | ||
6ba07e59 AN |
1266 | static asmlinkage void do_default_vi(void) |
1267 | { | |
1268 | show_regs(get_irq_regs()); | |
1269 | panic("Caught unexpected vectored interrupt."); | |
1270 | } | |
1271 | ||
ef300e42 | 1272 | static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs) |
e01402b1 RB |
1273 | { |
1274 | unsigned long handler; | |
1275 | unsigned long old_handler = vi_handlers[n]; | |
f6771dbb | 1276 | int srssets = current_cpu_data.srsets; |
e01402b1 RB |
1277 | u32 *w; |
1278 | unsigned char *b; | |
1279 | ||
1280 | if (!cpu_has_veic && !cpu_has_vint) | |
1281 | BUG(); | |
1282 | ||
1283 | if (addr == NULL) { | |
1284 | handler = (unsigned long) do_default_vi; | |
1285 | srs = 0; | |
41c594ab | 1286 | } else |
e01402b1 RB |
1287 | handler = (unsigned long) addr; |
1288 | vi_handlers[n] = (unsigned long) addr; | |
1289 | ||
1290 | b = (unsigned char *)(ebase + 0x200 + n*VECTORSPACING); | |
1291 | ||
f6771dbb | 1292 | if (srs >= srssets) |
e01402b1 RB |
1293 | panic("Shadow register set %d not supported", srs); |
1294 | ||
1295 | if (cpu_has_veic) { | |
1296 | if (board_bind_eic_interrupt) | |
49a89efb | 1297 | board_bind_eic_interrupt(n, srs); |
41c594ab | 1298 | } else if (cpu_has_vint) { |
e01402b1 | 1299 | /* SRSMap is only defined if shadow sets are implemented */ |
f6771dbb | 1300 | if (srssets > 1) |
49a89efb | 1301 | change_c0_srsmap(0xf << n*4, srs << n*4); |
e01402b1 RB |
1302 | } |
1303 | ||
1304 | if (srs == 0) { | |
1305 | /* | |
1306 | * If no shadow set is selected then use the default handler | |
1307 | * that does normal register saving and a standard interrupt exit | |
1308 | */ | |
1309 | ||
1310 | extern char except_vec_vi, except_vec_vi_lui; | |
1311 | extern char except_vec_vi_ori, except_vec_vi_end; | |
c65a5480 AN |
1312 | extern char rollback_except_vec_vi; |
1313 | char *vec_start = (cpu_wait == r4k_wait) ? | |
1314 | &rollback_except_vec_vi : &except_vec_vi; | |
41c594ab RB |
1315 | #ifdef CONFIG_MIPS_MT_SMTC |
1316 | /* | |
1317 | * We need to provide the SMTC vectored interrupt handler | |
1318 | * not only with the address of the handler, but with the | |
1319 | * Status.IM bit to be masked before going there. | |
1320 | */ | |
1321 | extern char except_vec_vi_mori; | |
c65a5480 | 1322 | const int mori_offset = &except_vec_vi_mori - vec_start; |
41c594ab | 1323 | #endif /* CONFIG_MIPS_MT_SMTC */ |
c65a5480 AN |
1324 | const int handler_len = &except_vec_vi_end - vec_start; |
1325 | const int lui_offset = &except_vec_vi_lui - vec_start; | |
1326 | const int ori_offset = &except_vec_vi_ori - vec_start; | |
e01402b1 RB |
1327 | |
1328 | if (handler_len > VECTORSPACING) { | |
1329 | /* | |
1330 | * Sigh... panicing won't help as the console | |
1331 | * is probably not configured :( | |
1332 | */ | |
49a89efb | 1333 | panic("VECTORSPACING too small"); |
e01402b1 RB |
1334 | } |
1335 | ||
c65a5480 | 1336 | memcpy(b, vec_start, handler_len); |
41c594ab | 1337 | #ifdef CONFIG_MIPS_MT_SMTC |
8e8a52ed RB |
1338 | BUG_ON(n > 7); /* Vector index %d exceeds SMTC maximum. */ |
1339 | ||
41c594ab RB |
1340 | w = (u32 *)(b + mori_offset); |
1341 | *w = (*w & 0xffff0000) | (0x100 << n); | |
1342 | #endif /* CONFIG_MIPS_MT_SMTC */ | |
e01402b1 RB |
1343 | w = (u32 *)(b + lui_offset); |
1344 | *w = (*w & 0xffff0000) | (((u32)handler >> 16) & 0xffff); | |
1345 | w = (u32 *)(b + ori_offset); | |
1346 | *w = (*w & 0xffff0000) | ((u32)handler & 0xffff); | |
e0cee3ee TB |
1347 | local_flush_icache_range((unsigned long)b, |
1348 | (unsigned long)(b+handler_len)); | |
e01402b1 RB |
1349 | } |
1350 | else { | |
1351 | /* | |
1352 | * In other cases jump directly to the interrupt handler | |
1353 | * | |
1354 | * It is the handlers responsibility to save registers if required | |
1355 | * (eg hi/lo) and return from the exception using "eret" | |
1356 | */ | |
1357 | w = (u32 *)b; | |
1358 | *w++ = 0x08000000 | (((u32)handler >> 2) & 0x03fffff); /* j handler */ | |
1359 | *w = 0; | |
e0cee3ee TB |
1360 | local_flush_icache_range((unsigned long)b, |
1361 | (unsigned long)(b+8)); | |
1da177e4 | 1362 | } |
e01402b1 | 1363 | |
1da177e4 LT |
1364 | return (void *)old_handler; |
1365 | } | |
1366 | ||
ef300e42 | 1367 | void *set_vi_handler(int n, vi_handler_t addr) |
e01402b1 | 1368 | { |
ff3eab2a | 1369 | return set_vi_srs_handler(n, addr, 0); |
e01402b1 | 1370 | } |
f41ae0b2 | 1371 | |
1da177e4 LT |
1372 | /* |
1373 | * This is used by native signal handling | |
1374 | */ | |
53dc8028 AN |
1375 | asmlinkage int (*save_fp_context)(struct sigcontext __user *sc); |
1376 | asmlinkage int (*restore_fp_context)(struct sigcontext __user *sc); | |
1da177e4 | 1377 | |
53dc8028 AN |
1378 | extern asmlinkage int _save_fp_context(struct sigcontext __user *sc); |
1379 | extern asmlinkage int _restore_fp_context(struct sigcontext __user *sc); | |
1da177e4 | 1380 | |
53dc8028 AN |
1381 | extern asmlinkage int fpu_emulator_save_context(struct sigcontext __user *sc); |
1382 | extern asmlinkage int fpu_emulator_restore_context(struct sigcontext __user *sc); | |
1da177e4 | 1383 | |
41c594ab | 1384 | #ifdef CONFIG_SMP |
53dc8028 | 1385 | static int smp_save_fp_context(struct sigcontext __user *sc) |
41c594ab | 1386 | { |
53dc8028 | 1387 | return raw_cpu_has_fpu |
41c594ab RB |
1388 | ? _save_fp_context(sc) |
1389 | : fpu_emulator_save_context(sc); | |
1390 | } | |
1391 | ||
53dc8028 | 1392 | static int smp_restore_fp_context(struct sigcontext __user *sc) |
41c594ab | 1393 | { |
53dc8028 | 1394 | return raw_cpu_has_fpu |
41c594ab RB |
1395 | ? _restore_fp_context(sc) |
1396 | : fpu_emulator_restore_context(sc); | |
1397 | } | |
1398 | #endif | |
1399 | ||
1da177e4 LT |
1400 | static inline void signal_init(void) |
1401 | { | |
41c594ab RB |
1402 | #ifdef CONFIG_SMP |
1403 | /* For now just do the cpu_has_fpu check when the functions are invoked */ | |
1404 | save_fp_context = smp_save_fp_context; | |
1405 | restore_fp_context = smp_restore_fp_context; | |
1406 | #else | |
1da177e4 LT |
1407 | if (cpu_has_fpu) { |
1408 | save_fp_context = _save_fp_context; | |
1409 | restore_fp_context = _restore_fp_context; | |
1410 | } else { | |
1411 | save_fp_context = fpu_emulator_save_context; | |
1412 | restore_fp_context = fpu_emulator_restore_context; | |
1413 | } | |
41c594ab | 1414 | #endif |
1da177e4 LT |
1415 | } |
1416 | ||
1417 | #ifdef CONFIG_MIPS32_COMPAT | |
1418 | ||
1419 | /* | |
1420 | * This is used by 32-bit signal stuff on the 64-bit kernel | |
1421 | */ | |
53dc8028 AN |
1422 | asmlinkage int (*save_fp_context32)(struct sigcontext32 __user *sc); |
1423 | asmlinkage int (*restore_fp_context32)(struct sigcontext32 __user *sc); | |
1da177e4 | 1424 | |
53dc8028 AN |
1425 | extern asmlinkage int _save_fp_context32(struct sigcontext32 __user *sc); |
1426 | extern asmlinkage int _restore_fp_context32(struct sigcontext32 __user *sc); | |
1da177e4 | 1427 | |
53dc8028 AN |
1428 | extern asmlinkage int fpu_emulator_save_context32(struct sigcontext32 __user *sc); |
1429 | extern asmlinkage int fpu_emulator_restore_context32(struct sigcontext32 __user *sc); | |
1da177e4 LT |
1430 | |
1431 | static inline void signal32_init(void) | |
1432 | { | |
1433 | if (cpu_has_fpu) { | |
1434 | save_fp_context32 = _save_fp_context32; | |
1435 | restore_fp_context32 = _restore_fp_context32; | |
1436 | } else { | |
1437 | save_fp_context32 = fpu_emulator_save_context32; | |
1438 | restore_fp_context32 = fpu_emulator_restore_context32; | |
1439 | } | |
1440 | } | |
1441 | #endif | |
1442 | ||
1443 | extern void cpu_cache_init(void); | |
1444 | extern void tlb_init(void); | |
1d40cfcd | 1445 | extern void flush_tlb_handlers(void); |
1da177e4 | 1446 | |
42f77542 RB |
1447 | /* |
1448 | * Timer interrupt | |
1449 | */ | |
1450 | int cp0_compare_irq; | |
1451 | ||
1452 | /* | |
1453 | * Performance counter IRQ or -1 if shared with timer | |
1454 | */ | |
1455 | int cp0_perfcount_irq; | |
1456 | EXPORT_SYMBOL_GPL(cp0_perfcount_irq); | |
1457 | ||
bdc94eb4 CD |
1458 | static int __cpuinitdata noulri; |
1459 | ||
1460 | static int __init ulri_disable(char *s) | |
1461 | { | |
1462 | pr_info("Disabling ulri\n"); | |
1463 | noulri = 1; | |
1464 | ||
1465 | return 1; | |
1466 | } | |
1467 | __setup("noulri", ulri_disable); | |
1468 | ||
234fcd14 | 1469 | void __cpuinit per_cpu_trap_init(void) |
1da177e4 LT |
1470 | { |
1471 | unsigned int cpu = smp_processor_id(); | |
1472 | unsigned int status_set = ST0_CU0; | |
41c594ab RB |
1473 | #ifdef CONFIG_MIPS_MT_SMTC |
1474 | int secondaryTC = 0; | |
1475 | int bootTC = (cpu == 0); | |
1476 | ||
1477 | /* | |
1478 | * Only do per_cpu_trap_init() for first TC of Each VPE. | |
1479 | * Note that this hack assumes that the SMTC init code | |
1480 | * assigns TCs consecutively and in ascending order. | |
1481 | */ | |
1482 | ||
1483 | if (((read_c0_tcbind() & TCBIND_CURTC) != 0) && | |
1484 | ((read_c0_tcbind() & TCBIND_CURVPE) == cpu_data[cpu - 1].vpe_id)) | |
1485 | secondaryTC = 1; | |
1486 | #endif /* CONFIG_MIPS_MT_SMTC */ | |
1da177e4 LT |
1487 | |
1488 | /* | |
1489 | * Disable coprocessors and select 32-bit or 64-bit addressing | |
1490 | * and the 16/32 or 32/32 FPR register model. Reset the BEV | |
1491 | * flag that some firmware may have left set and the TS bit (for | |
1492 | * IP27). Set XX for ISA IV code to work. | |
1493 | */ | |
875d43e7 | 1494 | #ifdef CONFIG_64BIT |
1da177e4 LT |
1495 | status_set |= ST0_FR|ST0_KX|ST0_SX|ST0_UX; |
1496 | #endif | |
1497 | if (current_cpu_data.isa_level == MIPS_CPU_ISA_IV) | |
1498 | status_set |= ST0_XX; | |
bbaf238b CD |
1499 | if (cpu_has_dsp) |
1500 | status_set |= ST0_MX; | |
1501 | ||
b38c7399 | 1502 | change_c0_status(ST0_CU|ST0_MX|ST0_RE|ST0_FR|ST0_BEV|ST0_TS|ST0_KX|ST0_SX|ST0_UX, |
1da177e4 LT |
1503 | status_set); |
1504 | ||
a3692020 RB |
1505 | if (cpu_has_mips_r2) { |
1506 | unsigned int enable = 0x0000000f; | |
1507 | ||
bdc94eb4 | 1508 | if (!noulri && cpu_has_userlocal) |
a3692020 RB |
1509 | enable |= (1 << 29); |
1510 | ||
1511 | write_c0_hwrena(enable); | |
1512 | } | |
e01402b1 | 1513 | |
f9bb4cf3 DD |
1514 | #ifdef CONFIG_CPU_CAVIUM_OCTEON |
1515 | write_c0_hwrena(0xc000000f); /* Octeon has register 30 and 31 */ | |
1516 | #endif | |
1517 | ||
41c594ab RB |
1518 | #ifdef CONFIG_MIPS_MT_SMTC |
1519 | if (!secondaryTC) { | |
1520 | #endif /* CONFIG_MIPS_MT_SMTC */ | |
1521 | ||
e01402b1 | 1522 | if (cpu_has_veic || cpu_has_vint) { |
49a89efb | 1523 | write_c0_ebase(ebase); |
e01402b1 | 1524 | /* Setting vector spacing enables EI/VI mode */ |
49a89efb | 1525 | change_c0_intctl(0x3e0, VECTORSPACING); |
e01402b1 | 1526 | } |
d03d0a57 RB |
1527 | if (cpu_has_divec) { |
1528 | if (cpu_has_mipsmt) { | |
1529 | unsigned int vpflags = dvpe(); | |
1530 | set_c0_cause(CAUSEF_IV); | |
1531 | evpe(vpflags); | |
1532 | } else | |
1533 | set_c0_cause(CAUSEF_IV); | |
1534 | } | |
3b1d4ed5 RB |
1535 | |
1536 | /* | |
1537 | * Before R2 both interrupt numbers were fixed to 7, so on R2 only: | |
1538 | * | |
1539 | * o read IntCtl.IPTI to determine the timer interrupt | |
1540 | * o read IntCtl.IPPCI to determine the performance counter interrupt | |
1541 | */ | |
1542 | if (cpu_has_mips_r2) { | |
49a89efb RB |
1543 | cp0_compare_irq = (read_c0_intctl() >> 29) & 7; |
1544 | cp0_perfcount_irq = (read_c0_intctl() >> 26) & 7; | |
c3e838a2 | 1545 | if (cp0_perfcount_irq == cp0_compare_irq) |
3b1d4ed5 | 1546 | cp0_perfcount_irq = -1; |
c3e838a2 CD |
1547 | } else { |
1548 | cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ; | |
1549 | cp0_perfcount_irq = -1; | |
3b1d4ed5 RB |
1550 | } |
1551 | ||
41c594ab RB |
1552 | #ifdef CONFIG_MIPS_MT_SMTC |
1553 | } | |
1554 | #endif /* CONFIG_MIPS_MT_SMTC */ | |
1da177e4 LT |
1555 | |
1556 | cpu_data[cpu].asid_cache = ASID_FIRST_VERSION; | |
1557 | TLBMISS_HANDLER_SETUP(); | |
1558 | ||
1559 | atomic_inc(&init_mm.mm_count); | |
1560 | current->active_mm = &init_mm; | |
1561 | BUG_ON(current->mm); | |
1562 | enter_lazy_tlb(&init_mm, current); | |
1563 | ||
41c594ab RB |
1564 | #ifdef CONFIG_MIPS_MT_SMTC |
1565 | if (bootTC) { | |
1566 | #endif /* CONFIG_MIPS_MT_SMTC */ | |
1567 | cpu_cache_init(); | |
1568 | tlb_init(); | |
1569 | #ifdef CONFIG_MIPS_MT_SMTC | |
6a05888d RB |
1570 | } else if (!secondaryTC) { |
1571 | /* | |
1572 | * First TC in non-boot VPE must do subset of tlb_init() | |
1573 | * for MMU countrol registers. | |
1574 | */ | |
1575 | write_c0_pagemask(PM_DEFAULT_MASK); | |
1576 | write_c0_wired(0); | |
41c594ab RB |
1577 | } |
1578 | #endif /* CONFIG_MIPS_MT_SMTC */ | |
1da177e4 LT |
1579 | } |
1580 | ||
e01402b1 | 1581 | /* Install CPU exception handler */ |
49a89efb | 1582 | void __init set_handler(unsigned long offset, void *addr, unsigned long size) |
e01402b1 RB |
1583 | { |
1584 | memcpy((void *)(ebase + offset), addr, size); | |
e0cee3ee | 1585 | local_flush_icache_range(ebase + offset, ebase + offset + size); |
e01402b1 RB |
1586 | } |
1587 | ||
234fcd14 | 1588 | static char panic_null_cerr[] __cpuinitdata = |
641e97f3 RB |
1589 | "Trying to set NULL cache error exception handler"; |
1590 | ||
42fe7ee3 RB |
1591 | /* |
1592 | * Install uncached CPU exception handler. | |
1593 | * This is suitable only for the cache error exception which is the only | |
1594 | * exception handler that is being run uncached. | |
1595 | */ | |
234fcd14 RB |
1596 | void __cpuinit set_uncached_handler(unsigned long offset, void *addr, |
1597 | unsigned long size) | |
e01402b1 RB |
1598 | { |
1599 | #ifdef CONFIG_32BIT | |
1600 | unsigned long uncached_ebase = KSEG1ADDR(ebase); | |
1601 | #endif | |
1602 | #ifdef CONFIG_64BIT | |
1603 | unsigned long uncached_ebase = TO_UNCAC(ebase); | |
1604 | #endif | |
566f74f6 | 1605 | if (cpu_has_mips_r2) |
42fe7ee3 | 1606 | uncached_ebase += (read_c0_ebase() & 0x3ffff000); |
e01402b1 | 1607 | |
641e97f3 RB |
1608 | if (!addr) |
1609 | panic(panic_null_cerr); | |
1610 | ||
e01402b1 RB |
1611 | memcpy((void *)(uncached_ebase + offset), addr, size); |
1612 | } | |
1613 | ||
5b10496b AN |
1614 | static int __initdata rdhwr_noopt; |
1615 | static int __init set_rdhwr_noopt(char *str) | |
1616 | { | |
1617 | rdhwr_noopt = 1; | |
1618 | return 1; | |
1619 | } | |
1620 | ||
1621 | __setup("rdhwr_noopt", set_rdhwr_noopt); | |
1622 | ||
1da177e4 LT |
1623 | void __init trap_init(void) |
1624 | { | |
1625 | extern char except_vec3_generic, except_vec3_r4000; | |
1da177e4 LT |
1626 | extern char except_vec4; |
1627 | unsigned long i; | |
c65a5480 AN |
1628 | int rollback; |
1629 | ||
1630 | check_wait(); | |
1631 | rollback = (cpu_wait == r4k_wait); | |
1da177e4 | 1632 | |
88547001 JW |
1633 | #if defined(CONFIG_KGDB) |
1634 | if (kgdb_early_setup) | |
1635 | return; /* Already done */ | |
1636 | #endif | |
1637 | ||
e01402b1 | 1638 | if (cpu_has_veic || cpu_has_vint) |
49a89efb | 1639 | ebase = (unsigned long) alloc_bootmem_low_pages(0x200 + VECTORSPACING*64); |
566f74f6 | 1640 | else { |
e01402b1 | 1641 | ebase = CAC_BASE; |
566f74f6 DD |
1642 | if (cpu_has_mips_r2) |
1643 | ebase += (read_c0_ebase() & 0x3ffff000); | |
1644 | } | |
e01402b1 | 1645 | |
1da177e4 LT |
1646 | per_cpu_trap_init(); |
1647 | ||
1648 | /* | |
1649 | * Copy the generic exception handlers to their final destination. | |
1650 | * This will be overriden later as suitable for a particular | |
1651 | * configuration. | |
1652 | */ | |
e01402b1 | 1653 | set_handler(0x180, &except_vec3_generic, 0x80); |
1da177e4 LT |
1654 | |
1655 | /* | |
1656 | * Setup default vectors | |
1657 | */ | |
1658 | for (i = 0; i <= 31; i++) | |
1659 | set_except_vector(i, handle_reserved); | |
1660 | ||
1661 | /* | |
1662 | * Copy the EJTAG debug exception vector handler code to it's final | |
1663 | * destination. | |
1664 | */ | |
e01402b1 | 1665 | if (cpu_has_ejtag && board_ejtag_handler_setup) |
49a89efb | 1666 | board_ejtag_handler_setup(); |
1da177e4 LT |
1667 | |
1668 | /* | |
1669 | * Only some CPUs have the watch exceptions. | |
1670 | */ | |
1671 | if (cpu_has_watch) | |
1672 | set_except_vector(23, handle_watch); | |
1673 | ||
1674 | /* | |
e01402b1 | 1675 | * Initialise interrupt handlers |
1da177e4 | 1676 | */ |
e01402b1 RB |
1677 | if (cpu_has_veic || cpu_has_vint) { |
1678 | int nvec = cpu_has_veic ? 64 : 8; | |
1679 | for (i = 0; i < nvec; i++) | |
ff3eab2a | 1680 | set_vi_handler(i, NULL); |
e01402b1 RB |
1681 | } |
1682 | else if (cpu_has_divec) | |
1683 | set_handler(0x200, &except_vec4, 0x8); | |
1da177e4 LT |
1684 | |
1685 | /* | |
1686 | * Some CPUs can enable/disable for cache parity detection, but does | |
1687 | * it different ways. | |
1688 | */ | |
1689 | parity_protection_init(); | |
1690 | ||
1691 | /* | |
1692 | * The Data Bus Errors / Instruction Bus Errors are signaled | |
1693 | * by external hardware. Therefore these two exceptions | |
1694 | * may have board specific handlers. | |
1695 | */ | |
1696 | if (board_be_init) | |
1697 | board_be_init(); | |
1698 | ||
c65a5480 | 1699 | set_except_vector(0, rollback ? rollback_handle_int : handle_int); |
1da177e4 LT |
1700 | set_except_vector(1, handle_tlbm); |
1701 | set_except_vector(2, handle_tlbl); | |
1702 | set_except_vector(3, handle_tlbs); | |
1703 | ||
1704 | set_except_vector(4, handle_adel); | |
1705 | set_except_vector(5, handle_ades); | |
1706 | ||
1707 | set_except_vector(6, handle_ibe); | |
1708 | set_except_vector(7, handle_dbe); | |
1709 | ||
1710 | set_except_vector(8, handle_sys); | |
1711 | set_except_vector(9, handle_bp); | |
5b10496b AN |
1712 | set_except_vector(10, rdhwr_noopt ? handle_ri : |
1713 | (cpu_has_vtag_icache ? | |
1714 | handle_ri_rdhwr_vivt : handle_ri_rdhwr)); | |
1da177e4 LT |
1715 | set_except_vector(11, handle_cpu); |
1716 | set_except_vector(12, handle_ov); | |
1717 | set_except_vector(13, handle_tr); | |
1da177e4 | 1718 | |
10cc3529 RB |
1719 | if (current_cpu_type() == CPU_R6000 || |
1720 | current_cpu_type() == CPU_R6000A) { | |
1da177e4 LT |
1721 | /* |
1722 | * The R6000 is the only R-series CPU that features a machine | |
1723 | * check exception (similar to the R4000 cache error) and | |
1724 | * unaligned ldc1/sdc1 exception. The handlers have not been | |
1725 | * written yet. Well, anyway there is no R6000 machine on the | |
1726 | * current list of targets for Linux/MIPS. | |
1727 | * (Duh, crap, there is someone with a triple R6k machine) | |
1728 | */ | |
1729 | //set_except_vector(14, handle_mc); | |
1730 | //set_except_vector(15, handle_ndc); | |
1731 | } | |
1732 | ||
e01402b1 RB |
1733 | |
1734 | if (board_nmi_handler_setup) | |
1735 | board_nmi_handler_setup(); | |
1736 | ||
e50c0a8f RB |
1737 | if (cpu_has_fpu && !cpu_has_nofpuex) |
1738 | set_except_vector(15, handle_fpe); | |
1739 | ||
1740 | set_except_vector(22, handle_mdmx); | |
1741 | ||
1742 | if (cpu_has_mcheck) | |
1743 | set_except_vector(24, handle_mcheck); | |
1744 | ||
340ee4b9 RB |
1745 | if (cpu_has_mipsmt) |
1746 | set_except_vector(25, handle_mt); | |
1747 | ||
acaec427 | 1748 | set_except_vector(26, handle_dsp); |
e50c0a8f RB |
1749 | |
1750 | if (cpu_has_vce) | |
1751 | /* Special exception: R4[04]00 uses also the divec space. */ | |
566f74f6 | 1752 | memcpy((void *)(ebase + 0x180), &except_vec3_r4000, 0x100); |
e50c0a8f | 1753 | else if (cpu_has_4kex) |
566f74f6 | 1754 | memcpy((void *)(ebase + 0x180), &except_vec3_generic, 0x80); |
e50c0a8f | 1755 | else |
566f74f6 | 1756 | memcpy((void *)(ebase + 0x080), &except_vec3_generic, 0x80); |
e50c0a8f | 1757 | |
1da177e4 LT |
1758 | signal_init(); |
1759 | #ifdef CONFIG_MIPS32_COMPAT | |
1760 | signal32_init(); | |
1761 | #endif | |
1762 | ||
e0cee3ee | 1763 | local_flush_icache_range(ebase, ebase + 0x400); |
1d40cfcd | 1764 | flush_tlb_handlers(); |
0510617b TB |
1765 | |
1766 | sort_extable(__start___dbe_table, __stop___dbe_table); | |
1da177e4 | 1767 | } |