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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public | |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
36ccf1c0 | 6 | * Copyright (C) 1994 - 1999, 2000, 01, 06 Ralf Baechle |
1da177e4 LT |
7 | * Copyright (C) 1995, 1996 Paul M. Antoine |
8 | * Copyright (C) 1998 Ulf Carlsson | |
9 | * Copyright (C) 1999 Silicon Graphics, Inc. | |
10 | * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com | |
60b0d655 | 11 | * Copyright (C) 2002, 2003, 2004, 2005, 2007 Maciej W. Rozycki |
2a0b24f5 | 12 | * Copyright (C) 2000, 2001, 2012 MIPS Technologies, Inc. All rights reserved. |
1da177e4 | 13 | */ |
8e8a52ed | 14 | #include <linux/bug.h> |
60b0d655 | 15 | #include <linux/compiler.h> |
7aa1c8f4 | 16 | #include <linux/kexec.h> |
1da177e4 | 17 | #include <linux/init.h> |
8742cd23 | 18 | #include <linux/kernel.h> |
f9ded569 | 19 | #include <linux/module.h> |
1da177e4 | 20 | #include <linux/mm.h> |
1da177e4 LT |
21 | #include <linux/sched.h> |
22 | #include <linux/smp.h> | |
1da177e4 LT |
23 | #include <linux/spinlock.h> |
24 | #include <linux/kallsyms.h> | |
e01402b1 | 25 | #include <linux/bootmem.h> |
d4fd1989 | 26 | #include <linux/interrupt.h> |
39b8d525 | 27 | #include <linux/ptrace.h> |
88547001 JW |
28 | #include <linux/kgdb.h> |
29 | #include <linux/kdebug.h> | |
c1bf207d | 30 | #include <linux/kprobes.h> |
69f3a7de | 31 | #include <linux/notifier.h> |
5dd11d5d | 32 | #include <linux/kdb.h> |
ca4d3e67 | 33 | #include <linux/irq.h> |
7f788d2d | 34 | #include <linux/perf_event.h> |
1da177e4 LT |
35 | |
36 | #include <asm/bootinfo.h> | |
37 | #include <asm/branch.h> | |
38 | #include <asm/break.h> | |
69f3a7de | 39 | #include <asm/cop2.h> |
1da177e4 | 40 | #include <asm/cpu.h> |
e50c0a8f | 41 | #include <asm/dsp.h> |
1da177e4 | 42 | #include <asm/fpu.h> |
ba3049ed | 43 | #include <asm/fpu_emulator.h> |
340ee4b9 RB |
44 | #include <asm/mipsregs.h> |
45 | #include <asm/mipsmtregs.h> | |
1da177e4 LT |
46 | #include <asm/module.h> |
47 | #include <asm/pgtable.h> | |
48 | #include <asm/ptrace.h> | |
49 | #include <asm/sections.h> | |
1da177e4 LT |
50 | #include <asm/tlbdebug.h> |
51 | #include <asm/traps.h> | |
52 | #include <asm/uaccess.h> | |
b67b2b70 | 53 | #include <asm/watch.h> |
1da177e4 | 54 | #include <asm/mmu_context.h> |
1da177e4 | 55 | #include <asm/types.h> |
1df0f0ff | 56 | #include <asm/stacktrace.h> |
92bbe1b9 | 57 | #include <asm/uasm.h> |
1da177e4 | 58 | |
c65a5480 AN |
59 | extern void check_wait(void); |
60 | extern asmlinkage void r4k_wait(void); | |
61 | extern asmlinkage void rollback_handle_int(void); | |
e4ac58af | 62 | extern asmlinkage void handle_int(void); |
86a1708a RB |
63 | extern u32 handle_tlbl[]; |
64 | extern u32 handle_tlbs[]; | |
65 | extern u32 handle_tlbm[]; | |
1da177e4 LT |
66 | extern asmlinkage void handle_adel(void); |
67 | extern asmlinkage void handle_ades(void); | |
68 | extern asmlinkage void handle_ibe(void); | |
69 | extern asmlinkage void handle_dbe(void); | |
70 | extern asmlinkage void handle_sys(void); | |
71 | extern asmlinkage void handle_bp(void); | |
72 | extern asmlinkage void handle_ri(void); | |
5b10496b AN |
73 | extern asmlinkage void handle_ri_rdhwr_vivt(void); |
74 | extern asmlinkage void handle_ri_rdhwr(void); | |
1da177e4 LT |
75 | extern asmlinkage void handle_cpu(void); |
76 | extern asmlinkage void handle_ov(void); | |
77 | extern asmlinkage void handle_tr(void); | |
78 | extern asmlinkage void handle_fpe(void); | |
79 | extern asmlinkage void handle_mdmx(void); | |
80 | extern asmlinkage void handle_watch(void); | |
340ee4b9 | 81 | extern asmlinkage void handle_mt(void); |
e50c0a8f | 82 | extern asmlinkage void handle_dsp(void); |
1da177e4 LT |
83 | extern asmlinkage void handle_mcheck(void); |
84 | extern asmlinkage void handle_reserved(void); | |
85 | ||
1da177e4 LT |
86 | void (*board_be_init)(void); |
87 | int (*board_be_handler)(struct pt_regs *regs, int is_fixup); | |
e01402b1 RB |
88 | void (*board_nmi_handler_setup)(void); |
89 | void (*board_ejtag_handler_setup)(void); | |
90 | void (*board_bind_eic_interrupt)(int irq, int regset); | |
6fb97eff | 91 | void (*board_ebase_setup)(void); |
fcbf1dfd | 92 | void __cpuinitdata(*board_cache_error_setup)(void); |
1da177e4 | 93 | |
4d157d5e | 94 | static void show_raw_backtrace(unsigned long reg29) |
e889d78f | 95 | { |
39b8d525 | 96 | unsigned long *sp = (unsigned long *)(reg29 & ~3); |
e889d78f AN |
97 | unsigned long addr; |
98 | ||
99 | printk("Call Trace:"); | |
100 | #ifdef CONFIG_KALLSYMS | |
101 | printk("\n"); | |
102 | #endif | |
10220c88 TB |
103 | while (!kstack_end(sp)) { |
104 | unsigned long __user *p = | |
105 | (unsigned long __user *)(unsigned long)sp++; | |
106 | if (__get_user(addr, p)) { | |
107 | printk(" (Bad stack address)"); | |
108 | break; | |
39b8d525 | 109 | } |
10220c88 TB |
110 | if (__kernel_text_address(addr)) |
111 | print_ip_sym(addr); | |
e889d78f | 112 | } |
10220c88 | 113 | printk("\n"); |
e889d78f AN |
114 | } |
115 | ||
f66686f7 | 116 | #ifdef CONFIG_KALLSYMS |
1df0f0ff | 117 | int raw_show_trace; |
f66686f7 AN |
118 | static int __init set_raw_show_trace(char *str) |
119 | { | |
120 | raw_show_trace = 1; | |
121 | return 1; | |
122 | } | |
123 | __setup("raw_show_trace", set_raw_show_trace); | |
1df0f0ff | 124 | #endif |
4d157d5e | 125 | |
eae23f2c | 126 | static void show_backtrace(struct task_struct *task, const struct pt_regs *regs) |
f66686f7 | 127 | { |
4d157d5e FBH |
128 | unsigned long sp = regs->regs[29]; |
129 | unsigned long ra = regs->regs[31]; | |
f66686f7 | 130 | unsigned long pc = regs->cp0_epc; |
f66686f7 | 131 | |
e909be82 VW |
132 | if (!task) |
133 | task = current; | |
134 | ||
f66686f7 | 135 | if (raw_show_trace || !__kernel_text_address(pc)) { |
87151ae3 | 136 | show_raw_backtrace(sp); |
f66686f7 AN |
137 | return; |
138 | } | |
139 | printk("Call Trace:\n"); | |
4d157d5e | 140 | do { |
87151ae3 | 141 | print_ip_sym(pc); |
1924600c | 142 | pc = unwind_stack(task, &sp, pc, &ra); |
4d157d5e | 143 | } while (pc); |
f66686f7 AN |
144 | printk("\n"); |
145 | } | |
f66686f7 | 146 | |
1da177e4 LT |
147 | /* |
148 | * This routine abuses get_user()/put_user() to reference pointers | |
149 | * with at least a bit of error checking ... | |
150 | */ | |
eae23f2c RB |
151 | static void show_stacktrace(struct task_struct *task, |
152 | const struct pt_regs *regs) | |
1da177e4 LT |
153 | { |
154 | const int field = 2 * sizeof(unsigned long); | |
155 | long stackdata; | |
156 | int i; | |
5e0373b8 | 157 | unsigned long __user *sp = (unsigned long __user *)regs->regs[29]; |
1da177e4 LT |
158 | |
159 | printk("Stack :"); | |
160 | i = 0; | |
161 | while ((unsigned long) sp & (PAGE_SIZE - 1)) { | |
162 | if (i && ((i % (64 / field)) == 0)) | |
70342287 | 163 | printk("\n "); |
1da177e4 LT |
164 | if (i > 39) { |
165 | printk(" ..."); | |
166 | break; | |
167 | } | |
168 | ||
169 | if (__get_user(stackdata, sp++)) { | |
170 | printk(" (Bad stack address)"); | |
171 | break; | |
172 | } | |
173 | ||
174 | printk(" %0*lx", field, stackdata); | |
175 | i++; | |
176 | } | |
177 | printk("\n"); | |
87151ae3 | 178 | show_backtrace(task, regs); |
f66686f7 AN |
179 | } |
180 | ||
f66686f7 AN |
181 | void show_stack(struct task_struct *task, unsigned long *sp) |
182 | { | |
183 | struct pt_regs regs; | |
184 | if (sp) { | |
185 | regs.regs[29] = (unsigned long)sp; | |
186 | regs.regs[31] = 0; | |
187 | regs.cp0_epc = 0; | |
188 | } else { | |
189 | if (task && task != current) { | |
190 | regs.regs[29] = task->thread.reg29; | |
191 | regs.regs[31] = 0; | |
192 | regs.cp0_epc = task->thread.reg31; | |
5dd11d5d JW |
193 | #ifdef CONFIG_KGDB_KDB |
194 | } else if (atomic_read(&kgdb_active) != -1 && | |
195 | kdb_current_regs) { | |
196 | memcpy(®s, kdb_current_regs, sizeof(regs)); | |
197 | #endif /* CONFIG_KGDB_KDB */ | |
f66686f7 AN |
198 | } else { |
199 | prepare_frametrace(®s); | |
200 | } | |
201 | } | |
202 | show_stacktrace(task, ®s); | |
1da177e4 LT |
203 | } |
204 | ||
e1bb8289 | 205 | static void show_code(unsigned int __user *pc) |
1da177e4 LT |
206 | { |
207 | long i; | |
39b8d525 | 208 | unsigned short __user *pc16 = NULL; |
1da177e4 LT |
209 | |
210 | printk("\nCode:"); | |
211 | ||
39b8d525 RB |
212 | if ((unsigned long)pc & 1) |
213 | pc16 = (unsigned short __user *)((unsigned long)pc & ~1); | |
1da177e4 LT |
214 | for(i = -3 ; i < 6 ; i++) { |
215 | unsigned int insn; | |
39b8d525 | 216 | if (pc16 ? __get_user(insn, pc16 + i) : __get_user(insn, pc + i)) { |
1da177e4 LT |
217 | printk(" (Bad address in epc)\n"); |
218 | break; | |
219 | } | |
39b8d525 | 220 | printk("%c%0*x%c", (i?' ':'<'), pc16 ? 4 : 8, insn, (i?' ':'>')); |
1da177e4 LT |
221 | } |
222 | } | |
223 | ||
eae23f2c | 224 | static void __show_regs(const struct pt_regs *regs) |
1da177e4 LT |
225 | { |
226 | const int field = 2 * sizeof(unsigned long); | |
227 | unsigned int cause = regs->cp0_cause; | |
228 | int i; | |
229 | ||
a43cb95d | 230 | show_regs_print_info(KERN_DEFAULT); |
1da177e4 LT |
231 | |
232 | /* | |
233 | * Saved main processor registers | |
234 | */ | |
235 | for (i = 0; i < 32; ) { | |
236 | if ((i % 4) == 0) | |
237 | printk("$%2d :", i); | |
238 | if (i == 0) | |
239 | printk(" %0*lx", field, 0UL); | |
240 | else if (i == 26 || i == 27) | |
241 | printk(" %*s", field, ""); | |
242 | else | |
243 | printk(" %0*lx", field, regs->regs[i]); | |
244 | ||
245 | i++; | |
246 | if ((i % 4) == 0) | |
247 | printk("\n"); | |
248 | } | |
249 | ||
9693a853 FBH |
250 | #ifdef CONFIG_CPU_HAS_SMARTMIPS |
251 | printk("Acx : %0*lx\n", field, regs->acx); | |
252 | #endif | |
1da177e4 LT |
253 | printk("Hi : %0*lx\n", field, regs->hi); |
254 | printk("Lo : %0*lx\n", field, regs->lo); | |
255 | ||
256 | /* | |
257 | * Saved cp0 registers | |
258 | */ | |
b012cffe RB |
259 | printk("epc : %0*lx %pS\n", field, regs->cp0_epc, |
260 | (void *) regs->cp0_epc); | |
1da177e4 | 261 | printk(" %s\n", print_tainted()); |
b012cffe RB |
262 | printk("ra : %0*lx %pS\n", field, regs->regs[31], |
263 | (void *) regs->regs[31]); | |
1da177e4 | 264 | |
70342287 | 265 | printk("Status: %08x ", (uint32_t) regs->cp0_status); |
1da177e4 | 266 | |
3b2396d9 MR |
267 | if (current_cpu_data.isa_level == MIPS_CPU_ISA_I) { |
268 | if (regs->cp0_status & ST0_KUO) | |
269 | printk("KUo "); | |
270 | if (regs->cp0_status & ST0_IEO) | |
271 | printk("IEo "); | |
272 | if (regs->cp0_status & ST0_KUP) | |
273 | printk("KUp "); | |
274 | if (regs->cp0_status & ST0_IEP) | |
275 | printk("IEp "); | |
276 | if (regs->cp0_status & ST0_KUC) | |
277 | printk("KUc "); | |
278 | if (regs->cp0_status & ST0_IEC) | |
279 | printk("IEc "); | |
280 | } else { | |
281 | if (regs->cp0_status & ST0_KX) | |
282 | printk("KX "); | |
283 | if (regs->cp0_status & ST0_SX) | |
284 | printk("SX "); | |
285 | if (regs->cp0_status & ST0_UX) | |
286 | printk("UX "); | |
287 | switch (regs->cp0_status & ST0_KSU) { | |
288 | case KSU_USER: | |
289 | printk("USER "); | |
290 | break; | |
291 | case KSU_SUPERVISOR: | |
292 | printk("SUPERVISOR "); | |
293 | break; | |
294 | case KSU_KERNEL: | |
295 | printk("KERNEL "); | |
296 | break; | |
297 | default: | |
298 | printk("BAD_MODE "); | |
299 | break; | |
300 | } | |
301 | if (regs->cp0_status & ST0_ERL) | |
302 | printk("ERL "); | |
303 | if (regs->cp0_status & ST0_EXL) | |
304 | printk("EXL "); | |
305 | if (regs->cp0_status & ST0_IE) | |
306 | printk("IE "); | |
1da177e4 | 307 | } |
1da177e4 LT |
308 | printk("\n"); |
309 | ||
310 | printk("Cause : %08x\n", cause); | |
311 | ||
312 | cause = (cause & CAUSEF_EXCCODE) >> CAUSEB_EXCCODE; | |
313 | if (1 <= cause && cause <= 5) | |
314 | printk("BadVA : %0*lx\n", field, regs->cp0_badvaddr); | |
315 | ||
9966db25 RB |
316 | printk("PrId : %08x (%s)\n", read_c0_prid(), |
317 | cpu_name_string()); | |
1da177e4 LT |
318 | } |
319 | ||
eae23f2c RB |
320 | /* |
321 | * FIXME: really the generic show_regs should take a const pointer argument. | |
322 | */ | |
323 | void show_regs(struct pt_regs *regs) | |
324 | { | |
325 | __show_regs((struct pt_regs *)regs); | |
326 | } | |
327 | ||
c1bf207d | 328 | void show_registers(struct pt_regs *regs) |
1da177e4 | 329 | { |
39b8d525 RB |
330 | const int field = 2 * sizeof(unsigned long); |
331 | ||
eae23f2c | 332 | __show_regs(regs); |
1da177e4 | 333 | print_modules(); |
39b8d525 RB |
334 | printk("Process %s (pid: %d, threadinfo=%p, task=%p, tls=%0*lx)\n", |
335 | current->comm, current->pid, current_thread_info(), current, | |
336 | field, current_thread_info()->tp_value); | |
337 | if (cpu_has_userlocal) { | |
338 | unsigned long tls; | |
339 | ||
340 | tls = read_c0_userlocal(); | |
341 | if (tls != current_thread_info()->tp_value) | |
342 | printk("*HwTLS: %0*lx\n", field, tls); | |
343 | } | |
344 | ||
f66686f7 | 345 | show_stacktrace(current, regs); |
e1bb8289 | 346 | show_code((unsigned int __user *) regs->cp0_epc); |
1da177e4 LT |
347 | printk("\n"); |
348 | } | |
349 | ||
70dc6f04 DD |
350 | static int regs_to_trapnr(struct pt_regs *regs) |
351 | { | |
352 | return (regs->cp0_cause >> 2) & 0x1f; | |
353 | } | |
354 | ||
4d85f6af | 355 | static DEFINE_RAW_SPINLOCK(die_lock); |
1da177e4 | 356 | |
70dc6f04 | 357 | void __noreturn die(const char *str, struct pt_regs *regs) |
1da177e4 LT |
358 | { |
359 | static int die_counter; | |
ce384d83 | 360 | int sig = SIGSEGV; |
41c594ab | 361 | #ifdef CONFIG_MIPS_MT_SMTC |
8742cd23 | 362 | unsigned long dvpret; |
41c594ab | 363 | #endif /* CONFIG_MIPS_MT_SMTC */ |
1da177e4 | 364 | |
8742cd23 NL |
365 | oops_enter(); |
366 | ||
10423c91 RB |
367 | if (notify_die(DIE_OOPS, str, regs, 0, regs_to_trapnr(regs), SIGSEGV) == NOTIFY_STOP) |
368 | sig = 0; | |
5dd11d5d | 369 | |
1da177e4 | 370 | console_verbose(); |
4d85f6af | 371 | raw_spin_lock_irq(&die_lock); |
8742cd23 NL |
372 | #ifdef CONFIG_MIPS_MT_SMTC |
373 | dvpret = dvpe(); | |
374 | #endif /* CONFIG_MIPS_MT_SMTC */ | |
41c594ab RB |
375 | bust_spinlocks(1); |
376 | #ifdef CONFIG_MIPS_MT_SMTC | |
377 | mips_mt_regdump(dvpret); | |
378 | #endif /* CONFIG_MIPS_MT_SMTC */ | |
ce384d83 | 379 | |
178086c8 | 380 | printk("%s[#%d]:\n", str, ++die_counter); |
1da177e4 | 381 | show_registers(regs); |
373d4d09 | 382 | add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE); |
4d85f6af | 383 | raw_spin_unlock_irq(&die_lock); |
d4fd1989 | 384 | |
8742cd23 NL |
385 | oops_exit(); |
386 | ||
d4fd1989 MB |
387 | if (in_interrupt()) |
388 | panic("Fatal exception in interrupt"); | |
389 | ||
390 | if (panic_on_oops) { | |
ab75dc02 | 391 | printk(KERN_EMERG "Fatal exception: panic in 5 seconds"); |
d4fd1989 MB |
392 | ssleep(5); |
393 | panic("Fatal exception"); | |
394 | } | |
395 | ||
7aa1c8f4 RB |
396 | if (regs && kexec_should_crash(current)) |
397 | crash_kexec(regs); | |
398 | ||
ce384d83 | 399 | do_exit(sig); |
1da177e4 LT |
400 | } |
401 | ||
0510617b TB |
402 | extern struct exception_table_entry __start___dbe_table[]; |
403 | extern struct exception_table_entry __stop___dbe_table[]; | |
1da177e4 | 404 | |
b6dcec9b RB |
405 | __asm__( |
406 | " .section __dbe_table, \"a\"\n" | |
407 | " .previous \n"); | |
1da177e4 LT |
408 | |
409 | /* Given an address, look for it in the exception tables. */ | |
410 | static const struct exception_table_entry *search_dbe_tables(unsigned long addr) | |
411 | { | |
412 | const struct exception_table_entry *e; | |
413 | ||
414 | e = search_extable(__start___dbe_table, __stop___dbe_table - 1, addr); | |
415 | if (!e) | |
416 | e = search_module_dbetables(addr); | |
417 | return e; | |
418 | } | |
419 | ||
420 | asmlinkage void do_be(struct pt_regs *regs) | |
421 | { | |
422 | const int field = 2 * sizeof(unsigned long); | |
423 | const struct exception_table_entry *fixup = NULL; | |
424 | int data = regs->cp0_cause & 4; | |
425 | int action = MIPS_BE_FATAL; | |
426 | ||
70342287 | 427 | /* XXX For now. Fixme, this searches the wrong table ... */ |
1da177e4 LT |
428 | if (data && !user_mode(regs)) |
429 | fixup = search_dbe_tables(exception_epc(regs)); | |
430 | ||
431 | if (fixup) | |
432 | action = MIPS_BE_FIXUP; | |
433 | ||
434 | if (board_be_handler) | |
28fc582c | 435 | action = board_be_handler(regs, fixup != NULL); |
1da177e4 LT |
436 | |
437 | switch (action) { | |
438 | case MIPS_BE_DISCARD: | |
439 | return; | |
440 | case MIPS_BE_FIXUP: | |
441 | if (fixup) { | |
442 | regs->cp0_epc = fixup->nextinsn; | |
443 | return; | |
444 | } | |
445 | break; | |
446 | default: | |
447 | break; | |
448 | } | |
449 | ||
450 | /* | |
451 | * Assume it would be too dangerous to continue ... | |
452 | */ | |
453 | printk(KERN_ALERT "%s bus error, epc == %0*lx, ra == %0*lx\n", | |
454 | data ? "Data" : "Instruction", | |
455 | field, regs->cp0_epc, field, regs->regs[31]); | |
70dc6f04 | 456 | if (notify_die(DIE_OOPS, "bus error", regs, 0, regs_to_trapnr(regs), SIGBUS) |
88547001 JW |
457 | == NOTIFY_STOP) |
458 | return; | |
459 | ||
1da177e4 LT |
460 | die_if_kernel("Oops", regs); |
461 | force_sig(SIGBUS, current); | |
462 | } | |
463 | ||
1da177e4 | 464 | /* |
60b0d655 | 465 | * ll/sc, rdhwr, sync emulation |
1da177e4 LT |
466 | */ |
467 | ||
468 | #define OPCODE 0xfc000000 | |
469 | #define BASE 0x03e00000 | |
470 | #define RT 0x001f0000 | |
471 | #define OFFSET 0x0000ffff | |
472 | #define LL 0xc0000000 | |
473 | #define SC 0xe0000000 | |
60b0d655 | 474 | #define SPEC0 0x00000000 |
3c37026d RB |
475 | #define SPEC3 0x7c000000 |
476 | #define RD 0x0000f800 | |
477 | #define FUNC 0x0000003f | |
60b0d655 | 478 | #define SYNC 0x0000000f |
3c37026d | 479 | #define RDHWR 0x0000003b |
1da177e4 | 480 | |
2a0b24f5 SH |
481 | /* microMIPS definitions */ |
482 | #define MM_POOL32A_FUNC 0xfc00ffff | |
483 | #define MM_RDHWR 0x00006b3c | |
484 | #define MM_RS 0x001f0000 | |
485 | #define MM_RT 0x03e00000 | |
486 | ||
1da177e4 LT |
487 | /* |
488 | * The ll_bit is cleared by r*_switch.S | |
489 | */ | |
490 | ||
f1e39a4a RB |
491 | unsigned int ll_bit; |
492 | struct task_struct *ll_task; | |
1da177e4 | 493 | |
60b0d655 | 494 | static inline int simulate_ll(struct pt_regs *regs, unsigned int opcode) |
1da177e4 | 495 | { |
fe00f943 | 496 | unsigned long value, __user *vaddr; |
1da177e4 | 497 | long offset; |
1da177e4 LT |
498 | |
499 | /* | |
500 | * analyse the ll instruction that just caused a ri exception | |
501 | * and put the referenced address to addr. | |
502 | */ | |
503 | ||
504 | /* sign extend offset */ | |
505 | offset = opcode & OFFSET; | |
506 | offset <<= 16; | |
507 | offset >>= 16; | |
508 | ||
fe00f943 | 509 | vaddr = (unsigned long __user *) |
b9688310 | 510 | ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset); |
1da177e4 | 511 | |
60b0d655 MR |
512 | if ((unsigned long)vaddr & 3) |
513 | return SIGBUS; | |
514 | if (get_user(value, vaddr)) | |
515 | return SIGSEGV; | |
1da177e4 LT |
516 | |
517 | preempt_disable(); | |
518 | ||
519 | if (ll_task == NULL || ll_task == current) { | |
520 | ll_bit = 1; | |
521 | } else { | |
522 | ll_bit = 0; | |
523 | } | |
524 | ll_task = current; | |
525 | ||
526 | preempt_enable(); | |
527 | ||
528 | regs->regs[(opcode & RT) >> 16] = value; | |
529 | ||
60b0d655 | 530 | return 0; |
1da177e4 LT |
531 | } |
532 | ||
60b0d655 | 533 | static inline int simulate_sc(struct pt_regs *regs, unsigned int opcode) |
1da177e4 | 534 | { |
fe00f943 RB |
535 | unsigned long __user *vaddr; |
536 | unsigned long reg; | |
1da177e4 | 537 | long offset; |
1da177e4 LT |
538 | |
539 | /* | |
540 | * analyse the sc instruction that just caused a ri exception | |
541 | * and put the referenced address to addr. | |
542 | */ | |
543 | ||
544 | /* sign extend offset */ | |
545 | offset = opcode & OFFSET; | |
546 | offset <<= 16; | |
547 | offset >>= 16; | |
548 | ||
fe00f943 | 549 | vaddr = (unsigned long __user *) |
b9688310 | 550 | ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset); |
1da177e4 LT |
551 | reg = (opcode & RT) >> 16; |
552 | ||
60b0d655 MR |
553 | if ((unsigned long)vaddr & 3) |
554 | return SIGBUS; | |
1da177e4 LT |
555 | |
556 | preempt_disable(); | |
557 | ||
558 | if (ll_bit == 0 || ll_task != current) { | |
559 | regs->regs[reg] = 0; | |
560 | preempt_enable(); | |
60b0d655 | 561 | return 0; |
1da177e4 LT |
562 | } |
563 | ||
564 | preempt_enable(); | |
565 | ||
60b0d655 MR |
566 | if (put_user(regs->regs[reg], vaddr)) |
567 | return SIGSEGV; | |
1da177e4 LT |
568 | |
569 | regs->regs[reg] = 1; | |
570 | ||
60b0d655 | 571 | return 0; |
1da177e4 LT |
572 | } |
573 | ||
574 | /* | |
575 | * ll uses the opcode of lwc0 and sc uses the opcode of swc0. That is both | |
576 | * opcodes are supposed to result in coprocessor unusable exceptions if | |
577 | * executed on ll/sc-less processors. That's the theory. In practice a | |
578 | * few processors such as NEC's VR4100 throw reserved instruction exceptions | |
579 | * instead, so we're doing the emulation thing in both exception handlers. | |
580 | */ | |
60b0d655 | 581 | static int simulate_llsc(struct pt_regs *regs, unsigned int opcode) |
1da177e4 | 582 | { |
7f788d2d DCZ |
583 | if ((opcode & OPCODE) == LL) { |
584 | perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, | |
a8b0ca17 | 585 | 1, regs, 0); |
60b0d655 | 586 | return simulate_ll(regs, opcode); |
7f788d2d DCZ |
587 | } |
588 | if ((opcode & OPCODE) == SC) { | |
589 | perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, | |
a8b0ca17 | 590 | 1, regs, 0); |
60b0d655 | 591 | return simulate_sc(regs, opcode); |
7f788d2d | 592 | } |
1da177e4 | 593 | |
60b0d655 | 594 | return -1; /* Must be something else ... */ |
1da177e4 LT |
595 | } |
596 | ||
3c37026d RB |
597 | /* |
598 | * Simulate trapping 'rdhwr' instructions to provide user accessible | |
1f5826bd | 599 | * registers not implemented in hardware. |
3c37026d | 600 | */ |
2a0b24f5 | 601 | static int simulate_rdhwr(struct pt_regs *regs, int rd, int rt) |
3c37026d | 602 | { |
dc8f6029 | 603 | struct thread_info *ti = task_thread_info(current); |
3c37026d | 604 | |
2a0b24f5 SH |
605 | perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, |
606 | 1, regs, 0); | |
607 | switch (rd) { | |
608 | case 0: /* CPU number */ | |
609 | regs->regs[rt] = smp_processor_id(); | |
610 | return 0; | |
611 | case 1: /* SYNCI length */ | |
612 | regs->regs[rt] = min(current_cpu_data.dcache.linesz, | |
613 | current_cpu_data.icache.linesz); | |
614 | return 0; | |
615 | case 2: /* Read count register */ | |
616 | regs->regs[rt] = read_c0_count(); | |
617 | return 0; | |
618 | case 3: /* Count register resolution */ | |
619 | switch (current_cpu_data.cputype) { | |
620 | case CPU_20KC: | |
621 | case CPU_25KF: | |
622 | regs->regs[rt] = 1; | |
623 | break; | |
624 | default: | |
625 | regs->regs[rt] = 2; | |
626 | } | |
627 | return 0; | |
628 | case 29: | |
629 | regs->regs[rt] = ti->tp_value; | |
630 | return 0; | |
631 | default: | |
632 | return -1; | |
633 | } | |
634 | } | |
635 | ||
636 | static int simulate_rdhwr_normal(struct pt_regs *regs, unsigned int opcode) | |
637 | { | |
3c37026d RB |
638 | if ((opcode & OPCODE) == SPEC3 && (opcode & FUNC) == RDHWR) { |
639 | int rd = (opcode & RD) >> 11; | |
640 | int rt = (opcode & RT) >> 16; | |
2a0b24f5 SH |
641 | |
642 | simulate_rdhwr(regs, rd, rt); | |
643 | return 0; | |
644 | } | |
645 | ||
646 | /* Not ours. */ | |
647 | return -1; | |
648 | } | |
649 | ||
650 | static int simulate_rdhwr_mm(struct pt_regs *regs, unsigned short opcode) | |
651 | { | |
652 | if ((opcode & MM_POOL32A_FUNC) == MM_RDHWR) { | |
653 | int rd = (opcode & MM_RS) >> 16; | |
654 | int rt = (opcode & MM_RT) >> 21; | |
655 | simulate_rdhwr(regs, rd, rt); | |
656 | return 0; | |
3c37026d RB |
657 | } |
658 | ||
56ebd51b | 659 | /* Not ours. */ |
60b0d655 MR |
660 | return -1; |
661 | } | |
e5679882 | 662 | |
60b0d655 MR |
663 | static int simulate_sync(struct pt_regs *regs, unsigned int opcode) |
664 | { | |
7f788d2d DCZ |
665 | if ((opcode & OPCODE) == SPEC0 && (opcode & FUNC) == SYNC) { |
666 | perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, | |
a8b0ca17 | 667 | 1, regs, 0); |
60b0d655 | 668 | return 0; |
7f788d2d | 669 | } |
60b0d655 MR |
670 | |
671 | return -1; /* Must be something else ... */ | |
3c37026d RB |
672 | } |
673 | ||
1da177e4 LT |
674 | asmlinkage void do_ov(struct pt_regs *regs) |
675 | { | |
676 | siginfo_t info; | |
677 | ||
36ccf1c0 RB |
678 | die_if_kernel("Integer overflow", regs); |
679 | ||
1da177e4 LT |
680 | info.si_code = FPE_INTOVF; |
681 | info.si_signo = SIGFPE; | |
682 | info.si_errno = 0; | |
fe00f943 | 683 | info.si_addr = (void __user *) regs->cp0_epc; |
1da177e4 LT |
684 | force_sig_info(SIGFPE, &info, current); |
685 | } | |
686 | ||
102cedc3 | 687 | int process_fpemu_return(int sig, void __user *fault_addr) |
515b029d DD |
688 | { |
689 | if (sig == SIGSEGV || sig == SIGBUS) { | |
690 | struct siginfo si = {0}; | |
691 | si.si_addr = fault_addr; | |
692 | si.si_signo = sig; | |
693 | if (sig == SIGSEGV) { | |
694 | if (find_vma(current->mm, (unsigned long)fault_addr)) | |
695 | si.si_code = SEGV_ACCERR; | |
696 | else | |
697 | si.si_code = SEGV_MAPERR; | |
698 | } else { | |
699 | si.si_code = BUS_ADRERR; | |
700 | } | |
701 | force_sig_info(sig, &si, current); | |
702 | return 1; | |
703 | } else if (sig) { | |
704 | force_sig(sig, current); | |
705 | return 1; | |
706 | } else { | |
707 | return 0; | |
708 | } | |
709 | } | |
710 | ||
1da177e4 LT |
711 | /* |
712 | * XXX Delayed fp exceptions when doing a lazy ctx switch XXX | |
713 | */ | |
714 | asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31) | |
715 | { | |
515b029d | 716 | siginfo_t info = {0}; |
948a34cf | 717 | |
70dc6f04 | 718 | if (notify_die(DIE_FP, "FP exception", regs, 0, regs_to_trapnr(regs), SIGFPE) |
88547001 JW |
719 | == NOTIFY_STOP) |
720 | return; | |
57725f9e CD |
721 | die_if_kernel("FP exception in kernel code", regs); |
722 | ||
1da177e4 LT |
723 | if (fcr31 & FPU_CSR_UNI_X) { |
724 | int sig; | |
515b029d | 725 | void __user *fault_addr = NULL; |
1da177e4 | 726 | |
1da177e4 | 727 | /* |
a3dddd56 | 728 | * Unimplemented operation exception. If we've got the full |
1da177e4 LT |
729 | * software emulator on-board, let's use it... |
730 | * | |
731 | * Force FPU to dump state into task/thread context. We're | |
732 | * moving a lot of data here for what is probably a single | |
733 | * instruction, but the alternative is to pre-decode the FP | |
734 | * register operands before invoking the emulator, which seems | |
735 | * a bit extreme for what should be an infrequent event. | |
736 | */ | |
cd21dfcf | 737 | /* Ensure 'resume' not overwrite saved fp context again. */ |
53dc8028 | 738 | lose_fpu(1); |
1da177e4 LT |
739 | |
740 | /* Run the emulator */ | |
515b029d DD |
741 | sig = fpu_emulator_cop1Handler(regs, ¤t->thread.fpu, 1, |
742 | &fault_addr); | |
1da177e4 LT |
743 | |
744 | /* | |
745 | * We can't allow the emulated instruction to leave any of | |
746 | * the cause bit set in $fcr31. | |
747 | */ | |
eae89076 | 748 | current->thread.fpu.fcr31 &= ~FPU_CSR_ALL_X; |
1da177e4 LT |
749 | |
750 | /* Restore the hardware register state */ | |
70342287 | 751 | own_fpu(1); /* Using the FPU again. */ |
1da177e4 LT |
752 | |
753 | /* If something went wrong, signal */ | |
515b029d | 754 | process_fpemu_return(sig, fault_addr); |
1da177e4 LT |
755 | |
756 | return; | |
948a34cf TS |
757 | } else if (fcr31 & FPU_CSR_INV_X) |
758 | info.si_code = FPE_FLTINV; | |
759 | else if (fcr31 & FPU_CSR_DIV_X) | |
760 | info.si_code = FPE_FLTDIV; | |
761 | else if (fcr31 & FPU_CSR_OVF_X) | |
762 | info.si_code = FPE_FLTOVF; | |
763 | else if (fcr31 & FPU_CSR_UDF_X) | |
764 | info.si_code = FPE_FLTUND; | |
765 | else if (fcr31 & FPU_CSR_INE_X) | |
766 | info.si_code = FPE_FLTRES; | |
767 | else | |
768 | info.si_code = __SI_FAULT; | |
769 | info.si_signo = SIGFPE; | |
770 | info.si_errno = 0; | |
771 | info.si_addr = (void __user *) regs->cp0_epc; | |
772 | force_sig_info(SIGFPE, &info, current); | |
1da177e4 LT |
773 | } |
774 | ||
df270051 RB |
775 | static void do_trap_or_bp(struct pt_regs *regs, unsigned int code, |
776 | const char *str) | |
1da177e4 | 777 | { |
1da177e4 | 778 | siginfo_t info; |
df270051 | 779 | char b[40]; |
1da177e4 | 780 | |
5dd11d5d | 781 | #ifdef CONFIG_KGDB_LOW_LEVEL_TRAP |
70dc6f04 | 782 | if (kgdb_ll_trap(DIE_TRAP, str, regs, code, regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP) |
5dd11d5d JW |
783 | return; |
784 | #endif /* CONFIG_KGDB_LOW_LEVEL_TRAP */ | |
785 | ||
70dc6f04 | 786 | if (notify_die(DIE_TRAP, str, regs, code, regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP) |
88547001 JW |
787 | return; |
788 | ||
1da177e4 | 789 | /* |
df270051 RB |
790 | * A short test says that IRIX 5.3 sends SIGTRAP for all trap |
791 | * insns, even for trap and break codes that indicate arithmetic | |
792 | * failures. Weird ... | |
1da177e4 LT |
793 | * But should we continue the brokenness??? --macro |
794 | */ | |
df270051 RB |
795 | switch (code) { |
796 | case BRK_OVERFLOW: | |
797 | case BRK_DIVZERO: | |
798 | scnprintf(b, sizeof(b), "%s instruction in kernel code", str); | |
799 | die_if_kernel(b, regs); | |
800 | if (code == BRK_DIVZERO) | |
1da177e4 LT |
801 | info.si_code = FPE_INTDIV; |
802 | else | |
803 | info.si_code = FPE_INTOVF; | |
804 | info.si_signo = SIGFPE; | |
805 | info.si_errno = 0; | |
fe00f943 | 806 | info.si_addr = (void __user *) regs->cp0_epc; |
1da177e4 LT |
807 | force_sig_info(SIGFPE, &info, current); |
808 | break; | |
63dc68a8 | 809 | case BRK_BUG: |
df270051 RB |
810 | die_if_kernel("Kernel bug detected", regs); |
811 | force_sig(SIGTRAP, current); | |
63dc68a8 | 812 | break; |
ba3049ed RB |
813 | case BRK_MEMU: |
814 | /* | |
815 | * Address errors may be deliberately induced by the FPU | |
816 | * emulator to retake control of the CPU after executing the | |
817 | * instruction in the delay slot of an emulated branch. | |
818 | * | |
819 | * Terminate if exception was recognized as a delay slot return | |
820 | * otherwise handle as normal. | |
821 | */ | |
822 | if (do_dsemulret(regs)) | |
823 | return; | |
824 | ||
825 | die_if_kernel("Math emu break/trap", regs); | |
826 | force_sig(SIGTRAP, current); | |
827 | break; | |
1da177e4 | 828 | default: |
df270051 RB |
829 | scnprintf(b, sizeof(b), "%s instruction in kernel code", str); |
830 | die_if_kernel(b, regs); | |
1da177e4 LT |
831 | force_sig(SIGTRAP, current); |
832 | } | |
df270051 RB |
833 | } |
834 | ||
835 | asmlinkage void do_bp(struct pt_regs *regs) | |
836 | { | |
837 | unsigned int opcode, bcode; | |
2a0b24f5 SH |
838 | unsigned long epc; |
839 | u16 instr[2]; | |
840 | ||
841 | if (get_isa16_mode(regs->cp0_epc)) { | |
842 | /* Calculate EPC. */ | |
843 | epc = exception_epc(regs); | |
844 | if (cpu_has_mmips) { | |
845 | if ((__get_user(instr[0], (u16 __user *)msk_isa16_mode(epc)) || | |
846 | (__get_user(instr[1], (u16 __user *)msk_isa16_mode(epc + 2))))) | |
847 | goto out_sigsegv; | |
848 | opcode = (instr[0] << 16) | instr[1]; | |
849 | } else { | |
850 | /* MIPS16e mode */ | |
851 | if (__get_user(instr[0], (u16 __user *)msk_isa16_mode(epc))) | |
852 | goto out_sigsegv; | |
853 | bcode = (instr[0] >> 6) & 0x3f; | |
854 | do_trap_or_bp(regs, bcode, "Break"); | |
855 | return; | |
856 | } | |
857 | } else { | |
858 | if (__get_user(opcode, (unsigned int __user *) exception_epc(regs))) | |
859 | goto out_sigsegv; | |
860 | } | |
df270051 RB |
861 | |
862 | /* | |
863 | * There is the ancient bug in the MIPS assemblers that the break | |
864 | * code starts left to bit 16 instead to bit 6 in the opcode. | |
865 | * Gas is bug-compatible, but not always, grrr... | |
866 | * We handle both cases with a simple heuristics. --macro | |
867 | */ | |
868 | bcode = ((opcode >> 6) & ((1 << 20) - 1)); | |
869 | if (bcode >= (1 << 10)) | |
870 | bcode >>= 10; | |
871 | ||
c1bf207d DD |
872 | /* |
873 | * notify the kprobe handlers, if instruction is likely to | |
874 | * pertain to them. | |
875 | */ | |
876 | switch (bcode) { | |
877 | case BRK_KPROBE_BP: | |
70dc6f04 | 878 | if (notify_die(DIE_BREAK, "debug", regs, bcode, regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP) |
c1bf207d DD |
879 | return; |
880 | else | |
881 | break; | |
882 | case BRK_KPROBE_SSTEPBP: | |
70dc6f04 | 883 | if (notify_die(DIE_SSTEPBP, "single_step", regs, bcode, regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP) |
c1bf207d DD |
884 | return; |
885 | else | |
886 | break; | |
887 | default: | |
888 | break; | |
889 | } | |
890 | ||
df270051 | 891 | do_trap_or_bp(regs, bcode, "Break"); |
90fccb13 | 892 | return; |
e5679882 RB |
893 | |
894 | out_sigsegv: | |
895 | force_sig(SIGSEGV, current); | |
1da177e4 LT |
896 | } |
897 | ||
898 | asmlinkage void do_tr(struct pt_regs *regs) | |
899 | { | |
900 | unsigned int opcode, tcode = 0; | |
2a0b24f5 SH |
901 | u16 instr[2]; |
902 | unsigned long epc = exception_epc(regs); | |
1da177e4 | 903 | |
2a0b24f5 SH |
904 | if ((__get_user(instr[0], (u16 __user *)msk_isa16_mode(epc))) || |
905 | (__get_user(instr[1], (u16 __user *)msk_isa16_mode(epc + 2)))) | |
906 | goto out_sigsegv; | |
907 | opcode = (instr[0] << 16) | instr[1]; | |
1da177e4 LT |
908 | |
909 | /* Immediate versions don't provide a code. */ | |
2a0b24f5 SH |
910 | if (!(opcode & OPCODE)) { |
911 | if (get_isa16_mode(regs->cp0_epc)) | |
912 | /* microMIPS */ | |
913 | tcode = (opcode >> 12) & 0x1f; | |
914 | else | |
915 | tcode = ((opcode >> 6) & ((1 << 10) - 1)); | |
916 | } | |
1da177e4 | 917 | |
df270051 | 918 | do_trap_or_bp(regs, tcode, "Trap"); |
90fccb13 | 919 | return; |
e5679882 RB |
920 | |
921 | out_sigsegv: | |
922 | force_sig(SIGSEGV, current); | |
1da177e4 LT |
923 | } |
924 | ||
925 | asmlinkage void do_ri(struct pt_regs *regs) | |
926 | { | |
60b0d655 MR |
927 | unsigned int __user *epc = (unsigned int __user *)exception_epc(regs); |
928 | unsigned long old_epc = regs->cp0_epc; | |
2a0b24f5 | 929 | unsigned long old31 = regs->regs[31]; |
60b0d655 MR |
930 | unsigned int opcode = 0; |
931 | int status = -1; | |
1da177e4 | 932 | |
70dc6f04 | 933 | if (notify_die(DIE_RI, "RI Fault", regs, 0, regs_to_trapnr(regs), SIGILL) |
88547001 JW |
934 | == NOTIFY_STOP) |
935 | return; | |
936 | ||
60b0d655 | 937 | die_if_kernel("Reserved instruction in kernel code", regs); |
1da177e4 | 938 | |
60b0d655 | 939 | if (unlikely(compute_return_epc(regs) < 0)) |
3c37026d RB |
940 | return; |
941 | ||
2a0b24f5 SH |
942 | if (get_isa16_mode(regs->cp0_epc)) { |
943 | unsigned short mmop[2] = { 0 }; | |
60b0d655 | 944 | |
2a0b24f5 SH |
945 | if (unlikely(get_user(mmop[0], epc) < 0)) |
946 | status = SIGSEGV; | |
947 | if (unlikely(get_user(mmop[1], epc) < 0)) | |
948 | status = SIGSEGV; | |
949 | opcode = (mmop[0] << 16) | mmop[1]; | |
60b0d655 | 950 | |
2a0b24f5 SH |
951 | if (status < 0) |
952 | status = simulate_rdhwr_mm(regs, opcode); | |
953 | } else { | |
954 | if (unlikely(get_user(opcode, epc) < 0)) | |
955 | status = SIGSEGV; | |
60b0d655 | 956 | |
2a0b24f5 SH |
957 | if (!cpu_has_llsc && status < 0) |
958 | status = simulate_llsc(regs, opcode); | |
959 | ||
960 | if (status < 0) | |
961 | status = simulate_rdhwr_normal(regs, opcode); | |
962 | ||
963 | if (status < 0) | |
964 | status = simulate_sync(regs, opcode); | |
965 | } | |
60b0d655 MR |
966 | |
967 | if (status < 0) | |
968 | status = SIGILL; | |
969 | ||
970 | if (unlikely(status > 0)) { | |
971 | regs->cp0_epc = old_epc; /* Undo skip-over. */ | |
2a0b24f5 | 972 | regs->regs[31] = old31; |
60b0d655 MR |
973 | force_sig(status, current); |
974 | } | |
1da177e4 LT |
975 | } |
976 | ||
d223a861 RB |
977 | /* |
978 | * MIPS MT processors may have fewer FPU contexts than CPU threads. If we've | |
979 | * emulated more than some threshold number of instructions, force migration to | |
980 | * a "CPU" that has FP support. | |
981 | */ | |
982 | static void mt_ase_fp_affinity(void) | |
983 | { | |
984 | #ifdef CONFIG_MIPS_MT_FPAFF | |
985 | if (mt_fpemul_threshold > 0 && | |
986 | ((current->thread.emulated_fp++ > mt_fpemul_threshold))) { | |
987 | /* | |
988 | * If there's no FPU present, or if the application has already | |
989 | * restricted the allowed set to exclude any CPUs with FPUs, | |
990 | * we'll skip the procedure. | |
991 | */ | |
992 | if (cpus_intersects(current->cpus_allowed, mt_fpu_cpumask)) { | |
993 | cpumask_t tmask; | |
994 | ||
9cc12363 KK |
995 | current->thread.user_cpus_allowed |
996 | = current->cpus_allowed; | |
997 | cpus_and(tmask, current->cpus_allowed, | |
998 | mt_fpu_cpumask); | |
ed1bbdef | 999 | set_cpus_allowed_ptr(current, &tmask); |
293c5bd1 | 1000 | set_thread_flag(TIF_FPUBOUND); |
d223a861 RB |
1001 | } |
1002 | } | |
1003 | #endif /* CONFIG_MIPS_MT_FPAFF */ | |
1004 | } | |
1005 | ||
69f3a7de RB |
1006 | /* |
1007 | * No lock; only written during early bootup by CPU 0. | |
1008 | */ | |
1009 | static RAW_NOTIFIER_HEAD(cu2_chain); | |
1010 | ||
1011 | int __ref register_cu2_notifier(struct notifier_block *nb) | |
1012 | { | |
1013 | return raw_notifier_chain_register(&cu2_chain, nb); | |
1014 | } | |
1015 | ||
1016 | int cu2_notifier_call_chain(unsigned long val, void *v) | |
1017 | { | |
1018 | return raw_notifier_call_chain(&cu2_chain, val, v); | |
1019 | } | |
1020 | ||
1021 | static int default_cu2_call(struct notifier_block *nfb, unsigned long action, | |
70342287 | 1022 | void *data) |
69f3a7de RB |
1023 | { |
1024 | struct pt_regs *regs = data; | |
1025 | ||
1026 | switch (action) { | |
1027 | default: | |
1028 | die_if_kernel("Unhandled kernel unaligned access or invalid " | |
1029 | "instruction", regs); | |
70342287 | 1030 | /* Fall through */ |
69f3a7de RB |
1031 | |
1032 | case CU2_EXCEPTION: | |
1033 | force_sig(SIGILL, current); | |
1034 | } | |
1035 | ||
1036 | return NOTIFY_OK; | |
1037 | } | |
1038 | ||
1da177e4 LT |
1039 | asmlinkage void do_cpu(struct pt_regs *regs) |
1040 | { | |
60b0d655 | 1041 | unsigned int __user *epc; |
2a0b24f5 | 1042 | unsigned long old_epc, old31; |
60b0d655 | 1043 | unsigned int opcode; |
1da177e4 | 1044 | unsigned int cpid; |
60b0d655 | 1045 | int status; |
f9bb4cf3 | 1046 | unsigned long __maybe_unused flags; |
1da177e4 | 1047 | |
5323180d AN |
1048 | die_if_kernel("do_cpu invoked from kernel context!", regs); |
1049 | ||
1da177e4 LT |
1050 | cpid = (regs->cp0_cause >> CAUSEB_CE) & 3; |
1051 | ||
1052 | switch (cpid) { | |
1053 | case 0: | |
60b0d655 MR |
1054 | epc = (unsigned int __user *)exception_epc(regs); |
1055 | old_epc = regs->cp0_epc; | |
2a0b24f5 | 1056 | old31 = regs->regs[31]; |
60b0d655 MR |
1057 | opcode = 0; |
1058 | status = -1; | |
1da177e4 | 1059 | |
60b0d655 | 1060 | if (unlikely(compute_return_epc(regs) < 0)) |
1da177e4 | 1061 | return; |
3c37026d | 1062 | |
2a0b24f5 SH |
1063 | if (get_isa16_mode(regs->cp0_epc)) { |
1064 | unsigned short mmop[2] = { 0 }; | |
60b0d655 | 1065 | |
2a0b24f5 SH |
1066 | if (unlikely(get_user(mmop[0], epc) < 0)) |
1067 | status = SIGSEGV; | |
1068 | if (unlikely(get_user(mmop[1], epc) < 0)) | |
1069 | status = SIGSEGV; | |
1070 | opcode = (mmop[0] << 16) | mmop[1]; | |
60b0d655 | 1071 | |
2a0b24f5 SH |
1072 | if (status < 0) |
1073 | status = simulate_rdhwr_mm(regs, opcode); | |
1074 | } else { | |
1075 | if (unlikely(get_user(opcode, epc) < 0)) | |
1076 | status = SIGSEGV; | |
1077 | ||
1078 | if (!cpu_has_llsc && status < 0) | |
1079 | status = simulate_llsc(regs, opcode); | |
1080 | ||
1081 | if (status < 0) | |
1082 | status = simulate_rdhwr_normal(regs, opcode); | |
1083 | } | |
60b0d655 MR |
1084 | |
1085 | if (status < 0) | |
1086 | status = SIGILL; | |
1087 | ||
1088 | if (unlikely(status > 0)) { | |
1089 | regs->cp0_epc = old_epc; /* Undo skip-over. */ | |
2a0b24f5 | 1090 | regs->regs[31] = old31; |
60b0d655 MR |
1091 | force_sig(status, current); |
1092 | } | |
1093 | ||
1094 | return; | |
1da177e4 | 1095 | |
051ff44a MR |
1096 | case 3: |
1097 | /* | |
1098 | * Old (MIPS I and MIPS II) processors will set this code | |
1099 | * for COP1X opcode instructions that replaced the original | |
70342287 | 1100 | * COP3 space. We don't limit COP1 space instructions in |
051ff44a MR |
1101 | * the emulator according to the CPU ISA, so we want to |
1102 | * treat COP1X instructions consistently regardless of which | |
70342287 | 1103 | * code the CPU chose. Therefore we redirect this trap to |
051ff44a MR |
1104 | * the FP emulator too. |
1105 | * | |
1106 | * Then some newer FPU-less processors use this code | |
1107 | * erroneously too, so they are covered by this choice | |
1108 | * as well. | |
1109 | */ | |
1110 | if (raw_cpu_has_fpu) | |
1111 | break; | |
1112 | /* Fall through. */ | |
1113 | ||
1da177e4 | 1114 | case 1: |
70342287 | 1115 | if (used_math()) /* Using the FPU again. */ |
53dc8028 | 1116 | own_fpu(1); |
70342287 | 1117 | else { /* First time FPU user. */ |
1da177e4 LT |
1118 | init_fpu(); |
1119 | set_used_math(); | |
1120 | } | |
1121 | ||
5323180d | 1122 | if (!raw_cpu_has_fpu) { |
e04582b7 | 1123 | int sig; |
515b029d | 1124 | void __user *fault_addr = NULL; |
e04582b7 | 1125 | sig = fpu_emulator_cop1Handler(regs, |
515b029d DD |
1126 | ¤t->thread.fpu, |
1127 | 0, &fault_addr); | |
1128 | if (!process_fpemu_return(sig, fault_addr)) | |
d223a861 | 1129 | mt_ase_fp_affinity(); |
1da177e4 LT |
1130 | } |
1131 | ||
1da177e4 LT |
1132 | return; |
1133 | ||
1134 | case 2: | |
69f3a7de | 1135 | raw_notifier_call_chain(&cu2_chain, CU2_EXCEPTION, regs); |
55dc9d51 | 1136 | return; |
1da177e4 LT |
1137 | } |
1138 | ||
1139 | force_sig(SIGILL, current); | |
1140 | } | |
1141 | ||
1142 | asmlinkage void do_mdmx(struct pt_regs *regs) | |
1143 | { | |
1144 | force_sig(SIGILL, current); | |
1145 | } | |
1146 | ||
8bc6d05b DD |
1147 | /* |
1148 | * Called with interrupts disabled. | |
1149 | */ | |
1da177e4 LT |
1150 | asmlinkage void do_watch(struct pt_regs *regs) |
1151 | { | |
b67b2b70 DD |
1152 | u32 cause; |
1153 | ||
1da177e4 | 1154 | /* |
b67b2b70 DD |
1155 | * Clear WP (bit 22) bit of cause register so we don't loop |
1156 | * forever. | |
1da177e4 | 1157 | */ |
b67b2b70 DD |
1158 | cause = read_c0_cause(); |
1159 | cause &= ~(1 << 22); | |
1160 | write_c0_cause(cause); | |
1161 | ||
1162 | /* | |
1163 | * If the current thread has the watch registers loaded, save | |
1164 | * their values and send SIGTRAP. Otherwise another thread | |
1165 | * left the registers set, clear them and continue. | |
1166 | */ | |
1167 | if (test_tsk_thread_flag(current, TIF_LOAD_WATCH)) { | |
1168 | mips_read_watch_registers(); | |
8bc6d05b | 1169 | local_irq_enable(); |
b67b2b70 | 1170 | force_sig(SIGTRAP, current); |
8bc6d05b | 1171 | } else { |
b67b2b70 | 1172 | mips_clear_watch_registers(); |
8bc6d05b DD |
1173 | local_irq_enable(); |
1174 | } | |
1da177e4 LT |
1175 | } |
1176 | ||
1177 | asmlinkage void do_mcheck(struct pt_regs *regs) | |
1178 | { | |
cac4bcbc RB |
1179 | const int field = 2 * sizeof(unsigned long); |
1180 | int multi_match = regs->cp0_status & ST0_TS; | |
1181 | ||
1da177e4 | 1182 | show_regs(regs); |
cac4bcbc RB |
1183 | |
1184 | if (multi_match) { | |
70342287 | 1185 | printk("Index : %0x\n", read_c0_index()); |
cac4bcbc RB |
1186 | printk("Pagemask: %0x\n", read_c0_pagemask()); |
1187 | printk("EntryHi : %0*lx\n", field, read_c0_entryhi()); | |
1188 | printk("EntryLo0: %0*lx\n", field, read_c0_entrylo0()); | |
1189 | printk("EntryLo1: %0*lx\n", field, read_c0_entrylo1()); | |
1190 | printk("\n"); | |
1191 | dump_tlb_all(); | |
1192 | } | |
1193 | ||
e1bb8289 | 1194 | show_code((unsigned int __user *) regs->cp0_epc); |
cac4bcbc | 1195 | |
1da177e4 LT |
1196 | /* |
1197 | * Some chips may have other causes of machine check (e.g. SB1 | |
1198 | * graduation timer) | |
1199 | */ | |
1200 | panic("Caught Machine Check exception - %scaused by multiple " | |
1201 | "matching entries in the TLB.", | |
cac4bcbc | 1202 | (multi_match) ? "" : "not "); |
1da177e4 LT |
1203 | } |
1204 | ||
340ee4b9 RB |
1205 | asmlinkage void do_mt(struct pt_regs *regs) |
1206 | { | |
41c594ab RB |
1207 | int subcode; |
1208 | ||
41c594ab RB |
1209 | subcode = (read_vpe_c0_vpecontrol() & VPECONTROL_EXCPT) |
1210 | >> VPECONTROL_EXCPT_SHIFT; | |
1211 | switch (subcode) { | |
1212 | case 0: | |
e35a5e35 | 1213 | printk(KERN_DEBUG "Thread Underflow\n"); |
41c594ab RB |
1214 | break; |
1215 | case 1: | |
e35a5e35 | 1216 | printk(KERN_DEBUG "Thread Overflow\n"); |
41c594ab RB |
1217 | break; |
1218 | case 2: | |
e35a5e35 | 1219 | printk(KERN_DEBUG "Invalid YIELD Qualifier\n"); |
41c594ab RB |
1220 | break; |
1221 | case 3: | |
e35a5e35 | 1222 | printk(KERN_DEBUG "Gating Storage Exception\n"); |
41c594ab RB |
1223 | break; |
1224 | case 4: | |
e35a5e35 | 1225 | printk(KERN_DEBUG "YIELD Scheduler Exception\n"); |
41c594ab RB |
1226 | break; |
1227 | case 5: | |
f232c7e8 | 1228 | printk(KERN_DEBUG "Gating Storage Scheduler Exception\n"); |
41c594ab RB |
1229 | break; |
1230 | default: | |
e35a5e35 | 1231 | printk(KERN_DEBUG "*** UNKNOWN THREAD EXCEPTION %d ***\n", |
41c594ab RB |
1232 | subcode); |
1233 | break; | |
1234 | } | |
340ee4b9 RB |
1235 | die_if_kernel("MIPS MT Thread exception in kernel", regs); |
1236 | ||
1237 | force_sig(SIGILL, current); | |
1238 | } | |
1239 | ||
1240 | ||
e50c0a8f RB |
1241 | asmlinkage void do_dsp(struct pt_regs *regs) |
1242 | { | |
1243 | if (cpu_has_dsp) | |
ab75dc02 | 1244 | panic("Unexpected DSP exception"); |
e50c0a8f RB |
1245 | |
1246 | force_sig(SIGILL, current); | |
1247 | } | |
1248 | ||
1da177e4 LT |
1249 | asmlinkage void do_reserved(struct pt_regs *regs) |
1250 | { | |
1251 | /* | |
70342287 | 1252 | * Game over - no way to handle this if it ever occurs. Most probably |
1da177e4 LT |
1253 | * caused by a new unknown cpu type or after another deadly |
1254 | * hard/software error. | |
1255 | */ | |
1256 | show_regs(regs); | |
1257 | panic("Caught reserved exception %ld - should not happen.", | |
1258 | (regs->cp0_cause & 0x7f) >> 2); | |
1259 | } | |
1260 | ||
39b8d525 RB |
1261 | static int __initdata l1parity = 1; |
1262 | static int __init nol1parity(char *s) | |
1263 | { | |
1264 | l1parity = 0; | |
1265 | return 1; | |
1266 | } | |
1267 | __setup("nol1par", nol1parity); | |
1268 | static int __initdata l2parity = 1; | |
1269 | static int __init nol2parity(char *s) | |
1270 | { | |
1271 | l2parity = 0; | |
1272 | return 1; | |
1273 | } | |
1274 | __setup("nol2par", nol2parity); | |
1275 | ||
1da177e4 LT |
1276 | /* |
1277 | * Some MIPS CPUs can enable/disable for cache parity detection, but do | |
1278 | * it different ways. | |
1279 | */ | |
1280 | static inline void parity_protection_init(void) | |
1281 | { | |
10cc3529 | 1282 | switch (current_cpu_type()) { |
1da177e4 | 1283 | case CPU_24K: |
98a41de9 | 1284 | case CPU_34K: |
39b8d525 RB |
1285 | case CPU_74K: |
1286 | case CPU_1004K: | |
1287 | { | |
1288 | #define ERRCTL_PE 0x80000000 | |
1289 | #define ERRCTL_L2P 0x00800000 | |
1290 | unsigned long errctl; | |
1291 | unsigned int l1parity_present, l2parity_present; | |
1292 | ||
1293 | errctl = read_c0_ecc(); | |
1294 | errctl &= ~(ERRCTL_PE|ERRCTL_L2P); | |
1295 | ||
1296 | /* probe L1 parity support */ | |
1297 | write_c0_ecc(errctl | ERRCTL_PE); | |
1298 | back_to_back_c0_hazard(); | |
1299 | l1parity_present = (read_c0_ecc() & ERRCTL_PE); | |
1300 | ||
1301 | /* probe L2 parity support */ | |
1302 | write_c0_ecc(errctl|ERRCTL_L2P); | |
1303 | back_to_back_c0_hazard(); | |
1304 | l2parity_present = (read_c0_ecc() & ERRCTL_L2P); | |
1305 | ||
1306 | if (l1parity_present && l2parity_present) { | |
1307 | if (l1parity) | |
1308 | errctl |= ERRCTL_PE; | |
1309 | if (l1parity ^ l2parity) | |
1310 | errctl |= ERRCTL_L2P; | |
1311 | } else if (l1parity_present) { | |
1312 | if (l1parity) | |
1313 | errctl |= ERRCTL_PE; | |
1314 | } else if (l2parity_present) { | |
1315 | if (l2parity) | |
1316 | errctl |= ERRCTL_L2P; | |
1317 | } else { | |
1318 | /* No parity available */ | |
1319 | } | |
1320 | ||
1321 | printk(KERN_INFO "Writing ErrCtl register=%08lx\n", errctl); | |
1322 | ||
1323 | write_c0_ecc(errctl); | |
1324 | back_to_back_c0_hazard(); | |
1325 | errctl = read_c0_ecc(); | |
1326 | printk(KERN_INFO "Readback ErrCtl register=%08lx\n", errctl); | |
1327 | ||
1328 | if (l1parity_present) | |
1329 | printk(KERN_INFO "Cache parity protection %sabled\n", | |
1330 | (errctl & ERRCTL_PE) ? "en" : "dis"); | |
1331 | ||
1332 | if (l2parity_present) { | |
1333 | if (l1parity_present && l1parity) | |
1334 | errctl ^= ERRCTL_L2P; | |
1335 | printk(KERN_INFO "L2 cache parity protection %sabled\n", | |
1336 | (errctl & ERRCTL_L2P) ? "en" : "dis"); | |
1337 | } | |
1338 | } | |
1339 | break; | |
1340 | ||
1da177e4 | 1341 | case CPU_5KC: |
78d4803f | 1342 | case CPU_5KE: |
2fa36399 | 1343 | case CPU_LOONGSON1: |
14f18b7f RB |
1344 | write_c0_ecc(0x80000000); |
1345 | back_to_back_c0_hazard(); | |
1346 | /* Set the PE bit (bit 31) in the c0_errctl register. */ | |
1347 | printk(KERN_INFO "Cache parity protection %sabled\n", | |
1348 | (read_c0_ecc() & 0x80000000) ? "en" : "dis"); | |
1da177e4 LT |
1349 | break; |
1350 | case CPU_20KC: | |
1351 | case CPU_25KF: | |
1352 | /* Clear the DE bit (bit 16) in the c0_status register. */ | |
1353 | printk(KERN_INFO "Enable cache parity protection for " | |
1354 | "MIPS 20KC/25KF CPUs.\n"); | |
1355 | clear_c0_status(ST0_DE); | |
1356 | break; | |
1357 | default: | |
1358 | break; | |
1359 | } | |
1360 | } | |
1361 | ||
1362 | asmlinkage void cache_parity_error(void) | |
1363 | { | |
1364 | const int field = 2 * sizeof(unsigned long); | |
1365 | unsigned int reg_val; | |
1366 | ||
1367 | /* For the moment, report the problem and hang. */ | |
1368 | printk("Cache error exception:\n"); | |
1369 | printk("cp0_errorepc == %0*lx\n", field, read_c0_errorepc()); | |
1370 | reg_val = read_c0_cacheerr(); | |
1371 | printk("c0_cacheerr == %08x\n", reg_val); | |
1372 | ||
1373 | printk("Decoded c0_cacheerr: %s cache fault in %s reference.\n", | |
1374 | reg_val & (1<<30) ? "secondary" : "primary", | |
1375 | reg_val & (1<<31) ? "data" : "insn"); | |
1376 | printk("Error bits: %s%s%s%s%s%s%s\n", | |
1377 | reg_val & (1<<29) ? "ED " : "", | |
1378 | reg_val & (1<<28) ? "ET " : "", | |
1379 | reg_val & (1<<26) ? "EE " : "", | |
1380 | reg_val & (1<<25) ? "EB " : "", | |
1381 | reg_val & (1<<24) ? "EI " : "", | |
1382 | reg_val & (1<<23) ? "E1 " : "", | |
1383 | reg_val & (1<<22) ? "E0 " : ""); | |
1384 | printk("IDX: 0x%08x\n", reg_val & ((1<<22)-1)); | |
1385 | ||
ec917c2c | 1386 | #if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64) |
1da177e4 LT |
1387 | if (reg_val & (1<<22)) |
1388 | printk("DErrAddr0: 0x%0*lx\n", field, read_c0_derraddr0()); | |
1389 | ||
1390 | if (reg_val & (1<<23)) | |
1391 | printk("DErrAddr1: 0x%0*lx\n", field, read_c0_derraddr1()); | |
1392 | #endif | |
1393 | ||
1394 | panic("Can't handle the cache error!"); | |
1395 | } | |
1396 | ||
1397 | /* | |
1398 | * SDBBP EJTAG debug exception handler. | |
1399 | * We skip the instruction and return to the next instruction. | |
1400 | */ | |
1401 | void ejtag_exception_handler(struct pt_regs *regs) | |
1402 | { | |
1403 | const int field = 2 * sizeof(unsigned long); | |
2a0b24f5 | 1404 | unsigned long depc, old_epc, old_ra; |
1da177e4 LT |
1405 | unsigned int debug; |
1406 | ||
70ae6126 | 1407 | printk(KERN_DEBUG "SDBBP EJTAG debug exception - not handled yet, just ignored!\n"); |
1da177e4 LT |
1408 | depc = read_c0_depc(); |
1409 | debug = read_c0_debug(); | |
70ae6126 | 1410 | printk(KERN_DEBUG "c0_depc = %0*lx, DEBUG = %08x\n", field, depc, debug); |
1da177e4 LT |
1411 | if (debug & 0x80000000) { |
1412 | /* | |
1413 | * In branch delay slot. | |
1414 | * We cheat a little bit here and use EPC to calculate the | |
1415 | * debug return address (DEPC). EPC is restored after the | |
1416 | * calculation. | |
1417 | */ | |
1418 | old_epc = regs->cp0_epc; | |
2a0b24f5 | 1419 | old_ra = regs->regs[31]; |
1da177e4 | 1420 | regs->cp0_epc = depc; |
2a0b24f5 | 1421 | compute_return_epc(regs); |
1da177e4 LT |
1422 | depc = regs->cp0_epc; |
1423 | regs->cp0_epc = old_epc; | |
2a0b24f5 | 1424 | regs->regs[31] = old_ra; |
1da177e4 LT |
1425 | } else |
1426 | depc += 4; | |
1427 | write_c0_depc(depc); | |
1428 | ||
1429 | #if 0 | |
70ae6126 | 1430 | printk(KERN_DEBUG "\n\n----- Enable EJTAG single stepping ----\n\n"); |
1da177e4 LT |
1431 | write_c0_debug(debug | 0x100); |
1432 | #endif | |
1433 | } | |
1434 | ||
1435 | /* | |
1436 | * NMI exception handler. | |
34bd92e2 | 1437 | * No lock; only written during early bootup by CPU 0. |
1da177e4 | 1438 | */ |
34bd92e2 KC |
1439 | static RAW_NOTIFIER_HEAD(nmi_chain); |
1440 | ||
1441 | int register_nmi_notifier(struct notifier_block *nb) | |
1442 | { | |
1443 | return raw_notifier_chain_register(&nmi_chain, nb); | |
1444 | } | |
1445 | ||
ff2d8b19 | 1446 | void __noreturn nmi_exception_handler(struct pt_regs *regs) |
1da177e4 | 1447 | { |
34bd92e2 | 1448 | raw_notifier_call_chain(&nmi_chain, 0, regs); |
41c594ab | 1449 | bust_spinlocks(1); |
1da177e4 LT |
1450 | printk("NMI taken!!!!\n"); |
1451 | die("NMI", regs); | |
1da177e4 LT |
1452 | } |
1453 | ||
e01402b1 RB |
1454 | #define VECTORSPACING 0x100 /* for EI/VI mode */ |
1455 | ||
1456 | unsigned long ebase; | |
1da177e4 | 1457 | unsigned long exception_handlers[32]; |
e01402b1 | 1458 | unsigned long vi_handlers[64]; |
1da177e4 | 1459 | |
2d1b6e95 | 1460 | void __init *set_except_vector(int n, void *addr) |
1da177e4 LT |
1461 | { |
1462 | unsigned long handler = (unsigned long) addr; | |
b22d1b6a | 1463 | unsigned long old_handler; |
1da177e4 | 1464 | |
2a0b24f5 SH |
1465 | #ifdef CONFIG_CPU_MICROMIPS |
1466 | /* | |
1467 | * Only the TLB handlers are cache aligned with an even | |
1468 | * address. All other handlers are on an odd address and | |
1469 | * require no modification. Otherwise, MIPS32 mode will | |
1470 | * be entered when handling any TLB exceptions. That | |
1471 | * would be bad...since we must stay in microMIPS mode. | |
1472 | */ | |
1473 | if (!(handler & 0x1)) | |
1474 | handler |= 1; | |
1475 | #endif | |
b22d1b6a | 1476 | old_handler = xchg(&exception_handlers[n], handler); |
1da177e4 | 1477 | |
1da177e4 | 1478 | if (n == 0 && cpu_has_divec) { |
2a0b24f5 SH |
1479 | #ifdef CONFIG_CPU_MICROMIPS |
1480 | unsigned long jump_mask = ~((1 << 27) - 1); | |
1481 | #else | |
92bbe1b9 | 1482 | unsigned long jump_mask = ~((1 << 28) - 1); |
2a0b24f5 | 1483 | #endif |
92bbe1b9 FF |
1484 | u32 *buf = (u32 *)(ebase + 0x200); |
1485 | unsigned int k0 = 26; | |
1486 | if ((handler & jump_mask) == ((ebase + 0x200) & jump_mask)) { | |
1487 | uasm_i_j(&buf, handler & ~jump_mask); | |
1488 | uasm_i_nop(&buf); | |
1489 | } else { | |
1490 | UASM_i_LA(&buf, k0, handler); | |
1491 | uasm_i_jr(&buf, k0); | |
1492 | uasm_i_nop(&buf); | |
1493 | } | |
1494 | local_flush_icache_range(ebase + 0x200, (unsigned long)buf); | |
e01402b1 RB |
1495 | } |
1496 | return (void *)old_handler; | |
1497 | } | |
1498 | ||
86a1708a | 1499 | static void do_default_vi(void) |
6ba07e59 AN |
1500 | { |
1501 | show_regs(get_irq_regs()); | |
1502 | panic("Caught unexpected vectored interrupt."); | |
1503 | } | |
1504 | ||
ef300e42 | 1505 | static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs) |
e01402b1 RB |
1506 | { |
1507 | unsigned long handler; | |
1508 | unsigned long old_handler = vi_handlers[n]; | |
f6771dbb | 1509 | int srssets = current_cpu_data.srsets; |
2a0b24f5 | 1510 | u16 *h; |
e01402b1 RB |
1511 | unsigned char *b; |
1512 | ||
b72b7092 | 1513 | BUG_ON(!cpu_has_veic && !cpu_has_vint); |
2a0b24f5 | 1514 | BUG_ON((n < 0) && (n > 9)); |
e01402b1 RB |
1515 | |
1516 | if (addr == NULL) { | |
1517 | handler = (unsigned long) do_default_vi; | |
1518 | srs = 0; | |
41c594ab | 1519 | } else |
e01402b1 | 1520 | handler = (unsigned long) addr; |
2a0b24f5 | 1521 | vi_handlers[n] = handler; |
e01402b1 RB |
1522 | |
1523 | b = (unsigned char *)(ebase + 0x200 + n*VECTORSPACING); | |
1524 | ||
f6771dbb | 1525 | if (srs >= srssets) |
e01402b1 RB |
1526 | panic("Shadow register set %d not supported", srs); |
1527 | ||
1528 | if (cpu_has_veic) { | |
1529 | if (board_bind_eic_interrupt) | |
49a89efb | 1530 | board_bind_eic_interrupt(n, srs); |
41c594ab | 1531 | } else if (cpu_has_vint) { |
e01402b1 | 1532 | /* SRSMap is only defined if shadow sets are implemented */ |
f6771dbb | 1533 | if (srssets > 1) |
49a89efb | 1534 | change_c0_srsmap(0xf << n*4, srs << n*4); |
e01402b1 RB |
1535 | } |
1536 | ||
1537 | if (srs == 0) { | |
1538 | /* | |
1539 | * If no shadow set is selected then use the default handler | |
2a0b24f5 | 1540 | * that does normal register saving and standard interrupt exit |
e01402b1 | 1541 | */ |
e01402b1 RB |
1542 | extern char except_vec_vi, except_vec_vi_lui; |
1543 | extern char except_vec_vi_ori, except_vec_vi_end; | |
c65a5480 AN |
1544 | extern char rollback_except_vec_vi; |
1545 | char *vec_start = (cpu_wait == r4k_wait) ? | |
1546 | &rollback_except_vec_vi : &except_vec_vi; | |
41c594ab RB |
1547 | #ifdef CONFIG_MIPS_MT_SMTC |
1548 | /* | |
1549 | * We need to provide the SMTC vectored interrupt handler | |
1550 | * not only with the address of the handler, but with the | |
1551 | * Status.IM bit to be masked before going there. | |
1552 | */ | |
1553 | extern char except_vec_vi_mori; | |
2a0b24f5 SH |
1554 | #if defined(CONFIG_CPU_MICROMIPS) || defined(CONFIG_CPU_BIG_ENDIAN) |
1555 | const int mori_offset = &except_vec_vi_mori - vec_start + 2; | |
1556 | #else | |
c65a5480 | 1557 | const int mori_offset = &except_vec_vi_mori - vec_start; |
2a0b24f5 | 1558 | #endif |
41c594ab | 1559 | #endif /* CONFIG_MIPS_MT_SMTC */ |
2a0b24f5 SH |
1560 | #if defined(CONFIG_CPU_MICROMIPS) || defined(CONFIG_CPU_BIG_ENDIAN) |
1561 | const int lui_offset = &except_vec_vi_lui - vec_start + 2; | |
1562 | const int ori_offset = &except_vec_vi_ori - vec_start + 2; | |
1563 | #else | |
c65a5480 AN |
1564 | const int lui_offset = &except_vec_vi_lui - vec_start; |
1565 | const int ori_offset = &except_vec_vi_ori - vec_start; | |
2a0b24f5 SH |
1566 | #endif |
1567 | const int handler_len = &except_vec_vi_end - vec_start; | |
e01402b1 RB |
1568 | |
1569 | if (handler_len > VECTORSPACING) { | |
1570 | /* | |
1571 | * Sigh... panicing won't help as the console | |
1572 | * is probably not configured :( | |
1573 | */ | |
49a89efb | 1574 | panic("VECTORSPACING too small"); |
e01402b1 RB |
1575 | } |
1576 | ||
2a0b24f5 SH |
1577 | set_handler(((unsigned long)b - ebase), vec_start, |
1578 | #ifdef CONFIG_CPU_MICROMIPS | |
1579 | (handler_len - 1)); | |
1580 | #else | |
1581 | handler_len); | |
1582 | #endif | |
41c594ab | 1583 | #ifdef CONFIG_MIPS_MT_SMTC |
8e8a52ed RB |
1584 | BUG_ON(n > 7); /* Vector index %d exceeds SMTC maximum. */ |
1585 | ||
2a0b24f5 SH |
1586 | h = (u16 *)(b + mori_offset); |
1587 | *h = (0x100 << n); | |
41c594ab | 1588 | #endif /* CONFIG_MIPS_MT_SMTC */ |
2a0b24f5 SH |
1589 | h = (u16 *)(b + lui_offset); |
1590 | *h = (handler >> 16) & 0xffff; | |
1591 | h = (u16 *)(b + ori_offset); | |
1592 | *h = (handler & 0xffff); | |
e0cee3ee TB |
1593 | local_flush_icache_range((unsigned long)b, |
1594 | (unsigned long)(b+handler_len)); | |
e01402b1 RB |
1595 | } |
1596 | else { | |
1597 | /* | |
2a0b24f5 SH |
1598 | * In other cases jump directly to the interrupt handler. It |
1599 | * is the handler's responsibility to save registers if required | |
1600 | * (eg hi/lo) and return from the exception using "eret". | |
e01402b1 | 1601 | */ |
2a0b24f5 SH |
1602 | u32 insn; |
1603 | ||
1604 | h = (u16 *)b; | |
1605 | /* j handler */ | |
1606 | #ifdef CONFIG_CPU_MICROMIPS | |
1607 | insn = 0xd4000000 | (((u32)handler & 0x07ffffff) >> 1); | |
1608 | #else | |
1609 | insn = 0x08000000 | (((u32)handler & 0x0fffffff) >> 2); | |
1610 | #endif | |
1611 | h[0] = (insn >> 16) & 0xffff; | |
1612 | h[1] = insn & 0xffff; | |
1613 | h[2] = 0; | |
1614 | h[3] = 0; | |
e0cee3ee TB |
1615 | local_flush_icache_range((unsigned long)b, |
1616 | (unsigned long)(b+8)); | |
1da177e4 | 1617 | } |
e01402b1 | 1618 | |
1da177e4 LT |
1619 | return (void *)old_handler; |
1620 | } | |
1621 | ||
ef300e42 | 1622 | void *set_vi_handler(int n, vi_handler_t addr) |
e01402b1 | 1623 | { |
ff3eab2a | 1624 | return set_vi_srs_handler(n, addr, 0); |
e01402b1 | 1625 | } |
f41ae0b2 | 1626 | |
1da177e4 | 1627 | extern void tlb_init(void); |
1d40cfcd | 1628 | extern void flush_tlb_handlers(void); |
1da177e4 | 1629 | |
42f77542 RB |
1630 | /* |
1631 | * Timer interrupt | |
1632 | */ | |
1633 | int cp0_compare_irq; | |
68b6352c | 1634 | EXPORT_SYMBOL_GPL(cp0_compare_irq); |
010c108d | 1635 | int cp0_compare_irq_shift; |
42f77542 RB |
1636 | |
1637 | /* | |
1638 | * Performance counter IRQ or -1 if shared with timer | |
1639 | */ | |
1640 | int cp0_perfcount_irq; | |
1641 | EXPORT_SYMBOL_GPL(cp0_perfcount_irq); | |
1642 | ||
bdc94eb4 CD |
1643 | static int __cpuinitdata noulri; |
1644 | ||
1645 | static int __init ulri_disable(char *s) | |
1646 | { | |
1647 | pr_info("Disabling ulri\n"); | |
1648 | noulri = 1; | |
1649 | ||
1650 | return 1; | |
1651 | } | |
1652 | __setup("noulri", ulri_disable); | |
1653 | ||
6650df3c | 1654 | void __cpuinit per_cpu_trap_init(bool is_boot_cpu) |
1da177e4 LT |
1655 | { |
1656 | unsigned int cpu = smp_processor_id(); | |
1657 | unsigned int status_set = ST0_CU0; | |
18d693b3 | 1658 | unsigned int hwrena = cpu_hwrena_impl_bits; |
d532f3d2 | 1659 | unsigned long asid = 0; |
41c594ab RB |
1660 | #ifdef CONFIG_MIPS_MT_SMTC |
1661 | int secondaryTC = 0; | |
1662 | int bootTC = (cpu == 0); | |
1663 | ||
1664 | /* | |
1665 | * Only do per_cpu_trap_init() for first TC of Each VPE. | |
1666 | * Note that this hack assumes that the SMTC init code | |
1667 | * assigns TCs consecutively and in ascending order. | |
1668 | */ | |
1669 | ||
1670 | if (((read_c0_tcbind() & TCBIND_CURTC) != 0) && | |
1671 | ((read_c0_tcbind() & TCBIND_CURVPE) == cpu_data[cpu - 1].vpe_id)) | |
1672 | secondaryTC = 1; | |
1673 | #endif /* CONFIG_MIPS_MT_SMTC */ | |
1da177e4 LT |
1674 | |
1675 | /* | |
1676 | * Disable coprocessors and select 32-bit or 64-bit addressing | |
1677 | * and the 16/32 or 32/32 FPR register model. Reset the BEV | |
1678 | * flag that some firmware may have left set and the TS bit (for | |
1679 | * IP27). Set XX for ISA IV code to work. | |
1680 | */ | |
875d43e7 | 1681 | #ifdef CONFIG_64BIT |
1da177e4 LT |
1682 | status_set |= ST0_FR|ST0_KX|ST0_SX|ST0_UX; |
1683 | #endif | |
adb37892 | 1684 | if (current_cpu_data.isa_level & MIPS_CPU_ISA_IV) |
1da177e4 | 1685 | status_set |= ST0_XX; |
bbaf238b CD |
1686 | if (cpu_has_dsp) |
1687 | status_set |= ST0_MX; | |
1688 | ||
b38c7399 | 1689 | change_c0_status(ST0_CU|ST0_MX|ST0_RE|ST0_FR|ST0_BEV|ST0_TS|ST0_KX|ST0_SX|ST0_UX, |
1da177e4 LT |
1690 | status_set); |
1691 | ||
18d693b3 KC |
1692 | if (cpu_has_mips_r2) |
1693 | hwrena |= 0x0000000f; | |
a3692020 | 1694 | |
18d693b3 KC |
1695 | if (!noulri && cpu_has_userlocal) |
1696 | hwrena |= (1 << 29); | |
a3692020 | 1697 | |
18d693b3 KC |
1698 | if (hwrena) |
1699 | write_c0_hwrena(hwrena); | |
e01402b1 | 1700 | |
41c594ab RB |
1701 | #ifdef CONFIG_MIPS_MT_SMTC |
1702 | if (!secondaryTC) { | |
1703 | #endif /* CONFIG_MIPS_MT_SMTC */ | |
1704 | ||
e01402b1 | 1705 | if (cpu_has_veic || cpu_has_vint) { |
9fb4c2b9 | 1706 | unsigned long sr = set_c0_status(ST0_BEV); |
49a89efb | 1707 | write_c0_ebase(ebase); |
9fb4c2b9 | 1708 | write_c0_status(sr); |
e01402b1 | 1709 | /* Setting vector spacing enables EI/VI mode */ |
49a89efb | 1710 | change_c0_intctl(0x3e0, VECTORSPACING); |
e01402b1 | 1711 | } |
d03d0a57 RB |
1712 | if (cpu_has_divec) { |
1713 | if (cpu_has_mipsmt) { | |
1714 | unsigned int vpflags = dvpe(); | |
1715 | set_c0_cause(CAUSEF_IV); | |
1716 | evpe(vpflags); | |
1717 | } else | |
1718 | set_c0_cause(CAUSEF_IV); | |
1719 | } | |
3b1d4ed5 RB |
1720 | |
1721 | /* | |
1722 | * Before R2 both interrupt numbers were fixed to 7, so on R2 only: | |
1723 | * | |
1724 | * o read IntCtl.IPTI to determine the timer interrupt | |
1725 | * o read IntCtl.IPPCI to determine the performance counter interrupt | |
1726 | */ | |
1727 | if (cpu_has_mips_r2) { | |
010c108d DV |
1728 | cp0_compare_irq_shift = CAUSEB_TI - CAUSEB_IP; |
1729 | cp0_compare_irq = (read_c0_intctl() >> INTCTLB_IPTI) & 7; | |
1730 | cp0_perfcount_irq = (read_c0_intctl() >> INTCTLB_IPPCI) & 7; | |
c3e838a2 | 1731 | if (cp0_perfcount_irq == cp0_compare_irq) |
3b1d4ed5 | 1732 | cp0_perfcount_irq = -1; |
c3e838a2 CD |
1733 | } else { |
1734 | cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ; | |
c6a4ebb9 | 1735 | cp0_compare_irq_shift = CP0_LEGACY_PERFCNT_IRQ; |
c3e838a2 | 1736 | cp0_perfcount_irq = -1; |
3b1d4ed5 RB |
1737 | } |
1738 | ||
41c594ab RB |
1739 | #ifdef CONFIG_MIPS_MT_SMTC |
1740 | } | |
1741 | #endif /* CONFIG_MIPS_MT_SMTC */ | |
1da177e4 | 1742 | |
d532f3d2 SH |
1743 | asid = ASID_FIRST_VERSION; |
1744 | cpu_data[cpu].asid_cache = asid; | |
1745 | TLBMISS_HANDLER_SETUP(); | |
1da177e4 LT |
1746 | |
1747 | atomic_inc(&init_mm.mm_count); | |
1748 | current->active_mm = &init_mm; | |
1749 | BUG_ON(current->mm); | |
1750 | enter_lazy_tlb(&init_mm, current); | |
1751 | ||
41c594ab RB |
1752 | #ifdef CONFIG_MIPS_MT_SMTC |
1753 | if (bootTC) { | |
1754 | #endif /* CONFIG_MIPS_MT_SMTC */ | |
6650df3c DD |
1755 | /* Boot CPU's cache setup in setup_arch(). */ |
1756 | if (!is_boot_cpu) | |
1757 | cpu_cache_init(); | |
41c594ab RB |
1758 | tlb_init(); |
1759 | #ifdef CONFIG_MIPS_MT_SMTC | |
6a05888d RB |
1760 | } else if (!secondaryTC) { |
1761 | /* | |
1762 | * First TC in non-boot VPE must do subset of tlb_init() | |
1763 | * for MMU countrol registers. | |
1764 | */ | |
1765 | write_c0_pagemask(PM_DEFAULT_MASK); | |
1766 | write_c0_wired(0); | |
41c594ab RB |
1767 | } |
1768 | #endif /* CONFIG_MIPS_MT_SMTC */ | |
3d8bfdd0 | 1769 | TLBMISS_HANDLER_SETUP(); |
1da177e4 LT |
1770 | } |
1771 | ||
e01402b1 | 1772 | /* Install CPU exception handler */ |
e3dc81f2 | 1773 | void __cpuinit set_handler(unsigned long offset, void *addr, unsigned long size) |
e01402b1 | 1774 | { |
2a0b24f5 SH |
1775 | #ifdef CONFIG_CPU_MICROMIPS |
1776 | memcpy((void *)(ebase + offset), ((unsigned char *)addr - 1), size); | |
1777 | #else | |
e01402b1 | 1778 | memcpy((void *)(ebase + offset), addr, size); |
2a0b24f5 | 1779 | #endif |
e0cee3ee | 1780 | local_flush_icache_range(ebase + offset, ebase + offset + size); |
e01402b1 RB |
1781 | } |
1782 | ||
234fcd14 | 1783 | static char panic_null_cerr[] __cpuinitdata = |
641e97f3 RB |
1784 | "Trying to set NULL cache error exception handler"; |
1785 | ||
42fe7ee3 RB |
1786 | /* |
1787 | * Install uncached CPU exception handler. | |
1788 | * This is suitable only for the cache error exception which is the only | |
1789 | * exception handler that is being run uncached. | |
1790 | */ | |
234fcd14 RB |
1791 | void __cpuinit set_uncached_handler(unsigned long offset, void *addr, |
1792 | unsigned long size) | |
e01402b1 | 1793 | { |
4f81b01a | 1794 | unsigned long uncached_ebase = CKSEG1ADDR(ebase); |
e01402b1 | 1795 | |
641e97f3 RB |
1796 | if (!addr) |
1797 | panic(panic_null_cerr); | |
1798 | ||
e01402b1 RB |
1799 | memcpy((void *)(uncached_ebase + offset), addr, size); |
1800 | } | |
1801 | ||
5b10496b AN |
1802 | static int __initdata rdhwr_noopt; |
1803 | static int __init set_rdhwr_noopt(char *str) | |
1804 | { | |
1805 | rdhwr_noopt = 1; | |
1806 | return 1; | |
1807 | } | |
1808 | ||
1809 | __setup("rdhwr_noopt", set_rdhwr_noopt); | |
1810 | ||
1da177e4 LT |
1811 | void __init trap_init(void) |
1812 | { | |
2a0b24f5 | 1813 | extern char except_vec3_generic; |
1da177e4 | 1814 | extern char except_vec4; |
2a0b24f5 | 1815 | extern char except_vec3_r4000; |
1da177e4 | 1816 | unsigned long i; |
c65a5480 AN |
1817 | int rollback; |
1818 | ||
1819 | check_wait(); | |
1820 | rollback = (cpu_wait == r4k_wait); | |
1da177e4 | 1821 | |
88547001 JW |
1822 | #if defined(CONFIG_KGDB) |
1823 | if (kgdb_early_setup) | |
70342287 | 1824 | return; /* Already done */ |
88547001 JW |
1825 | #endif |
1826 | ||
9fb4c2b9 CD |
1827 | if (cpu_has_veic || cpu_has_vint) { |
1828 | unsigned long size = 0x200 + VECTORSPACING*64; | |
1829 | ebase = (unsigned long) | |
1830 | __alloc_bootmem(size, 1 << fls(size), 0); | |
1831 | } else { | |
9843b030 SL |
1832 | #ifdef CONFIG_KVM_GUEST |
1833 | #define KVM_GUEST_KSEG0 0x40000000 | |
1834 | ebase = KVM_GUEST_KSEG0; | |
1835 | #else | |
1836 | ebase = CKSEG0; | |
1837 | #endif | |
566f74f6 DD |
1838 | if (cpu_has_mips_r2) |
1839 | ebase += (read_c0_ebase() & 0x3ffff000); | |
1840 | } | |
e01402b1 | 1841 | |
6fb97eff KC |
1842 | if (board_ebase_setup) |
1843 | board_ebase_setup(); | |
6650df3c | 1844 | per_cpu_trap_init(true); |
1da177e4 LT |
1845 | |
1846 | /* | |
1847 | * Copy the generic exception handlers to their final destination. | |
1848 | * This will be overriden later as suitable for a particular | |
1849 | * configuration. | |
1850 | */ | |
e01402b1 | 1851 | set_handler(0x180, &except_vec3_generic, 0x80); |
1da177e4 LT |
1852 | |
1853 | /* | |
1854 | * Setup default vectors | |
1855 | */ | |
1856 | for (i = 0; i <= 31; i++) | |
1857 | set_except_vector(i, handle_reserved); | |
1858 | ||
1859 | /* | |
1860 | * Copy the EJTAG debug exception vector handler code to it's final | |
1861 | * destination. | |
1862 | */ | |
e01402b1 | 1863 | if (cpu_has_ejtag && board_ejtag_handler_setup) |
49a89efb | 1864 | board_ejtag_handler_setup(); |
1da177e4 LT |
1865 | |
1866 | /* | |
1867 | * Only some CPUs have the watch exceptions. | |
1868 | */ | |
1869 | if (cpu_has_watch) | |
1870 | set_except_vector(23, handle_watch); | |
1871 | ||
1872 | /* | |
e01402b1 | 1873 | * Initialise interrupt handlers |
1da177e4 | 1874 | */ |
e01402b1 RB |
1875 | if (cpu_has_veic || cpu_has_vint) { |
1876 | int nvec = cpu_has_veic ? 64 : 8; | |
1877 | for (i = 0; i < nvec; i++) | |
ff3eab2a | 1878 | set_vi_handler(i, NULL); |
e01402b1 RB |
1879 | } |
1880 | else if (cpu_has_divec) | |
1881 | set_handler(0x200, &except_vec4, 0x8); | |
1da177e4 LT |
1882 | |
1883 | /* | |
1884 | * Some CPUs can enable/disable for cache parity detection, but does | |
1885 | * it different ways. | |
1886 | */ | |
1887 | parity_protection_init(); | |
1888 | ||
1889 | /* | |
1890 | * The Data Bus Errors / Instruction Bus Errors are signaled | |
1891 | * by external hardware. Therefore these two exceptions | |
1892 | * may have board specific handlers. | |
1893 | */ | |
1894 | if (board_be_init) | |
1895 | board_be_init(); | |
1896 | ||
c65a5480 | 1897 | set_except_vector(0, rollback ? rollback_handle_int : handle_int); |
1da177e4 LT |
1898 | set_except_vector(1, handle_tlbm); |
1899 | set_except_vector(2, handle_tlbl); | |
1900 | set_except_vector(3, handle_tlbs); | |
1901 | ||
1902 | set_except_vector(4, handle_adel); | |
1903 | set_except_vector(5, handle_ades); | |
1904 | ||
1905 | set_except_vector(6, handle_ibe); | |
1906 | set_except_vector(7, handle_dbe); | |
1907 | ||
1908 | set_except_vector(8, handle_sys); | |
1909 | set_except_vector(9, handle_bp); | |
5b10496b AN |
1910 | set_except_vector(10, rdhwr_noopt ? handle_ri : |
1911 | (cpu_has_vtag_icache ? | |
1912 | handle_ri_rdhwr_vivt : handle_ri_rdhwr)); | |
1da177e4 LT |
1913 | set_except_vector(11, handle_cpu); |
1914 | set_except_vector(12, handle_ov); | |
1915 | set_except_vector(13, handle_tr); | |
1da177e4 | 1916 | |
10cc3529 RB |
1917 | if (current_cpu_type() == CPU_R6000 || |
1918 | current_cpu_type() == CPU_R6000A) { | |
1da177e4 LT |
1919 | /* |
1920 | * The R6000 is the only R-series CPU that features a machine | |
1921 | * check exception (similar to the R4000 cache error) and | |
1922 | * unaligned ldc1/sdc1 exception. The handlers have not been | |
70342287 | 1923 | * written yet. Well, anyway there is no R6000 machine on the |
1da177e4 LT |
1924 | * current list of targets for Linux/MIPS. |
1925 | * (Duh, crap, there is someone with a triple R6k machine) | |
1926 | */ | |
1927 | //set_except_vector(14, handle_mc); | |
1928 | //set_except_vector(15, handle_ndc); | |
1929 | } | |
1930 | ||
e01402b1 RB |
1931 | |
1932 | if (board_nmi_handler_setup) | |
1933 | board_nmi_handler_setup(); | |
1934 | ||
e50c0a8f RB |
1935 | if (cpu_has_fpu && !cpu_has_nofpuex) |
1936 | set_except_vector(15, handle_fpe); | |
1937 | ||
1938 | set_except_vector(22, handle_mdmx); | |
1939 | ||
1940 | if (cpu_has_mcheck) | |
1941 | set_except_vector(24, handle_mcheck); | |
1942 | ||
340ee4b9 RB |
1943 | if (cpu_has_mipsmt) |
1944 | set_except_vector(25, handle_mt); | |
1945 | ||
acaec427 | 1946 | set_except_vector(26, handle_dsp); |
e50c0a8f | 1947 | |
fcbf1dfd DD |
1948 | if (board_cache_error_setup) |
1949 | board_cache_error_setup(); | |
1950 | ||
e50c0a8f RB |
1951 | if (cpu_has_vce) |
1952 | /* Special exception: R4[04]00 uses also the divec space. */ | |
2a0b24f5 | 1953 | set_handler(0x180, &except_vec3_r4000, 0x100); |
e50c0a8f | 1954 | else if (cpu_has_4kex) |
2a0b24f5 | 1955 | set_handler(0x180, &except_vec3_generic, 0x80); |
e50c0a8f | 1956 | else |
2a0b24f5 | 1957 | set_handler(0x080, &except_vec3_generic, 0x80); |
e50c0a8f | 1958 | |
e0cee3ee | 1959 | local_flush_icache_range(ebase, ebase + 0x400); |
1d40cfcd | 1960 | flush_tlb_handlers(); |
0510617b TB |
1961 | |
1962 | sort_extable(__start___dbe_table, __stop___dbe_table); | |
69f3a7de | 1963 | |
4483b159 | 1964 | cu2_notifier(default_cu2_call, 0x80000000); /* Run last */ |
1da177e4 | 1965 | } |