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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public | |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
36ccf1c0 | 6 | * Copyright (C) 1994 - 1999, 2000, 01, 06 Ralf Baechle |
1da177e4 LT |
7 | * Copyright (C) 1995, 1996 Paul M. Antoine |
8 | * Copyright (C) 1998 Ulf Carlsson | |
9 | * Copyright (C) 1999 Silicon Graphics, Inc. | |
10 | * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com | |
60b0d655 | 11 | * Copyright (C) 2002, 2003, 2004, 2005, 2007 Maciej W. Rozycki |
2a0b24f5 | 12 | * Copyright (C) 2000, 2001, 2012 MIPS Technologies, Inc. All rights reserved. |
1da177e4 | 13 | */ |
8e8a52ed | 14 | #include <linux/bug.h> |
60b0d655 | 15 | #include <linux/compiler.h> |
c3fc5cd5 | 16 | #include <linux/context_tracking.h> |
7aa1c8f4 | 17 | #include <linux/kexec.h> |
1da177e4 | 18 | #include <linux/init.h> |
8742cd23 | 19 | #include <linux/kernel.h> |
f9ded569 | 20 | #include <linux/module.h> |
1da177e4 | 21 | #include <linux/mm.h> |
1da177e4 LT |
22 | #include <linux/sched.h> |
23 | #include <linux/smp.h> | |
1da177e4 LT |
24 | #include <linux/spinlock.h> |
25 | #include <linux/kallsyms.h> | |
e01402b1 | 26 | #include <linux/bootmem.h> |
d4fd1989 | 27 | #include <linux/interrupt.h> |
39b8d525 | 28 | #include <linux/ptrace.h> |
88547001 JW |
29 | #include <linux/kgdb.h> |
30 | #include <linux/kdebug.h> | |
c1bf207d | 31 | #include <linux/kprobes.h> |
69f3a7de | 32 | #include <linux/notifier.h> |
5dd11d5d | 33 | #include <linux/kdb.h> |
ca4d3e67 | 34 | #include <linux/irq.h> |
7f788d2d | 35 | #include <linux/perf_event.h> |
1da177e4 LT |
36 | |
37 | #include <asm/bootinfo.h> | |
38 | #include <asm/branch.h> | |
39 | #include <asm/break.h> | |
69f3a7de | 40 | #include <asm/cop2.h> |
1da177e4 | 41 | #include <asm/cpu.h> |
69f24d17 | 42 | #include <asm/cpu-type.h> |
e50c0a8f | 43 | #include <asm/dsp.h> |
1da177e4 | 44 | #include <asm/fpu.h> |
ba3049ed | 45 | #include <asm/fpu_emulator.h> |
bdc92d74 | 46 | #include <asm/idle.h> |
340ee4b9 RB |
47 | #include <asm/mipsregs.h> |
48 | #include <asm/mipsmtregs.h> | |
1da177e4 LT |
49 | #include <asm/module.h> |
50 | #include <asm/pgtable.h> | |
51 | #include <asm/ptrace.h> | |
52 | #include <asm/sections.h> | |
1da177e4 LT |
53 | #include <asm/tlbdebug.h> |
54 | #include <asm/traps.h> | |
55 | #include <asm/uaccess.h> | |
b67b2b70 | 56 | #include <asm/watch.h> |
1da177e4 | 57 | #include <asm/mmu_context.h> |
1da177e4 | 58 | #include <asm/types.h> |
1df0f0ff | 59 | #include <asm/stacktrace.h> |
92bbe1b9 | 60 | #include <asm/uasm.h> |
1da177e4 | 61 | |
c65a5480 | 62 | extern void check_wait(void); |
c65a5480 | 63 | extern asmlinkage void rollback_handle_int(void); |
e4ac58af | 64 | extern asmlinkage void handle_int(void); |
86a1708a RB |
65 | extern u32 handle_tlbl[]; |
66 | extern u32 handle_tlbs[]; | |
67 | extern u32 handle_tlbm[]; | |
1da177e4 LT |
68 | extern asmlinkage void handle_adel(void); |
69 | extern asmlinkage void handle_ades(void); | |
70 | extern asmlinkage void handle_ibe(void); | |
71 | extern asmlinkage void handle_dbe(void); | |
72 | extern asmlinkage void handle_sys(void); | |
73 | extern asmlinkage void handle_bp(void); | |
74 | extern asmlinkage void handle_ri(void); | |
5b10496b AN |
75 | extern asmlinkage void handle_ri_rdhwr_vivt(void); |
76 | extern asmlinkage void handle_ri_rdhwr(void); | |
1da177e4 LT |
77 | extern asmlinkage void handle_cpu(void); |
78 | extern asmlinkage void handle_ov(void); | |
79 | extern asmlinkage void handle_tr(void); | |
80 | extern asmlinkage void handle_fpe(void); | |
75b5b5e0 | 81 | extern asmlinkage void handle_ftlb(void); |
1da177e4 LT |
82 | extern asmlinkage void handle_mdmx(void); |
83 | extern asmlinkage void handle_watch(void); | |
340ee4b9 | 84 | extern asmlinkage void handle_mt(void); |
e50c0a8f | 85 | extern asmlinkage void handle_dsp(void); |
1da177e4 LT |
86 | extern asmlinkage void handle_mcheck(void); |
87 | extern asmlinkage void handle_reserved(void); | |
88 | ||
1da177e4 LT |
89 | void (*board_be_init)(void); |
90 | int (*board_be_handler)(struct pt_regs *regs, int is_fixup); | |
e01402b1 RB |
91 | void (*board_nmi_handler_setup)(void); |
92 | void (*board_ejtag_handler_setup)(void); | |
93 | void (*board_bind_eic_interrupt)(int irq, int regset); | |
6fb97eff | 94 | void (*board_ebase_setup)(void); |
078a55fc | 95 | void(*board_cache_error_setup)(void); |
1da177e4 | 96 | |
4d157d5e | 97 | static void show_raw_backtrace(unsigned long reg29) |
e889d78f | 98 | { |
39b8d525 | 99 | unsigned long *sp = (unsigned long *)(reg29 & ~3); |
e889d78f AN |
100 | unsigned long addr; |
101 | ||
102 | printk("Call Trace:"); | |
103 | #ifdef CONFIG_KALLSYMS | |
104 | printk("\n"); | |
105 | #endif | |
10220c88 TB |
106 | while (!kstack_end(sp)) { |
107 | unsigned long __user *p = | |
108 | (unsigned long __user *)(unsigned long)sp++; | |
109 | if (__get_user(addr, p)) { | |
110 | printk(" (Bad stack address)"); | |
111 | break; | |
39b8d525 | 112 | } |
10220c88 TB |
113 | if (__kernel_text_address(addr)) |
114 | print_ip_sym(addr); | |
e889d78f | 115 | } |
10220c88 | 116 | printk("\n"); |
e889d78f AN |
117 | } |
118 | ||
f66686f7 | 119 | #ifdef CONFIG_KALLSYMS |
1df0f0ff | 120 | int raw_show_trace; |
f66686f7 AN |
121 | static int __init set_raw_show_trace(char *str) |
122 | { | |
123 | raw_show_trace = 1; | |
124 | return 1; | |
125 | } | |
126 | __setup("raw_show_trace", set_raw_show_trace); | |
1df0f0ff | 127 | #endif |
4d157d5e | 128 | |
eae23f2c | 129 | static void show_backtrace(struct task_struct *task, const struct pt_regs *regs) |
f66686f7 | 130 | { |
4d157d5e FBH |
131 | unsigned long sp = regs->regs[29]; |
132 | unsigned long ra = regs->regs[31]; | |
f66686f7 | 133 | unsigned long pc = regs->cp0_epc; |
f66686f7 | 134 | |
e909be82 VW |
135 | if (!task) |
136 | task = current; | |
137 | ||
f66686f7 | 138 | if (raw_show_trace || !__kernel_text_address(pc)) { |
87151ae3 | 139 | show_raw_backtrace(sp); |
f66686f7 AN |
140 | return; |
141 | } | |
142 | printk("Call Trace:\n"); | |
4d157d5e | 143 | do { |
87151ae3 | 144 | print_ip_sym(pc); |
1924600c | 145 | pc = unwind_stack(task, &sp, pc, &ra); |
4d157d5e | 146 | } while (pc); |
f66686f7 AN |
147 | printk("\n"); |
148 | } | |
f66686f7 | 149 | |
1da177e4 LT |
150 | /* |
151 | * This routine abuses get_user()/put_user() to reference pointers | |
152 | * with at least a bit of error checking ... | |
153 | */ | |
eae23f2c RB |
154 | static void show_stacktrace(struct task_struct *task, |
155 | const struct pt_regs *regs) | |
1da177e4 LT |
156 | { |
157 | const int field = 2 * sizeof(unsigned long); | |
158 | long stackdata; | |
159 | int i; | |
5e0373b8 | 160 | unsigned long __user *sp = (unsigned long __user *)regs->regs[29]; |
1da177e4 LT |
161 | |
162 | printk("Stack :"); | |
163 | i = 0; | |
164 | while ((unsigned long) sp & (PAGE_SIZE - 1)) { | |
165 | if (i && ((i % (64 / field)) == 0)) | |
70342287 | 166 | printk("\n "); |
1da177e4 LT |
167 | if (i > 39) { |
168 | printk(" ..."); | |
169 | break; | |
170 | } | |
171 | ||
172 | if (__get_user(stackdata, sp++)) { | |
173 | printk(" (Bad stack address)"); | |
174 | break; | |
175 | } | |
176 | ||
177 | printk(" %0*lx", field, stackdata); | |
178 | i++; | |
179 | } | |
180 | printk("\n"); | |
87151ae3 | 181 | show_backtrace(task, regs); |
f66686f7 AN |
182 | } |
183 | ||
f66686f7 AN |
184 | void show_stack(struct task_struct *task, unsigned long *sp) |
185 | { | |
186 | struct pt_regs regs; | |
187 | if (sp) { | |
188 | regs.regs[29] = (unsigned long)sp; | |
189 | regs.regs[31] = 0; | |
190 | regs.cp0_epc = 0; | |
191 | } else { | |
192 | if (task && task != current) { | |
193 | regs.regs[29] = task->thread.reg29; | |
194 | regs.regs[31] = 0; | |
195 | regs.cp0_epc = task->thread.reg31; | |
5dd11d5d JW |
196 | #ifdef CONFIG_KGDB_KDB |
197 | } else if (atomic_read(&kgdb_active) != -1 && | |
198 | kdb_current_regs) { | |
199 | memcpy(®s, kdb_current_regs, sizeof(regs)); | |
200 | #endif /* CONFIG_KGDB_KDB */ | |
f66686f7 AN |
201 | } else { |
202 | prepare_frametrace(®s); | |
203 | } | |
204 | } | |
205 | show_stacktrace(task, ®s); | |
1da177e4 LT |
206 | } |
207 | ||
e1bb8289 | 208 | static void show_code(unsigned int __user *pc) |
1da177e4 LT |
209 | { |
210 | long i; | |
39b8d525 | 211 | unsigned short __user *pc16 = NULL; |
1da177e4 LT |
212 | |
213 | printk("\nCode:"); | |
214 | ||
39b8d525 RB |
215 | if ((unsigned long)pc & 1) |
216 | pc16 = (unsigned short __user *)((unsigned long)pc & ~1); | |
1da177e4 LT |
217 | for(i = -3 ; i < 6 ; i++) { |
218 | unsigned int insn; | |
39b8d525 | 219 | if (pc16 ? __get_user(insn, pc16 + i) : __get_user(insn, pc + i)) { |
1da177e4 LT |
220 | printk(" (Bad address in epc)\n"); |
221 | break; | |
222 | } | |
39b8d525 | 223 | printk("%c%0*x%c", (i?' ':'<'), pc16 ? 4 : 8, insn, (i?' ':'>')); |
1da177e4 LT |
224 | } |
225 | } | |
226 | ||
eae23f2c | 227 | static void __show_regs(const struct pt_regs *regs) |
1da177e4 LT |
228 | { |
229 | const int field = 2 * sizeof(unsigned long); | |
230 | unsigned int cause = regs->cp0_cause; | |
231 | int i; | |
232 | ||
a43cb95d | 233 | show_regs_print_info(KERN_DEFAULT); |
1da177e4 LT |
234 | |
235 | /* | |
236 | * Saved main processor registers | |
237 | */ | |
238 | for (i = 0; i < 32; ) { | |
239 | if ((i % 4) == 0) | |
240 | printk("$%2d :", i); | |
241 | if (i == 0) | |
242 | printk(" %0*lx", field, 0UL); | |
243 | else if (i == 26 || i == 27) | |
244 | printk(" %*s", field, ""); | |
245 | else | |
246 | printk(" %0*lx", field, regs->regs[i]); | |
247 | ||
248 | i++; | |
249 | if ((i % 4) == 0) | |
250 | printk("\n"); | |
251 | } | |
252 | ||
9693a853 FBH |
253 | #ifdef CONFIG_CPU_HAS_SMARTMIPS |
254 | printk("Acx : %0*lx\n", field, regs->acx); | |
255 | #endif | |
1da177e4 LT |
256 | printk("Hi : %0*lx\n", field, regs->hi); |
257 | printk("Lo : %0*lx\n", field, regs->lo); | |
258 | ||
259 | /* | |
260 | * Saved cp0 registers | |
261 | */ | |
b012cffe RB |
262 | printk("epc : %0*lx %pS\n", field, regs->cp0_epc, |
263 | (void *) regs->cp0_epc); | |
1da177e4 | 264 | printk(" %s\n", print_tainted()); |
b012cffe RB |
265 | printk("ra : %0*lx %pS\n", field, regs->regs[31], |
266 | (void *) regs->regs[31]); | |
1da177e4 | 267 | |
70342287 | 268 | printk("Status: %08x ", (uint32_t) regs->cp0_status); |
1da177e4 | 269 | |
1990e542 | 270 | if (cpu_has_3kex) { |
3b2396d9 MR |
271 | if (regs->cp0_status & ST0_KUO) |
272 | printk("KUo "); | |
273 | if (regs->cp0_status & ST0_IEO) | |
274 | printk("IEo "); | |
275 | if (regs->cp0_status & ST0_KUP) | |
276 | printk("KUp "); | |
277 | if (regs->cp0_status & ST0_IEP) | |
278 | printk("IEp "); | |
279 | if (regs->cp0_status & ST0_KUC) | |
280 | printk("KUc "); | |
281 | if (regs->cp0_status & ST0_IEC) | |
282 | printk("IEc "); | |
1990e542 | 283 | } else if (cpu_has_4kex) { |
3b2396d9 MR |
284 | if (regs->cp0_status & ST0_KX) |
285 | printk("KX "); | |
286 | if (regs->cp0_status & ST0_SX) | |
287 | printk("SX "); | |
288 | if (regs->cp0_status & ST0_UX) | |
289 | printk("UX "); | |
290 | switch (regs->cp0_status & ST0_KSU) { | |
291 | case KSU_USER: | |
292 | printk("USER "); | |
293 | break; | |
294 | case KSU_SUPERVISOR: | |
295 | printk("SUPERVISOR "); | |
296 | break; | |
297 | case KSU_KERNEL: | |
298 | printk("KERNEL "); | |
299 | break; | |
300 | default: | |
301 | printk("BAD_MODE "); | |
302 | break; | |
303 | } | |
304 | if (regs->cp0_status & ST0_ERL) | |
305 | printk("ERL "); | |
306 | if (regs->cp0_status & ST0_EXL) | |
307 | printk("EXL "); | |
308 | if (regs->cp0_status & ST0_IE) | |
309 | printk("IE "); | |
1da177e4 | 310 | } |
1da177e4 LT |
311 | printk("\n"); |
312 | ||
313 | printk("Cause : %08x\n", cause); | |
314 | ||
315 | cause = (cause & CAUSEF_EXCCODE) >> CAUSEB_EXCCODE; | |
316 | if (1 <= cause && cause <= 5) | |
317 | printk("BadVA : %0*lx\n", field, regs->cp0_badvaddr); | |
318 | ||
9966db25 RB |
319 | printk("PrId : %08x (%s)\n", read_c0_prid(), |
320 | cpu_name_string()); | |
1da177e4 LT |
321 | } |
322 | ||
eae23f2c RB |
323 | /* |
324 | * FIXME: really the generic show_regs should take a const pointer argument. | |
325 | */ | |
326 | void show_regs(struct pt_regs *regs) | |
327 | { | |
328 | __show_regs((struct pt_regs *)regs); | |
329 | } | |
330 | ||
c1bf207d | 331 | void show_registers(struct pt_regs *regs) |
1da177e4 | 332 | { |
39b8d525 | 333 | const int field = 2 * sizeof(unsigned long); |
83e4da1e | 334 | mm_segment_t old_fs = get_fs(); |
39b8d525 | 335 | |
eae23f2c | 336 | __show_regs(regs); |
1da177e4 | 337 | print_modules(); |
39b8d525 RB |
338 | printk("Process %s (pid: %d, threadinfo=%p, task=%p, tls=%0*lx)\n", |
339 | current->comm, current->pid, current_thread_info(), current, | |
340 | field, current_thread_info()->tp_value); | |
341 | if (cpu_has_userlocal) { | |
342 | unsigned long tls; | |
343 | ||
344 | tls = read_c0_userlocal(); | |
345 | if (tls != current_thread_info()->tp_value) | |
346 | printk("*HwTLS: %0*lx\n", field, tls); | |
347 | } | |
348 | ||
83e4da1e LY |
349 | if (!user_mode(regs)) |
350 | /* Necessary for getting the correct stack content */ | |
351 | set_fs(KERNEL_DS); | |
f66686f7 | 352 | show_stacktrace(current, regs); |
e1bb8289 | 353 | show_code((unsigned int __user *) regs->cp0_epc); |
1da177e4 | 354 | printk("\n"); |
83e4da1e | 355 | set_fs(old_fs); |
1da177e4 LT |
356 | } |
357 | ||
70dc6f04 DD |
358 | static int regs_to_trapnr(struct pt_regs *regs) |
359 | { | |
360 | return (regs->cp0_cause >> 2) & 0x1f; | |
361 | } | |
362 | ||
4d85f6af | 363 | static DEFINE_RAW_SPINLOCK(die_lock); |
1da177e4 | 364 | |
70dc6f04 | 365 | void __noreturn die(const char *str, struct pt_regs *regs) |
1da177e4 LT |
366 | { |
367 | static int die_counter; | |
ce384d83 | 368 | int sig = SIGSEGV; |
41c594ab | 369 | #ifdef CONFIG_MIPS_MT_SMTC |
8742cd23 | 370 | unsigned long dvpret; |
41c594ab | 371 | #endif /* CONFIG_MIPS_MT_SMTC */ |
1da177e4 | 372 | |
8742cd23 NL |
373 | oops_enter(); |
374 | ||
dc73e4c1 RB |
375 | if (notify_die(DIE_OOPS, str, regs, 0, regs_to_trapnr(regs), |
376 | SIGSEGV) == NOTIFY_STOP) | |
10423c91 | 377 | sig = 0; |
5dd11d5d | 378 | |
1da177e4 | 379 | console_verbose(); |
4d85f6af | 380 | raw_spin_lock_irq(&die_lock); |
8742cd23 NL |
381 | #ifdef CONFIG_MIPS_MT_SMTC |
382 | dvpret = dvpe(); | |
383 | #endif /* CONFIG_MIPS_MT_SMTC */ | |
41c594ab RB |
384 | bust_spinlocks(1); |
385 | #ifdef CONFIG_MIPS_MT_SMTC | |
386 | mips_mt_regdump(dvpret); | |
387 | #endif /* CONFIG_MIPS_MT_SMTC */ | |
ce384d83 | 388 | |
178086c8 | 389 | printk("%s[#%d]:\n", str, ++die_counter); |
1da177e4 | 390 | show_registers(regs); |
373d4d09 | 391 | add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE); |
4d85f6af | 392 | raw_spin_unlock_irq(&die_lock); |
d4fd1989 | 393 | |
8742cd23 NL |
394 | oops_exit(); |
395 | ||
d4fd1989 MB |
396 | if (in_interrupt()) |
397 | panic("Fatal exception in interrupt"); | |
398 | ||
399 | if (panic_on_oops) { | |
ab75dc02 | 400 | printk(KERN_EMERG "Fatal exception: panic in 5 seconds"); |
d4fd1989 MB |
401 | ssleep(5); |
402 | panic("Fatal exception"); | |
403 | } | |
404 | ||
7aa1c8f4 RB |
405 | if (regs && kexec_should_crash(current)) |
406 | crash_kexec(regs); | |
407 | ||
ce384d83 | 408 | do_exit(sig); |
1da177e4 LT |
409 | } |
410 | ||
0510617b TB |
411 | extern struct exception_table_entry __start___dbe_table[]; |
412 | extern struct exception_table_entry __stop___dbe_table[]; | |
1da177e4 | 413 | |
b6dcec9b RB |
414 | __asm__( |
415 | " .section __dbe_table, \"a\"\n" | |
416 | " .previous \n"); | |
1da177e4 LT |
417 | |
418 | /* Given an address, look for it in the exception tables. */ | |
419 | static const struct exception_table_entry *search_dbe_tables(unsigned long addr) | |
420 | { | |
421 | const struct exception_table_entry *e; | |
422 | ||
423 | e = search_extable(__start___dbe_table, __stop___dbe_table - 1, addr); | |
424 | if (!e) | |
425 | e = search_module_dbetables(addr); | |
426 | return e; | |
427 | } | |
428 | ||
429 | asmlinkage void do_be(struct pt_regs *regs) | |
430 | { | |
431 | const int field = 2 * sizeof(unsigned long); | |
432 | const struct exception_table_entry *fixup = NULL; | |
433 | int data = regs->cp0_cause & 4; | |
434 | int action = MIPS_BE_FATAL; | |
c3fc5cd5 | 435 | enum ctx_state prev_state; |
1da177e4 | 436 | |
c3fc5cd5 | 437 | prev_state = exception_enter(); |
70342287 | 438 | /* XXX For now. Fixme, this searches the wrong table ... */ |
1da177e4 LT |
439 | if (data && !user_mode(regs)) |
440 | fixup = search_dbe_tables(exception_epc(regs)); | |
441 | ||
442 | if (fixup) | |
443 | action = MIPS_BE_FIXUP; | |
444 | ||
445 | if (board_be_handler) | |
28fc582c | 446 | action = board_be_handler(regs, fixup != NULL); |
1da177e4 LT |
447 | |
448 | switch (action) { | |
449 | case MIPS_BE_DISCARD: | |
c3fc5cd5 | 450 | goto out; |
1da177e4 LT |
451 | case MIPS_BE_FIXUP: |
452 | if (fixup) { | |
453 | regs->cp0_epc = fixup->nextinsn; | |
c3fc5cd5 | 454 | goto out; |
1da177e4 LT |
455 | } |
456 | break; | |
457 | default: | |
458 | break; | |
459 | } | |
460 | ||
461 | /* | |
462 | * Assume it would be too dangerous to continue ... | |
463 | */ | |
464 | printk(KERN_ALERT "%s bus error, epc == %0*lx, ra == %0*lx\n", | |
465 | data ? "Data" : "Instruction", | |
466 | field, regs->cp0_epc, field, regs->regs[31]); | |
dc73e4c1 RB |
467 | if (notify_die(DIE_OOPS, "bus error", regs, 0, regs_to_trapnr(regs), |
468 | SIGBUS) == NOTIFY_STOP) | |
c3fc5cd5 | 469 | goto out; |
88547001 | 470 | |
1da177e4 LT |
471 | die_if_kernel("Oops", regs); |
472 | force_sig(SIGBUS, current); | |
c3fc5cd5 RB |
473 | |
474 | out: | |
475 | exception_exit(prev_state); | |
1da177e4 LT |
476 | } |
477 | ||
1da177e4 | 478 | /* |
60b0d655 | 479 | * ll/sc, rdhwr, sync emulation |
1da177e4 LT |
480 | */ |
481 | ||
482 | #define OPCODE 0xfc000000 | |
483 | #define BASE 0x03e00000 | |
484 | #define RT 0x001f0000 | |
485 | #define OFFSET 0x0000ffff | |
486 | #define LL 0xc0000000 | |
487 | #define SC 0xe0000000 | |
60b0d655 | 488 | #define SPEC0 0x00000000 |
3c37026d RB |
489 | #define SPEC3 0x7c000000 |
490 | #define RD 0x0000f800 | |
491 | #define FUNC 0x0000003f | |
60b0d655 | 492 | #define SYNC 0x0000000f |
3c37026d | 493 | #define RDHWR 0x0000003b |
1da177e4 | 494 | |
2a0b24f5 SH |
495 | /* microMIPS definitions */ |
496 | #define MM_POOL32A_FUNC 0xfc00ffff | |
497 | #define MM_RDHWR 0x00006b3c | |
498 | #define MM_RS 0x001f0000 | |
499 | #define MM_RT 0x03e00000 | |
500 | ||
1da177e4 LT |
501 | /* |
502 | * The ll_bit is cleared by r*_switch.S | |
503 | */ | |
504 | ||
f1e39a4a RB |
505 | unsigned int ll_bit; |
506 | struct task_struct *ll_task; | |
1da177e4 | 507 | |
60b0d655 | 508 | static inline int simulate_ll(struct pt_regs *regs, unsigned int opcode) |
1da177e4 | 509 | { |
fe00f943 | 510 | unsigned long value, __user *vaddr; |
1da177e4 | 511 | long offset; |
1da177e4 LT |
512 | |
513 | /* | |
514 | * analyse the ll instruction that just caused a ri exception | |
515 | * and put the referenced address to addr. | |
516 | */ | |
517 | ||
518 | /* sign extend offset */ | |
519 | offset = opcode & OFFSET; | |
520 | offset <<= 16; | |
521 | offset >>= 16; | |
522 | ||
fe00f943 | 523 | vaddr = (unsigned long __user *) |
b9688310 | 524 | ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset); |
1da177e4 | 525 | |
60b0d655 MR |
526 | if ((unsigned long)vaddr & 3) |
527 | return SIGBUS; | |
528 | if (get_user(value, vaddr)) | |
529 | return SIGSEGV; | |
1da177e4 LT |
530 | |
531 | preempt_disable(); | |
532 | ||
533 | if (ll_task == NULL || ll_task == current) { | |
534 | ll_bit = 1; | |
535 | } else { | |
536 | ll_bit = 0; | |
537 | } | |
538 | ll_task = current; | |
539 | ||
540 | preempt_enable(); | |
541 | ||
542 | regs->regs[(opcode & RT) >> 16] = value; | |
543 | ||
60b0d655 | 544 | return 0; |
1da177e4 LT |
545 | } |
546 | ||
60b0d655 | 547 | static inline int simulate_sc(struct pt_regs *regs, unsigned int opcode) |
1da177e4 | 548 | { |
fe00f943 RB |
549 | unsigned long __user *vaddr; |
550 | unsigned long reg; | |
1da177e4 | 551 | long offset; |
1da177e4 LT |
552 | |
553 | /* | |
554 | * analyse the sc instruction that just caused a ri exception | |
555 | * and put the referenced address to addr. | |
556 | */ | |
557 | ||
558 | /* sign extend offset */ | |
559 | offset = opcode & OFFSET; | |
560 | offset <<= 16; | |
561 | offset >>= 16; | |
562 | ||
fe00f943 | 563 | vaddr = (unsigned long __user *) |
b9688310 | 564 | ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset); |
1da177e4 LT |
565 | reg = (opcode & RT) >> 16; |
566 | ||
60b0d655 MR |
567 | if ((unsigned long)vaddr & 3) |
568 | return SIGBUS; | |
1da177e4 LT |
569 | |
570 | preempt_disable(); | |
571 | ||
572 | if (ll_bit == 0 || ll_task != current) { | |
573 | regs->regs[reg] = 0; | |
574 | preempt_enable(); | |
60b0d655 | 575 | return 0; |
1da177e4 LT |
576 | } |
577 | ||
578 | preempt_enable(); | |
579 | ||
60b0d655 MR |
580 | if (put_user(regs->regs[reg], vaddr)) |
581 | return SIGSEGV; | |
1da177e4 LT |
582 | |
583 | regs->regs[reg] = 1; | |
584 | ||
60b0d655 | 585 | return 0; |
1da177e4 LT |
586 | } |
587 | ||
588 | /* | |
589 | * ll uses the opcode of lwc0 and sc uses the opcode of swc0. That is both | |
590 | * opcodes are supposed to result in coprocessor unusable exceptions if | |
591 | * executed on ll/sc-less processors. That's the theory. In practice a | |
592 | * few processors such as NEC's VR4100 throw reserved instruction exceptions | |
593 | * instead, so we're doing the emulation thing in both exception handlers. | |
594 | */ | |
60b0d655 | 595 | static int simulate_llsc(struct pt_regs *regs, unsigned int opcode) |
1da177e4 | 596 | { |
7f788d2d DCZ |
597 | if ((opcode & OPCODE) == LL) { |
598 | perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, | |
a8b0ca17 | 599 | 1, regs, 0); |
60b0d655 | 600 | return simulate_ll(regs, opcode); |
7f788d2d DCZ |
601 | } |
602 | if ((opcode & OPCODE) == SC) { | |
603 | perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, | |
a8b0ca17 | 604 | 1, regs, 0); |
60b0d655 | 605 | return simulate_sc(regs, opcode); |
7f788d2d | 606 | } |
1da177e4 | 607 | |
60b0d655 | 608 | return -1; /* Must be something else ... */ |
1da177e4 LT |
609 | } |
610 | ||
3c37026d RB |
611 | /* |
612 | * Simulate trapping 'rdhwr' instructions to provide user accessible | |
1f5826bd | 613 | * registers not implemented in hardware. |
3c37026d | 614 | */ |
2a0b24f5 | 615 | static int simulate_rdhwr(struct pt_regs *regs, int rd, int rt) |
3c37026d | 616 | { |
dc8f6029 | 617 | struct thread_info *ti = task_thread_info(current); |
3c37026d | 618 | |
2a0b24f5 SH |
619 | perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, |
620 | 1, regs, 0); | |
621 | switch (rd) { | |
622 | case 0: /* CPU number */ | |
623 | regs->regs[rt] = smp_processor_id(); | |
624 | return 0; | |
625 | case 1: /* SYNCI length */ | |
626 | regs->regs[rt] = min(current_cpu_data.dcache.linesz, | |
627 | current_cpu_data.icache.linesz); | |
628 | return 0; | |
629 | case 2: /* Read count register */ | |
630 | regs->regs[rt] = read_c0_count(); | |
631 | return 0; | |
632 | case 3: /* Count register resolution */ | |
69f24d17 | 633 | switch (current_cpu_type()) { |
2a0b24f5 SH |
634 | case CPU_20KC: |
635 | case CPU_25KF: | |
636 | regs->regs[rt] = 1; | |
637 | break; | |
638 | default: | |
639 | regs->regs[rt] = 2; | |
640 | } | |
641 | return 0; | |
642 | case 29: | |
643 | regs->regs[rt] = ti->tp_value; | |
644 | return 0; | |
645 | default: | |
646 | return -1; | |
647 | } | |
648 | } | |
649 | ||
650 | static int simulate_rdhwr_normal(struct pt_regs *regs, unsigned int opcode) | |
651 | { | |
3c37026d RB |
652 | if ((opcode & OPCODE) == SPEC3 && (opcode & FUNC) == RDHWR) { |
653 | int rd = (opcode & RD) >> 11; | |
654 | int rt = (opcode & RT) >> 16; | |
2a0b24f5 SH |
655 | |
656 | simulate_rdhwr(regs, rd, rt); | |
657 | return 0; | |
658 | } | |
659 | ||
660 | /* Not ours. */ | |
661 | return -1; | |
662 | } | |
663 | ||
664 | static int simulate_rdhwr_mm(struct pt_regs *regs, unsigned short opcode) | |
665 | { | |
666 | if ((opcode & MM_POOL32A_FUNC) == MM_RDHWR) { | |
667 | int rd = (opcode & MM_RS) >> 16; | |
668 | int rt = (opcode & MM_RT) >> 21; | |
669 | simulate_rdhwr(regs, rd, rt); | |
670 | return 0; | |
3c37026d RB |
671 | } |
672 | ||
56ebd51b | 673 | /* Not ours. */ |
60b0d655 MR |
674 | return -1; |
675 | } | |
e5679882 | 676 | |
60b0d655 MR |
677 | static int simulate_sync(struct pt_regs *regs, unsigned int opcode) |
678 | { | |
7f788d2d DCZ |
679 | if ((opcode & OPCODE) == SPEC0 && (opcode & FUNC) == SYNC) { |
680 | perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, | |
a8b0ca17 | 681 | 1, regs, 0); |
60b0d655 | 682 | return 0; |
7f788d2d | 683 | } |
60b0d655 MR |
684 | |
685 | return -1; /* Must be something else ... */ | |
3c37026d RB |
686 | } |
687 | ||
1da177e4 LT |
688 | asmlinkage void do_ov(struct pt_regs *regs) |
689 | { | |
c3fc5cd5 | 690 | enum ctx_state prev_state; |
1da177e4 LT |
691 | siginfo_t info; |
692 | ||
c3fc5cd5 | 693 | prev_state = exception_enter(); |
36ccf1c0 RB |
694 | die_if_kernel("Integer overflow", regs); |
695 | ||
1da177e4 LT |
696 | info.si_code = FPE_INTOVF; |
697 | info.si_signo = SIGFPE; | |
698 | info.si_errno = 0; | |
fe00f943 | 699 | info.si_addr = (void __user *) regs->cp0_epc; |
1da177e4 | 700 | force_sig_info(SIGFPE, &info, current); |
c3fc5cd5 | 701 | exception_exit(prev_state); |
1da177e4 LT |
702 | } |
703 | ||
102cedc3 | 704 | int process_fpemu_return(int sig, void __user *fault_addr) |
515b029d DD |
705 | { |
706 | if (sig == SIGSEGV || sig == SIGBUS) { | |
707 | struct siginfo si = {0}; | |
708 | si.si_addr = fault_addr; | |
709 | si.si_signo = sig; | |
710 | if (sig == SIGSEGV) { | |
711 | if (find_vma(current->mm, (unsigned long)fault_addr)) | |
712 | si.si_code = SEGV_ACCERR; | |
713 | else | |
714 | si.si_code = SEGV_MAPERR; | |
715 | } else { | |
716 | si.si_code = BUS_ADRERR; | |
717 | } | |
718 | force_sig_info(sig, &si, current); | |
719 | return 1; | |
720 | } else if (sig) { | |
721 | force_sig(sig, current); | |
722 | return 1; | |
723 | } else { | |
724 | return 0; | |
725 | } | |
726 | } | |
727 | ||
1da177e4 LT |
728 | /* |
729 | * XXX Delayed fp exceptions when doing a lazy ctx switch XXX | |
730 | */ | |
731 | asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31) | |
732 | { | |
c3fc5cd5 | 733 | enum ctx_state prev_state; |
515b029d | 734 | siginfo_t info = {0}; |
948a34cf | 735 | |
c3fc5cd5 | 736 | prev_state = exception_enter(); |
dc73e4c1 RB |
737 | if (notify_die(DIE_FP, "FP exception", regs, 0, regs_to_trapnr(regs), |
738 | SIGFPE) == NOTIFY_STOP) | |
c3fc5cd5 | 739 | goto out; |
57725f9e CD |
740 | die_if_kernel("FP exception in kernel code", regs); |
741 | ||
1da177e4 LT |
742 | if (fcr31 & FPU_CSR_UNI_X) { |
743 | int sig; | |
515b029d | 744 | void __user *fault_addr = NULL; |
1da177e4 | 745 | |
1da177e4 | 746 | /* |
a3dddd56 | 747 | * Unimplemented operation exception. If we've got the full |
1da177e4 LT |
748 | * software emulator on-board, let's use it... |
749 | * | |
750 | * Force FPU to dump state into task/thread context. We're | |
751 | * moving a lot of data here for what is probably a single | |
752 | * instruction, but the alternative is to pre-decode the FP | |
753 | * register operands before invoking the emulator, which seems | |
754 | * a bit extreme for what should be an infrequent event. | |
755 | */ | |
cd21dfcf | 756 | /* Ensure 'resume' not overwrite saved fp context again. */ |
53dc8028 | 757 | lose_fpu(1); |
1da177e4 LT |
758 | |
759 | /* Run the emulator */ | |
515b029d DD |
760 | sig = fpu_emulator_cop1Handler(regs, ¤t->thread.fpu, 1, |
761 | &fault_addr); | |
1da177e4 LT |
762 | |
763 | /* | |
764 | * We can't allow the emulated instruction to leave any of | |
765 | * the cause bit set in $fcr31. | |
766 | */ | |
eae89076 | 767 | current->thread.fpu.fcr31 &= ~FPU_CSR_ALL_X; |
1da177e4 LT |
768 | |
769 | /* Restore the hardware register state */ | |
70342287 | 770 | own_fpu(1); /* Using the FPU again. */ |
1da177e4 LT |
771 | |
772 | /* If something went wrong, signal */ | |
515b029d | 773 | process_fpemu_return(sig, fault_addr); |
1da177e4 | 774 | |
c3fc5cd5 | 775 | goto out; |
948a34cf TS |
776 | } else if (fcr31 & FPU_CSR_INV_X) |
777 | info.si_code = FPE_FLTINV; | |
778 | else if (fcr31 & FPU_CSR_DIV_X) | |
779 | info.si_code = FPE_FLTDIV; | |
780 | else if (fcr31 & FPU_CSR_OVF_X) | |
781 | info.si_code = FPE_FLTOVF; | |
782 | else if (fcr31 & FPU_CSR_UDF_X) | |
783 | info.si_code = FPE_FLTUND; | |
784 | else if (fcr31 & FPU_CSR_INE_X) | |
785 | info.si_code = FPE_FLTRES; | |
786 | else | |
787 | info.si_code = __SI_FAULT; | |
788 | info.si_signo = SIGFPE; | |
789 | info.si_errno = 0; | |
790 | info.si_addr = (void __user *) regs->cp0_epc; | |
791 | force_sig_info(SIGFPE, &info, current); | |
c3fc5cd5 RB |
792 | |
793 | out: | |
794 | exception_exit(prev_state); | |
1da177e4 LT |
795 | } |
796 | ||
df270051 RB |
797 | static void do_trap_or_bp(struct pt_regs *regs, unsigned int code, |
798 | const char *str) | |
1da177e4 | 799 | { |
1da177e4 | 800 | siginfo_t info; |
df270051 | 801 | char b[40]; |
1da177e4 | 802 | |
5dd11d5d | 803 | #ifdef CONFIG_KGDB_LOW_LEVEL_TRAP |
70dc6f04 | 804 | if (kgdb_ll_trap(DIE_TRAP, str, regs, code, regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP) |
5dd11d5d JW |
805 | return; |
806 | #endif /* CONFIG_KGDB_LOW_LEVEL_TRAP */ | |
807 | ||
dc73e4c1 RB |
808 | if (notify_die(DIE_TRAP, str, regs, code, regs_to_trapnr(regs), |
809 | SIGTRAP) == NOTIFY_STOP) | |
88547001 JW |
810 | return; |
811 | ||
1da177e4 | 812 | /* |
df270051 RB |
813 | * A short test says that IRIX 5.3 sends SIGTRAP for all trap |
814 | * insns, even for trap and break codes that indicate arithmetic | |
815 | * failures. Weird ... | |
1da177e4 LT |
816 | * But should we continue the brokenness??? --macro |
817 | */ | |
df270051 RB |
818 | switch (code) { |
819 | case BRK_OVERFLOW: | |
820 | case BRK_DIVZERO: | |
821 | scnprintf(b, sizeof(b), "%s instruction in kernel code", str); | |
822 | die_if_kernel(b, regs); | |
823 | if (code == BRK_DIVZERO) | |
1da177e4 LT |
824 | info.si_code = FPE_INTDIV; |
825 | else | |
826 | info.si_code = FPE_INTOVF; | |
827 | info.si_signo = SIGFPE; | |
828 | info.si_errno = 0; | |
fe00f943 | 829 | info.si_addr = (void __user *) regs->cp0_epc; |
1da177e4 LT |
830 | force_sig_info(SIGFPE, &info, current); |
831 | break; | |
63dc68a8 | 832 | case BRK_BUG: |
df270051 RB |
833 | die_if_kernel("Kernel bug detected", regs); |
834 | force_sig(SIGTRAP, current); | |
63dc68a8 | 835 | break; |
ba3049ed RB |
836 | case BRK_MEMU: |
837 | /* | |
838 | * Address errors may be deliberately induced by the FPU | |
839 | * emulator to retake control of the CPU after executing the | |
840 | * instruction in the delay slot of an emulated branch. | |
841 | * | |
842 | * Terminate if exception was recognized as a delay slot return | |
843 | * otherwise handle as normal. | |
844 | */ | |
845 | if (do_dsemulret(regs)) | |
846 | return; | |
847 | ||
848 | die_if_kernel("Math emu break/trap", regs); | |
849 | force_sig(SIGTRAP, current); | |
850 | break; | |
1da177e4 | 851 | default: |
df270051 RB |
852 | scnprintf(b, sizeof(b), "%s instruction in kernel code", str); |
853 | die_if_kernel(b, regs); | |
1da177e4 LT |
854 | force_sig(SIGTRAP, current); |
855 | } | |
df270051 RB |
856 | } |
857 | ||
858 | asmlinkage void do_bp(struct pt_regs *regs) | |
859 | { | |
860 | unsigned int opcode, bcode; | |
c3fc5cd5 | 861 | enum ctx_state prev_state; |
2a0b24f5 SH |
862 | unsigned long epc; |
863 | u16 instr[2]; | |
864 | ||
c3fc5cd5 | 865 | prev_state = exception_enter(); |
2a0b24f5 SH |
866 | if (get_isa16_mode(regs->cp0_epc)) { |
867 | /* Calculate EPC. */ | |
868 | epc = exception_epc(regs); | |
869 | if (cpu_has_mmips) { | |
870 | if ((__get_user(instr[0], (u16 __user *)msk_isa16_mode(epc)) || | |
871 | (__get_user(instr[1], (u16 __user *)msk_isa16_mode(epc + 2))))) | |
872 | goto out_sigsegv; | |
873 | opcode = (instr[0] << 16) | instr[1]; | |
874 | } else { | |
875 | /* MIPS16e mode */ | |
876 | if (__get_user(instr[0], (u16 __user *)msk_isa16_mode(epc))) | |
877 | goto out_sigsegv; | |
878 | bcode = (instr[0] >> 6) & 0x3f; | |
879 | do_trap_or_bp(regs, bcode, "Break"); | |
c3fc5cd5 | 880 | goto out; |
2a0b24f5 SH |
881 | } |
882 | } else { | |
883 | if (__get_user(opcode, (unsigned int __user *) exception_epc(regs))) | |
884 | goto out_sigsegv; | |
885 | } | |
df270051 RB |
886 | |
887 | /* | |
888 | * There is the ancient bug in the MIPS assemblers that the break | |
889 | * code starts left to bit 16 instead to bit 6 in the opcode. | |
890 | * Gas is bug-compatible, but not always, grrr... | |
891 | * We handle both cases with a simple heuristics. --macro | |
892 | */ | |
893 | bcode = ((opcode >> 6) & ((1 << 20) - 1)); | |
894 | if (bcode >= (1 << 10)) | |
895 | bcode >>= 10; | |
896 | ||
c1bf207d DD |
897 | /* |
898 | * notify the kprobe handlers, if instruction is likely to | |
899 | * pertain to them. | |
900 | */ | |
901 | switch (bcode) { | |
902 | case BRK_KPROBE_BP: | |
dc73e4c1 RB |
903 | if (notify_die(DIE_BREAK, "debug", regs, bcode, |
904 | regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP) | |
c3fc5cd5 | 905 | goto out; |
c1bf207d DD |
906 | else |
907 | break; | |
908 | case BRK_KPROBE_SSTEPBP: | |
dc73e4c1 RB |
909 | if (notify_die(DIE_SSTEPBP, "single_step", regs, bcode, |
910 | regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP) | |
c3fc5cd5 | 911 | goto out; |
c1bf207d DD |
912 | else |
913 | break; | |
914 | default: | |
915 | break; | |
916 | } | |
917 | ||
df270051 | 918 | do_trap_or_bp(regs, bcode, "Break"); |
c3fc5cd5 RB |
919 | |
920 | out: | |
921 | exception_exit(prev_state); | |
90fccb13 | 922 | return; |
e5679882 RB |
923 | |
924 | out_sigsegv: | |
925 | force_sig(SIGSEGV, current); | |
c3fc5cd5 | 926 | goto out; |
1da177e4 LT |
927 | } |
928 | ||
929 | asmlinkage void do_tr(struct pt_regs *regs) | |
930 | { | |
a9a6e7a0 | 931 | u32 opcode, tcode = 0; |
c3fc5cd5 | 932 | enum ctx_state prev_state; |
2a0b24f5 | 933 | u16 instr[2]; |
a9a6e7a0 | 934 | unsigned long epc = msk_isa16_mode(exception_epc(regs)); |
1da177e4 | 935 | |
c3fc5cd5 | 936 | prev_state = exception_enter(); |
a9a6e7a0 MR |
937 | if (get_isa16_mode(regs->cp0_epc)) { |
938 | if (__get_user(instr[0], (u16 __user *)(epc + 0)) || | |
939 | __get_user(instr[1], (u16 __user *)(epc + 2))) | |
2a0b24f5 | 940 | goto out_sigsegv; |
a9a6e7a0 MR |
941 | opcode = (instr[0] << 16) | instr[1]; |
942 | /* Immediate versions don't provide a code. */ | |
943 | if (!(opcode & OPCODE)) | |
944 | tcode = (opcode >> 12) & ((1 << 4) - 1); | |
945 | } else { | |
946 | if (__get_user(opcode, (u32 __user *)epc)) | |
947 | goto out_sigsegv; | |
948 | /* Immediate versions don't provide a code. */ | |
949 | if (!(opcode & OPCODE)) | |
950 | tcode = (opcode >> 6) & ((1 << 10) - 1); | |
2a0b24f5 | 951 | } |
1da177e4 | 952 | |
df270051 | 953 | do_trap_or_bp(regs, tcode, "Trap"); |
c3fc5cd5 RB |
954 | |
955 | out: | |
956 | exception_exit(prev_state); | |
90fccb13 | 957 | return; |
e5679882 RB |
958 | |
959 | out_sigsegv: | |
960 | force_sig(SIGSEGV, current); | |
c3fc5cd5 | 961 | goto out; |
1da177e4 LT |
962 | } |
963 | ||
964 | asmlinkage void do_ri(struct pt_regs *regs) | |
965 | { | |
60b0d655 MR |
966 | unsigned int __user *epc = (unsigned int __user *)exception_epc(regs); |
967 | unsigned long old_epc = regs->cp0_epc; | |
2a0b24f5 | 968 | unsigned long old31 = regs->regs[31]; |
c3fc5cd5 | 969 | enum ctx_state prev_state; |
60b0d655 MR |
970 | unsigned int opcode = 0; |
971 | int status = -1; | |
1da177e4 | 972 | |
c3fc5cd5 | 973 | prev_state = exception_enter(); |
dc73e4c1 RB |
974 | if (notify_die(DIE_RI, "RI Fault", regs, 0, regs_to_trapnr(regs), |
975 | SIGILL) == NOTIFY_STOP) | |
c3fc5cd5 | 976 | goto out; |
88547001 | 977 | |
60b0d655 | 978 | die_if_kernel("Reserved instruction in kernel code", regs); |
1da177e4 | 979 | |
60b0d655 | 980 | if (unlikely(compute_return_epc(regs) < 0)) |
c3fc5cd5 | 981 | goto out; |
3c37026d | 982 | |
2a0b24f5 SH |
983 | if (get_isa16_mode(regs->cp0_epc)) { |
984 | unsigned short mmop[2] = { 0 }; | |
60b0d655 | 985 | |
2a0b24f5 SH |
986 | if (unlikely(get_user(mmop[0], epc) < 0)) |
987 | status = SIGSEGV; | |
988 | if (unlikely(get_user(mmop[1], epc) < 0)) | |
989 | status = SIGSEGV; | |
990 | opcode = (mmop[0] << 16) | mmop[1]; | |
60b0d655 | 991 | |
2a0b24f5 SH |
992 | if (status < 0) |
993 | status = simulate_rdhwr_mm(regs, opcode); | |
994 | } else { | |
995 | if (unlikely(get_user(opcode, epc) < 0)) | |
996 | status = SIGSEGV; | |
60b0d655 | 997 | |
2a0b24f5 SH |
998 | if (!cpu_has_llsc && status < 0) |
999 | status = simulate_llsc(regs, opcode); | |
1000 | ||
1001 | if (status < 0) | |
1002 | status = simulate_rdhwr_normal(regs, opcode); | |
1003 | ||
1004 | if (status < 0) | |
1005 | status = simulate_sync(regs, opcode); | |
1006 | } | |
60b0d655 MR |
1007 | |
1008 | if (status < 0) | |
1009 | status = SIGILL; | |
1010 | ||
1011 | if (unlikely(status > 0)) { | |
1012 | regs->cp0_epc = old_epc; /* Undo skip-over. */ | |
2a0b24f5 | 1013 | regs->regs[31] = old31; |
60b0d655 MR |
1014 | force_sig(status, current); |
1015 | } | |
c3fc5cd5 RB |
1016 | |
1017 | out: | |
1018 | exception_exit(prev_state); | |
1da177e4 LT |
1019 | } |
1020 | ||
d223a861 RB |
1021 | /* |
1022 | * MIPS MT processors may have fewer FPU contexts than CPU threads. If we've | |
1023 | * emulated more than some threshold number of instructions, force migration to | |
1024 | * a "CPU" that has FP support. | |
1025 | */ | |
1026 | static void mt_ase_fp_affinity(void) | |
1027 | { | |
1028 | #ifdef CONFIG_MIPS_MT_FPAFF | |
1029 | if (mt_fpemul_threshold > 0 && | |
1030 | ((current->thread.emulated_fp++ > mt_fpemul_threshold))) { | |
1031 | /* | |
1032 | * If there's no FPU present, or if the application has already | |
1033 | * restricted the allowed set to exclude any CPUs with FPUs, | |
1034 | * we'll skip the procedure. | |
1035 | */ | |
1036 | if (cpus_intersects(current->cpus_allowed, mt_fpu_cpumask)) { | |
1037 | cpumask_t tmask; | |
1038 | ||
9cc12363 KK |
1039 | current->thread.user_cpus_allowed |
1040 | = current->cpus_allowed; | |
1041 | cpus_and(tmask, current->cpus_allowed, | |
1042 | mt_fpu_cpumask); | |
ed1bbdef | 1043 | set_cpus_allowed_ptr(current, &tmask); |
293c5bd1 | 1044 | set_thread_flag(TIF_FPUBOUND); |
d223a861 RB |
1045 | } |
1046 | } | |
1047 | #endif /* CONFIG_MIPS_MT_FPAFF */ | |
1048 | } | |
1049 | ||
69f3a7de RB |
1050 | /* |
1051 | * No lock; only written during early bootup by CPU 0. | |
1052 | */ | |
1053 | static RAW_NOTIFIER_HEAD(cu2_chain); | |
1054 | ||
1055 | int __ref register_cu2_notifier(struct notifier_block *nb) | |
1056 | { | |
1057 | return raw_notifier_chain_register(&cu2_chain, nb); | |
1058 | } | |
1059 | ||
1060 | int cu2_notifier_call_chain(unsigned long val, void *v) | |
1061 | { | |
1062 | return raw_notifier_call_chain(&cu2_chain, val, v); | |
1063 | } | |
1064 | ||
1065 | static int default_cu2_call(struct notifier_block *nfb, unsigned long action, | |
70342287 | 1066 | void *data) |
69f3a7de RB |
1067 | { |
1068 | struct pt_regs *regs = data; | |
1069 | ||
83bee792 | 1070 | die_if_kernel("COP2: Unhandled kernel unaligned access or invalid " |
69f3a7de | 1071 | "instruction", regs); |
83bee792 | 1072 | force_sig(SIGILL, current); |
69f3a7de RB |
1073 | |
1074 | return NOTIFY_OK; | |
1075 | } | |
1076 | ||
1da177e4 LT |
1077 | asmlinkage void do_cpu(struct pt_regs *regs) |
1078 | { | |
c3fc5cd5 | 1079 | enum ctx_state prev_state; |
60b0d655 | 1080 | unsigned int __user *epc; |
2a0b24f5 | 1081 | unsigned long old_epc, old31; |
60b0d655 | 1082 | unsigned int opcode; |
1da177e4 | 1083 | unsigned int cpid; |
597ce172 | 1084 | int status, err; |
f9bb4cf3 | 1085 | unsigned long __maybe_unused flags; |
1da177e4 | 1086 | |
c3fc5cd5 | 1087 | prev_state = exception_enter(); |
1da177e4 LT |
1088 | cpid = (regs->cp0_cause >> CAUSEB_CE) & 3; |
1089 | ||
83bee792 J |
1090 | if (cpid != 2) |
1091 | die_if_kernel("do_cpu invoked from kernel context!", regs); | |
1092 | ||
1da177e4 LT |
1093 | switch (cpid) { |
1094 | case 0: | |
60b0d655 MR |
1095 | epc = (unsigned int __user *)exception_epc(regs); |
1096 | old_epc = regs->cp0_epc; | |
2a0b24f5 | 1097 | old31 = regs->regs[31]; |
60b0d655 MR |
1098 | opcode = 0; |
1099 | status = -1; | |
1da177e4 | 1100 | |
60b0d655 | 1101 | if (unlikely(compute_return_epc(regs) < 0)) |
c3fc5cd5 | 1102 | goto out; |
3c37026d | 1103 | |
2a0b24f5 SH |
1104 | if (get_isa16_mode(regs->cp0_epc)) { |
1105 | unsigned short mmop[2] = { 0 }; | |
60b0d655 | 1106 | |
2a0b24f5 SH |
1107 | if (unlikely(get_user(mmop[0], epc) < 0)) |
1108 | status = SIGSEGV; | |
1109 | if (unlikely(get_user(mmop[1], epc) < 0)) | |
1110 | status = SIGSEGV; | |
1111 | opcode = (mmop[0] << 16) | mmop[1]; | |
60b0d655 | 1112 | |
2a0b24f5 SH |
1113 | if (status < 0) |
1114 | status = simulate_rdhwr_mm(regs, opcode); | |
1115 | } else { | |
1116 | if (unlikely(get_user(opcode, epc) < 0)) | |
1117 | status = SIGSEGV; | |
1118 | ||
1119 | if (!cpu_has_llsc && status < 0) | |
1120 | status = simulate_llsc(regs, opcode); | |
1121 | ||
1122 | if (status < 0) | |
1123 | status = simulate_rdhwr_normal(regs, opcode); | |
1124 | } | |
60b0d655 MR |
1125 | |
1126 | if (status < 0) | |
1127 | status = SIGILL; | |
1128 | ||
1129 | if (unlikely(status > 0)) { | |
1130 | regs->cp0_epc = old_epc; /* Undo skip-over. */ | |
2a0b24f5 | 1131 | regs->regs[31] = old31; |
60b0d655 MR |
1132 | force_sig(status, current); |
1133 | } | |
1134 | ||
c3fc5cd5 | 1135 | goto out; |
1da177e4 | 1136 | |
051ff44a MR |
1137 | case 3: |
1138 | /* | |
1139 | * Old (MIPS I and MIPS II) processors will set this code | |
1140 | * for COP1X opcode instructions that replaced the original | |
70342287 | 1141 | * COP3 space. We don't limit COP1 space instructions in |
051ff44a MR |
1142 | * the emulator according to the CPU ISA, so we want to |
1143 | * treat COP1X instructions consistently regardless of which | |
70342287 | 1144 | * code the CPU chose. Therefore we redirect this trap to |
051ff44a MR |
1145 | * the FP emulator too. |
1146 | * | |
1147 | * Then some newer FPU-less processors use this code | |
1148 | * erroneously too, so they are covered by this choice | |
1149 | * as well. | |
1150 | */ | |
1151 | if (raw_cpu_has_fpu) | |
1152 | break; | |
1153 | /* Fall through. */ | |
1154 | ||
1da177e4 | 1155 | case 1: |
70342287 | 1156 | if (used_math()) /* Using the FPU again. */ |
597ce172 | 1157 | err = own_fpu(1); |
70342287 | 1158 | else { /* First time FPU user. */ |
597ce172 | 1159 | err = init_fpu(); |
1da177e4 LT |
1160 | set_used_math(); |
1161 | } | |
1162 | ||
597ce172 | 1163 | if (!raw_cpu_has_fpu || err) { |
e04582b7 | 1164 | int sig; |
515b029d | 1165 | void __user *fault_addr = NULL; |
e04582b7 | 1166 | sig = fpu_emulator_cop1Handler(regs, |
515b029d DD |
1167 | ¤t->thread.fpu, |
1168 | 0, &fault_addr); | |
597ce172 | 1169 | if (!process_fpemu_return(sig, fault_addr) && !err) |
d223a861 | 1170 | mt_ase_fp_affinity(); |
1da177e4 LT |
1171 | } |
1172 | ||
c3fc5cd5 | 1173 | goto out; |
1da177e4 LT |
1174 | |
1175 | case 2: | |
69f3a7de | 1176 | raw_notifier_call_chain(&cu2_chain, CU2_EXCEPTION, regs); |
c3fc5cd5 | 1177 | goto out; |
1da177e4 LT |
1178 | } |
1179 | ||
1180 | force_sig(SIGILL, current); | |
c3fc5cd5 RB |
1181 | |
1182 | out: | |
1183 | exception_exit(prev_state); | |
1da177e4 LT |
1184 | } |
1185 | ||
1186 | asmlinkage void do_mdmx(struct pt_regs *regs) | |
1187 | { | |
c3fc5cd5 RB |
1188 | enum ctx_state prev_state; |
1189 | ||
1190 | prev_state = exception_enter(); | |
1da177e4 | 1191 | force_sig(SIGILL, current); |
c3fc5cd5 | 1192 | exception_exit(prev_state); |
1da177e4 LT |
1193 | } |
1194 | ||
8bc6d05b DD |
1195 | /* |
1196 | * Called with interrupts disabled. | |
1197 | */ | |
1da177e4 LT |
1198 | asmlinkage void do_watch(struct pt_regs *regs) |
1199 | { | |
c3fc5cd5 | 1200 | enum ctx_state prev_state; |
b67b2b70 DD |
1201 | u32 cause; |
1202 | ||
c3fc5cd5 | 1203 | prev_state = exception_enter(); |
1da177e4 | 1204 | /* |
b67b2b70 DD |
1205 | * Clear WP (bit 22) bit of cause register so we don't loop |
1206 | * forever. | |
1da177e4 | 1207 | */ |
b67b2b70 DD |
1208 | cause = read_c0_cause(); |
1209 | cause &= ~(1 << 22); | |
1210 | write_c0_cause(cause); | |
1211 | ||
1212 | /* | |
1213 | * If the current thread has the watch registers loaded, save | |
1214 | * their values and send SIGTRAP. Otherwise another thread | |
1215 | * left the registers set, clear them and continue. | |
1216 | */ | |
1217 | if (test_tsk_thread_flag(current, TIF_LOAD_WATCH)) { | |
1218 | mips_read_watch_registers(); | |
8bc6d05b | 1219 | local_irq_enable(); |
b67b2b70 | 1220 | force_sig(SIGTRAP, current); |
8bc6d05b | 1221 | } else { |
b67b2b70 | 1222 | mips_clear_watch_registers(); |
8bc6d05b DD |
1223 | local_irq_enable(); |
1224 | } | |
c3fc5cd5 | 1225 | exception_exit(prev_state); |
1da177e4 LT |
1226 | } |
1227 | ||
1228 | asmlinkage void do_mcheck(struct pt_regs *regs) | |
1229 | { | |
cac4bcbc RB |
1230 | const int field = 2 * sizeof(unsigned long); |
1231 | int multi_match = regs->cp0_status & ST0_TS; | |
c3fc5cd5 | 1232 | enum ctx_state prev_state; |
cac4bcbc | 1233 | |
c3fc5cd5 | 1234 | prev_state = exception_enter(); |
1da177e4 | 1235 | show_regs(regs); |
cac4bcbc RB |
1236 | |
1237 | if (multi_match) { | |
70342287 | 1238 | printk("Index : %0x\n", read_c0_index()); |
cac4bcbc RB |
1239 | printk("Pagemask: %0x\n", read_c0_pagemask()); |
1240 | printk("EntryHi : %0*lx\n", field, read_c0_entryhi()); | |
1241 | printk("EntryLo0: %0*lx\n", field, read_c0_entrylo0()); | |
1242 | printk("EntryLo1: %0*lx\n", field, read_c0_entrylo1()); | |
1243 | printk("\n"); | |
1244 | dump_tlb_all(); | |
1245 | } | |
1246 | ||
e1bb8289 | 1247 | show_code((unsigned int __user *) regs->cp0_epc); |
cac4bcbc | 1248 | |
1da177e4 LT |
1249 | /* |
1250 | * Some chips may have other causes of machine check (e.g. SB1 | |
1251 | * graduation timer) | |
1252 | */ | |
1253 | panic("Caught Machine Check exception - %scaused by multiple " | |
1254 | "matching entries in the TLB.", | |
cac4bcbc | 1255 | (multi_match) ? "" : "not "); |
1da177e4 LT |
1256 | } |
1257 | ||
340ee4b9 RB |
1258 | asmlinkage void do_mt(struct pt_regs *regs) |
1259 | { | |
41c594ab RB |
1260 | int subcode; |
1261 | ||
41c594ab RB |
1262 | subcode = (read_vpe_c0_vpecontrol() & VPECONTROL_EXCPT) |
1263 | >> VPECONTROL_EXCPT_SHIFT; | |
1264 | switch (subcode) { | |
1265 | case 0: | |
e35a5e35 | 1266 | printk(KERN_DEBUG "Thread Underflow\n"); |
41c594ab RB |
1267 | break; |
1268 | case 1: | |
e35a5e35 | 1269 | printk(KERN_DEBUG "Thread Overflow\n"); |
41c594ab RB |
1270 | break; |
1271 | case 2: | |
e35a5e35 | 1272 | printk(KERN_DEBUG "Invalid YIELD Qualifier\n"); |
41c594ab RB |
1273 | break; |
1274 | case 3: | |
e35a5e35 | 1275 | printk(KERN_DEBUG "Gating Storage Exception\n"); |
41c594ab RB |
1276 | break; |
1277 | case 4: | |
e35a5e35 | 1278 | printk(KERN_DEBUG "YIELD Scheduler Exception\n"); |
41c594ab RB |
1279 | break; |
1280 | case 5: | |
f232c7e8 | 1281 | printk(KERN_DEBUG "Gating Storage Scheduler Exception\n"); |
41c594ab RB |
1282 | break; |
1283 | default: | |
e35a5e35 | 1284 | printk(KERN_DEBUG "*** UNKNOWN THREAD EXCEPTION %d ***\n", |
41c594ab RB |
1285 | subcode); |
1286 | break; | |
1287 | } | |
340ee4b9 RB |
1288 | die_if_kernel("MIPS MT Thread exception in kernel", regs); |
1289 | ||
1290 | force_sig(SIGILL, current); | |
1291 | } | |
1292 | ||
1293 | ||
e50c0a8f RB |
1294 | asmlinkage void do_dsp(struct pt_regs *regs) |
1295 | { | |
1296 | if (cpu_has_dsp) | |
ab75dc02 | 1297 | panic("Unexpected DSP exception"); |
e50c0a8f RB |
1298 | |
1299 | force_sig(SIGILL, current); | |
1300 | } | |
1301 | ||
1da177e4 LT |
1302 | asmlinkage void do_reserved(struct pt_regs *regs) |
1303 | { | |
1304 | /* | |
70342287 | 1305 | * Game over - no way to handle this if it ever occurs. Most probably |
1da177e4 LT |
1306 | * caused by a new unknown cpu type or after another deadly |
1307 | * hard/software error. | |
1308 | */ | |
1309 | show_regs(regs); | |
1310 | panic("Caught reserved exception %ld - should not happen.", | |
1311 | (regs->cp0_cause & 0x7f) >> 2); | |
1312 | } | |
1313 | ||
39b8d525 RB |
1314 | static int __initdata l1parity = 1; |
1315 | static int __init nol1parity(char *s) | |
1316 | { | |
1317 | l1parity = 0; | |
1318 | return 1; | |
1319 | } | |
1320 | __setup("nol1par", nol1parity); | |
1321 | static int __initdata l2parity = 1; | |
1322 | static int __init nol2parity(char *s) | |
1323 | { | |
1324 | l2parity = 0; | |
1325 | return 1; | |
1326 | } | |
1327 | __setup("nol2par", nol2parity); | |
1328 | ||
1da177e4 LT |
1329 | /* |
1330 | * Some MIPS CPUs can enable/disable for cache parity detection, but do | |
1331 | * it different ways. | |
1332 | */ | |
1333 | static inline void parity_protection_init(void) | |
1334 | { | |
10cc3529 | 1335 | switch (current_cpu_type()) { |
1da177e4 | 1336 | case CPU_24K: |
98a41de9 | 1337 | case CPU_34K: |
39b8d525 RB |
1338 | case CPU_74K: |
1339 | case CPU_1004K: | |
442e14a2 | 1340 | case CPU_1074K: |
26ab96df | 1341 | case CPU_INTERAPTIV: |
708ac4b8 | 1342 | case CPU_PROAPTIV: |
39b8d525 RB |
1343 | { |
1344 | #define ERRCTL_PE 0x80000000 | |
1345 | #define ERRCTL_L2P 0x00800000 | |
1346 | unsigned long errctl; | |
1347 | unsigned int l1parity_present, l2parity_present; | |
1348 | ||
1349 | errctl = read_c0_ecc(); | |
1350 | errctl &= ~(ERRCTL_PE|ERRCTL_L2P); | |
1351 | ||
1352 | /* probe L1 parity support */ | |
1353 | write_c0_ecc(errctl | ERRCTL_PE); | |
1354 | back_to_back_c0_hazard(); | |
1355 | l1parity_present = (read_c0_ecc() & ERRCTL_PE); | |
1356 | ||
1357 | /* probe L2 parity support */ | |
1358 | write_c0_ecc(errctl|ERRCTL_L2P); | |
1359 | back_to_back_c0_hazard(); | |
1360 | l2parity_present = (read_c0_ecc() & ERRCTL_L2P); | |
1361 | ||
1362 | if (l1parity_present && l2parity_present) { | |
1363 | if (l1parity) | |
1364 | errctl |= ERRCTL_PE; | |
1365 | if (l1parity ^ l2parity) | |
1366 | errctl |= ERRCTL_L2P; | |
1367 | } else if (l1parity_present) { | |
1368 | if (l1parity) | |
1369 | errctl |= ERRCTL_PE; | |
1370 | } else if (l2parity_present) { | |
1371 | if (l2parity) | |
1372 | errctl |= ERRCTL_L2P; | |
1373 | } else { | |
1374 | /* No parity available */ | |
1375 | } | |
1376 | ||
1377 | printk(KERN_INFO "Writing ErrCtl register=%08lx\n", errctl); | |
1378 | ||
1379 | write_c0_ecc(errctl); | |
1380 | back_to_back_c0_hazard(); | |
1381 | errctl = read_c0_ecc(); | |
1382 | printk(KERN_INFO "Readback ErrCtl register=%08lx\n", errctl); | |
1383 | ||
1384 | if (l1parity_present) | |
1385 | printk(KERN_INFO "Cache parity protection %sabled\n", | |
1386 | (errctl & ERRCTL_PE) ? "en" : "dis"); | |
1387 | ||
1388 | if (l2parity_present) { | |
1389 | if (l1parity_present && l1parity) | |
1390 | errctl ^= ERRCTL_L2P; | |
1391 | printk(KERN_INFO "L2 cache parity protection %sabled\n", | |
1392 | (errctl & ERRCTL_L2P) ? "en" : "dis"); | |
1393 | } | |
1394 | } | |
1395 | break; | |
1396 | ||
1da177e4 | 1397 | case CPU_5KC: |
78d4803f | 1398 | case CPU_5KE: |
2fa36399 | 1399 | case CPU_LOONGSON1: |
14f18b7f RB |
1400 | write_c0_ecc(0x80000000); |
1401 | back_to_back_c0_hazard(); | |
1402 | /* Set the PE bit (bit 31) in the c0_errctl register. */ | |
1403 | printk(KERN_INFO "Cache parity protection %sabled\n", | |
1404 | (read_c0_ecc() & 0x80000000) ? "en" : "dis"); | |
1da177e4 LT |
1405 | break; |
1406 | case CPU_20KC: | |
1407 | case CPU_25KF: | |
1408 | /* Clear the DE bit (bit 16) in the c0_status register. */ | |
1409 | printk(KERN_INFO "Enable cache parity protection for " | |
1410 | "MIPS 20KC/25KF CPUs.\n"); | |
1411 | clear_c0_status(ST0_DE); | |
1412 | break; | |
1413 | default: | |
1414 | break; | |
1415 | } | |
1416 | } | |
1417 | ||
1418 | asmlinkage void cache_parity_error(void) | |
1419 | { | |
1420 | const int field = 2 * sizeof(unsigned long); | |
1421 | unsigned int reg_val; | |
1422 | ||
1423 | /* For the moment, report the problem and hang. */ | |
1424 | printk("Cache error exception:\n"); | |
1425 | printk("cp0_errorepc == %0*lx\n", field, read_c0_errorepc()); | |
1426 | reg_val = read_c0_cacheerr(); | |
1427 | printk("c0_cacheerr == %08x\n", reg_val); | |
1428 | ||
1429 | printk("Decoded c0_cacheerr: %s cache fault in %s reference.\n", | |
1430 | reg_val & (1<<30) ? "secondary" : "primary", | |
1431 | reg_val & (1<<31) ? "data" : "insn"); | |
6de20451 LY |
1432 | if (cpu_has_mips_r2 && |
1433 | ((current_cpu_data.processor_id && 0xff0000) == PRID_COMP_MIPS)) { | |
1434 | pr_err("Error bits: %s%s%s%s%s%s%s%s\n", | |
1435 | reg_val & (1<<29) ? "ED " : "", | |
1436 | reg_val & (1<<28) ? "ET " : "", | |
1437 | reg_val & (1<<27) ? "ES " : "", | |
1438 | reg_val & (1<<26) ? "EE " : "", | |
1439 | reg_val & (1<<25) ? "EB " : "", | |
1440 | reg_val & (1<<24) ? "EI " : "", | |
1441 | reg_val & (1<<23) ? "E1 " : "", | |
1442 | reg_val & (1<<22) ? "E0 " : ""); | |
1443 | } else { | |
1444 | pr_err("Error bits: %s%s%s%s%s%s%s\n", | |
1445 | reg_val & (1<<29) ? "ED " : "", | |
1446 | reg_val & (1<<28) ? "ET " : "", | |
1447 | reg_val & (1<<26) ? "EE " : "", | |
1448 | reg_val & (1<<25) ? "EB " : "", | |
1449 | reg_val & (1<<24) ? "EI " : "", | |
1450 | reg_val & (1<<23) ? "E1 " : "", | |
1451 | reg_val & (1<<22) ? "E0 " : ""); | |
1452 | } | |
1da177e4 LT |
1453 | printk("IDX: 0x%08x\n", reg_val & ((1<<22)-1)); |
1454 | ||
ec917c2c | 1455 | #if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64) |
1da177e4 LT |
1456 | if (reg_val & (1<<22)) |
1457 | printk("DErrAddr0: 0x%0*lx\n", field, read_c0_derraddr0()); | |
1458 | ||
1459 | if (reg_val & (1<<23)) | |
1460 | printk("DErrAddr1: 0x%0*lx\n", field, read_c0_derraddr1()); | |
1461 | #endif | |
1462 | ||
1463 | panic("Can't handle the cache error!"); | |
1464 | } | |
1465 | ||
75b5b5e0 LY |
1466 | asmlinkage void do_ftlb(void) |
1467 | { | |
1468 | const int field = 2 * sizeof(unsigned long); | |
1469 | unsigned int reg_val; | |
1470 | ||
1471 | /* For the moment, report the problem and hang. */ | |
1472 | if (cpu_has_mips_r2 && | |
1473 | ((current_cpu_data.processor_id && 0xff0000) == PRID_COMP_MIPS)) { | |
1474 | pr_err("FTLB error exception, cp0_ecc=0x%08x:\n", | |
1475 | read_c0_ecc()); | |
1476 | pr_err("cp0_errorepc == %0*lx\n", field, read_c0_errorepc()); | |
1477 | reg_val = read_c0_cacheerr(); | |
1478 | pr_err("c0_cacheerr == %08x\n", reg_val); | |
1479 | ||
1480 | if ((reg_val & 0xc0000000) == 0xc0000000) { | |
1481 | pr_err("Decoded c0_cacheerr: FTLB parity error\n"); | |
1482 | } else { | |
1483 | pr_err("Decoded c0_cacheerr: %s cache fault in %s reference.\n", | |
1484 | reg_val & (1<<30) ? "secondary" : "primary", | |
1485 | reg_val & (1<<31) ? "data" : "insn"); | |
1486 | } | |
1487 | } else { | |
1488 | pr_err("FTLB error exception\n"); | |
1489 | } | |
1490 | /* Just print the cacheerr bits for now */ | |
1491 | cache_parity_error(); | |
1492 | } | |
1493 | ||
1da177e4 LT |
1494 | /* |
1495 | * SDBBP EJTAG debug exception handler. | |
1496 | * We skip the instruction and return to the next instruction. | |
1497 | */ | |
1498 | void ejtag_exception_handler(struct pt_regs *regs) | |
1499 | { | |
1500 | const int field = 2 * sizeof(unsigned long); | |
2a0b24f5 | 1501 | unsigned long depc, old_epc, old_ra; |
1da177e4 LT |
1502 | unsigned int debug; |
1503 | ||
70ae6126 | 1504 | printk(KERN_DEBUG "SDBBP EJTAG debug exception - not handled yet, just ignored!\n"); |
1da177e4 LT |
1505 | depc = read_c0_depc(); |
1506 | debug = read_c0_debug(); | |
70ae6126 | 1507 | printk(KERN_DEBUG "c0_depc = %0*lx, DEBUG = %08x\n", field, depc, debug); |
1da177e4 LT |
1508 | if (debug & 0x80000000) { |
1509 | /* | |
1510 | * In branch delay slot. | |
1511 | * We cheat a little bit here and use EPC to calculate the | |
1512 | * debug return address (DEPC). EPC is restored after the | |
1513 | * calculation. | |
1514 | */ | |
1515 | old_epc = regs->cp0_epc; | |
2a0b24f5 | 1516 | old_ra = regs->regs[31]; |
1da177e4 | 1517 | regs->cp0_epc = depc; |
2a0b24f5 | 1518 | compute_return_epc(regs); |
1da177e4 LT |
1519 | depc = regs->cp0_epc; |
1520 | regs->cp0_epc = old_epc; | |
2a0b24f5 | 1521 | regs->regs[31] = old_ra; |
1da177e4 LT |
1522 | } else |
1523 | depc += 4; | |
1524 | write_c0_depc(depc); | |
1525 | ||
1526 | #if 0 | |
70ae6126 | 1527 | printk(KERN_DEBUG "\n\n----- Enable EJTAG single stepping ----\n\n"); |
1da177e4 LT |
1528 | write_c0_debug(debug | 0x100); |
1529 | #endif | |
1530 | } | |
1531 | ||
1532 | /* | |
1533 | * NMI exception handler. | |
34bd92e2 | 1534 | * No lock; only written during early bootup by CPU 0. |
1da177e4 | 1535 | */ |
34bd92e2 KC |
1536 | static RAW_NOTIFIER_HEAD(nmi_chain); |
1537 | ||
1538 | int register_nmi_notifier(struct notifier_block *nb) | |
1539 | { | |
1540 | return raw_notifier_chain_register(&nmi_chain, nb); | |
1541 | } | |
1542 | ||
ff2d8b19 | 1543 | void __noreturn nmi_exception_handler(struct pt_regs *regs) |
1da177e4 | 1544 | { |
83e4da1e LY |
1545 | char str[100]; |
1546 | ||
34bd92e2 | 1547 | raw_notifier_call_chain(&nmi_chain, 0, regs); |
41c594ab | 1548 | bust_spinlocks(1); |
83e4da1e LY |
1549 | snprintf(str, 100, "CPU%d NMI taken, CP0_EPC=%lx\n", |
1550 | smp_processor_id(), regs->cp0_epc); | |
1551 | regs->cp0_epc = read_c0_errorepc(); | |
1552 | die(str, regs); | |
1da177e4 LT |
1553 | } |
1554 | ||
e01402b1 RB |
1555 | #define VECTORSPACING 0x100 /* for EI/VI mode */ |
1556 | ||
1557 | unsigned long ebase; | |
1da177e4 | 1558 | unsigned long exception_handlers[32]; |
e01402b1 | 1559 | unsigned long vi_handlers[64]; |
1da177e4 | 1560 | |
2d1b6e95 | 1561 | void __init *set_except_vector(int n, void *addr) |
1da177e4 LT |
1562 | { |
1563 | unsigned long handler = (unsigned long) addr; | |
b22d1b6a | 1564 | unsigned long old_handler; |
1da177e4 | 1565 | |
2a0b24f5 SH |
1566 | #ifdef CONFIG_CPU_MICROMIPS |
1567 | /* | |
1568 | * Only the TLB handlers are cache aligned with an even | |
1569 | * address. All other handlers are on an odd address and | |
1570 | * require no modification. Otherwise, MIPS32 mode will | |
1571 | * be entered when handling any TLB exceptions. That | |
1572 | * would be bad...since we must stay in microMIPS mode. | |
1573 | */ | |
1574 | if (!(handler & 0x1)) | |
1575 | handler |= 1; | |
1576 | #endif | |
b22d1b6a | 1577 | old_handler = xchg(&exception_handlers[n], handler); |
1da177e4 | 1578 | |
1da177e4 | 1579 | if (n == 0 && cpu_has_divec) { |
2a0b24f5 SH |
1580 | #ifdef CONFIG_CPU_MICROMIPS |
1581 | unsigned long jump_mask = ~((1 << 27) - 1); | |
1582 | #else | |
92bbe1b9 | 1583 | unsigned long jump_mask = ~((1 << 28) - 1); |
2a0b24f5 | 1584 | #endif |
92bbe1b9 FF |
1585 | u32 *buf = (u32 *)(ebase + 0x200); |
1586 | unsigned int k0 = 26; | |
1587 | if ((handler & jump_mask) == ((ebase + 0x200) & jump_mask)) { | |
1588 | uasm_i_j(&buf, handler & ~jump_mask); | |
1589 | uasm_i_nop(&buf); | |
1590 | } else { | |
1591 | UASM_i_LA(&buf, k0, handler); | |
1592 | uasm_i_jr(&buf, k0); | |
1593 | uasm_i_nop(&buf); | |
1594 | } | |
1595 | local_flush_icache_range(ebase + 0x200, (unsigned long)buf); | |
e01402b1 RB |
1596 | } |
1597 | return (void *)old_handler; | |
1598 | } | |
1599 | ||
86a1708a | 1600 | static void do_default_vi(void) |
6ba07e59 AN |
1601 | { |
1602 | show_regs(get_irq_regs()); | |
1603 | panic("Caught unexpected vectored interrupt."); | |
1604 | } | |
1605 | ||
ef300e42 | 1606 | static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs) |
e01402b1 RB |
1607 | { |
1608 | unsigned long handler; | |
1609 | unsigned long old_handler = vi_handlers[n]; | |
f6771dbb | 1610 | int srssets = current_cpu_data.srsets; |
2a0b24f5 | 1611 | u16 *h; |
e01402b1 RB |
1612 | unsigned char *b; |
1613 | ||
b72b7092 | 1614 | BUG_ON(!cpu_has_veic && !cpu_has_vint); |
e01402b1 RB |
1615 | |
1616 | if (addr == NULL) { | |
1617 | handler = (unsigned long) do_default_vi; | |
1618 | srs = 0; | |
41c594ab | 1619 | } else |
e01402b1 | 1620 | handler = (unsigned long) addr; |
2a0b24f5 | 1621 | vi_handlers[n] = handler; |
e01402b1 RB |
1622 | |
1623 | b = (unsigned char *)(ebase + 0x200 + n*VECTORSPACING); | |
1624 | ||
f6771dbb | 1625 | if (srs >= srssets) |
e01402b1 RB |
1626 | panic("Shadow register set %d not supported", srs); |
1627 | ||
1628 | if (cpu_has_veic) { | |
1629 | if (board_bind_eic_interrupt) | |
49a89efb | 1630 | board_bind_eic_interrupt(n, srs); |
41c594ab | 1631 | } else if (cpu_has_vint) { |
e01402b1 | 1632 | /* SRSMap is only defined if shadow sets are implemented */ |
f6771dbb | 1633 | if (srssets > 1) |
49a89efb | 1634 | change_c0_srsmap(0xf << n*4, srs << n*4); |
e01402b1 RB |
1635 | } |
1636 | ||
1637 | if (srs == 0) { | |
1638 | /* | |
1639 | * If no shadow set is selected then use the default handler | |
2a0b24f5 | 1640 | * that does normal register saving and standard interrupt exit |
e01402b1 | 1641 | */ |
e01402b1 RB |
1642 | extern char except_vec_vi, except_vec_vi_lui; |
1643 | extern char except_vec_vi_ori, except_vec_vi_end; | |
c65a5480 | 1644 | extern char rollback_except_vec_vi; |
f94d9a8e | 1645 | char *vec_start = using_rollback_handler() ? |
c65a5480 | 1646 | &rollback_except_vec_vi : &except_vec_vi; |
41c594ab RB |
1647 | #ifdef CONFIG_MIPS_MT_SMTC |
1648 | /* | |
1649 | * We need to provide the SMTC vectored interrupt handler | |
1650 | * not only with the address of the handler, but with the | |
1651 | * Status.IM bit to be masked before going there. | |
1652 | */ | |
1653 | extern char except_vec_vi_mori; | |
2a0b24f5 SH |
1654 | #if defined(CONFIG_CPU_MICROMIPS) || defined(CONFIG_CPU_BIG_ENDIAN) |
1655 | const int mori_offset = &except_vec_vi_mori - vec_start + 2; | |
1656 | #else | |
c65a5480 | 1657 | const int mori_offset = &except_vec_vi_mori - vec_start; |
2a0b24f5 | 1658 | #endif |
41c594ab | 1659 | #endif /* CONFIG_MIPS_MT_SMTC */ |
2a0b24f5 SH |
1660 | #if defined(CONFIG_CPU_MICROMIPS) || defined(CONFIG_CPU_BIG_ENDIAN) |
1661 | const int lui_offset = &except_vec_vi_lui - vec_start + 2; | |
1662 | const int ori_offset = &except_vec_vi_ori - vec_start + 2; | |
1663 | #else | |
c65a5480 AN |
1664 | const int lui_offset = &except_vec_vi_lui - vec_start; |
1665 | const int ori_offset = &except_vec_vi_ori - vec_start; | |
2a0b24f5 SH |
1666 | #endif |
1667 | const int handler_len = &except_vec_vi_end - vec_start; | |
e01402b1 RB |
1668 | |
1669 | if (handler_len > VECTORSPACING) { | |
1670 | /* | |
1671 | * Sigh... panicing won't help as the console | |
1672 | * is probably not configured :( | |
1673 | */ | |
49a89efb | 1674 | panic("VECTORSPACING too small"); |
e01402b1 RB |
1675 | } |
1676 | ||
2a0b24f5 SH |
1677 | set_handler(((unsigned long)b - ebase), vec_start, |
1678 | #ifdef CONFIG_CPU_MICROMIPS | |
1679 | (handler_len - 1)); | |
1680 | #else | |
1681 | handler_len); | |
1682 | #endif | |
41c594ab | 1683 | #ifdef CONFIG_MIPS_MT_SMTC |
8e8a52ed RB |
1684 | BUG_ON(n > 7); /* Vector index %d exceeds SMTC maximum. */ |
1685 | ||
2a0b24f5 SH |
1686 | h = (u16 *)(b + mori_offset); |
1687 | *h = (0x100 << n); | |
41c594ab | 1688 | #endif /* CONFIG_MIPS_MT_SMTC */ |
2a0b24f5 SH |
1689 | h = (u16 *)(b + lui_offset); |
1690 | *h = (handler >> 16) & 0xffff; | |
1691 | h = (u16 *)(b + ori_offset); | |
1692 | *h = (handler & 0xffff); | |
e0cee3ee TB |
1693 | local_flush_icache_range((unsigned long)b, |
1694 | (unsigned long)(b+handler_len)); | |
e01402b1 RB |
1695 | } |
1696 | else { | |
1697 | /* | |
2a0b24f5 SH |
1698 | * In other cases jump directly to the interrupt handler. It |
1699 | * is the handler's responsibility to save registers if required | |
1700 | * (eg hi/lo) and return from the exception using "eret". | |
e01402b1 | 1701 | */ |
2a0b24f5 SH |
1702 | u32 insn; |
1703 | ||
1704 | h = (u16 *)b; | |
1705 | /* j handler */ | |
1706 | #ifdef CONFIG_CPU_MICROMIPS | |
1707 | insn = 0xd4000000 | (((u32)handler & 0x07ffffff) >> 1); | |
1708 | #else | |
1709 | insn = 0x08000000 | (((u32)handler & 0x0fffffff) >> 2); | |
1710 | #endif | |
1711 | h[0] = (insn >> 16) & 0xffff; | |
1712 | h[1] = insn & 0xffff; | |
1713 | h[2] = 0; | |
1714 | h[3] = 0; | |
e0cee3ee TB |
1715 | local_flush_icache_range((unsigned long)b, |
1716 | (unsigned long)(b+8)); | |
1da177e4 | 1717 | } |
e01402b1 | 1718 | |
1da177e4 LT |
1719 | return (void *)old_handler; |
1720 | } | |
1721 | ||
ef300e42 | 1722 | void *set_vi_handler(int n, vi_handler_t addr) |
e01402b1 | 1723 | { |
ff3eab2a | 1724 | return set_vi_srs_handler(n, addr, 0); |
e01402b1 | 1725 | } |
f41ae0b2 | 1726 | |
1da177e4 LT |
1727 | extern void tlb_init(void); |
1728 | ||
42f77542 RB |
1729 | /* |
1730 | * Timer interrupt | |
1731 | */ | |
1732 | int cp0_compare_irq; | |
68b6352c | 1733 | EXPORT_SYMBOL_GPL(cp0_compare_irq); |
010c108d | 1734 | int cp0_compare_irq_shift; |
42f77542 RB |
1735 | |
1736 | /* | |
1737 | * Performance counter IRQ or -1 if shared with timer | |
1738 | */ | |
1739 | int cp0_perfcount_irq; | |
1740 | EXPORT_SYMBOL_GPL(cp0_perfcount_irq); | |
1741 | ||
078a55fc | 1742 | static int noulri; |
bdc94eb4 CD |
1743 | |
1744 | static int __init ulri_disable(char *s) | |
1745 | { | |
1746 | pr_info("Disabling ulri\n"); | |
1747 | noulri = 1; | |
1748 | ||
1749 | return 1; | |
1750 | } | |
1751 | __setup("noulri", ulri_disable); | |
1752 | ||
078a55fc | 1753 | void per_cpu_trap_init(bool is_boot_cpu) |
1da177e4 LT |
1754 | { |
1755 | unsigned int cpu = smp_processor_id(); | |
1756 | unsigned int status_set = ST0_CU0; | |
18d693b3 | 1757 | unsigned int hwrena = cpu_hwrena_impl_bits; |
41c594ab RB |
1758 | #ifdef CONFIG_MIPS_MT_SMTC |
1759 | int secondaryTC = 0; | |
1760 | int bootTC = (cpu == 0); | |
1761 | ||
1762 | /* | |
1763 | * Only do per_cpu_trap_init() for first TC of Each VPE. | |
1764 | * Note that this hack assumes that the SMTC init code | |
1765 | * assigns TCs consecutively and in ascending order. | |
1766 | */ | |
1767 | ||
1768 | if (((read_c0_tcbind() & TCBIND_CURTC) != 0) && | |
1769 | ((read_c0_tcbind() & TCBIND_CURVPE) == cpu_data[cpu - 1].vpe_id)) | |
1770 | secondaryTC = 1; | |
1771 | #endif /* CONFIG_MIPS_MT_SMTC */ | |
1da177e4 LT |
1772 | |
1773 | /* | |
1774 | * Disable coprocessors and select 32-bit or 64-bit addressing | |
1775 | * and the 16/32 or 32/32 FPR register model. Reset the BEV | |
1776 | * flag that some firmware may have left set and the TS bit (for | |
1777 | * IP27). Set XX for ISA IV code to work. | |
1778 | */ | |
875d43e7 | 1779 | #ifdef CONFIG_64BIT |
1da177e4 LT |
1780 | status_set |= ST0_FR|ST0_KX|ST0_SX|ST0_UX; |
1781 | #endif | |
adb37892 | 1782 | if (current_cpu_data.isa_level & MIPS_CPU_ISA_IV) |
1da177e4 | 1783 | status_set |= ST0_XX; |
bbaf238b CD |
1784 | if (cpu_has_dsp) |
1785 | status_set |= ST0_MX; | |
1786 | ||
b38c7399 | 1787 | change_c0_status(ST0_CU|ST0_MX|ST0_RE|ST0_FR|ST0_BEV|ST0_TS|ST0_KX|ST0_SX|ST0_UX, |
1da177e4 LT |
1788 | status_set); |
1789 | ||
18d693b3 KC |
1790 | if (cpu_has_mips_r2) |
1791 | hwrena |= 0x0000000f; | |
a3692020 | 1792 | |
18d693b3 KC |
1793 | if (!noulri && cpu_has_userlocal) |
1794 | hwrena |= (1 << 29); | |
a3692020 | 1795 | |
18d693b3 KC |
1796 | if (hwrena) |
1797 | write_c0_hwrena(hwrena); | |
e01402b1 | 1798 | |
41c594ab RB |
1799 | #ifdef CONFIG_MIPS_MT_SMTC |
1800 | if (!secondaryTC) { | |
1801 | #endif /* CONFIG_MIPS_MT_SMTC */ | |
1802 | ||
e01402b1 | 1803 | if (cpu_has_veic || cpu_has_vint) { |
9fb4c2b9 | 1804 | unsigned long sr = set_c0_status(ST0_BEV); |
49a89efb | 1805 | write_c0_ebase(ebase); |
9fb4c2b9 | 1806 | write_c0_status(sr); |
e01402b1 | 1807 | /* Setting vector spacing enables EI/VI mode */ |
49a89efb | 1808 | change_c0_intctl(0x3e0, VECTORSPACING); |
e01402b1 | 1809 | } |
d03d0a57 RB |
1810 | if (cpu_has_divec) { |
1811 | if (cpu_has_mipsmt) { | |
1812 | unsigned int vpflags = dvpe(); | |
1813 | set_c0_cause(CAUSEF_IV); | |
1814 | evpe(vpflags); | |
1815 | } else | |
1816 | set_c0_cause(CAUSEF_IV); | |
1817 | } | |
3b1d4ed5 RB |
1818 | |
1819 | /* | |
1820 | * Before R2 both interrupt numbers were fixed to 7, so on R2 only: | |
1821 | * | |
1822 | * o read IntCtl.IPTI to determine the timer interrupt | |
1823 | * o read IntCtl.IPPCI to determine the performance counter interrupt | |
1824 | */ | |
1825 | if (cpu_has_mips_r2) { | |
010c108d DV |
1826 | cp0_compare_irq_shift = CAUSEB_TI - CAUSEB_IP; |
1827 | cp0_compare_irq = (read_c0_intctl() >> INTCTLB_IPTI) & 7; | |
1828 | cp0_perfcount_irq = (read_c0_intctl() >> INTCTLB_IPPCI) & 7; | |
c3e838a2 | 1829 | if (cp0_perfcount_irq == cp0_compare_irq) |
3b1d4ed5 | 1830 | cp0_perfcount_irq = -1; |
c3e838a2 CD |
1831 | } else { |
1832 | cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ; | |
c6a4ebb9 | 1833 | cp0_compare_irq_shift = CP0_LEGACY_PERFCNT_IRQ; |
c3e838a2 | 1834 | cp0_perfcount_irq = -1; |
3b1d4ed5 RB |
1835 | } |
1836 | ||
41c594ab RB |
1837 | #ifdef CONFIG_MIPS_MT_SMTC |
1838 | } | |
1839 | #endif /* CONFIG_MIPS_MT_SMTC */ | |
1da177e4 | 1840 | |
48c4ac97 DD |
1841 | if (!cpu_data[cpu].asid_cache) |
1842 | cpu_data[cpu].asid_cache = ASID_FIRST_VERSION; | |
1da177e4 LT |
1843 | |
1844 | atomic_inc(&init_mm.mm_count); | |
1845 | current->active_mm = &init_mm; | |
1846 | BUG_ON(current->mm); | |
1847 | enter_lazy_tlb(&init_mm, current); | |
1848 | ||
41c594ab RB |
1849 | #ifdef CONFIG_MIPS_MT_SMTC |
1850 | if (bootTC) { | |
1851 | #endif /* CONFIG_MIPS_MT_SMTC */ | |
6650df3c DD |
1852 | /* Boot CPU's cache setup in setup_arch(). */ |
1853 | if (!is_boot_cpu) | |
1854 | cpu_cache_init(); | |
41c594ab RB |
1855 | tlb_init(); |
1856 | #ifdef CONFIG_MIPS_MT_SMTC | |
6a05888d RB |
1857 | } else if (!secondaryTC) { |
1858 | /* | |
1859 | * First TC in non-boot VPE must do subset of tlb_init() | |
1860 | * for MMU countrol registers. | |
1861 | */ | |
1862 | write_c0_pagemask(PM_DEFAULT_MASK); | |
1863 | write_c0_wired(0); | |
41c594ab RB |
1864 | } |
1865 | #endif /* CONFIG_MIPS_MT_SMTC */ | |
3d8bfdd0 | 1866 | TLBMISS_HANDLER_SETUP(); |
1da177e4 LT |
1867 | } |
1868 | ||
e01402b1 | 1869 | /* Install CPU exception handler */ |
078a55fc | 1870 | void set_handler(unsigned long offset, void *addr, unsigned long size) |
e01402b1 | 1871 | { |
2a0b24f5 SH |
1872 | #ifdef CONFIG_CPU_MICROMIPS |
1873 | memcpy((void *)(ebase + offset), ((unsigned char *)addr - 1), size); | |
1874 | #else | |
e01402b1 | 1875 | memcpy((void *)(ebase + offset), addr, size); |
2a0b24f5 | 1876 | #endif |
e0cee3ee | 1877 | local_flush_icache_range(ebase + offset, ebase + offset + size); |
e01402b1 RB |
1878 | } |
1879 | ||
078a55fc | 1880 | static char panic_null_cerr[] = |
641e97f3 RB |
1881 | "Trying to set NULL cache error exception handler"; |
1882 | ||
42fe7ee3 RB |
1883 | /* |
1884 | * Install uncached CPU exception handler. | |
1885 | * This is suitable only for the cache error exception which is the only | |
1886 | * exception handler that is being run uncached. | |
1887 | */ | |
078a55fc | 1888 | void set_uncached_handler(unsigned long offset, void *addr, |
234fcd14 | 1889 | unsigned long size) |
e01402b1 | 1890 | { |
4f81b01a | 1891 | unsigned long uncached_ebase = CKSEG1ADDR(ebase); |
e01402b1 | 1892 | |
641e97f3 RB |
1893 | if (!addr) |
1894 | panic(panic_null_cerr); | |
1895 | ||
e01402b1 RB |
1896 | memcpy((void *)(uncached_ebase + offset), addr, size); |
1897 | } | |
1898 | ||
5b10496b AN |
1899 | static int __initdata rdhwr_noopt; |
1900 | static int __init set_rdhwr_noopt(char *str) | |
1901 | { | |
1902 | rdhwr_noopt = 1; | |
1903 | return 1; | |
1904 | } | |
1905 | ||
1906 | __setup("rdhwr_noopt", set_rdhwr_noopt); | |
1907 | ||
1da177e4 LT |
1908 | void __init trap_init(void) |
1909 | { | |
2a0b24f5 | 1910 | extern char except_vec3_generic; |
1da177e4 | 1911 | extern char except_vec4; |
2a0b24f5 | 1912 | extern char except_vec3_r4000; |
1da177e4 | 1913 | unsigned long i; |
c65a5480 AN |
1914 | |
1915 | check_wait(); | |
1da177e4 | 1916 | |
88547001 JW |
1917 | #if defined(CONFIG_KGDB) |
1918 | if (kgdb_early_setup) | |
70342287 | 1919 | return; /* Already done */ |
88547001 JW |
1920 | #endif |
1921 | ||
9fb4c2b9 CD |
1922 | if (cpu_has_veic || cpu_has_vint) { |
1923 | unsigned long size = 0x200 + VECTORSPACING*64; | |
1924 | ebase = (unsigned long) | |
1925 | __alloc_bootmem(size, 1 << fls(size), 0); | |
1926 | } else { | |
9843b030 SL |
1927 | #ifdef CONFIG_KVM_GUEST |
1928 | #define KVM_GUEST_KSEG0 0x40000000 | |
1929 | ebase = KVM_GUEST_KSEG0; | |
1930 | #else | |
1931 | ebase = CKSEG0; | |
1932 | #endif | |
566f74f6 DD |
1933 | if (cpu_has_mips_r2) |
1934 | ebase += (read_c0_ebase() & 0x3ffff000); | |
1935 | } | |
e01402b1 | 1936 | |
c6213c6c SH |
1937 | if (cpu_has_mmips) { |
1938 | unsigned int config3 = read_c0_config3(); | |
1939 | ||
1940 | if (IS_ENABLED(CONFIG_CPU_MICROMIPS)) | |
1941 | write_c0_config3(config3 | MIPS_CONF3_ISA_OE); | |
1942 | else | |
1943 | write_c0_config3(config3 & ~MIPS_CONF3_ISA_OE); | |
1944 | } | |
1945 | ||
6fb97eff KC |
1946 | if (board_ebase_setup) |
1947 | board_ebase_setup(); | |
6650df3c | 1948 | per_cpu_trap_init(true); |
1da177e4 LT |
1949 | |
1950 | /* | |
1951 | * Copy the generic exception handlers to their final destination. | |
1952 | * This will be overriden later as suitable for a particular | |
1953 | * configuration. | |
1954 | */ | |
e01402b1 | 1955 | set_handler(0x180, &except_vec3_generic, 0x80); |
1da177e4 LT |
1956 | |
1957 | /* | |
1958 | * Setup default vectors | |
1959 | */ | |
1960 | for (i = 0; i <= 31; i++) | |
1961 | set_except_vector(i, handle_reserved); | |
1962 | ||
1963 | /* | |
1964 | * Copy the EJTAG debug exception vector handler code to it's final | |
1965 | * destination. | |
1966 | */ | |
e01402b1 | 1967 | if (cpu_has_ejtag && board_ejtag_handler_setup) |
49a89efb | 1968 | board_ejtag_handler_setup(); |
1da177e4 LT |
1969 | |
1970 | /* | |
1971 | * Only some CPUs have the watch exceptions. | |
1972 | */ | |
1973 | if (cpu_has_watch) | |
1974 | set_except_vector(23, handle_watch); | |
1975 | ||
1976 | /* | |
e01402b1 | 1977 | * Initialise interrupt handlers |
1da177e4 | 1978 | */ |
e01402b1 RB |
1979 | if (cpu_has_veic || cpu_has_vint) { |
1980 | int nvec = cpu_has_veic ? 64 : 8; | |
1981 | for (i = 0; i < nvec; i++) | |
ff3eab2a | 1982 | set_vi_handler(i, NULL); |
e01402b1 RB |
1983 | } |
1984 | else if (cpu_has_divec) | |
1985 | set_handler(0x200, &except_vec4, 0x8); | |
1da177e4 LT |
1986 | |
1987 | /* | |
1988 | * Some CPUs can enable/disable for cache parity detection, but does | |
1989 | * it different ways. | |
1990 | */ | |
1991 | parity_protection_init(); | |
1992 | ||
1993 | /* | |
1994 | * The Data Bus Errors / Instruction Bus Errors are signaled | |
1995 | * by external hardware. Therefore these two exceptions | |
1996 | * may have board specific handlers. | |
1997 | */ | |
1998 | if (board_be_init) | |
1999 | board_be_init(); | |
2000 | ||
f94d9a8e RB |
2001 | set_except_vector(0, using_rollback_handler() ? rollback_handle_int |
2002 | : handle_int); | |
1da177e4 LT |
2003 | set_except_vector(1, handle_tlbm); |
2004 | set_except_vector(2, handle_tlbl); | |
2005 | set_except_vector(3, handle_tlbs); | |
2006 | ||
2007 | set_except_vector(4, handle_adel); | |
2008 | set_except_vector(5, handle_ades); | |
2009 | ||
2010 | set_except_vector(6, handle_ibe); | |
2011 | set_except_vector(7, handle_dbe); | |
2012 | ||
2013 | set_except_vector(8, handle_sys); | |
2014 | set_except_vector(9, handle_bp); | |
5b10496b AN |
2015 | set_except_vector(10, rdhwr_noopt ? handle_ri : |
2016 | (cpu_has_vtag_icache ? | |
2017 | handle_ri_rdhwr_vivt : handle_ri_rdhwr)); | |
1da177e4 LT |
2018 | set_except_vector(11, handle_cpu); |
2019 | set_except_vector(12, handle_ov); | |
2020 | set_except_vector(13, handle_tr); | |
1da177e4 | 2021 | |
10cc3529 RB |
2022 | if (current_cpu_type() == CPU_R6000 || |
2023 | current_cpu_type() == CPU_R6000A) { | |
1da177e4 LT |
2024 | /* |
2025 | * The R6000 is the only R-series CPU that features a machine | |
2026 | * check exception (similar to the R4000 cache error) and | |
2027 | * unaligned ldc1/sdc1 exception. The handlers have not been | |
70342287 | 2028 | * written yet. Well, anyway there is no R6000 machine on the |
1da177e4 LT |
2029 | * current list of targets for Linux/MIPS. |
2030 | * (Duh, crap, there is someone with a triple R6k machine) | |
2031 | */ | |
2032 | //set_except_vector(14, handle_mc); | |
2033 | //set_except_vector(15, handle_ndc); | |
2034 | } | |
2035 | ||
e01402b1 RB |
2036 | |
2037 | if (board_nmi_handler_setup) | |
2038 | board_nmi_handler_setup(); | |
2039 | ||
e50c0a8f RB |
2040 | if (cpu_has_fpu && !cpu_has_nofpuex) |
2041 | set_except_vector(15, handle_fpe); | |
2042 | ||
75b5b5e0 | 2043 | set_except_vector(16, handle_ftlb); |
e50c0a8f RB |
2044 | set_except_vector(22, handle_mdmx); |
2045 | ||
2046 | if (cpu_has_mcheck) | |
2047 | set_except_vector(24, handle_mcheck); | |
2048 | ||
340ee4b9 RB |
2049 | if (cpu_has_mipsmt) |
2050 | set_except_vector(25, handle_mt); | |
2051 | ||
acaec427 | 2052 | set_except_vector(26, handle_dsp); |
e50c0a8f | 2053 | |
fcbf1dfd DD |
2054 | if (board_cache_error_setup) |
2055 | board_cache_error_setup(); | |
2056 | ||
e50c0a8f RB |
2057 | if (cpu_has_vce) |
2058 | /* Special exception: R4[04]00 uses also the divec space. */ | |
2a0b24f5 | 2059 | set_handler(0x180, &except_vec3_r4000, 0x100); |
e50c0a8f | 2060 | else if (cpu_has_4kex) |
2a0b24f5 | 2061 | set_handler(0x180, &except_vec3_generic, 0x80); |
e50c0a8f | 2062 | else |
2a0b24f5 | 2063 | set_handler(0x080, &except_vec3_generic, 0x80); |
e50c0a8f | 2064 | |
e0cee3ee | 2065 | local_flush_icache_range(ebase, ebase + 0x400); |
0510617b TB |
2066 | |
2067 | sort_extable(__start___dbe_table, __stop___dbe_table); | |
69f3a7de | 2068 | |
4483b159 | 2069 | cu2_notifier(default_cu2_call, 0x80000000); /* Run last */ |
1da177e4 | 2070 | } |